^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for the ST Microelectronics SPEAr1310 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "pinctrl-spear.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DRIVER_NAME "spear1310-pinmux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const struct pinctrl_pin_desc spear1310_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) SPEAR_PIN_0_TO_101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SPEAR_PIN_102_TO_245,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PERIP_CFG 0x3B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCIF_SEL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PCIE_SATA_CFG 0x3A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_SATA2_SEL_PCIE (0 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PCIE_SATA1_SEL_PCIE (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PCIE_SATA0_SEL_PCIE (0 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PCIE_SATA2_SEL_SATA (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PCIE_SATA1_SEL_SATA (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PCIE_SATA0_SEL_SATA (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SATA2_CFG_TX_CLK_EN (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SATA2_CFG_RX_CLK_EN (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SATA2_CFG_POWERUP_RESET (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SATA2_CFG_PM_CLK_EN (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SATA1_CFG_TX_CLK_EN (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SATA1_CFG_RX_CLK_EN (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SATA1_CFG_POWERUP_RESET (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SATA1_CFG_PM_CLK_EN (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SATA0_CFG_TX_CLK_EN (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SATA0_CFG_RX_CLK_EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SATA0_CFG_POWERUP_RESET (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SATA0_CFG_PM_CLK_EN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCIE2_CFG_POWERUP_RESET (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCIE1_CFG_POWERUP_RESET (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PCIE0_CFG_POWERUP_RESET (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PAD_FUNCTION_EN_0 0x650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PMX_UART0_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PMX_I2C0_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PMX_I2S0_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMX_SSP0_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PMX_CLCD1_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PMX_EGPIO00_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PMX_EGPIO01_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PMX_EGPIO02_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PMX_EGPIO03_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PMX_EGPIO04_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PMX_EGPIO05_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PMX_EGPIO06_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PMX_EGPIO07_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PMX_EGPIO08_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PMX_EGPIO09_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PMX_SMI_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PMX_NAND8_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PMX_GMIICLK_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PMX_GMIID47_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PMX_MDC_MDIO_MASK (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMX_MCI_DATA8_15_MASK (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PMX_NFAD23_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PMX_NFAD24_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PMX_NFAD25_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define PMX_NFCE3_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PMX_NFWPRT3_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PMX_NFRSTPWDWN0_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PMX_NFRSTPWDWN1_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PMX_NFRSTPWDWN2_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PAD_FUNCTION_EN_1 0x654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PMX_NFRSTPWDWN3_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMX_SMINCS2_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PMX_SMINCS3_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMX_CLCD2_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PMX_KBD_ROWCOL68_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define PMX_EGPIO10_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMX_EGPIO11_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PMX_EGPIO12_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PMX_EGPIO13_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMX_EGPIO14_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMX_EGPIO15_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PMX_UART0_MODEM_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PMX_GPT0_TMR0_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMX_GPT0_TMR1_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PMX_GPT1_TMR0_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PMX_GPT1_TMR1_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PMX_I2S1_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PMX_KBD_ROWCOL25_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PMX_NFIO8_15_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PMX_KBD_COL1_MASK (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PMX_NFCE1_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PMX_KBD_COL0_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PMX_NFCE2_MASK (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PMX_KBD_ROW1_MASK (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PMX_NFWPRT1_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PMX_KBD_ROW0_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PMX_NFWPRT2_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PMX_MCIDATA0_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PMX_MCIDATA1_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PMX_MCIDATA2_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PMX_MCIDATA3_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PMX_MCIDATA4_MASK (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PAD_FUNCTION_EN_2 0x658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PMX_MCIDATA5_MASK (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PMX_MCIDATA6_MASK (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PMX_MCIDATA7_MASK (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PMX_MCIDATA1SD_MASK (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PMX_MCIDATA2SD_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PMX_MCIDATA3SD_MASK (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PMX_MCIADDR0ALE_MASK (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PMX_MCIADDR2_MASK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PMX_MCICECF_MASK (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PMX_MCICEXD_MASK (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PMX_MCICESDMMC_MASK (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PMX_MCICDCF1_MASK (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PMX_MCICDCF2_MASK (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PMX_MCICDXD_MASK (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PMX_MCICDSDMMC_MASK (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PMX_MCIDATADIR_MASK (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PMX_MCIDMARQWP_MASK (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PMX_MCIIORDRE_MASK (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PMX_MCIIOWRWE_MASK (1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PMX_MCIRESETCF_MASK (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PMX_MCICS0CE_MASK (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PMX_MCICFINTR_MASK (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PMX_MCIIORDY_MASK (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PMX_MCICS1_MASK (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define PMX_MCIDMAACK_MASK (1 << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PMX_MCISDCMD_MASK (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PMX_MCILEDS_MASK (1 << 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PMX_TOUCH_XY_MASK (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PMX_SSP0_CS0_MASK (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PMX_SSP0_CS1_2_MASK (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PAD_DIRECTION_SEL_0 0x65C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PAD_DIRECTION_SEL_1 0x660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PAD_DIRECTION_SEL_2 0x664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* combined macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PMX_RXCLK_RDV_TXEN_D03_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PMX_EGPIO02_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PMX_EGPIO09_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PMX_KBD_COL1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PMX_NFCE3_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define PMX_MCIFALL_1_MASK 0xF8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define PMX_MCIFALL_2_MASK 0x0FFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PMX_NFCE2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PMX_SSP0_CS1_2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PMX_GMIID47_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PMX_SSP0_CS1_2_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PCIE##x##_CFG_AUX_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PCIE##x##_CFG_CORE_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PCIE##x##_CFG_POWERUP_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PCIE##x##_CFG_DEVICE_PRESENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SATA##x##_CFG_PM_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SATA##x##_CFG_POWERUP_RESET | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SATA##x##_CFG_RX_CLK_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SATA##x##_CFG_TX_CLK_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Pad multiplexing for i2c0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const unsigned i2c0_pins[] = { 102, 103 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static struct spear_muxreg i2c0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .mask = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .val = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .mask = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .val = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct spear_modemux i2c0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .muxregs = i2c0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static struct spear_pingroup i2c0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .name = "i2c0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .pins = i2c0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .npins = ARRAY_SIZE(i2c0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .modemuxs = i2c0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const char *const i2c0_grps[] = { "i2c0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static struct spear_function i2c0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .groups = i2c0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .ngroups = ARRAY_SIZE(i2c0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* Pad multiplexing for ssp0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static struct spear_muxreg ssp0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .mask = PMX_SSP0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .val = PMX_SSP0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .mask = PMX_SSP0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .val = PMX_SSP0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static struct spear_modemux ssp0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .muxregs = ssp0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct spear_pingroup ssp0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .name = "ssp0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .pins = ssp0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .npins = ARRAY_SIZE(ssp0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .modemuxs = ssp0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Pad multiplexing for ssp0_cs0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const unsigned ssp0_cs0_pins[] = { 96 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct spear_muxreg ssp0_cs0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .mask = PMX_SSP0_CS0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .val = PMX_SSP0_CS0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .mask = PMX_SSP0_CS0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .val = PMX_SSP0_CS0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static struct spear_modemux ssp0_cs0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .muxregs = ssp0_cs0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static struct spear_pingroup ssp0_cs0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .name = "ssp0_cs0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .pins = ssp0_cs0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .npins = ARRAY_SIZE(ssp0_cs0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .modemuxs = ssp0_cs0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* ssp0_cs1_2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .mask = PMX_SSP0_CS1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .val = PMX_SSP0_CS1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .mask = PMX_SSP0_CS1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .val = PMX_SSP0_CS1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static struct spear_modemux ssp0_cs1_2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .muxregs = ssp0_cs1_2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct spear_pingroup ssp0_cs1_2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .name = "ssp0_cs1_2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .pins = ssp0_cs1_2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .modemuxs = ssp0_cs1_2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "ssp0_cs1_2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static struct spear_function ssp0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = "ssp0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .groups = ssp0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .ngroups = ARRAY_SIZE(ssp0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Pad multiplexing for i2s0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static struct spear_muxreg i2s0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .mask = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .val = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .mask = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .val = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static struct spear_modemux i2s0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .muxregs = i2s0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static struct spear_pingroup i2s0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .name = "i2s0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pins = i2s0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .npins = ARRAY_SIZE(i2s0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .modemuxs = i2s0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const char *const i2s0_grps[] = { "i2s0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct spear_function i2s0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .name = "i2s0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .groups = i2s0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .ngroups = ARRAY_SIZE(i2s0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Pad multiplexing for i2s1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct spear_muxreg i2s1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mask = PMX_I2S1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .val = PMX_I2S1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .mask = PMX_I2S1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .val = PMX_I2S1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static struct spear_modemux i2s1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .muxregs = i2s1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static struct spear_pingroup i2s1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .name = "i2s1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .pins = i2s1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .npins = ARRAY_SIZE(i2s1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .modemuxs = i2s1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static const char *const i2s1_grps[] = { "i2s1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static struct spear_function i2s1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .name = "i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .groups = i2s1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .ngroups = ARRAY_SIZE(i2s1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Pad multiplexing for clcd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 135, 136, 137, 138, 139, 140, 141, 142 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static struct spear_muxreg clcd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .val = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .val = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct spear_modemux clcd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .muxregs = clcd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .nmuxregs = ARRAY_SIZE(clcd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct spear_pingroup clcd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .name = "clcd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .pins = clcd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .npins = ARRAY_SIZE(clcd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .modemuxs = clcd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .nmodemuxs = ARRAY_SIZE(clcd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static struct spear_muxreg clcd_high_res_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .mask = PMX_CLCD2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .val = PMX_CLCD2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .mask = PMX_CLCD2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .val = PMX_CLCD2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct spear_modemux clcd_high_res_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .muxregs = clcd_high_res_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static struct spear_pingroup clcd_high_res_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "clcd_high_res_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .pins = clcd_high_res_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .npins = ARRAY_SIZE(clcd_high_res_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .modemuxs = clcd_high_res_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static struct spear_function clcd_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .name = "clcd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .groups = clcd_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .ngroups = ARRAY_SIZE(clcd_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 146, 147, 148, 149, 150, 151, 152 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static struct spear_muxreg arm_gpio_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .mask = PMX_EGPIO_0_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .val = PMX_EGPIO_0_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .mask = PMX_EGPIO_1_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .val = PMX_EGPIO_1_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .mask = PMX_EGPIO_0_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .val = PMX_EGPIO_0_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .mask = PMX_EGPIO_1_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .val = PMX_EGPIO_1_GRP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static struct spear_modemux arm_gpio_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .muxregs = arm_gpio_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static struct spear_pingroup arm_gpio_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .name = "arm_gpio_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .pins = arm_gpio_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .npins = ARRAY_SIZE(arm_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .modemuxs = arm_gpio_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static struct spear_function arm_gpio_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "arm_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .groups = arm_gpio_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .ngroups = ARRAY_SIZE(arm_gpio_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Pad multiplexing for smi 2 chips device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static struct spear_muxreg smi_2_chips_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mask = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .val = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .mask = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .val = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static struct spear_modemux smi_2_chips_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .muxregs = smi_2_chips_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static struct spear_pingroup smi_2_chips_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .name = "smi_2_chips_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .pins = smi_2_chips_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .npins = ARRAY_SIZE(smi_2_chips_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .modemuxs = smi_2_chips_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const unsigned smi_4_chips_pins[] = { 54, 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static struct spear_muxreg smi_4_chips_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .mask = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .val = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .mask = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .val = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static struct spear_modemux smi_4_chips_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .muxregs = smi_4_chips_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct spear_pingroup smi_4_chips_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .name = "smi_4_chips_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .pins = smi_4_chips_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .npins = ARRAY_SIZE(smi_4_chips_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .modemuxs = smi_4_chips_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static struct spear_function smi_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .name = "smi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .groups = smi_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .ngroups = ARRAY_SIZE(smi_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Pad multiplexing for gmii device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 195, 196, 197, 198, 199, 200 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static struct spear_muxreg gmii_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .mask = PMX_GMII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .val = PMX_GMII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .mask = PMX_GMII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .val = PMX_GMII_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static struct spear_modemux gmii_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .muxregs = gmii_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .nmuxregs = ARRAY_SIZE(gmii_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static struct spear_pingroup gmii_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .name = "gmii_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .pins = gmii_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .npins = ARRAY_SIZE(gmii_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .modemuxs = gmii_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .nmodemuxs = ARRAY_SIZE(gmii_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const char *const gmii_grps[] = { "gmii_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static struct spear_function gmii_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .name = "gmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .groups = gmii_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .ngroups = ARRAY_SIZE(gmii_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Pad multiplexing for rgmii device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct spear_muxreg rgmii_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .mask = PMX_RGMII_REG0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .mask = PMX_RGMII_REG1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .mask = PMX_RGMII_REG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .mask = PMX_RGMII_REG0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .val = PMX_RGMII_REG0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .mask = PMX_RGMII_REG1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .val = PMX_RGMII_REG1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .mask = PMX_RGMII_REG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .val = PMX_RGMII_REG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct spear_modemux rgmii_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .muxregs = rgmii_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static struct spear_pingroup rgmii_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .name = "rgmii_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .pins = rgmii_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .npins = ARRAY_SIZE(rgmii_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .modemuxs = rgmii_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const char *const rgmii_grps[] = { "rgmii_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct spear_function rgmii_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .name = "rgmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .groups = rgmii_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .ngroups = ARRAY_SIZE(rgmii_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /* Pad multiplexing for smii_0_1_2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 51, 52, 53, 54, 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static struct spear_muxreg smii_0_1_2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .mask = PMX_SMII_0_1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .mask = PMX_SMII_0_1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .val = PMX_SMII_0_1_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct spear_modemux smii_0_1_2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .muxregs = smii_0_1_2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static struct spear_pingroup smii_0_1_2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .name = "smii_0_1_2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .pins = smii_0_1_2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .npins = ARRAY_SIZE(smii_0_1_2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .modemuxs = smii_0_1_2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct spear_function smii_0_1_2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .name = "smii_0_1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .groups = smii_0_1_2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* Pad multiplexing for ras_mii_txclk device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static struct spear_muxreg ras_mii_txclk_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .mask = PMX_NFCE2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .mask = PMX_NFCE2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .val = PMX_NFCE2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct spear_modemux ras_mii_txclk_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .muxregs = ras_mii_txclk_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static struct spear_pingroup ras_mii_txclk_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .name = "ras_mii_txclk_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .pins = ras_mii_txclk_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .npins = ARRAY_SIZE(ras_mii_txclk_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .modemuxs = ras_mii_txclk_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct spear_function ras_mii_txclk_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .name = "ras_mii_txclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .groups = ras_mii_txclk_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* Pad multiplexing for nand 8bit device (cs0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) 212 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static struct spear_muxreg nand_8bit_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .mask = PMX_NAND8BIT_0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .val = PMX_NAND8BIT_0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .mask = PMX_NAND8BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .val = PMX_NAND8BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .mask = PMX_NAND8BIT_0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .val = PMX_NAND8BIT_0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .mask = PMX_NAND8BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .val = PMX_NAND8BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct spear_modemux nand_8bit_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .muxregs = nand_8bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static struct spear_pingroup nand_8bit_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .name = "nand_8bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .pins = nand_8bit_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .npins = ARRAY_SIZE(nand_8bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .modemuxs = nand_8bit_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Pad multiplexing for nand 16bit device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) 210 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static struct spear_muxreg nand_16bit_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .mask = PMX_NAND16BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .val = PMX_NAND16BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .mask = PMX_NAND16BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .val = PMX_NAND16BIT_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static struct spear_modemux nand_16bit_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .muxregs = nand_16bit_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static struct spear_pingroup nand_16bit_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .name = "nand_16bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .pins = nand_16bit_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .npins = ARRAY_SIZE(nand_16bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .modemuxs = nand_16bit_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* Pad multiplexing for nand 4 chips */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static struct spear_muxreg nand_4_chips_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .mask = PMX_NAND_4CHIPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .val = PMX_NAND_4CHIPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .mask = PMX_NAND_4CHIPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .val = PMX_NAND_4CHIPS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static struct spear_modemux nand_4_chips_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .muxregs = nand_4_chips_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static struct spear_pingroup nand_4_chips_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .name = "nand_4_chips_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .pins = nand_4_chips_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .npins = ARRAY_SIZE(nand_4_chips_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .modemuxs = nand_4_chips_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "nand_4_chips_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static struct spear_function nand_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .name = "nand",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .groups = nand_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .ngroups = ARRAY_SIZE(nand_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Pad multiplexing for keyboard_6x6 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 208, 209, 210, 211, 212 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static struct spear_muxreg keyboard_6x6_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PMX_NFWPRT2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .val = PMX_KEYBOARD_6X6_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static struct spear_modemux keyboard_6x6_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .muxregs = keyboard_6x6_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static struct spear_pingroup keyboard_6x6_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .name = "keyboard_6x6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .pins = keyboard_6x6_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .npins = ARRAY_SIZE(keyboard_6x6_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .modemuxs = keyboard_6x6_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Pad multiplexing for keyboard_rowcol6_8 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .mask = PMX_KBD_ROWCOL68_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .val = PMX_KBD_ROWCOL68_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .mask = PMX_KBD_ROWCOL68_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .val = PMX_KBD_ROWCOL68_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .muxregs = keyboard_rowcol6_8_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .name = "keyboard_rowcol6_8_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .pins = keyboard_rowcol6_8_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .modemuxs = keyboard_rowcol6_8_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "keyboard_rowcol6_8_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static struct spear_function keyboard_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .name = "keyboard",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .groups = keyboard_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .ngroups = ARRAY_SIZE(keyboard_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Pad multiplexing for uart0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned uart0_pins[] = { 100, 101 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static struct spear_muxreg uart0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .mask = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .val = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .mask = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .val = PMX_UART0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static struct spear_modemux uart0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .muxregs = uart0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .nmuxregs = ARRAY_SIZE(uart0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static struct spear_pingroup uart0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .name = "uart0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .pins = uart0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .npins = ARRAY_SIZE(uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .modemuxs = uart0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .nmodemuxs = ARRAY_SIZE(uart0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Pad multiplexing for uart0_modem device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static struct spear_muxreg uart0_modem_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .val = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .mask = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .val = PMX_UART0_MODEM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static struct spear_modemux uart0_modem_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .muxregs = uart0_modem_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static struct spear_pingroup uart0_modem_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .name = "uart0_modem_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .pins = uart0_modem_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .npins = ARRAY_SIZE(uart0_modem_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .modemuxs = uart0_modem_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) static struct spear_function uart0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .name = "uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .groups = uart0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .ngroups = ARRAY_SIZE(uart0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Pad multiplexing for gpt0_tmr0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static struct spear_muxreg gpt0_tmr0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .mask = PMX_GPT0_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) .val = PMX_GPT0_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .mask = PMX_GPT0_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .val = PMX_GPT0_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static struct spear_modemux gpt0_tmr0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .muxregs = gpt0_tmr0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static struct spear_pingroup gpt0_tmr0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .name = "gpt0_tmr0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .pins = gpt0_tmr0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .npins = ARRAY_SIZE(gpt0_tmr0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .modemuxs = gpt0_tmr0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Pad multiplexing for gpt0_tmr1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static struct spear_muxreg gpt0_tmr1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .mask = PMX_GPT0_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .val = PMX_GPT0_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .mask = PMX_GPT0_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .val = PMX_GPT0_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static struct spear_modemux gpt0_tmr1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .muxregs = gpt0_tmr1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static struct spear_pingroup gpt0_tmr1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .name = "gpt0_tmr1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .pins = gpt0_tmr1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .npins = ARRAY_SIZE(gpt0_tmr1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .modemuxs = gpt0_tmr1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static struct spear_function gpt0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .name = "gpt0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .groups = gpt0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .ngroups = ARRAY_SIZE(gpt0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Pad multiplexing for gpt1_tmr0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static struct spear_muxreg gpt1_tmr0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) .mask = PMX_GPT1_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .val = PMX_GPT1_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .mask = PMX_GPT1_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .val = PMX_GPT1_TMR0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static struct spear_modemux gpt1_tmr0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .muxregs = gpt1_tmr0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static struct spear_pingroup gpt1_tmr0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .name = "gpt1_tmr0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .pins = gpt1_tmr0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .npins = ARRAY_SIZE(gpt1_tmr0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) .modemuxs = gpt1_tmr0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Pad multiplexing for gpt1_tmr1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static struct spear_muxreg gpt1_tmr1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .mask = PMX_GPT1_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .val = PMX_GPT1_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .mask = PMX_GPT1_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .val = PMX_GPT1_TMR1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static struct spear_modemux gpt1_tmr1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .muxregs = gpt1_tmr1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static struct spear_pingroup gpt1_tmr1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .name = "gpt1_tmr1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .pins = gpt1_tmr1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .npins = ARRAY_SIZE(gpt1_tmr1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .modemuxs = gpt1_tmr1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static struct spear_function gpt1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .name = "gpt1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .groups = gpt1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .ngroups = ARRAY_SIZE(gpt1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Pad multiplexing for mcif device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) 243, 244, 245 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define MCIF_MUXREG \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .reg = PAD_FUNCTION_EN_0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .mask = PMX_MCI_DATA8_15_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .val = PMX_MCI_DATA8_15_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .reg = PAD_FUNCTION_EN_1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PMX_NFWPRT2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .val = PMX_MCIFALL_1_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) .reg = PAD_FUNCTION_EN_2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .mask = PMX_MCIFALL_2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .val = PMX_MCIFALL_2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .reg = PAD_DIRECTION_SEL_0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) .mask = PMX_MCI_DATA8_15_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) .val = PMX_MCI_DATA8_15_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .reg = PAD_DIRECTION_SEL_1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PMX_NFWPRT2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PMX_NFWPRT2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .reg = PAD_DIRECTION_SEL_2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .mask = PMX_MCIFALL_2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .val = PMX_MCIFALL_2_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* sdhci device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static struct spear_muxreg sdhci_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) MCIF_MUXREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .reg = PERIP_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .mask = MCIF_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) .val = MCIF_SEL_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) static struct spear_modemux sdhci_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .muxregs = sdhci_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static struct spear_pingroup sdhci_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .name = "sdhci_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .pins = mcif_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .npins = ARRAY_SIZE(mcif_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .modemuxs = sdhci_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const char *const sdhci_grps[] = { "sdhci_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static struct spear_function sdhci_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .name = "sdhci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .groups = sdhci_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .ngroups = ARRAY_SIZE(sdhci_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* cf device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static struct spear_muxreg cf_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) MCIF_MUXREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .reg = PERIP_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .mask = MCIF_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .val = MCIF_SEL_CF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static struct spear_modemux cf_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .muxregs = cf_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .nmuxregs = ARRAY_SIZE(cf_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static struct spear_pingroup cf_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .name = "cf_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) .pins = mcif_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .npins = ARRAY_SIZE(mcif_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .modemuxs = cf_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .nmodemuxs = ARRAY_SIZE(cf_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const char *const cf_grps[] = { "cf_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static struct spear_function cf_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .name = "cf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .groups = cf_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .ngroups = ARRAY_SIZE(cf_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* xd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct spear_muxreg xd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) MCIF_MUXREG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .reg = PERIP_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .mask = MCIF_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .val = MCIF_SEL_XD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static struct spear_modemux xd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .muxregs = xd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .nmuxregs = ARRAY_SIZE(xd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static struct spear_pingroup xd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) .name = "xd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) .pins = mcif_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) .npins = ARRAY_SIZE(mcif_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) .modemuxs = xd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .nmodemuxs = ARRAY_SIZE(xd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const char *const xd_grps[] = { "xd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static struct spear_function xd_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) .name = "xd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .groups = xd_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .ngroups = ARRAY_SIZE(xd_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Pad multiplexing for touch_xy device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static const unsigned touch_xy_pins[] = { 97 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static struct spear_muxreg touch_xy_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .mask = PMX_TOUCH_XY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .val = PMX_TOUCH_XY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .mask = PMX_TOUCH_XY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) .val = PMX_TOUCH_XY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static struct spear_modemux touch_xy_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .muxregs = touch_xy_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static struct spear_pingroup touch_xy_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .name = "touch_xy_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .pins = touch_xy_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .npins = ARRAY_SIZE(touch_xy_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .modemuxs = touch_xy_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const char *const touch_xy_grps[] = { "touch_xy_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static struct spear_function touch_xy_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .name = "touchscreen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .groups = touch_xy_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .ngroups = ARRAY_SIZE(touch_xy_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* Pad multiplexing for uart1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* Muxed with I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .mask = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .mask = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .val = PMX_I2C0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static struct spear_modemux uart1_dis_i2c_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .muxregs = uart1_dis_i2c_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static struct spear_pingroup uart_1_dis_i2c_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .name = "uart1_disable_i2c_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .pins = uart1_dis_i2c_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .modemuxs = uart1_dis_i2c_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* Muxed with SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static struct spear_muxreg uart1_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .mask = PMX_MCIDATA1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PMX_MCIDATA2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .mask = PMX_MCIDATA1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PMX_MCIDATA2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .val = PMX_MCIDATA1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PMX_MCIDATA2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static struct spear_modemux uart1_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .muxregs = uart1_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static struct spear_pingroup uart_1_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .name = "uart1_disable_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .pins = uart1_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .npins = ARRAY_SIZE(uart1_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .modemuxs = uart1_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) "uart1_disable_sd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static struct spear_function uart1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .name = "uart1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .groups = uart1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .ngroups = ARRAY_SIZE(uart1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Pad multiplexing for uart2_3 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static struct spear_muxreg uart2_3_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .mask = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .mask = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .val = PMX_I2S0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static struct spear_modemux uart2_3_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .muxregs = uart2_3_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static struct spear_pingroup uart_2_3_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .name = "uart2_3_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .pins = uart2_3_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .npins = ARRAY_SIZE(uart2_3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .modemuxs = uart2_3_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const char *const uart2_3_grps[] = { "uart2_3_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static struct spear_function uart2_3_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) .name = "uart2_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .groups = uart2_3_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .ngroups = ARRAY_SIZE(uart2_3_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Pad multiplexing for uart4 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static const unsigned uart4_pins[] = { 108, 113 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static struct spear_muxreg uart4_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static struct spear_modemux uart4_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .muxregs = uart4_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .nmuxregs = ARRAY_SIZE(uart4_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static struct spear_pingroup uart_4_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .name = "uart4_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .pins = uart4_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .npins = ARRAY_SIZE(uart4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .modemuxs = uart4_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .nmodemuxs = ARRAY_SIZE(uart4_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const char *const uart4_grps[] = { "uart4_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static struct spear_function uart4_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .name = "uart4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .groups = uart4_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .ngroups = ARRAY_SIZE(uart4_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* Pad multiplexing for uart5 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const unsigned uart5_pins[] = { 114, 115 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static struct spear_muxreg uart5_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .val = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static struct spear_modemux uart5_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .muxregs = uart5_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .nmuxregs = ARRAY_SIZE(uart5_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static struct spear_pingroup uart_5_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .name = "uart5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .pins = uart5_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .npins = ARRAY_SIZE(uart5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .modemuxs = uart5_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .nmodemuxs = ARRAY_SIZE(uart5_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static const char *const uart5_grps[] = { "uart5_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static struct spear_function uart5_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .name = "uart5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .groups = uart5_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .ngroups = ARRAY_SIZE(uart5_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Pad multiplexing for rs485_0_1_tdm_0_1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) 136, 137 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .val = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .muxregs = rs485_0_1_tdm_0_1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .name = "rs485_0_1_tdm_0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .pins = rs485_0_1_tdm_0_1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .modemuxs = rs485_0_1_tdm_0_1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static struct spear_function rs485_0_1_tdm_0_1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) .name = "rs485_0_1_tdm_0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) .groups = rs485_0_1_tdm_0_1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Pad multiplexing for i2c_1_2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static struct spear_muxreg i2c_1_2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .mask = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .val = PMX_CLCD1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static struct spear_modemux i2c_1_2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .muxregs = i2c_1_2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static struct spear_pingroup i2c_1_2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .name = "i2c_1_2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .pins = i2c_1_2_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .npins = ARRAY_SIZE(i2c_1_2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .modemuxs = i2c_1_2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static struct spear_function i2c_1_2_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .name = "i2c_1_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .groups = i2c_1_2_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .ngroups = ARRAY_SIZE(i2c_1_2_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) /* Pad multiplexing for i2c3_dis_smi_clcd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* Muxed with SMI & CLCD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .val = PMX_CLCD1_MASK | PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .muxregs = i2c3_dis_smi_clcd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .name = "i2c3_dis_smi_clcd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .pins = i2c3_dis_smi_clcd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .modemuxs = i2c3_dis_smi_clcd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* Pad multiplexing for i2c3_dis_sd_i2s0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* Muxed with SD/MMC & I2S1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .muxregs = i2c3_dis_sd_i2s0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .name = "i2c3_dis_sd_i2s0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .pins = i2c3_dis_sd_i2s0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .modemuxs = i2c3_dis_sd_i2s0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) "i2c3_dis_sd_i2s0_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static struct spear_function i2c3_unction = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .name = "i2c3_i2s1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .groups = i2c3_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .ngroups = ARRAY_SIZE(i2c3_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* Pad multiplexing for i2c_4_5_dis_smi device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /* Muxed with SMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .mask = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .mask = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .val = PMX_SMI_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .muxregs = i2c_4_5_dis_smi_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .name = "i2c_4_5_dis_smi_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .pins = i2c_4_5_dis_smi_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .modemuxs = i2c_4_5_dis_smi_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* Pad multiplexing for i2c4_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* Muxed with SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .mask = PMX_MCIDATA4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .mask = PMX_MCIDATA5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .mask = PMX_MCIDATA4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .val = PMX_MCIDATA4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .mask = PMX_MCIDATA5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .val = PMX_MCIDATA5_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static struct spear_modemux i2c4_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .muxregs = i2c4_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static struct spear_pingroup i2c4_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .name = "i2c4_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .pins = i2c4_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .modemuxs = i2c4_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* Pad multiplexing for i2c5_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Muxed with SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .mask = PMX_MCIDATA6_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) PMX_MCIDATA7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .mask = PMX_MCIDATA6_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) PMX_MCIDATA7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .val = PMX_MCIDATA6_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) PMX_MCIDATA7_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static struct spear_modemux i2c5_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .muxregs = i2c5_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static struct spear_pingroup i2c5_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) .name = "i2c5_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) .pins = i2c5_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .modemuxs = i2c5_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static struct spear_function i2c_4_5_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) .name = "i2c_4_5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .groups = i2c_4_5_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .ngroups = ARRAY_SIZE(i2c_4_5_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* Pad multiplexing for i2c_6_7_dis_kbd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* Muxed with KBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) .mask = PMX_KBD_ROWCOL25_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .mask = PMX_KBD_ROWCOL25_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .val = PMX_KBD_ROWCOL25_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .muxregs = i2c_6_7_dis_kbd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) .name = "i2c_6_7_dis_kbd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) .pins = i2c_6_7_dis_kbd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) .modemuxs = i2c_6_7_dis_kbd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* Pad multiplexing for i2c6_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) /* Muxed with SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .mask = PMX_MCIIORDRE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) PMX_MCIIOWRWE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .mask = PMX_MCIIORDRE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) PMX_MCIIOWRWE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .val = PMX_MCIIORDRE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) PMX_MCIIOWRWE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static struct spear_modemux i2c6_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .muxregs = i2c6_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static struct spear_pingroup i2c6_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .name = "i2c6_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .pins = i2c6_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .modemuxs = i2c6_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* Pad multiplexing for i2c7_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) .mask = PMX_MCIRESETCF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) PMX_MCICS0CE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .mask = PMX_MCIRESETCF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) PMX_MCICS0CE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .val = PMX_MCIRESETCF_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) PMX_MCICS0CE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static struct spear_modemux i2c7_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .muxregs = i2c7_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static struct spear_pingroup i2c7_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .name = "i2c7_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .pins = i2c7_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .modemuxs = i2c7_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static struct spear_function i2c_6_7_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .name = "i2c_6_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .groups = i2c_6_7_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .ngroups = ARRAY_SIZE(i2c_6_7_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* Pad multiplexing for can0_dis_nor device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* Muxed with NOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static const unsigned can0_dis_nor_pins[] = { 56, 57 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static struct spear_muxreg can0_dis_nor_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .mask = PMX_NFRSTPWDWN2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .mask = PMX_NFRSTPWDWN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .mask = PMX_NFRSTPWDWN2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .val = PMX_NFRSTPWDWN2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) .mask = PMX_NFRSTPWDWN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .val = PMX_NFRSTPWDWN3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static struct spear_modemux can0_dis_nor_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .muxregs = can0_dis_nor_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static struct spear_pingroup can0_dis_nor_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .name = "can0_dis_nor_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .pins = can0_dis_nor_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .npins = ARRAY_SIZE(can0_dis_nor_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .modemuxs = can0_dis_nor_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* Pad multiplexing for can0_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* Muxed with SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static const unsigned can0_dis_sd_pins[] = { 240, 241 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static struct spear_muxreg can0_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static struct spear_modemux can0_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) .muxregs = can0_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static struct spear_pingroup can0_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .name = "can0_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .pins = can0_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) .npins = ARRAY_SIZE(can0_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) .modemuxs = can0_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static struct spear_function can0_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .name = "can0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) .groups = can0_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) .ngroups = ARRAY_SIZE(can0_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* Pad multiplexing for can1_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* Muxed with SD/MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static const unsigned can1_dis_sd_pins[] = { 242, 243 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static struct spear_muxreg can1_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static struct spear_modemux can1_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .muxregs = can1_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static struct spear_pingroup can1_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) .name = "can1_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .pins = can1_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .npins = ARRAY_SIZE(can1_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) .modemuxs = can1_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /* Pad multiplexing for can1_dis_kbd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* Muxed with KBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static struct spear_muxreg can1_dis_kbd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) .mask = PMX_KBD_ROWCOL25_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) .mask = PMX_KBD_ROWCOL25_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) .val = PMX_KBD_ROWCOL25_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static struct spear_modemux can1_dis_kbd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) .muxregs = can1_dis_kbd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static struct spear_pingroup can1_dis_kbd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) .name = "can1_dis_kbd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) .pins = can1_dis_kbd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) .npins = ARRAY_SIZE(can1_dis_kbd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) .modemuxs = can1_dis_kbd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static struct spear_function can1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) .name = "can1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) .groups = can1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) .ngroups = ARRAY_SIZE(can1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* Pad multiplexing for (ras-ip) pci device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static struct spear_muxreg pci_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .reg = PAD_FUNCTION_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) .mask = PMX_MCI_DATA8_15_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) .mask = PMX_PCI_REG1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) .mask = PMX_PCI_REG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .reg = PAD_DIRECTION_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) .mask = PMX_MCI_DATA8_15_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) .val = PMX_MCI_DATA8_15_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .mask = PMX_PCI_REG1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .val = PMX_PCI_REG1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .mask = PMX_PCI_REG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .val = PMX_PCI_REG2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static struct spear_modemux pci_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) .muxregs = pci_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .nmuxregs = ARRAY_SIZE(pci_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static struct spear_pingroup pci_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .name = "pci_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .pins = pci_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .npins = ARRAY_SIZE(pci_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .modemuxs = pci_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .nmodemuxs = ARRAY_SIZE(pci_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const char *const pci_grps[] = { "pci_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static struct spear_function pci_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) .name = "pci",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .groups = pci_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .ngroups = ARRAY_SIZE(pci_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* pad multiplexing for (fix-part) pcie0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static struct spear_muxreg pcie0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .reg = PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .mask = PCIE_CFG_VAL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .val = PCIE_CFG_VAL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static struct spear_modemux pcie0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .muxregs = pcie0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static struct spear_pingroup pcie0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .name = "pcie0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .modemuxs = pcie0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* pad multiplexing for (fix-part) pcie1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static struct spear_muxreg pcie1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) .reg = PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .mask = PCIE_CFG_VAL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .val = PCIE_CFG_VAL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) static struct spear_modemux pcie1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) .muxregs = pcie1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static struct spear_pingroup pcie1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .name = "pcie1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .modemuxs = pcie1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* pad multiplexing for (fix-part) pcie2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) static struct spear_muxreg pcie2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .reg = PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .mask = PCIE_CFG_VAL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .val = PCIE_CFG_VAL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static struct spear_modemux pcie2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) .muxregs = pcie2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static struct spear_pingroup pcie2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .name = "pcie2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .modemuxs = pcie2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static struct spear_function pcie_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .name = "pci_express",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .groups = pcie_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .ngroups = ARRAY_SIZE(pcie_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /* pad multiplexing for sata0 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static struct spear_muxreg sata0_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) .reg = PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) .mask = SATA_CFG_VAL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) .val = SATA_CFG_VAL(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) static struct spear_modemux sata0_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) .muxregs = sata0_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) .nmuxregs = ARRAY_SIZE(sata0_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static struct spear_pingroup sata0_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) .name = "sata0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) .modemuxs = sata0_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) .nmodemuxs = ARRAY_SIZE(sata0_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* pad multiplexing for sata1 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static struct spear_muxreg sata1_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .reg = PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .mask = SATA_CFG_VAL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .val = SATA_CFG_VAL(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static struct spear_modemux sata1_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .muxregs = sata1_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .nmuxregs = ARRAY_SIZE(sata1_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static struct spear_pingroup sata1_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) .name = "sata1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) .modemuxs = sata1_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) .nmodemuxs = ARRAY_SIZE(sata1_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) /* pad multiplexing for sata2 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static struct spear_muxreg sata2_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) .reg = PCIE_SATA_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) .mask = SATA_CFG_VAL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) .val = SATA_CFG_VAL(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static struct spear_modemux sata2_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) .muxregs = sata2_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) .nmuxregs = ARRAY_SIZE(sata2_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static struct spear_pingroup sata2_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .name = "sata2_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .modemuxs = sata2_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) .nmodemuxs = ARRAY_SIZE(sata2_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static struct spear_function sata_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .name = "sata",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .groups = sata_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .ngroups = ARRAY_SIZE(sata_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) /* Pad multiplexing for ssp1_dis_kbd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .reg = PAD_FUNCTION_EN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) PMX_NFCE2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) .reg = PAD_DIRECTION_SEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) PMX_NFCE2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) PMX_NFCE2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) static struct spear_modemux ssp1_dis_kbd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .muxregs = ssp1_dis_kbd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static struct spear_pingroup ssp1_dis_kbd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) .name = "ssp1_dis_kbd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) .pins = ssp1_dis_kbd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .modemuxs = ssp1_dis_kbd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* Pad multiplexing for ssp1_dis_sd device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) static struct spear_modemux ssp1_dis_sd_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) .muxregs = ssp1_dis_sd_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static struct spear_pingroup ssp1_dis_sd_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .name = "ssp1_dis_sd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .pins = ssp1_dis_sd_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .modemuxs = ssp1_dis_sd_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) "ssp1_dis_sd_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) static struct spear_function ssp1_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .name = "ssp1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .groups = ssp1_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .ngroups = ARRAY_SIZE(ssp1_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) /* Pad multiplexing for gpt64 device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static struct spear_muxreg gpt64_muxreg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .reg = PAD_FUNCTION_EN_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) | PMX_MCILEDS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .val = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .reg = PAD_DIRECTION_SEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) | PMX_MCILEDS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) | PMX_MCILEDS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) static struct spear_modemux gpt64_modemux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .muxregs = gpt64_muxreg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static struct spear_pingroup gpt64_pingroup = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) .name = "gpt64_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) .pins = gpt64_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .npins = ARRAY_SIZE(gpt64_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .modemuxs = gpt64_modemux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static const char *const gpt64_grps[] = { "gpt64_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static struct spear_function gpt64_function = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .name = "gpt64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .groups = gpt64_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .ngroups = ARRAY_SIZE(gpt64_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* pingroups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static struct spear_pingroup *spear1310_pingroups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) &i2c0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) &ssp0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) &i2s0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) &i2s1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) &clcd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) &clcd_high_res_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) &arm_gpio_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) &smi_2_chips_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) &smi_4_chips_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) &gmii_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) &rgmii_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) &smii_0_1_2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) &ras_mii_txclk_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) &nand_8bit_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) &nand_16bit_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) &nand_4_chips_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) &keyboard_6x6_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) &keyboard_rowcol6_8_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) &uart0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) &uart0_modem_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) &gpt0_tmr0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) &gpt0_tmr1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) &gpt1_tmr0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) &gpt1_tmr1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) &sdhci_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) &cf_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) &xd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) &touch_xy_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) &ssp0_cs0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) &ssp0_cs1_2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) &uart_1_dis_i2c_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) &uart_1_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) &uart_2_3_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) &uart_4_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) &uart_5_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) &rs485_0_1_tdm_0_1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) &i2c_1_2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) &i2c3_dis_smi_clcd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) &i2c3_dis_sd_i2s0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) &i2c_4_5_dis_smi_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) &i2c4_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) &i2c5_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) &i2c_6_7_dis_kbd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) &i2c6_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) &i2c7_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) &can0_dis_nor_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) &can0_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) &can1_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) &can1_dis_kbd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) &pci_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) &pcie0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) &pcie1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) &pcie2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) &sata0_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) &sata1_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) &sata2_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) &ssp1_dis_kbd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) &ssp1_dis_sd_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) &gpt64_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) static struct spear_function *spear1310_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) &i2c0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) &ssp0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) &i2s0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) &i2s1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) &clcd_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) &arm_gpio_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) &smi_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) &gmii_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) &rgmii_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) &smii_0_1_2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) &ras_mii_txclk_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) &nand_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) &keyboard_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) &uart0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) &gpt0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) &gpt1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) &sdhci_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) &cf_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) &xd_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) &touch_xy_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) &uart1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) &uart2_3_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) &uart4_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) &uart5_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) &rs485_0_1_tdm_0_1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) &i2c_1_2_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) &i2c3_unction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) &i2c_4_5_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) &i2c_6_7_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) &can0_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) &can1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) &pci_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) &pcie_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) &sata_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) &ssp1_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) &gpt64_function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static const unsigned pin18[] = { 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static const unsigned pin19[] = { 19, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const unsigned pin20[] = { 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) static const unsigned pin21[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static const unsigned pin22[] = { 22, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static const unsigned pin23[] = { 23, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static const unsigned pin54[] = { 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static const unsigned pin55[] = { 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) static const unsigned pin56[] = { 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static const unsigned pin57[] = { 57, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) static const unsigned pin58[] = { 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static const unsigned pin59[] = { 59, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) static const unsigned pin60[] = { 60, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static const unsigned pin61[] = { 61, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static const unsigned pin62[] = { 62, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static const unsigned pin63[] = { 63, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static const unsigned pin143[] = { 143, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static const unsigned pin144[] = { 144, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static const unsigned pin145[] = { 145, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) static const unsigned pin146[] = { 146, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const unsigned pin147[] = { 147, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static const unsigned pin148[] = { 148, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static const unsigned pin149[] = { 149, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static const unsigned pin150[] = { 150, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static const unsigned pin151[] = { 151, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static const unsigned pin152[] = { 152, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static const unsigned pin205[] = { 205, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const unsigned pin206[] = { 206, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static const unsigned pin211[] = { 211, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) static const unsigned pin212[] = { 212, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static const unsigned pin213[] = { 213, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static const unsigned pin214[] = { 214, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static const unsigned pin215[] = { 215, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static const unsigned pin216[] = { 216, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const unsigned pin217[] = { 217, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) static const unsigned pin218[] = { 218, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static const unsigned pin219[] = { 219, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static const unsigned pin220[] = { 220, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) static const unsigned pin221[] = { 221, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static const unsigned pin222[] = { 222, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) static const unsigned pin223[] = { 223, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) static const unsigned pin224[] = { 224, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) static const unsigned pin225[] = { 225, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static const unsigned pin226[] = { 226, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static const unsigned pin227[] = { 227, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static const unsigned pin228[] = { 228, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static const unsigned pin229[] = { 229, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const unsigned pin230[] = { 230, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static const unsigned pin231[] = { 231, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static const unsigned pin232[] = { 232, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static const unsigned pin233[] = { 233, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) static const unsigned pin234[] = { 234, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static const unsigned pin235[] = { 235, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static const unsigned pin236[] = { 236, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) static const unsigned pin237[] = { 237, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static const unsigned pin238[] = { 238, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static const unsigned pin239[] = { 239, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static const unsigned pin240[] = { 240, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static const unsigned pin241[] = { 241, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) static const unsigned pin242[] = { 242, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static const unsigned pin243[] = { 243, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static const unsigned pin244[] = { 244, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) static const unsigned pin245[] = { 245, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const unsigned pin_grp0[] = { 173, 174, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) 190, 191, 192, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static const unsigned pin_grp4[] = { 199, 200, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static const unsigned pin_grp7[] = { 98, 99, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) 166, 167, 168, 169, 170, 171, 172, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) /* Define muxreg arrays */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) GPIO_PINGROUP(i2c0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) GPIO_PINGROUP(ssp0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) GPIO_PINGROUP(ssp0_cs0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) GPIO_PINGROUP(ssp0_cs1_2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) GPIO_PINGROUP(i2s0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) GPIO_PINGROUP(i2s1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) GPIO_PINGROUP(clcd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) GPIO_PINGROUP(clcd_high_res_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) GPIO_PINGROUP(pin18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) GPIO_PINGROUP(pin19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) GPIO_PINGROUP(pin20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) GPIO_PINGROUP(pin21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) GPIO_PINGROUP(pin22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) GPIO_PINGROUP(pin23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) GPIO_PINGROUP(pin143),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) GPIO_PINGROUP(pin144),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) GPIO_PINGROUP(pin145),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) GPIO_PINGROUP(pin146),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) GPIO_PINGROUP(pin147),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) GPIO_PINGROUP(pin148),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) GPIO_PINGROUP(pin149),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) GPIO_PINGROUP(pin150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) GPIO_PINGROUP(pin151),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) GPIO_PINGROUP(pin152),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) GPIO_PINGROUP(smi_2_chips_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) GPIO_PINGROUP(pin54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) GPIO_PINGROUP(pin55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) GPIO_PINGROUP(pin56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) GPIO_PINGROUP(pin57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) GPIO_PINGROUP(pin58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) GPIO_PINGROUP(pin59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) GPIO_PINGROUP(pin60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) GPIO_PINGROUP(pin61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) GPIO_PINGROUP(pin62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) GPIO_PINGROUP(pin63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) GPIO_PINGROUP(pin_grp0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) GPIO_PINGROUP(pin_grp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) GPIO_PINGROUP(pin_grp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) GPIO_PINGROUP(pin_grp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) GPIO_PINGROUP(pin_grp4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) GPIO_PINGROUP(pin_grp5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) GPIO_PINGROUP(pin_grp6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) GPIO_PINGROUP(pin_grp7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) GPIO_PINGROUP(pin_grp8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) GPIO_PINGROUP(nand_16bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) GPIO_PINGROUP(pin205),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) GPIO_PINGROUP(pin206),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) GPIO_PINGROUP(pin211),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) GPIO_PINGROUP(pin212),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) GPIO_PINGROUP(pin213),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) GPIO_PINGROUP(pin214),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) GPIO_PINGROUP(pin215),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) GPIO_PINGROUP(pin216),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) GPIO_PINGROUP(pin217),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) GPIO_PINGROUP(pin218),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) GPIO_PINGROUP(pin219),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) GPIO_PINGROUP(pin220),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) GPIO_PINGROUP(pin221),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) GPIO_PINGROUP(pin222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) GPIO_PINGROUP(pin223),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) GPIO_PINGROUP(pin224),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) GPIO_PINGROUP(pin225),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) GPIO_PINGROUP(pin226),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) GPIO_PINGROUP(pin227),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) GPIO_PINGROUP(pin228),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) GPIO_PINGROUP(pin229),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) GPIO_PINGROUP(pin230),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) GPIO_PINGROUP(pin231),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) GPIO_PINGROUP(pin232),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) GPIO_PINGROUP(pin233),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) GPIO_PINGROUP(pin234),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) GPIO_PINGROUP(pin235),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) GPIO_PINGROUP(pin236),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) GPIO_PINGROUP(pin237),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) GPIO_PINGROUP(pin238),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) GPIO_PINGROUP(pin239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) GPIO_PINGROUP(pin240),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) GPIO_PINGROUP(pin241),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) GPIO_PINGROUP(pin242),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) GPIO_PINGROUP(pin243),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) GPIO_PINGROUP(pin244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) GPIO_PINGROUP(pin245),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) GPIO_PINGROUP(keyboard_rowcol6_8_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) GPIO_PINGROUP(uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) GPIO_PINGROUP(uart0_modem_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) GPIO_PINGROUP(gpt0_tmr0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) GPIO_PINGROUP(gpt0_tmr1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) GPIO_PINGROUP(gpt1_tmr0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) GPIO_PINGROUP(gpt1_tmr1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) GPIO_PINGROUP(touch_xy_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) static struct spear_pinctrl_machdata spear1310_machdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .pins = spear1310_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .npins = ARRAY_SIZE(spear1310_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .groups = spear1310_pingroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) .ngroups = ARRAY_SIZE(spear1310_pingroups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .functions = spear1310_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) .nfunctions = ARRAY_SIZE(spear1310_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) .gpio_pingroups = spear1310_gpio_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) .ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .modes_supported = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static const struct of_device_id spear1310_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) .compatible = "st,spear1310-pinmux",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static int spear1310_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) return spear_pinctrl_probe(pdev, &spear1310_machdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) static struct platform_driver spear1310_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .of_match_table = spear1310_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .probe = spear1310_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) static int __init spear1310_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) return platform_driver_register(&spear1310_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) arch_initcall(spear1310_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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