^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver header file for the ST Microelectronics SPEAr pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __PINMUX_SPEAR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __PINMUX_SPEAR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct spear_pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * struct spear_pmx_mode - SPEAr pmx mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @name: name of pmx mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @mode: mode id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @reg: register for configuring this mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @mask: mask of this mode in reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @val: val to be configured at reg after doing (val & mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct spear_pmx_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) const char *const name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * struct spear_muxreg - SPEAr mux reg configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @reg: register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @mask: mask bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @val: val to be written on mask bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct spear_muxreg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct spear_gpio_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct spear_muxreg *muxregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u8 nmuxregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* ste: set to enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DEFINE_MUXREG(__pins, __muxreg, __mask, __ste) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static struct spear_muxreg __pins##_muxregs[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .reg = __muxreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .mask = __mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .val = __ste ? __mask : 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DEFINE_2_MUXREG(__pins, __muxreg1, __muxreg2, __mask, __ste1, __ste2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static struct spear_muxreg __pins##_muxregs[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .reg = __muxreg1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mask = __mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .val = __ste1 ? __mask : 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }, { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .reg = __muxreg2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .mask = __mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .val = __ste2 ? __mask : 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPIO_PINGROUP(__pins) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .pins = __pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .npins = ARRAY_SIZE(__pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .muxregs = __pins##_muxregs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .nmuxregs = ARRAY_SIZE(__pins##_muxregs), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * struct spear_modemux - SPEAr mode mux configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @modes: mode ids supported by this group of muxregs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @nmuxregs: number of muxreg configurations to be done for modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @muxregs: array of muxreg configurations to be done for modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct spear_modemux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 nmuxregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct spear_muxreg *muxregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * struct spear_pingroup - SPEAr pin group configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @name: name of pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @pins: array containing pin numbers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @npins: size of pins array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @modemuxs: array of modemux configurations for this pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @nmodemuxs: size of array modemuxs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * A representation of a group of pins in the SPEAr pin controller. Each group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * allows some parameter or parameters to be configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct spear_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct spear_modemux *modemuxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned nmodemuxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * struct spear_function - SPEAr pinctrl mux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @name: The name of the function, exported to pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @groups: An array of pin groups that may select this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @ngroups: The number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct spear_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * struct spear_pinctrl_machdata - SPEAr pin controller machine driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @pins: An array describing all pins the pin controller affects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * All pins which are also GPIOs must be listed first within the *array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * and be numbered identically to the GPIO controller's *numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @npins: The numbmer of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @functions: An array describing all mux functions the SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @nfunctions: The numbmer of entries in @functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @groups: An array describing all pin groups the pin SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @ngroups: The numbmer of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @gpio_pingroups: gpio pingroups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @ngpio_pingroups: gpio pingroups count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @modes_supported: Does SoC support modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @mode: mode configured from probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @pmx_modes: array of modes supported by SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @npmx_modes: number of entries in pmx_modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct spear_pinctrl_machdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct spear_function **functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct spear_pingroup **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct spear_gpio_pingroup *gpio_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void (*gpio_request_endisable)(struct spear_pmx *pmx, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned ngpio_pingroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool modes_supported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct spear_pmx_mode **pmx_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned npmx_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * struct spear_pmx - SPEAr pinctrl mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @dev: pointer to struct dev of platform_device registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @pctl: pointer to struct pinctrl_dev
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @machdata: pointer to SoC or machine specific structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @vbase: virtual base address of pinmux controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct spear_pmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct spear_pinctrl_machdata *machdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) void __iomem *vbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* exported routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return readl_relaxed(pmx->vbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel_relaxed(val, pmx->vbase + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned count, u16 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int spear_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct spear_pinctrl_machdata *machdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SPEAR_PIN_0_TO_101 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(0, "PLGPIO0"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(1, "PLGPIO1"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(2, "PLGPIO2"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(3, "PLGPIO3"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(4, "PLGPIO4"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(5, "PLGPIO5"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(6, "PLGPIO6"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(7, "PLGPIO7"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(8, "PLGPIO8"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(9, "PLGPIO9"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(10, "PLGPIO10"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(11, "PLGPIO11"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(12, "PLGPIO12"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(13, "PLGPIO13"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(14, "PLGPIO14"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(15, "PLGPIO15"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(16, "PLGPIO16"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(17, "PLGPIO17"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(18, "PLGPIO18"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(19, "PLGPIO19"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(20, "PLGPIO20"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(21, "PLGPIO21"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(22, "PLGPIO22"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(23, "PLGPIO23"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(24, "PLGPIO24"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(25, "PLGPIO25"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(26, "PLGPIO26"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(27, "PLGPIO27"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(28, "PLGPIO28"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(29, "PLGPIO29"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(30, "PLGPIO30"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(31, "PLGPIO31"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(32, "PLGPIO32"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(33, "PLGPIO33"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(34, "PLGPIO34"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(35, "PLGPIO35"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(36, "PLGPIO36"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(37, "PLGPIO37"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(38, "PLGPIO38"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(39, "PLGPIO39"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(40, "PLGPIO40"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(41, "PLGPIO41"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(42, "PLGPIO42"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(43, "PLGPIO43"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(44, "PLGPIO44"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(45, "PLGPIO45"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(46, "PLGPIO46"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(47, "PLGPIO47"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(48, "PLGPIO48"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(49, "PLGPIO49"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(50, "PLGPIO50"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(51, "PLGPIO51"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(52, "PLGPIO52"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(53, "PLGPIO53"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(54, "PLGPIO54"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(55, "PLGPIO55"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(56, "PLGPIO56"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(57, "PLGPIO57"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(58, "PLGPIO58"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(59, "PLGPIO59"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(60, "PLGPIO60"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(61, "PLGPIO61"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(62, "PLGPIO62"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(63, "PLGPIO63"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(64, "PLGPIO64"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(65, "PLGPIO65"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(66, "PLGPIO66"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(67, "PLGPIO67"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(68, "PLGPIO68"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(69, "PLGPIO69"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(70, "PLGPIO70"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(71, "PLGPIO71"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(72, "PLGPIO72"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(73, "PLGPIO73"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(74, "PLGPIO74"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(75, "PLGPIO75"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(76, "PLGPIO76"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(77, "PLGPIO77"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(78, "PLGPIO78"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(79, "PLGPIO79"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(80, "PLGPIO80"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(81, "PLGPIO81"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(82, "PLGPIO82"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(83, "PLGPIO83"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(84, "PLGPIO84"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(85, "PLGPIO85"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(86, "PLGPIO86"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(87, "PLGPIO87"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(88, "PLGPIO88"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(89, "PLGPIO89"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(90, "PLGPIO90"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(91, "PLGPIO91"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(92, "PLGPIO92"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(93, "PLGPIO93"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(94, "PLGPIO94"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(95, "PLGPIO95"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(96, "PLGPIO96"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(97, "PLGPIO97"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(98, "PLGPIO98"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(99, "PLGPIO99"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(100, "PLGPIO100"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(101, "PLGPIO101")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SPEAR_PIN_102_TO_245 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(102, "PLGPIO102"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(103, "PLGPIO103"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(104, "PLGPIO104"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(105, "PLGPIO105"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(106, "PLGPIO106"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(107, "PLGPIO107"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(108, "PLGPIO108"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(109, "PLGPIO109"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(110, "PLGPIO110"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(111, "PLGPIO111"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(112, "PLGPIO112"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(113, "PLGPIO113"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(114, "PLGPIO114"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(115, "PLGPIO115"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(116, "PLGPIO116"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(117, "PLGPIO117"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(118, "PLGPIO118"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(119, "PLGPIO119"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(120, "PLGPIO120"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(121, "PLGPIO121"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(122, "PLGPIO122"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(123, "PLGPIO123"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(124, "PLGPIO124"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(125, "PLGPIO125"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(126, "PLGPIO126"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(127, "PLGPIO127"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(128, "PLGPIO128"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(129, "PLGPIO129"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(130, "PLGPIO130"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(131, "PLGPIO131"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(132, "PLGPIO132"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(133, "PLGPIO133"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(134, "PLGPIO134"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(135, "PLGPIO135"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(136, "PLGPIO136"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(137, "PLGPIO137"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(138, "PLGPIO138"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(139, "PLGPIO139"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(140, "PLGPIO140"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(141, "PLGPIO141"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(142, "PLGPIO142"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(143, "PLGPIO143"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(144, "PLGPIO144"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(145, "PLGPIO145"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(146, "PLGPIO146"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(147, "PLGPIO147"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(148, "PLGPIO148"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(149, "PLGPIO149"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(150, "PLGPIO150"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(151, "PLGPIO151"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(152, "PLGPIO152"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(153, "PLGPIO153"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(154, "PLGPIO154"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(155, "PLGPIO155"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(156, "PLGPIO156"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(157, "PLGPIO157"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(158, "PLGPIO158"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(159, "PLGPIO159"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(160, "PLGPIO160"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(161, "PLGPIO161"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(162, "PLGPIO162"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(163, "PLGPIO163"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(164, "PLGPIO164"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(165, "PLGPIO165"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(166, "PLGPIO166"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(167, "PLGPIO167"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(168, "PLGPIO168"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(169, "PLGPIO169"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(170, "PLGPIO170"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(171, "PLGPIO171"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(172, "PLGPIO172"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(173, "PLGPIO173"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(174, "PLGPIO174"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(175, "PLGPIO175"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(176, "PLGPIO176"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(177, "PLGPIO177"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(178, "PLGPIO178"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(179, "PLGPIO179"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(180, "PLGPIO180"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(181, "PLGPIO181"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(182, "PLGPIO182"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(183, "PLGPIO183"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(184, "PLGPIO184"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(185, "PLGPIO185"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(186, "PLGPIO186"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(187, "PLGPIO187"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(188, "PLGPIO188"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(189, "PLGPIO189"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(190, "PLGPIO190"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(191, "PLGPIO191"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(192, "PLGPIO192"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(193, "PLGPIO193"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(194, "PLGPIO194"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(195, "PLGPIO195"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(196, "PLGPIO196"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(197, "PLGPIO197"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(198, "PLGPIO198"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(199, "PLGPIO199"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(200, "PLGPIO200"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(201, "PLGPIO201"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(202, "PLGPIO202"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(203, "PLGPIO203"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(204, "PLGPIO204"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(205, "PLGPIO205"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(206, "PLGPIO206"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(207, "PLGPIO207"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(208, "PLGPIO208"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(209, "PLGPIO209"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(210, "PLGPIO210"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(211, "PLGPIO211"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(212, "PLGPIO212"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(213, "PLGPIO213"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(214, "PLGPIO214"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(215, "PLGPIO215"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(216, "PLGPIO216"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(217, "PLGPIO217"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(218, "PLGPIO218"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(219, "PLGPIO219"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(220, "PLGPIO220"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(221, "PLGPIO221"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(222, "PLGPIO222"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(223, "PLGPIO223"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(224, "PLGPIO224"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(225, "PLGPIO225"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(226, "PLGPIO226"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(227, "PLGPIO227"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(228, "PLGPIO228"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(229, "PLGPIO229"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(230, "PLGPIO230"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(231, "PLGPIO231"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(232, "PLGPIO232"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(233, "PLGPIO233"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(234, "PLGPIO234"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(235, "PLGPIO235"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(236, "PLGPIO236"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(237, "PLGPIO237"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(238, "PLGPIO238"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(239, "PLGPIO239"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(240, "PLGPIO240"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(241, "PLGPIO241"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(242, "PLGPIO242"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(243, "PLGPIO243"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(244, "PLGPIO244"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(245, "PLGPIO245")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #endif /* __PINMUX_SPEAR_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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