Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Driver for the ST Microelectronics SPEAr pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Viresh Kumar <vireshk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Inspired from:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * - U300 Pinctl drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * - Tegra Pinctl drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include "pinctrl-spear.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DRIVER_NAME "spear-pinmux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static void muxregs_endisable(struct spear_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 		struct spear_muxreg *muxregs, u8 count, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct spear_muxreg *muxreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 val, temp, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	for (j = 0; j < count; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		muxreg = &muxregs[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		val = pmx_readl(pmx, muxreg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 		val &= ~muxreg->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			temp = muxreg->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			temp = ~muxreg->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		val |= muxreg->mask & temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		pmx_writel(pmx, val, muxreg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int set_mode(struct spear_pmx *pmx, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct spear_pmx_mode *pmx_mode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	for (i = 0; i < pmx->machdata->npmx_modes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			pmx_mode = pmx->machdata->pmx_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (!pmx_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	val = pmx_readl(pmx, pmx_mode->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	val &= ~pmx_mode->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	val |= pmx_mode->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	pmx_writel(pmx, val, pmx_mode->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	pmx->machdata->mode = pmx_mode->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			pmx_mode->name ? pmx_mode->name : "no_name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			pmx_mode->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) void pmx_init_gpio_pingroup_addr(struct spear_gpio_pingroup *gpio_pingroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				 unsigned count, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		for (j = 0; j < gpio_pingroup[i].nmuxregs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			gpio_pingroup[i].muxregs[j].reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) void pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct spear_pingroup *pgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct spear_modemux *modemux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	int i, j, group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	for (group = 0; group < machdata->ngroups; group++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		pgroup = machdata->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		for (i = 0; i < pgroup->nmodemuxs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			modemux = &pgroup->modemuxs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			for (j = 0; j < modemux->nmuxregs; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				if (modemux->muxregs[j].reg == 0xFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 					modemux->muxregs[j].reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return pmx->machdata->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	return pmx->machdata->groups[group]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		unsigned group, const unsigned **pins, unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	*pins = pmx->machdata->groups[group]->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	*num_pins = pmx->machdata->groups[group]->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		struct seq_file *s, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	seq_printf(s, " " DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 					struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 					unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	const char *function, *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int ret, index = 0, count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	/* calculate number of maps required */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		ret = of_property_read_string(np, "st,function", &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		ret = of_property_count_strings(np, "st,pins");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		count += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	if (!count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		dev_err(pmx->dev, "No child nodes passed via DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	*map = kcalloc(count, sizeof(**map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	if (!*map)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	for_each_child_of_node(np_config, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		of_property_read_string(np, "st,function", &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		of_property_for_each_string(np, "st,pins", prop, group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			(*map)[index].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			(*map)[index].data.mux.group = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			(*map)[index].data.mux.function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	*num_maps = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				      struct pinctrl_map *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				      unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct pinctrl_ops spear_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	.get_groups_count = spear_pinctrl_get_groups_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	.get_group_name = spear_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.get_group_pins = spear_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.pin_dbg_show = spear_pinctrl_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.dt_node_to_map = spear_pinctrl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.dt_free_map = spear_pinctrl_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return pmx->machdata->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	return pmx->machdata->functions[function]->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		unsigned function, const char *const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		unsigned * const ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	*groups = pmx->machdata->functions[function]->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	*ngroups = pmx->machdata->functions[function]->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		unsigned function, unsigned group, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	const struct spear_pingroup *pgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	const struct spear_modemux *modemux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	pgroup = pmx->machdata->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	for (i = 0; i < pgroup->nmodemuxs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		modemux = &pgroup->modemuxs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		/* SoC have any modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		if (pmx->machdata->modes_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 			if (!(pmx->machdata->mode & modemux->modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		muxregs_endisable(pmx, modemux->muxregs, modemux->nmuxregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		dev_err(pmx->dev, "pinmux group: %s not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				pgroup->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static int spear_pinctrl_set_mux(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return spear_pinctrl_endisable(pctldev, function, group, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* gpio with pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static struct spear_gpio_pingroup *get_gpio_pingroup(struct spear_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	struct spear_gpio_pingroup *gpio_pingroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	if (!pmx->machdata->gpio_pingroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	for (i = 0; i < pmx->machdata->ngpio_pingroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		gpio_pingroup = &pmx->machdata->gpio_pingroups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		for (j = 0; j < gpio_pingroup->npins; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			if (gpio_pingroup->pins[j] == pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				return gpio_pingroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static int gpio_request_endisable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		struct pinctrl_gpio_range *range, unsigned offset, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	struct spear_pinctrl_machdata *machdata = pmx->machdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct spear_gpio_pingroup *gpio_pingroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	 * Some SoC have configuration options applicable to group of pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	 * rather than a single pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	gpio_pingroup = get_gpio_pingroup(pmx, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (gpio_pingroup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		muxregs_endisable(pmx, gpio_pingroup->muxregs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				gpio_pingroup->nmuxregs, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	 * SoC may need some extra configurations, or configurations for single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	 * pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	if (machdata->gpio_request_endisable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		machdata->gpio_request_endisable(pmx, offset, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		struct pinctrl_gpio_range *range, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	return gpio_request_endisable(pctldev, range, offset, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		struct pinctrl_gpio_range *range, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	gpio_request_endisable(pctldev, range, offset, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct pinmux_ops spear_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.get_functions_count = spear_pinctrl_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.get_function_name = spear_pinctrl_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.get_function_groups = spear_pinctrl_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.set_mux = spear_pinctrl_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.gpio_request_enable = gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.gpio_disable_free = gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static struct pinctrl_desc spear_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.pctlops = &spear_pinctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	.pmxops = &spear_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int spear_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			struct spear_pinctrl_machdata *machdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	struct spear_pmx *pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	if (!machdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	if (!pmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	pmx->vbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	if (IS_ERR(pmx->vbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		return PTR_ERR(pmx->vbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	pmx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	pmx->machdata = machdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/* configure mode, if supported by SoC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (machdata->modes_supported) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		int mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		if (of_property_read_u32(np, "st,pinmux-mode", &mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			dev_err(&pdev->dev, "OF: pinmux mode not passed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		if (set_mode(pmx, mode)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 			dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 					mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	platform_set_drvdata(pdev, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	spear_pinctrl_desc.pins = machdata->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	spear_pinctrl_desc.npins = machdata->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	pmx->pctl = devm_pinctrl_register(&pdev->dev, &spear_pinctrl_desc, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (IS_ERR(pmx->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		return PTR_ERR(pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }