^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * SPEAr platform PLGPIO driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 ST Microelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Viresh Kumar <viresh.kumar@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * License version 2. This program is licensed "as is" without any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * warranty of any kind, whether express or implied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_GPIO_PER_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PIN_OFFSET(pin) (pin % MAX_GPIO_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_OFFSET(base, reg, pin) (base + reg + (pin / MAX_GPIO_PER_REG) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * sizeof(int *))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * plgpio pins in all machines are not one to one mapped, bitwise with registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * bits. These set of macros define register masks for which below functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * (pin_to_offset and offset_to_pin) are required to be called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PTO_ENB_REG 0x001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PTO_WDATA_REG 0x002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PTO_DIR_REG 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PTO_IE_REG 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PTO_RDATA_REG 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PTO_MIS_REG 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct plgpio_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 enb; /* enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 wdata; /* write data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 dir; /* direction set register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 rdata; /* read data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 ie; /* interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 mis; /* mask interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 eit; /* edge interrupt type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * struct plgpio: plgpio driver specific structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * lock: lock for guarding gpio registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * base: base address of plgpio block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * chip: gpio framework specific chip information structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * p2o: function ptr for pin to offset conversion. This is required only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * machines where mapping b/w pin and offset is not 1-to-1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * o2p: function ptr for offset to pin conversion. This is required only for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * machines where mapping b/w pin and offset is not 1-to-1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * p2o_regs: mask of registers for which p2o and o2p are applicable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * regs: register offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * csave_regs: context save registers for standby/sleep/hibernate cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct plgpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int (*p2o)(int pin); /* pin_to_offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int (*o2p)(int offset); /* offset_to_pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 p2o_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct plgpio_regs regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct plgpio_regs *csave_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* register manipulation inline functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline u32 is_plgpio_set(void __iomem *base, u32 pin, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 offset = PIN_OFFSET(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void __iomem *reg_off = REG_OFFSET(base, reg, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 val = readl_relaxed(reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return !!(val & (1 << offset));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static inline void plgpio_reg_set(void __iomem *base, u32 pin, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 offset = PIN_OFFSET(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void __iomem *reg_off = REG_OFFSET(base, reg, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 val = readl_relaxed(reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writel_relaxed(val | (1 << offset), reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static inline void plgpio_reg_reset(void __iomem *base, u32 pin, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 offset = PIN_OFFSET(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) void __iomem *reg_off = REG_OFFSET(base, reg, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 val = readl_relaxed(reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writel_relaxed(val & ~(1 << offset), reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* gpio framework specific routines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int plgpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct plgpio *plgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) if (plgpio->p2o && (plgpio->p2o_regs & PTO_DIR_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spin_lock_irqsave(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) plgpio_reg_set(plgpio->base, offset, plgpio->regs.dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) spin_unlock_irqrestore(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int plgpio_direction_output(struct gpio_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct plgpio *plgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned dir_offset = offset, wdata_offset = offset, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (plgpio->p2o && (plgpio->p2o_regs & (PTO_DIR_REG | PTO_WDATA_REG))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tmp = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (tmp == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (plgpio->p2o_regs & PTO_DIR_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dir_offset = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (plgpio->p2o_regs & PTO_WDATA_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) wdata_offset = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) spin_lock_irqsave(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) plgpio_reg_set(plgpio->base, wdata_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) plgpio->regs.wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) plgpio_reg_reset(plgpio->base, wdata_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) plgpio->regs.wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) plgpio_reg_reset(plgpio->base, dir_offset, plgpio->regs.dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) spin_unlock_irqrestore(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int plgpio_get_value(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct plgpio *plgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (offset >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (plgpio->p2o && (plgpio->p2o_regs & PTO_RDATA_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return is_plgpio_set(plgpio->base, offset, plgpio->regs.rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static void plgpio_set_value(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct plgpio *plgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (offset >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (plgpio->p2o && (plgpio->p2o_regs & PTO_WDATA_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) plgpio_reg_set(plgpio->base, offset, plgpio->regs.wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) plgpio_reg_reset(plgpio->base, offset, plgpio->regs.wdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int plgpio_request(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct plgpio *plgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int gpio = chip->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (offset >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = pinctrl_gpio_request(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (!IS_ERR(plgpio->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = clk_enable(plgpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto err0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (plgpio->regs.enb == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * put gpio in IN mode before enabling it. This make enabling gpio safe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ret = plgpio_direction_input(chip, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (offset == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) spin_lock_irqsave(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) plgpio_reg_set(plgpio->base, offset, plgpio->regs.enb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) spin_unlock_irqrestore(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (!IS_ERR(plgpio->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) clk_disable(plgpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) err0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) pinctrl_gpio_free(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static void plgpio_free(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct plgpio *plgpio = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int gpio = chip->base + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (offset >= chip->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (plgpio->regs.enb == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (plgpio->p2o && (plgpio->p2o_regs & PTO_ENB_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) spin_lock_irqsave(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) plgpio_reg_reset(plgpio->base, offset, plgpio->regs.enb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spin_unlock_irqrestore(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (!IS_ERR(plgpio->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) clk_disable(plgpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pinctrl_gpio_free(gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* PLGPIO IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static void plgpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct plgpio *plgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) spin_lock_irqsave(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) plgpio_reg_set(plgpio->base, offset, plgpio->regs.ie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) spin_unlock_irqrestore(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static void plgpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct plgpio *plgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* get correct offset for "offset" pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (plgpio->p2o && (plgpio->p2o_regs & PTO_IE_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) offset = plgpio->p2o(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (offset == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) spin_lock_irqsave(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) plgpio_reg_reset(plgpio->base, offset, plgpio->regs.ie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_unlock_irqrestore(&plgpio->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int plgpio_irq_set_type(struct irq_data *d, unsigned trigger)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct plgpio *plgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int offset = d->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void __iomem *reg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int supported_type = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (offset >= plgpio->chip.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (plgpio->regs.eit == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) supported_type = IRQ_TYPE_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) supported_type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (!(trigger & supported_type))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (plgpio->regs.eit == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) reg_off = REG_OFFSET(plgpio->base, plgpio->regs.eit, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) val = readl_relaxed(reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) offset = PIN_OFFSET(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (trigger & IRQ_TYPE_EDGE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) writel_relaxed(val | (1 << offset), reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) writel_relaxed(val & ~(1 << offset), reg_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct irq_chip plgpio_irqchip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .name = "PLGPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .irq_enable = plgpio_irq_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .irq_disable = plgpio_irq_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .irq_set_type = plgpio_irq_set_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void plgpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct plgpio *plgpio = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct irq_chip *irqchip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int regs_count, count, pin, offset, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) unsigned long pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) count = plgpio->chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) regs_count = DIV_ROUND_UP(count, MAX_GPIO_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) chained_irq_enter(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* check all plgpio MIS registers for a possible interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) for (; i < regs_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pending = readl_relaxed(plgpio->base + plgpio->regs.mis +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i * sizeof(int *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (!pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* clear interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) writel_relaxed(~pending, plgpio->base + plgpio->regs.mis +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) i * sizeof(int *));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * clear extra bits in last register having gpios < MAX/REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * ex: Suppose there are max 102 plgpios. then last register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * must have only (102 - MAX_GPIO_PER_REG * 3) = 6 relevant bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * so, we must not take other 28 bits into consideration for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * checking interrupt. so clear those bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) count = count - i * MAX_GPIO_PER_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (count < MAX_GPIO_PER_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) pending &= (1 << count) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for_each_set_bit(offset, &pending, MAX_GPIO_PER_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* get correct pin for "offset" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (plgpio->o2p && (plgpio->p2o_regs & PTO_MIS_REG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) pin = plgpio->o2p(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (pin == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pin = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* get correct irq line number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pin = i * MAX_GPIO_PER_REG + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) generic_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) irq_find_mapping(gc->irq.domain, pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) chained_irq_exit(irqchip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * pin to offset and offset to pin converter functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * In spear310 there is inconsistency among bit positions in plgpio regiseters,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * for different plgpio pins. For example: for pin 27, bit offset is 23, pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * 28-33 are not supported, pin 95 has offset bit 95, bit 100 has offset bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int spear310_p2o(int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int offset = pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (pin <= 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) offset += 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) else if (pin <= 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) offset = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) else if (pin <= 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) offset -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else if (pin <= 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) offset = 101 - pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) offset = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int spear310_o2p(int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (offset <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return 101 - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else if (offset <= 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return offset - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return offset + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static int plgpio_probe_dt(struct platform_device *pdev, struct plgpio *plgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (of_machine_is_compatible("st,spear310")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) plgpio->p2o = spear310_p2o;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) plgpio->o2p = spear310_o2p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) plgpio->p2o_regs = PTO_WDATA_REG | PTO_DIR_REG | PTO_IE_REG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PTO_RDATA_REG | PTO_MIS_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!of_property_read_u32(np, "st-plgpio,ngpio", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) plgpio->chip.ngpio = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) dev_err(&pdev->dev, "DT: Invalid ngpio field\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (!of_property_read_u32(np, "st-plgpio,enb-reg", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) plgpio->regs.enb = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) plgpio->regs.enb = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!of_property_read_u32(np, "st-plgpio,wdata-reg", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) plgpio->regs.wdata = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(&pdev->dev, "DT: Invalid wdata reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (!of_property_read_u32(np, "st-plgpio,dir-reg", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) plgpio->regs.dir = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(&pdev->dev, "DT: Invalid dir reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (!of_property_read_u32(np, "st-plgpio,ie-reg", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) plgpio->regs.ie = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) dev_err(&pdev->dev, "DT: Invalid ie reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!of_property_read_u32(np, "st-plgpio,rdata-reg", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) plgpio->regs.rdata = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) dev_err(&pdev->dev, "DT: Invalid rdata reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (!of_property_read_u32(np, "st-plgpio,mis-reg", &val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) plgpio->regs.mis = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev_err(&pdev->dev, "DT: Invalid mis reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) goto end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!of_property_read_u32(np, "st-plgpio,eit-reg", &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) plgpio->regs.eit = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) plgpio->regs.eit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int plgpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct plgpio *plgpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!plgpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) plgpio->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (IS_ERR(plgpio->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return PTR_ERR(plgpio->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = plgpio_probe_dt(pdev, plgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(&pdev->dev, "DT probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) plgpio->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (IS_ERR(plgpio->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) plgpio->csave_regs = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) sizeof(*plgpio->csave_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!plgpio->csave_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) platform_set_drvdata(pdev, plgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) spin_lock_init(&plgpio->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) plgpio->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) plgpio->chip.request = plgpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) plgpio->chip.free = plgpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) plgpio->chip.direction_input = plgpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) plgpio->chip.direction_output = plgpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) plgpio->chip.get = plgpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) plgpio->chip.set = plgpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) plgpio->chip.label = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) plgpio->chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) plgpio->chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) plgpio->chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (!IS_ERR(plgpio->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = clk_prepare(plgpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev_err(&pdev->dev, "clk prepare failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (irq > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) girq = &plgpio->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) girq->chip = &plgpio_irqchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) girq->parent_handler = plgpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) girq->parents = devm_kcalloc(&pdev->dev, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) girq->parents[0] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) girq->handler = handle_simple_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dev_info(&pdev->dev, "PLGPIO registering with IRQs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_info(&pdev->dev, "PLGPIO registering without IRQs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = gpiochip_add_data(&plgpio->chip, plgpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dev_err(&pdev->dev, "unable to add gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) goto unprepare_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) unprepare_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (!IS_ERR(plgpio->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) clk_unprepare(plgpio->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int plgpio_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct plgpio *plgpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) void __iomem *off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) for (i = 0; i < reg_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) off = plgpio->base + i * sizeof(int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (plgpio->regs.enb != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) plgpio->csave_regs[i].enb =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) readl_relaxed(plgpio->regs.enb + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (plgpio->regs.eit != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) plgpio->csave_regs[i].eit =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) readl_relaxed(plgpio->regs.eit + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) plgpio->csave_regs[i].wdata = readl_relaxed(plgpio->regs.wdata +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) plgpio->csave_regs[i].dir = readl_relaxed(plgpio->regs.dir +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) plgpio->csave_regs[i].ie = readl_relaxed(plgpio->regs.ie + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * This is used to correct the values in end registers. End registers contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * extra bits that might be used for other purpose in platform. So, we shouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * overwrite these bits. This macro, reads given register again, preserves other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * bit values (non-plgpio bits), and retain captured value (plgpio bits).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define plgpio_prepare_reg(__reg, _off, _mask, _tmp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) _tmp = readl_relaxed(plgpio->regs.__reg + _off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) _tmp &= ~_mask; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) plgpio->csave_regs[i].__reg = \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) _tmp | (plgpio->csave_regs[i].__reg & _mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int plgpio_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct plgpio *plgpio = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int i, reg_count = DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) void __iomem *off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 mask, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) for (i = 0; i < reg_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) off = plgpio->base + i * sizeof(int *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (i == reg_count - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) mask = (1 << (plgpio->chip.ngpio - i *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MAX_GPIO_PER_REG)) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (plgpio->regs.enb != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) plgpio_prepare_reg(enb, off, mask, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (plgpio->regs.eit != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) plgpio_prepare_reg(eit, off, mask, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) plgpio_prepare_reg(wdata, off, mask, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) plgpio_prepare_reg(dir, off, mask, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) plgpio_prepare_reg(ie, off, mask, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) writel_relaxed(plgpio->csave_regs[i].wdata, plgpio->regs.wdata +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) writel_relaxed(plgpio->csave_regs[i].dir, plgpio->regs.dir +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (plgpio->regs.eit != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) writel_relaxed(plgpio->csave_regs[i].eit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) plgpio->regs.eit + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) writel_relaxed(plgpio->csave_regs[i].ie, plgpio->regs.ie + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (plgpio->regs.enb != -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel_relaxed(plgpio->csave_regs[i].enb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) plgpio->regs.enb + off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static SIMPLE_DEV_PM_OPS(plgpio_dev_pm_ops, plgpio_suspend, plgpio_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const struct of_device_id plgpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { .compatible = "st,spear-plgpio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static struct platform_driver plgpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .probe = plgpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .name = "spear-plgpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .pm = &plgpio_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .of_match_table = plgpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int __init plgpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return platform_driver_register(&plgpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) subsys_initcall(plgpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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