^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pinctrl pads, groups, functions for CSR SiRFprimaII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pinctrl-sirf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * pad list for the pinmux subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * refer to CS-131858-DC-6A.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) static const struct pinctrl_pin_desc sirfsoc_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PINCTRL_PIN(0, "gpio0-0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PINCTRL_PIN(1, "gpio0-1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PINCTRL_PIN(2, "gpio0-2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PINCTRL_PIN(3, "gpio0-3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PINCTRL_PIN(4, "pwm0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PINCTRL_PIN(5, "pwm1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PINCTRL_PIN(6, "pwm2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PINCTRL_PIN(7, "pwm3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PINCTRL_PIN(8, "warm_rst_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PINCTRL_PIN(9, "odo_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PINCTRL_PIN(10, "odo_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PINCTRL_PIN(11, "dr_dir"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PINCTRL_PIN(12, "viprom_fa"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PINCTRL_PIN(13, "scl_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PINCTRL_PIN(14, "ntrst"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINCTRL_PIN(15, "sda_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PINCTRL_PIN(16, "x_ldd[16]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PINCTRL_PIN(17, "x_ldd[17]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINCTRL_PIN(18, "x_ldd[18]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINCTRL_PIN(19, "x_ldd[19]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINCTRL_PIN(20, "x_ldd[20]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINCTRL_PIN(21, "x_ldd[21]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCTRL_PIN(22, "x_ldd[22]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINCTRL_PIN(23, "x_ldd[23], lcdrom_frdy"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINCTRL_PIN(24, "gps_sgn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINCTRL_PIN(25, "gps_mag"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINCTRL_PIN(26, "gps_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINCTRL_PIN(27, "sd_cd_b_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(28, "sd_vcc_on_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(29, "sd_wp_b_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(30, "sd_clk_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(31, "sd_cmd_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(32, "x_sd_dat_3[0]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(33, "x_sd_dat_3[1]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(34, "x_sd_dat_3[2]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(35, "x_sd_dat_3[3]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(36, "x_sd_clk_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(37, "x_sd_cmd_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(38, "x_sd_dat_4[0]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(39, "x_sd_dat_4[1]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(40, "x_sd_dat_4[2]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(41, "x_sd_dat_4[3]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(42, "x_cko_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(43, "x_ac97_bit_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(44, "x_ac97_dout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(45, "x_ac97_din"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(46, "x_ac97_sync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(47, "x_txd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(48, "x_txd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(49, "x_rxd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(50, "x_rxd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(51, "x_usclk_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(52, "x_utxd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(53, "x_urxd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(54, "x_utfs_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(55, "x_urfs_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(56, "x_usclk_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(57, "x_utxd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(58, "x_urxd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(59, "x_utfs_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(60, "x_urfs_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(61, "x_usclk_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(62, "x_utxd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(63, "x_urxd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(64, "x_utfs_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(65, "x_urfs_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(66, "x_df_we_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(67, "x_df_re_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(68, "x_txd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(69, "x_rxd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(78, "x_cko_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(79, "x_vip_pxd[7]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(80, "x_vip_pxd[6]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(81, "x_vip_pxd[5]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(82, "x_vip_pxd[4]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(83, "x_vip_pxd[3]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(84, "x_vip_pxd[2]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(85, "x_vip_pxd[1]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(86, "x_vip_pxd[0]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(87, "x_vip_vsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(88, "x_vip_hsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(89, "x_vip_pxclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(90, "x_sda_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(91, "x_scl_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(92, "x_df_ry_by"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(93, "x_df_cs_b[1]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(94, "x_df_cs_b[0]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(95, "x_l_pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(96, "x_l_lck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(97, "x_l_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(98, "x_l_de"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(99, "x_ldd[0]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(100, "x_ldd[1]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(101, "x_ldd[2]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(102, "x_ldd[3]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(103, "x_ldd[4]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(104, "x_ldd[5]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(105, "x_ldd[6]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(106, "x_ldd[7]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(107, "x_ldd[8]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(108, "x_ldd[9]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(109, "x_ldd[10]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(110, "x_ldd[11]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(111, "x_ldd[12]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(112, "x_ldd[13]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(113, "x_ldd[14]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(114, "x_ldd[15]"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(115, "x_usb1_dp"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(116, "x_usb1_dn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .group = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) BIT(17) | BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .mask = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static const struct sirfsoc_padmux lcd_16bits_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .muxmask = lcd_16bits_sirfsoc_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .funcmask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const unsigned lcd_16bits_pins[] = { 95, 96, 97, 98, 99, 100, 101, 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .group = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) BIT(17) | BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .mask = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .mask = BIT(16) | BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const struct sirfsoc_padmux lcd_18bits_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .muxmask = lcd_18bits_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .funcmask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned lcd_18bits_pins[] = { 16, 17, 95, 96, 97, 98, 99, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .group = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) BIT(17) | BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .mask = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .mask = BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) BIT(21) | BIT(22) | BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const struct sirfsoc_padmux lcd_24bits_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .muxmask = lcd_24bits_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .funcmask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned lcd_24bits_pins[] = { 16, 17, 18, 19, 20, 21, 22, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 110, 111, 112, 113, 114 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .group = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(5) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(10) | BIT(11) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) BIT(12) | BIT(13) | BIT(14) | BIT(15) | BIT(16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) BIT(17) | BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .mask = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .mask = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct sirfsoc_padmux lcdrom_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .muxmask = lcdrom_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .funcmask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .funcval = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const unsigned lcdrom_pins[] = { 23, 95, 96, 97, 98, 99, 100, 101, 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct sirfsoc_muxmask uart0_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .mask = BIT(4) | BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .mask = BIT(23) | BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const struct sirfsoc_padmux uart0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .muxmask = uart0_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .funcmask = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .funcval = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const unsigned uart0_pins[] = { 55, 60, 68, 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct sirfsoc_muxmask uart0_nostreamctrl_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .mask = BIT(4) | BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const struct sirfsoc_padmux uart0_nostreamctrl_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .muxmask_counts = ARRAY_SIZE(uart0_nostreamctrl_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .muxmask = uart0_nostreamctrl_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const unsigned uart0_nostreamctrl_pins[] = { 68, 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct sirfsoc_muxmask uart1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .mask = BIT(15) | BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct sirfsoc_padmux uart1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .muxmask_counts = ARRAY_SIZE(uart1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .muxmask = uart1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const unsigned uart1_pins[] = { 47, 49 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct sirfsoc_muxmask uart2_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .mask = BIT(16) | BIT(18) | BIT(24) | BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct sirfsoc_padmux uart2_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .muxmask = uart2_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .funcmask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .funcval = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const unsigned uart2_pins[] = { 48, 50, 56, 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct sirfsoc_muxmask uart2_nostreamctrl_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .mask = BIT(16) | BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const struct sirfsoc_padmux uart2_nostreamctrl_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .muxmask_counts = ARRAY_SIZE(uart2_nostreamctrl_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .muxmask = uart2_nostreamctrl_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned uart2_nostreamctrl_pins[] = { 48, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .mask = BIT(30) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const struct sirfsoc_padmux sdmmc3_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .muxmask = sdmmc3_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .funcmask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const unsigned sdmmc3_pins[] = { 30, 31, 32, 33, 34, 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct sirfsoc_muxmask spi0_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mask = BIT(0) | BIT(1) | BIT(2) | BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct sirfsoc_padmux spi0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .muxmask = spi0_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .funcmask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .funcval = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned spi0_pins[] = { 32, 33, 34, 35 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct sirfsoc_muxmask sdmmc4_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .mask = BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct sirfsoc_padmux sdmmc4_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .muxmask_counts = ARRAY_SIZE(sdmmc4_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .muxmask = sdmmc4_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const unsigned sdmmc4_pins[] = { 36, 37, 38, 39, 40, 41 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const struct sirfsoc_muxmask cko1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct sirfsoc_padmux cko1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .muxmask = cko1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .funcmask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const unsigned cko1_pins[] = { 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const struct sirfsoc_muxmask i2s_mclk_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .mask = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct sirfsoc_padmux i2s_mclk_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .muxmask_counts = ARRAY_SIZE(i2s_mclk_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .muxmask = i2s_mclk_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .funcmask = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .funcval = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const unsigned i2s_mclk_pins[] = { 42 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const struct sirfsoc_muxmask i2s_ext_clk_input_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mask = BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct sirfsoc_padmux i2s_ext_clk_input_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .muxmask_counts = ARRAY_SIZE(i2s_ext_clk_input_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .muxmask = i2s_ext_clk_input_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .funcmask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .funcval = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const unsigned i2s_ext_clk_input_pins[] = { 51 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const struct sirfsoc_muxmask i2s_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct sirfsoc_padmux i2s_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .muxmask = i2s_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const unsigned i2s_pins[] = { 43, 44, 45, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .mask = BIT(11) | BIT(12) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct sirfsoc_padmux i2s_no_din_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .muxmask = i2s_no_din_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const unsigned i2s_no_din_pins[] = { 43, 44, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) | BIT(23) | BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static const struct sirfsoc_padmux i2s_6chn_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .muxmask = i2s_6chn_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .funcmask = BIT(1) | BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .funcval = BIT(1) | BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const unsigned i2s_6chn_pins[] = { 43, 44, 45, 46, 55, 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const struct sirfsoc_muxmask ac97_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static const struct sirfsoc_padmux ac97_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .muxmask = ac97_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .funcmask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const unsigned ac97_pins[] = { 43, 44, 45, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const struct sirfsoc_muxmask spi1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .mask = BIT(11) | BIT(12) | BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct sirfsoc_padmux spi1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .muxmask = spi1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .funcmask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .funcval = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const unsigned spi1_pins[] = { 43, 44, 45, 46 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .mask = BIT(27) | BIT(28) | BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) static const struct sirfsoc_padmux sdmmc1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .muxmask = sdmmc1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned sdmmc1_pins[] = { 27, 28, 29 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const struct sirfsoc_muxmask gps_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .mask = BIT(24) | BIT(25) | BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct sirfsoc_padmux gps_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .muxmask_counts = ARRAY_SIZE(gps_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .muxmask = gps_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .funcmask = BIT(12) | BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .funcval = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const unsigned gps_pins[] = { 24, 25, 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .mask = BIT(24) | BIT(25) | BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const struct sirfsoc_padmux sdmmc5_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .muxmask = sdmmc5_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .funcmask = BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .funcval = BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct sirfsoc_muxmask usp0_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct sirfsoc_padmux usp0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .muxmask = usp0_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .muxmask = usp0_only_utfs_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .funcmask = BIT(1) | BIT(2) | BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .muxmask = usp0_only_urfs_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .funcmask = BIT(1) | BIT(2) | BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .mask = BIT(20) | BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .muxmask = usp0_uart_nostreamctrl_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct sirfsoc_muxmask usp1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .mask = BIT(24) | BIT(25) | BIT(26) | BIT(27) | BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct sirfsoc_padmux usp1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .muxmask = usp1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .mask = BIT(25) | BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .muxmask = usp1_uart_nostreamctrl_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const struct sirfsoc_muxmask usp2_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .mask = BIT(29) | BIT(30) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .mask = BIT(0) | BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const struct sirfsoc_padmux usp2_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .muxmask = usp2_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .funcmask = BIT(13) | BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .mask = BIT(30) | BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .muxmask = usp2_uart_nostreamctrl_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const struct sirfsoc_muxmask nand_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .mask = BIT(2) | BIT(3) | BIT(28) | BIT(29) | BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const struct sirfsoc_padmux nand_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .muxmask_counts = ARRAY_SIZE(nand_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .muxmask = nand_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .funcmask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct sirfsoc_padmux sdmmc0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .muxmask_counts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .funcmask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const unsigned sdmmc0_pins[] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .mask = BIT(2) | BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const struct sirfsoc_padmux sdmmc2_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .muxmask = sdmmc2_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .funcmask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .funcval = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const unsigned sdmmc2_pins[] = { 66, 67 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const struct sirfsoc_muxmask cko0_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .mask = BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const struct sirfsoc_padmux cko0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .muxmask_counts = ARRAY_SIZE(cko0_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .muxmask = cko0_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const unsigned cko0_pins[] = { 78 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const struct sirfsoc_muxmask vip_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct sirfsoc_padmux vip_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .muxmask_counts = ARRAY_SIZE(vip_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .muxmask = vip_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .funcmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const unsigned vip_pins[] = { 79, 80, 81, 82, 83, 84, 85, 86, 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 88, 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct sirfsoc_muxmask i2c0_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .mask = BIT(26) | BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const struct sirfsoc_padmux i2c0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .muxmask_counts = ARRAY_SIZE(i2c0_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .muxmask = i2c0_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const unsigned i2c0_pins[] = { 90, 91 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const struct sirfsoc_muxmask i2c1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .mask = BIT(13) | BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const struct sirfsoc_padmux i2c1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .muxmask = i2c1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const unsigned i2c1_pins[] = { 13, 15 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const struct sirfsoc_muxmask viprom_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .group = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .mask = BIT(15) | BIT(16) | BIT(17) | BIT(18) | BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) | BIT(20) | BIT(21) | BIT(22) | BIT(23) | BIT(24) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .mask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static const struct sirfsoc_padmux viprom_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .muxmask = viprom_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .funcmask = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .funcval = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const unsigned viprom_pins[] = { 12, 79, 80, 81, 82, 83, 84, 85, 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) 87, 88, 89 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct sirfsoc_muxmask pwm0_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .mask = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const struct sirfsoc_padmux pwm0_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .muxmask = pwm0_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .funcmask = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const unsigned pwm0_pins[] = { 4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const struct sirfsoc_muxmask pwm1_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .mask = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct sirfsoc_padmux pwm1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .muxmask_counts = ARRAY_SIZE(pwm1_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .muxmask = pwm1_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const unsigned pwm1_pins[] = { 5 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const struct sirfsoc_muxmask pwm2_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .mask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const struct sirfsoc_padmux pwm2_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .muxmask_counts = ARRAY_SIZE(pwm2_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .muxmask = pwm2_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const unsigned pwm2_pins[] = { 6 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const struct sirfsoc_muxmask pwm3_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .mask = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const struct sirfsoc_padmux pwm3_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .muxmask_counts = ARRAY_SIZE(pwm3_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .muxmask = pwm3_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const unsigned pwm3_pins[] = { 7 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) .mask = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const struct sirfsoc_padmux warm_rst_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .muxmask = warm_rst_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const unsigned warm_rst_pins[] = { 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .mask = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .muxmask = usb0_utmi_drvbus_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) .funcmask = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const unsigned usb0_utmi_drvbus_pins[] = { 54 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) .group = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .mask = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .muxmask = usb1_utmi_drvbus_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .ctrlreg = SIRFSOC_RSC_PIN_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .funcmask = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .muxmask_counts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .funcmask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .funcval = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .muxmask_counts = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .funcmask = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .funcval = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .group = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .mask = BIT(9) | BIT(10) | BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const struct sirfsoc_padmux pulse_count_padmux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .muxmask_counts = ARRAY_SIZE(pulse_count_muxmask),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .muxmask = pulse_count_muxmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const unsigned pulse_count_pins[] = { 9, 10, 11 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SIRFSOC_PIN_GROUP("lcd_16bitsgrp", lcd_16bits_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SIRFSOC_PIN_GROUP("lcd_18bitsgrp", lcd_18bits_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) usp0_uart_nostreamctrl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) usp1_uart_nostreamctrl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) usp2_uart_nostreamctrl_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) SIRFSOC_PIN_GROUP("pwm1grp", pwm1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) SIRFSOC_PIN_GROUP("pwm2grp", pwm2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) SIRFSOC_PIN_GROUP("pwm3grp", pwm3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) SIRFSOC_PIN_GROUP("vipgrp", vip_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) SIRFSOC_PIN_GROUP("vipromgrp", viprom_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) SIRFSOC_PIN_GROUP("warm_rstgrp", warm_rst_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) SIRFSOC_PIN_GROUP("cko0grp", cko0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) SIRFSOC_PIN_GROUP("cko1grp", cko1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) SIRFSOC_PIN_GROUP("sdmmc0grp", sdmmc0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) SIRFSOC_PIN_GROUP("sdmmc1grp", sdmmc1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) SIRFSOC_PIN_GROUP("sdmmc2grp", sdmmc2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) SIRFSOC_PIN_GROUP("sdmmc3grp", sdmmc3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SIRFSOC_PIN_GROUP("sdmmc4grp", sdmmc4_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) SIRFSOC_PIN_GROUP("i2smclkgrp", i2s_mclk_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) SIRFSOC_PIN_GROUP("i2s_ext_clk_inputgrp", i2s_ext_clk_input_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SIRFSOC_PIN_GROUP("i2s_6chngrp", i2s_6chn_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) SIRFSOC_PIN_GROUP("nandgrp", nand_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) SIRFSOC_PIN_GROUP("spi0grp", spi0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) SIRFSOC_PIN_GROUP("spi1grp", spi1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) SIRFSOC_PIN_GROUP("gpsgrp", gps_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const char * const lcd_16bitsgrp[] = { "lcd_16bitsgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const char * const lcdromgrp[] = { "lcdromgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const char * const uart0grp[] = { "uart0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const char * const uart1grp[] = { "uart1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const char * const uart2grp[] = { "uart2grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const char * const usp0grp[] = { "usp0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static const char * const usp0_uart_nostreamctrl_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "usp0_uart_nostreamctrl_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const char * const usp1grp[] = { "usp1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const char * const usp1_uart_nostreamctrl_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "usp1_uart_nostreamctrl_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const char * const usp2grp[] = { "usp2grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static const char * const usp2_uart_nostreamctrl_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) "usp2_uart_nostreamctrl_grp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const char * const i2c0grp[] = { "i2c0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static const char * const i2c1grp[] = { "i2c1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const char * const pwm0grp[] = { "pwm0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const char * const pwm1grp[] = { "pwm1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static const char * const pwm2grp[] = { "pwm2grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const char * const pwm3grp[] = { "pwm3grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const char * const vipgrp[] = { "vipgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const char * const vipromgrp[] = { "vipromgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const char * const warm_rstgrp[] = { "warm_rstgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static const char * const cko0grp[] = { "cko0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const char * const cko1grp[] = { "cko1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const char * const sdmmc0grp[] = { "sdmmc0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const char * const sdmmc1grp[] = { "sdmmc1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const char * const sdmmc2grp[] = { "sdmmc2grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const char * const sdmmc3grp[] = { "sdmmc3grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static const char * const sdmmc4grp[] = { "sdmmc4grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static const char * const sdmmc5grp[] = { "sdmmc5grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const char * const
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const char * const pulse_countgrp[] = { "pulse_countgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const char * const i2smclkgrp[] = { "i2smclkgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const char * const i2s_ext_clk_inputgrp[] = { "i2s_ext_clk_inputgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static const char * const i2sgrp[] = { "i2sgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const char * const i2s_6chngrp[] = { "i2s_6chngrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const char * const ac97grp[] = { "ac97grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const char * const nandgrp[] = { "nandgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const char * const spi0grp[] = { "spi0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static const char * const spi1grp[] = { "spi1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const char * const gpsgrp[] = { "gpsgrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) SIRFSOC_PMX_FUNCTION("lcd_16bits", lcd_16bitsgrp, lcd_16bits_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) SIRFSOC_PMX_FUNCTION("lcd_18bits", lcd_18bitsgrp, lcd_18bits_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) SIRFSOC_PMX_FUNCTION("usp0_only_utfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) usp0_only_utfs_grp, usp0_only_utfs_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) SIRFSOC_PMX_FUNCTION("usp0_only_urfs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) usp0_only_urfs_grp, usp0_only_urfs_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) SIRFSOC_PMX_FUNCTION("pwm1", pwm1grp, pwm1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) SIRFSOC_PMX_FUNCTION("pwm2", pwm2grp, pwm2_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) SIRFSOC_PMX_FUNCTION("pwm3", pwm3grp, pwm3_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) SIRFSOC_PMX_FUNCTION("vip", vipgrp, vip_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) SIRFSOC_PMX_FUNCTION("viprom", vipromgrp, viprom_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) SIRFSOC_PMX_FUNCTION("warm_rst", warm_rstgrp, warm_rst_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SIRFSOC_PMX_FUNCTION("cko0", cko0grp, cko0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SIRFSOC_PMX_FUNCTION("cko1", cko1grp, cko1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) SIRFSOC_PMX_FUNCTION("sdmmc0", sdmmc0grp, sdmmc0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) SIRFSOC_PMX_FUNCTION("sdmmc1", sdmmc1grp, sdmmc1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) SIRFSOC_PMX_FUNCTION("sdmmc2", sdmmc2grp, sdmmc2_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SIRFSOC_PMX_FUNCTION("sdmmc3", sdmmc3grp, sdmmc3_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) SIRFSOC_PMX_FUNCTION("sdmmc4", sdmmc4grp, sdmmc4_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) SIRFSOC_PMX_FUNCTION("i2s_mclk", i2smclkgrp, i2s_mclk_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SIRFSOC_PMX_FUNCTION("i2s_ext_clk_input", i2s_ext_clk_inputgrp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) i2s_ext_clk_input_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SIRFSOC_PMX_FUNCTION("i2s_6chn", i2s_6chngrp, i2s_6chn_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SIRFSOC_PMX_FUNCTION("nand", nandgrp, nand_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) SIRFSOC_PMX_FUNCTION("spi0", spi0grp, spi0_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SIRFSOC_PMX_FUNCTION("spi1", spi1grp, spi1_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) SIRFSOC_PMX_FUNCTION("gps", gpsgrp, gps_padmux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct sirfsoc_pinctrl_data prima2_pinctrl_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) (struct pinctrl_pin_desc *)sirfsoc_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ARRAY_SIZE(sirfsoc_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) (struct sirfsoc_pin_group *)sirfsoc_pin_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ARRAY_SIZE(sirfsoc_pin_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) (struct sirfsoc_pmx_func *)sirfsoc_pmx_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ARRAY_SIZE(sirfsoc_pmx_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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