^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pinctrl pads, groups, functions for CSR SiRFatlasVII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * company.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Definition of Pad&Mux Properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define N 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* The Bank contains input-disable regisgers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BANK_DS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Clear Register offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLR_REG(r) ((r) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Definition of multiple function select register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FUNC_CLEAR_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define FUNC_GPIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define FUNC_ANALOGUE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ANA_CLEAR_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* The Atlas7's Pad Type List */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enum altas7_pad_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PAD_T_4WE_PD = 0, /* ZIO_PAD3V_4WE_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PAD_T_4WE_PU, /* ZIO_PAD3V_4WE_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PAD_T_16ST, /* ZIO_PAD3V_SDCLK_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PAD_T_M31_0204_PD, /* PRDW0204SDGZ_M311311_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PAD_T_M31_0204_PU, /* PRDW0204SDGZ_M311311_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PAD_T_M31_0610_PD, /* PRUW0610SDGZ_M311311_PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PAD_T_M31_0610_PU, /* PRUW0610SDGZ_M311311_PU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PAD_T_AD, /* PRDWUWHW08SCDG_HZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Raw value of Driver-Strength Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DS3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DS2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DS1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DS0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DSZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Drive-Strength Intermediate Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DS_NULL -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DS_1BIT_IM_VAL DS0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DS_1BIT_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DS_2BIT_IM_VAL (DS1 | DS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DS_2BIT_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DS_4BIT_IM_VAL (DS3 | DS2 | DS1 | DS0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DS_4BIT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* The Drive-Strength of 4WE Pad DS1 0 CO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DS_4WE_3 (DS1 | DS0) /* 1 1 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DS_4WE_2 (DS1) /* 1 0 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DS_4WE_1 (DS0) /* 0 1 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DS_4WE_0 (DSZ) /* 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* The Drive-Strength of 16st Pad DS3 2 1 0 CO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DS_16ST_15 (DS3 | DS2 | DS1 | DS0) /* 1 1 1 1 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DS_16ST_14 (DS3 | DS2 | DS0) /* 1 1 0 1 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DS_16ST_13 (DS3 | DS2 | DS1) /* 1 1 1 0 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DS_16ST_12 (DS2 | DS1 | DS0) /* 0 1 1 1 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DS_16ST_11 (DS2 | DS0) /* 0 1 0 1 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DS_16ST_10 (DS3 | DS1 | DS0) /* 1 0 1 1 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DS_16ST_9 (DS3 | DS0) /* 1 0 0 1 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DS_16ST_8 (DS1 | DS0) /* 0 0 1 1 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DS_16ST_7 (DS2 | DS1) /* 0 1 1 0 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DS_16ST_6 (DS3 | DS2) /* 1 1 0 0 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DS_16ST_5 (DS2) /* 0 1 0 0 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DS_16ST_4 (DS3 | DS1) /* 1 0 1 0 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DS_16ST_3 (DS1) /* 0 0 1 0 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DS_16ST_2 (DS0) /* 0 0 0 1 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DS_16ST_1 (DSZ) /* 0 0 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DS_16ST_0 (DS3) /* 1 0 0 0 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* The Drive-Strength of M31 Pad DS0 CO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DS_M31_0 (DSZ) /* 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DS_M31_1 (DS0) /* 1 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Raw values of Pull Option Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PUN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define PD BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Definition of Pull Types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PULL_UP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HIGH_HYSTERESIS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HIGH_Z 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PULL_DOWN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PULL_DISABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PULL_ENABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PULL_UNKNOWN -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Pull Options for 4WE Pad PUN PD CO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define P4WE_PULL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define P4WE_PULL_DOWN (PUN | PD) /* 1 1 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define P4WE_HIGH_Z (PUN) /* 1 0 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define P4WE_HIGH_HYSTERESIS (PD) /* 0 1 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define P4WE_PULL_UP (PZ) /* 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Pull Options for 16ST Pad PUN PD CO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define P16ST_PULL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define P16ST_PULL_DOWN (PUN | PD) /* 1 1 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define P16ST_HIGH_Z (PUN) /* 1 0 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define P16ST_PULL_UP (PZ) /* 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Pull Options for M31 Pad PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PM31_PULL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PM31_PULL_ENABLED (PE) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PM31_PULL_DISABLED (PZ) /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Pull Options for A/D Pad PUN PD CO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PANGD_PULL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PANGD_PULL_DOWN (PUN | PD) /* 1 1 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PANGD_HIGH_Z (PUN) /* 1 0 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PANGD_PULL_UP (PZ) /* 0 0 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Definition of Input Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DI_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define DI_DISABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DI_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Definition of Input Disable Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define DIV_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DIV_DISABLE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DIV_ENABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Number of Function input disable registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define NUM_OF_IN_DISABLE_REG 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Offset of Function input disable registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IN_DISABLE_0_REG_SET 0x0A00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IN_DISABLE_0_REG_CLR 0x0A04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IN_DISABLE_1_REG_SET 0x0A08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IN_DISABLE_1_REG_CLR 0x0A0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IN_DISABLE_VAL_0_REG_SET 0x0A80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IN_DISABLE_VAL_0_REG_CLR 0x0A84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IN_DISABLE_VAL_1_REG_SET 0x0A88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IN_DISABLE_VAL_1_REG_CLR 0x0A8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Offset of the SDIO9SEL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SYS2PCI_SDIO9SEL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct dt_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const char *property;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * struct atlas7_pad_conf - Atlas7 Pad Configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @id: The ID of this Pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @type: The type of this Pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @mux_reg: The mux register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * This register contains the mux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @pupd_reg: The pull-up/down register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @drvstr_reg: The drive-strength register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @ad_ctrl_reg: The Analogue/Digital Control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * @mux_bit: The start bit of mux register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @pupd_bit: The start bit of pull-up/down register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @drvstr_bit: The start bit of drive-strength register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @ad_ctrl_bit: The start bit of analogue/digital register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct atlas7_pad_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 mux_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 pupd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 drvstr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 ad_ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* bits in register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 mux_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u8 pupd_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u8 drvstr_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u8 ad_ctrl_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PADCONF(pad, t, mr, pr, dsr, adr, mb, pb, dsb, adb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .id = pad, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .type = t, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .mux_reg = mr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .pupd_reg = pr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .drvstr_reg = dsr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ad_ctrl_reg = adr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .mux_bit = mb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pupd_bit = pb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .drvstr_bit = dsb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .ad_ctrl_bit = adb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * struct atlas7_pad_status - Atlas7 Pad status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct atlas7_pad_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u8 func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u8 dstr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * struct atlas7_pad_mux - Atlas7 mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @bank: The bank of this pad's registers on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @pin : The ID of this Pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @func: The mux func on this Pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @dinput_reg: The Input-Disable register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @dinput_bit: The start bit of Input-Disable register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @dinput_val_reg: The Input-Disable-value register offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * This register is used to set the value of this pad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * if this pad was disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @dinput_val_bit: The start bit of Input-Disable Value register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct atlas7_pad_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 dinput_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 dinput_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 dinput_val_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 dinput_val_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MUX(b, pad, f, dr, db, dvr, dvb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .bank = b, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pin = pad, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .func = f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .dinput_reg = dr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .dinput_bit = db, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dinput_val_reg = dvr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .dinput_val_bit = dvb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct atlas7_grp_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int pad_mux_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) const struct atlas7_pad_mux *pad_mux_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * struct sirfsoc_pin_group - describes a SiRFprimaII pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @name: the name of this specific pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @pins: an array of discrete physical pins used in this group, taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * from the driver-local pin enumeration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @num_pins: the number of pins in this group array, i.e. the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * elements in .pins so we can iterate over that array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct atlas7_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) const unsigned num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GROUP(n, p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .pins = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .num_pins = ARRAY_SIZE(p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct atlas7_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) const unsigned num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) const struct atlas7_grp_mux *grpmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FUNCTION(n, g, m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .groups = g, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .num_groups = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .grpmux = m, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct atlas7_pinctrl_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct pinctrl_pin_desc *pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int pads_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct atlas7_pin_group *grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int grps_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct atlas7_pmx_func *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int funcs_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct atlas7_pad_config *confs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int confs_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Platform info of atlas7 pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ATLAS7_PINCTRL_REG_BANKS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define ATLAS7_PINCTRL_BANK_0_PINS 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ATLAS7_PINCTRL_BANK_1_PINS 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define ATLAS7_PINCTRL_TOTAL_PINS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) (ATLAS7_PINCTRL_BANK_0_PINS + ATLAS7_PINCTRL_BANK_1_PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * Atlas7 GPIO Chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define NGPIO_OF_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GPIO_TO_BANK(gpio) ((gpio) / NGPIO_OF_BANK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Registers of GPIO Controllers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ATLAS7_GPIO_BASE(g, b) ((g)->reg + 0x100 * (b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define ATLAS7_GPIO_CTRL(b, i) ((b)->base + 4 * (i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define ATLAS7_GPIO_INT_STATUS(b) ((b)->base + 0x8C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Definition bits of GPIO Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ATLAS7_GPIO_CTL_INTR_LOW_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ATLAS7_GPIO_CTL_INTR_HIGH_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define ATLAS7_GPIO_CTL_INTR_TYPE_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define ATLAS7_GPIO_CTL_INTR_EN_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define ATLAS7_GPIO_CTL_INTR_STATUS_MASK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ATLAS7_GPIO_CTL_OUT_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ATLAS7_GPIO_CTL_DATAOUT_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ATLAS7_GPIO_CTL_DATAIN_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct atlas7_gpio_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) const unsigned int *gpio_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u32 sleep_data[NGPIO_OF_BANK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct atlas7_gpio_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct atlas7_gpio_bank banks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct atlas7_pmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct atlas7_pinctrl_data *pctl_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void __iomem *regs[ATLAS7_PINCTRL_REG_BANKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) void __iomem *sys2pci_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 status_ds[NUM_OF_IN_DISABLE_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 status_dsv[NUM_OF_IN_DISABLE_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct atlas7_pad_status sleep_data[ATLAS7_PINCTRL_TOTAL_PINS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * Pad list for the pinmux subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * refer to A7DA IO Summary - CS-314158-DD-4E.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Pads in IOC RTC & TOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct pinctrl_pin_desc atlas7_ioc_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* RTC PADs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(0, "rtc_gpio_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(1, "rtc_gpio_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(2, "rtc_gpio_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(3, "rtc_gpio_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(4, "low_bat_ind_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(5, "on_key_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(6, "ext_on"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(7, "mem_on"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(8, "core_on"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(9, "io_on"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(10, "can0_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(11, "can0_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(12, "spi0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(13, "spi0_cs_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(14, "spi0_io_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(15, "spi0_io_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(16, "spi0_io_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(17, "spi0_io_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* TOP PADs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(18, "spi1_en"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(19, "spi1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(20, "spi1_din"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(21, "spi1_dout"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(22, "trg_spi_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(23, "trg_spi_di"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(24, "trg_spi_do"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(25, "trg_spi_cs_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(26, "trg_acq_d1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(27, "trg_irq_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(28, "trg_acq_d0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(29, "trg_acq_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(30, "trg_shutdown_b_out"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINCTRL_PIN(31, "sdio2_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(32, "sdio2_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(33, "sdio2_dat_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(34, "sdio2_dat_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(35, "sdio2_dat_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(36, "sdio2_dat_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(37, "df_ad_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(38, "df_ad_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(39, "df_ad_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(40, "df_ad_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(41, "df_ad_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(42, "df_ad_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(43, "df_ad_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(44, "df_ad_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(45, "df_dqs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(46, "df_cle"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(47, "df_ale"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(48, "df_we_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(49, "df_re_b"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(50, "df_ry_by"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(51, "df_cs_b_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(52, "df_cs_b_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(53, "l_pclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(54, "l_lck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(55, "l_fck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(56, "l_de"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(57, "ldd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(58, "ldd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(59, "ldd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(60, "ldd_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(61, "ldd_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(62, "ldd_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(63, "ldd_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(64, "ldd_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(65, "ldd_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(66, "ldd_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(67, "ldd_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(68, "ldd_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(69, "ldd_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(70, "ldd_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(71, "ldd_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(72, "ldd_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(73, "lcd_gpio_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(74, "vip_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(75, "vip_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(76, "vip_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(77, "vip_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(78, "vip_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(79, "vip_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(80, "vip_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(81, "vip_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(82, "vip_pxclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(83, "vip_hsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(84, "vip_vsync"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(85, "sdio3_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(86, "sdio3_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(87, "sdio3_dat_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(88, "sdio3_dat_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(89, "sdio3_dat_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(90, "sdio3_dat_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(91, "sdio5_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(92, "sdio5_cmd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(93, "sdio5_dat_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(94, "sdio5_dat_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(95, "sdio5_dat_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(96, "sdio5_dat_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(97, "rgmii_txd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(98, "rgmii_txd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(99, "rgmii_txd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(100, "rgmii_txd_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(101, "rgmii_txclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(102, "rgmii_tx_ctl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(103, "rgmii_rxd_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(104, "rgmii_rxd_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(105, "rgmii_rxd_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(106, "rgmii_rxd_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(107, "rgmii_rx_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(108, "rgmii_rxc_ctl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(109, "rgmii_mdio"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(110, "rgmii_mdc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(111, "rgmii_intr_n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(112, "i2s_mclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(113, "i2s_bclk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(114, "i2s_ws"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(115, "i2s_dout0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(116, "i2s_dout1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(117, "i2s_dout2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(118, "i2s_din"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(119, "gpio_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(120, "gpio_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(121, "gpio_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(122, "gpio_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(123, "gpio_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(124, "gpio_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(125, "gpio_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(126, "gpio_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(127, "sda_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(128, "scl_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(129, "coex_pio_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(130, "coex_pio_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINCTRL_PIN(131, "coex_pio_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINCTRL_PIN(132, "coex_pio_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINCTRL_PIN(133, "uart0_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINCTRL_PIN(134, "uart0_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINCTRL_PIN(135, "uart1_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINCTRL_PIN(136, "uart1_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINCTRL_PIN(137, "uart3_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINCTRL_PIN(138, "uart3_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINCTRL_PIN(139, "uart4_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINCTRL_PIN(140, "uart4_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINCTRL_PIN(141, "usp0_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINCTRL_PIN(142, "usp0_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINCTRL_PIN(143, "usp0_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINCTRL_PIN(144, "usp0_fs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINCTRL_PIN(145, "usp1_clk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINCTRL_PIN(146, "usp1_tx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINCTRL_PIN(147, "usp1_rx"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINCTRL_PIN(148, "usp1_fs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINCTRL_PIN(149, "lvds_tx0d4p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINCTRL_PIN(150, "lvds_tx0d4n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINCTRL_PIN(151, "lvds_tx0d3p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINCTRL_PIN(152, "lvds_tx0d3n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINCTRL_PIN(153, "lvds_tx0d2p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINCTRL_PIN(154, "lvds_tx0d2n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINCTRL_PIN(155, "lvds_tx0d1p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(156, "lvds_tx0d1n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINCTRL_PIN(157, "lvds_tx0d0p"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(158, "lvds_tx0d0n"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(159, "jtag_tdo"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(160, "jtag_tms"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(161, "jtag_tck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(162, "jtag_tdi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINCTRL_PIN(163, "jtag_trstn"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct atlas7_pad_config atlas7_ioc_pad_confs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* The Configuration of IOC_RTC Pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PADCONF(0, 3, 0x0, 0x100, 0x200, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PADCONF(1, 3, 0x0, 0x100, 0x200, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PADCONF(2, 3, 0x0, 0x100, 0x200, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PADCONF(3, 5, 0x0, 0x100, 0x200, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PADCONF(4, 4, 0x0, 0x100, 0x200, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PADCONF(5, 4, 0x0, 0x100, 0x200, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PADCONF(6, 3, 0x0, 0x100, 0x200, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PADCONF(7, 3, 0x0, 0x100, 0x200, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PADCONF(8, 3, 0x8, 0x100, 0x200, -1, 0, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PADCONF(9, 3, 0x8, 0x100, 0x200, -1, 4, 18, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PADCONF(10, 4, 0x8, 0x100, 0x200, -1, 8, 20, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PADCONF(11, 4, 0x8, 0x100, 0x200, -1, 12, 22, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PADCONF(12, 5, 0x8, 0x100, 0x200, -1, 16, 24, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PADCONF(13, 6, 0x8, 0x100, 0x200, -1, 20, 26, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PADCONF(14, 5, 0x8, 0x100, 0x200, -1, 24, 28, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PADCONF(15, 5, 0x8, 0x100, 0x200, -1, 28, 30, 30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PADCONF(16, 5, 0x10, 0x108, 0x208, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PADCONF(17, 5, 0x10, 0x108, 0x208, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* The Configuration of IOC_TOP Pads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PADCONF(18, 5, 0x80, 0x180, 0x300, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PADCONF(19, 5, 0x80, 0x180, 0x300, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PADCONF(20, 5, 0x80, 0x180, 0x300, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PADCONF(21, 5, 0x80, 0x180, 0x300, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PADCONF(22, 5, 0x88, 0x188, 0x308, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PADCONF(23, 5, 0x88, 0x188, 0x308, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PADCONF(24, 5, 0x88, 0x188, 0x308, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PADCONF(25, 6, 0x88, 0x188, 0x308, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PADCONF(26, 5, 0x88, 0x188, 0x308, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PADCONF(27, 6, 0x88, 0x188, 0x308, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PADCONF(28, 5, 0x88, 0x188, 0x308, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PADCONF(29, 5, 0x88, 0x188, 0x308, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PADCONF(30, 5, 0x90, 0x188, 0x308, -1, 0, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PADCONF(31, 2, 0x98, 0x190, 0x310, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PADCONF(32, 1, 0x98, 0x190, 0x310, -1, 4, 2, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PADCONF(33, 1, 0x98, 0x190, 0x310, -1, 8, 4, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PADCONF(34, 1, 0x98, 0x190, 0x310, -1, 12, 6, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PADCONF(35, 1, 0x98, 0x190, 0x310, -1, 16, 8, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PADCONF(36, 1, 0x98, 0x190, 0x310, -1, 20, 10, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PADCONF(37, 1, 0xa0, 0x198, 0x318, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PADCONF(38, 1, 0xa0, 0x198, 0x318, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PADCONF(39, 1, 0xa0, 0x198, 0x318, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PADCONF(40, 1, 0xa0, 0x198, 0x318, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PADCONF(41, 1, 0xa0, 0x198, 0x318, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PADCONF(42, 1, 0xa0, 0x198, 0x318, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PADCONF(43, 1, 0xa0, 0x198, 0x318, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PADCONF(44, 1, 0xa0, 0x198, 0x318, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PADCONF(45, 0, 0xa8, 0x198, 0x318, -1, 0, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PADCONF(46, 0, 0xa8, 0x198, 0x318, -1, 4, 18, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PADCONF(47, 1, 0xa8, 0x198, 0x318, -1, 8, 20, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PADCONF(48, 1, 0xa8, 0x198, 0x318, -1, 12, 22, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PADCONF(49, 1, 0xa8, 0x198, 0x318, -1, 16, 24, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PADCONF(50, 1, 0xa8, 0x198, 0x318, -1, 20, 26, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PADCONF(51, 1, 0xa8, 0x198, 0x318, -1, 24, 28, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PADCONF(52, 1, 0xa8, 0x198, 0x318, -1, 28, 30, 30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PADCONF(53, 0, 0xb0, 0x1a0, 0x320, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PADCONF(54, 0, 0xb0, 0x1a0, 0x320, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PADCONF(55, 0, 0xb0, 0x1a0, 0x320, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PADCONF(56, 0, 0xb0, 0x1a0, 0x320, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PADCONF(57, 0, 0xb0, 0x1a0, 0x320, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PADCONF(58, 0, 0xb0, 0x1a0, 0x320, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PADCONF(59, 0, 0xb0, 0x1a0, 0x320, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PADCONF(60, 0, 0xb0, 0x1a0, 0x320, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PADCONF(61, 0, 0xb8, 0x1a0, 0x320, -1, 0, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PADCONF(62, 0, 0xb8, 0x1a0, 0x320, -1, 4, 18, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PADCONF(63, 0, 0xb8, 0x1a0, 0x320, -1, 8, 20, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PADCONF(64, 0, 0xb8, 0x1a0, 0x320, -1, 12, 22, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PADCONF(65, 0, 0xb8, 0x1a0, 0x320, -1, 16, 24, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PADCONF(66, 0, 0xb8, 0x1a0, 0x320, -1, 20, 26, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PADCONF(67, 0, 0xb8, 0x1a0, 0x320, -1, 24, 28, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PADCONF(68, 0, 0xb8, 0x1a0, 0x320, -1, 28, 30, 30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PADCONF(69, 0, 0xc0, 0x1a8, 0x328, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PADCONF(70, 0, 0xc0, 0x1a8, 0x328, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PADCONF(71, 0, 0xc0, 0x1a8, 0x328, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PADCONF(72, 0, 0xc0, 0x1a8, 0x328, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PADCONF(73, 0, 0xc0, 0x1a8, 0x328, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PADCONF(74, 0, 0xc8, 0x1b0, 0x330, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PADCONF(75, 0, 0xc8, 0x1b0, 0x330, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PADCONF(76, 0, 0xc8, 0x1b0, 0x330, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PADCONF(77, 0, 0xc8, 0x1b0, 0x330, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PADCONF(78, 0, 0xc8, 0x1b0, 0x330, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PADCONF(79, 0, 0xc8, 0x1b0, 0x330, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PADCONF(80, 0, 0xc8, 0x1b0, 0x330, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PADCONF(81, 0, 0xc8, 0x1b0, 0x330, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PADCONF(82, 0, 0xd0, 0x1b0, 0x330, -1, 0, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PADCONF(83, 0, 0xd0, 0x1b0, 0x330, -1, 4, 18, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PADCONF(84, 0, 0xd0, 0x1b0, 0x330, -1, 8, 20, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PADCONF(85, 2, 0xd8, 0x1b8, 0x338, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PADCONF(86, 1, 0xd8, 0x1b8, 0x338, -1, 4, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PADCONF(87, 1, 0xd8, 0x1b8, 0x338, -1, 8, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PADCONF(88, 1, 0xd8, 0x1b8, 0x338, -1, 12, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PADCONF(89, 1, 0xd8, 0x1b8, 0x338, -1, 16, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PADCONF(90, 1, 0xd8, 0x1b8, 0x338, -1, 20, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PADCONF(91, 2, 0xe0, 0x1c0, 0x340, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PADCONF(92, 1, 0xe0, 0x1c0, 0x340, -1, 4, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PADCONF(93, 1, 0xe0, 0x1c0, 0x340, -1, 8, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PADCONF(94, 1, 0xe0, 0x1c0, 0x340, -1, 12, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PADCONF(95, 1, 0xe0, 0x1c0, 0x340, -1, 16, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PADCONF(96, 1, 0xe0, 0x1c0, 0x340, -1, 20, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PADCONF(97, 0, 0xe8, 0x1c8, 0x348, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PADCONF(98, 0, 0xe8, 0x1c8, 0x348, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PADCONF(99, 0, 0xe8, 0x1c8, 0x348, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PADCONF(100, 0, 0xe8, 0x1c8, 0x348, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PADCONF(101, 2, 0xe8, 0x1c8, 0x348, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PADCONF(102, 0, 0xe8, 0x1c8, 0x348, -1, 20, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PADCONF(103, 0, 0xe8, 0x1c8, 0x348, -1, 24, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PADCONF(104, 0, 0xe8, 0x1c8, 0x348, -1, 28, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PADCONF(105, 0, 0xf0, 0x1c8, 0x348, -1, 0, 18, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PADCONF(106, 0, 0xf0, 0x1c8, 0x348, -1, 4, 20, 20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PADCONF(107, 0, 0xf0, 0x1c8, 0x348, -1, 8, 22, 22, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PADCONF(108, 0, 0xf0, 0x1c8, 0x348, -1, 12, 24, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PADCONF(109, 1, 0xf0, 0x1c8, 0x348, -1, 16, 26, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PADCONF(110, 0, 0xf0, 0x1c8, 0x348, -1, 20, 28, 28, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PADCONF(111, 1, 0xf0, 0x1c8, 0x348, -1, 24, 30, 30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PADCONF(112, 5, 0xf8, 0x200, 0x350, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PADCONF(113, 5, 0xf8, 0x200, 0x350, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PADCONF(114, 5, 0xf8, 0x200, 0x350, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PADCONF(115, 5, 0xf8, 0x200, 0x350, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PADCONF(116, 5, 0xf8, 0x200, 0x350, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PADCONF(117, 5, 0xf8, 0x200, 0x350, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PADCONF(118, 5, 0xf8, 0x200, 0x350, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PADCONF(119, 5, 0x100, 0x250, 0x358, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PADCONF(120, 5, 0x100, 0x250, 0x358, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PADCONF(121, 5, 0x100, 0x250, 0x358, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PADCONF(122, 5, 0x100, 0x250, 0x358, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PADCONF(123, 6, 0x100, 0x250, 0x358, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PADCONF(124, 6, 0x100, 0x250, 0x358, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PADCONF(125, 6, 0x100, 0x250, 0x358, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PADCONF(126, 6, 0x100, 0x250, 0x358, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PADCONF(127, 6, 0x108, 0x250, 0x358, -1, 16, 24, 24, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PADCONF(128, 6, 0x108, 0x250, 0x358, -1, 20, 26, 26, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PADCONF(129, 0, 0x110, 0x258, 0x360, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PADCONF(130, 0, 0x110, 0x258, 0x360, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PADCONF(131, 0, 0x110, 0x258, 0x360, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PADCONF(132, 0, 0x110, 0x258, 0x360, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PADCONF(133, 6, 0x118, 0x260, 0x368, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PADCONF(134, 6, 0x118, 0x260, 0x368, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PADCONF(135, 6, 0x118, 0x260, 0x368, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PADCONF(136, 6, 0x118, 0x260, 0x368, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PADCONF(137, 6, 0x118, 0x260, 0x368, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PADCONF(138, 6, 0x118, 0x260, 0x368, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PADCONF(139, 6, 0x120, 0x260, 0x368, -1, 0, 16, 16, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PADCONF(140, 6, 0x120, 0x260, 0x368, -1, 4, 18, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PADCONF(141, 5, 0x128, 0x268, 0x378, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PADCONF(142, 5, 0x128, 0x268, 0x378, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PADCONF(143, 5, 0x128, 0x268, 0x378, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PADCONF(144, 5, 0x128, 0x268, 0x378, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PADCONF(145, 5, 0x128, 0x268, 0x378, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PADCONF(146, 5, 0x128, 0x268, 0x378, -1, 20, 10, 10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PADCONF(147, 5, 0x128, 0x268, 0x378, -1, 24, 12, 12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PADCONF(148, 5, 0x128, 0x268, 0x378, -1, 28, 14, 14, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PADCONF(149, 7, 0x130, 0x270, -1, 0x480, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PADCONF(150, 7, 0x130, 0x270, -1, 0x480, 4, 2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PADCONF(151, 7, 0x130, 0x270, -1, 0x480, 8, 4, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PADCONF(152, 7, 0x130, 0x270, -1, 0x480, 12, 6, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PADCONF(153, 7, 0x130, 0x270, -1, 0x480, 16, 8, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PADCONF(154, 7, 0x130, 0x270, -1, 0x480, 20, 10, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PADCONF(155, 7, 0x130, 0x270, -1, 0x480, 24, 12, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PADCONF(156, 7, 0x130, 0x270, -1, 0x480, 28, 14, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PADCONF(157, 7, 0x138, 0x278, -1, 0x480, 0, 0, 0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PADCONF(158, 7, 0x138, 0x278, -1, 0x480, 4, 2, 0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PADCONF(159, 5, 0x140, 0x280, 0x380, -1, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PADCONF(160, 6, 0x140, 0x280, 0x380, -1, 4, 2, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PADCONF(161, 5, 0x140, 0x280, 0x380, -1, 8, 4, 4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PADCONF(162, 6, 0x140, 0x280, 0x380, -1, 12, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PADCONF(163, 6, 0x140, 0x280, 0x380, -1, 16, 8, 8, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* pin list of each pin group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const unsigned int gnss_gpio_pins[] = { 119, 120, 121, 122, 123, 124,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 125, 126, 127, 128, 22, 23, 24, 25, 26, 27, 28, 29, 30, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const unsigned int lcd_vip_gpio_pins[] = { 74, 75, 76, 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 81, 82, 83, 84, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const unsigned int sdio_i2s_gpio_pins[] = { 31, 32, 33, 34, 35, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 85, 86, 87, 88, 89, 90, 129, 130, 131, 132, 91, 92, 93, 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 95, 96, 112, 113, 114, 115, 116, 117, 118, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const unsigned int sp_rgmii_gpio_pins[] = { 97, 98, 99, 100, 101, 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 103, 104, 105, 106, 107, 108, 109, 110, 111, 18, 19, 20, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 141, 142, 143, 144, 145, 146, 147, 148, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const unsigned int lvds_gpio_pins[] = { 157, 158, 155, 156, 153, 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 151, 152, 149, 150, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const unsigned int jtag_uart_nand_gpio_pins[] = { 44, 43, 42, 41, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 39, 38, 37, 46, 47, 48, 49, 50, 52, 51, 45, 133, 134, 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 136, 137, 138, 139, 140, 159, 160, 161, 162, 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const unsigned int rtc_gpio_pins[] = { 0, 1, 2, 3, 4, 10, 11, 12, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 14, 15, 16, 17, 9, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const unsigned int audio_ac97_pins[] = { 113, 118, 115, 114, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const unsigned int audio_digmic_pins0[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned int audio_digmic_pins1[] = { 122, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const unsigned int audio_digmic_pins2[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const unsigned int audio_func_dbg_pins[] = { 141, 144, 44, 43, 42, 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 40, 39, 38, 37, 74, 75, 76, 77, 78, 79, 81, 113, 114, 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 115, 49, 50, 142, 143, 80, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const unsigned int audio_i2s_pins[] = { 118, 115, 116, 117, 112, 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 114, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const unsigned int audio_i2s_2ch_pins[] = { 118, 115, 112, 113, 114, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const unsigned int audio_i2s_extclk_pins[] = { 112, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const unsigned int audio_spdif_out_pins0[] = { 112, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const unsigned int audio_spdif_out_pins1[] = { 116, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const unsigned int audio_spdif_out_pins2[] = { 142, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const unsigned int audio_uart0_basic_pins[] = { 143, 142, 141, 144, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const unsigned int audio_uart0_urfs_pins0[] = { 117, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const unsigned int audio_uart0_urfs_pins1[] = { 139, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const unsigned int audio_uart0_urfs_pins2[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const unsigned int audio_uart0_urfs_pins3[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const unsigned int audio_uart1_basic_pins[] = { 147, 146, 145, 148, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const unsigned int audio_uart1_urfs_pins0[] = { 117, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const unsigned int audio_uart1_urfs_pins1[] = { 140, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const unsigned int audio_uart1_urfs_pins2[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const unsigned int audio_uart2_urfs_pins0[] = { 139, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const unsigned int audio_uart2_urfs_pins1[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const unsigned int audio_uart2_urfs_pins2[] = { 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const unsigned int audio_uart2_urxd_pins0[] = { 20, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const unsigned int audio_uart2_urxd_pins1[] = { 109, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const unsigned int audio_uart2_urxd_pins2[] = { 93, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const unsigned int audio_uart2_usclk_pins0[] = { 19, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const unsigned int audio_uart2_usclk_pins1[] = { 101, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const unsigned int audio_uart2_usclk_pins2[] = { 91, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const unsigned int audio_uart2_utfs_pins0[] = { 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const unsigned int audio_uart2_utfs_pins1[] = { 111, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const unsigned int audio_uart2_utfs_pins2[] = { 94, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const unsigned int audio_uart2_utxd_pins0[] = { 21, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const unsigned int audio_uart2_utxd_pins1[] = { 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const unsigned int audio_uart2_utxd_pins2[] = { 92, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const unsigned int c_can_trnsvr_en_pins0[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const unsigned int c_can_trnsvr_en_pins1[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const unsigned int c_can_trnsvr_intr_pins[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const unsigned int c_can_trnsvr_stb_n_pins[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const unsigned int c0_can_rxd_trnsv0_pins[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const unsigned int c0_can_rxd_trnsv1_pins[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const unsigned int c0_can_txd_trnsv0_pins[] = { 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const unsigned int c0_can_txd_trnsv1_pins[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const unsigned int c1_can_rxd_pins0[] = { 138, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const unsigned int c1_can_rxd_pins1[] = { 147, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const unsigned int c1_can_rxd_pins2[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const unsigned int c1_can_rxd_pins3[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const unsigned int c1_can_txd_pins0[] = { 137, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const unsigned int c1_can_txd_pins1[] = { 146, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const unsigned int c1_can_txd_pins2[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const unsigned int c1_can_txd_pins3[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const unsigned int ca_audio_lpc_pins[] = { 62, 63, 64, 65, 66, 67, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 69, 70, 71, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const unsigned int ca_bt_lpc_pins[] = { 85, 86, 87, 88, 89, 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const unsigned int ca_coex_pins[] = { 129, 130, 131, 132, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const unsigned int ca_curator_lpc_pins[] = { 57, 58, 59, 60, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const unsigned int ca_pcm_debug_pins[] = { 91, 93, 94, 92, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const unsigned int ca_pio_pins[] = { 121, 122, 125, 126, 38, 37, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 49, 50, 54, 55, 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const unsigned int ca_sdio_debug_pins[] = { 40, 39, 44, 43, 42, 41, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const unsigned int ca_spi_pins[] = { 82, 79, 80, 81, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const unsigned int ca_trb_pins[] = { 91, 93, 94, 95, 96, 78, 74, 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 76, 77, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const unsigned int ca_uart_debug_pins[] = { 136, 135, 134, 133, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const unsigned int clkc_pins0[] = { 30, 47, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const unsigned int clkc_pins1[] = { 78, 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const unsigned int gn_gnss_i2c_pins[] = { 128, 127, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const unsigned int gn_gnss_uart_nopause_pins[] = { 134, 133, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const unsigned int gn_gnss_uart_pins[] = { 134, 133, 136, 135, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const unsigned int gn_trg_spi_pins0[] = { 22, 25, 23, 24, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const unsigned int gn_trg_spi_pins1[] = { 82, 79, 80, 81, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const unsigned int cvbs_dbg_pins[] = { 54, 53, 82, 74, 75, 76, 77, 78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) 79, 80, 81, 83, 84, 73, 55, 56, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const unsigned int cvbs_dbg_test_pins0[] = { 57, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const unsigned int cvbs_dbg_test_pins1[] = { 58, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const unsigned int cvbs_dbg_test_pins2[] = { 59, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const unsigned int cvbs_dbg_test_pins3[] = { 60, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const unsigned int cvbs_dbg_test_pins4[] = { 61, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const unsigned int cvbs_dbg_test_pins5[] = { 62, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const unsigned int cvbs_dbg_test_pins6[] = { 63, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const unsigned int cvbs_dbg_test_pins7[] = { 64, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const unsigned int cvbs_dbg_test_pins8[] = { 65, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const unsigned int cvbs_dbg_test_pins9[] = { 66, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const unsigned int cvbs_dbg_test_pins10[] = { 67, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const unsigned int cvbs_dbg_test_pins11[] = { 68, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const unsigned int cvbs_dbg_test_pins12[] = { 69, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const unsigned int cvbs_dbg_test_pins13[] = { 70, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const unsigned int cvbs_dbg_test_pins14[] = { 71, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const unsigned int cvbs_dbg_test_pins15[] = { 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const unsigned int gn_gnss_power_pins[] = { 123, 124, 121, 122, 125,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) 120, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const unsigned int gn_gnss_sw_status_pins[] = { 57, 58, 59, 60, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 55, 56, 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const unsigned int gn_gnss_eclk_pins[] = { 113, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const unsigned int gn_gnss_irq1_pins0[] = { 112, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const unsigned int gn_gnss_irq2_pins0[] = { 118, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const unsigned int gn_gnss_tm_pins[] = { 115, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const unsigned int gn_gnss_tsync_pins[] = { 114, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const unsigned int gn_io_gnsssys_sw_cfg_pins[] = { 44, 43, 42, 41, 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 39, 38, 37, 49, 50, 91, 92, 93, 94, 95, 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const unsigned int gn_trg_pins0[] = { 29, 28, 26, 27, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const unsigned int gn_trg_pins1[] = { 77, 76, 74, 75, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const unsigned int gn_trg_shutdown_pins0[] = { 30, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const unsigned int gn_trg_shutdown_pins1[] = { 83, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const unsigned int gn_trg_shutdown_pins2[] = { 117, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const unsigned int gn_trg_shutdown_pins3[] = { 123, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const unsigned int i2c0_pins[] = { 128, 127, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const unsigned int i2c1_pins[] = { 126, 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const unsigned int i2s0_pins[] = { 91, 93, 94, 92, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const unsigned int i2s1_basic_pins[] = { 95, 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const unsigned int i2s1_rxd0_pins0[] = { 61, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const unsigned int i2s1_rxd0_pins1[] = { 131, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const unsigned int i2s1_rxd0_pins2[] = { 129, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const unsigned int i2s1_rxd0_pins3[] = { 117, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const unsigned int i2s1_rxd0_pins4[] = { 83, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const unsigned int i2s1_rxd1_pins0[] = { 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const unsigned int i2s1_rxd1_pins1[] = { 132, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const unsigned int i2s1_rxd1_pins2[] = { 130, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const unsigned int i2s1_rxd1_pins3[] = { 118, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const unsigned int i2s1_rxd1_pins4[] = { 84, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const unsigned int jtag_jt_dbg_nsrst_pins[] = { 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const unsigned int jtag_ntrst_pins0[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const unsigned int jtag_ntrst_pins1[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const unsigned int jtag_swdiotms_pins0[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const unsigned int jtag_swdiotms_pins1[] = { 160, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const unsigned int jtag_tck_pins0[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const unsigned int jtag_tck_pins1[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const unsigned int jtag_tdi_pins0[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const unsigned int jtag_tdi_pins1[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const unsigned int jtag_tdo_pins0[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const unsigned int jtag_tdo_pins1[] = { 159, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const unsigned int ks_kas_spi_pins0[] = { 141, 144, 143, 142, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const unsigned int ld_ldd_pins[] = { 57, 58, 59, 60, 61, 62, 63, 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) 81, 56, 53, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const unsigned int ld_ldd_16bit_pins[] = { 57, 58, 59, 60, 61, 62, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const unsigned int ld_ldd_fck_pins[] = { 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const unsigned int ld_ldd_lck_pins[] = { 54, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const unsigned int lr_lcdrom_pins[] = { 73, 54, 57, 58, 59, 60, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 56, 53, 55, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const unsigned int lvds_analog_pins[] = { 149, 150, 151, 152, 153, 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) 155, 156, 157, 158, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static const unsigned int nd_df_basic_pins[] = { 44, 43, 42, 41, 40, 39, 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) 37, 47, 46, 52, 45, 49, 50, 48, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const unsigned int nd_df_wp_pins[] = { 124, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const unsigned int nd_df_cs_pins[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const unsigned int ps_pins[] = { 120, 119, 121, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const unsigned int ps_no_dir_pins[] = { 119, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const unsigned int pwc_core_on_pins[] = { 8, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const unsigned int pwc_ext_on_pins[] = { 6, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const unsigned int pwc_gpio3_clk_pins[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const unsigned int pwc_io_on_pins[] = { 9, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const unsigned int pwc_lowbatt_b_pins0[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const unsigned int pwc_mem_on_pins[] = { 7, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const unsigned int pwc_on_key_b_pins0[] = { 5, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const unsigned int pwc_wakeup_src0_pins[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const unsigned int pwc_wakeup_src1_pins[] = { 1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const unsigned int pwc_wakeup_src2_pins[] = { 2, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const unsigned int pwc_wakeup_src3_pins[] = { 3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const unsigned int pw_cko0_pins0[] = { 123, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const unsigned int pw_cko0_pins1[] = { 101, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const unsigned int pw_cko0_pins2[] = { 82, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const unsigned int pw_cko0_pins3[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static const unsigned int pw_cko1_pins0[] = { 124, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const unsigned int pw_cko1_pins1[] = { 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const unsigned int pw_cko1_pins2[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static const unsigned int pw_i2s01_clk_pins0[] = { 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const unsigned int pw_i2s01_clk_pins1[] = { 117, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const unsigned int pw_i2s01_clk_pins2[] = { 132, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const unsigned int pw_pwm0_pins0[] = { 119, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const unsigned int pw_pwm0_pins1[] = { 159, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const unsigned int pw_pwm1_pins0[] = { 120, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static const unsigned int pw_pwm1_pins1[] = { 160, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const unsigned int pw_pwm1_pins2[] = { 131, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const unsigned int pw_pwm2_pins0[] = { 121, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) static const unsigned int pw_pwm2_pins1[] = { 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const unsigned int pw_pwm2_pins2[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const unsigned int pw_pwm3_pins0[] = { 122, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const unsigned int pw_pwm3_pins1[] = { 73, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const unsigned int pw_pwm_cpu_vol_pins0[] = { 121, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const unsigned int pw_pwm_cpu_vol_pins1[] = { 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const unsigned int pw_pwm_cpu_vol_pins2[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const unsigned int pw_backlight_pins0[] = { 122, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const unsigned int pw_backlight_pins1[] = { 73, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const unsigned int rg_eth_mac_pins[] = { 108, 103, 104, 105, 106, 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) 102, 97, 98, 99, 100, 101, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const unsigned int rg_gmac_phy_intr_n_pins[] = { 111, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const unsigned int rg_rgmii_mac_pins[] = { 109, 110, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const unsigned int rg_rgmii_phy_ref_clk_pins0[] = { 111, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const unsigned int rg_rgmii_phy_ref_clk_pins1[] = { 53, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const unsigned int sd0_pins[] = { 46, 47, 44, 43, 42, 41, 40, 39, 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) 37, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const unsigned int sd0_4bit_pins[] = { 46, 47, 44, 43, 42, 41, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const unsigned int sd1_pins[] = { 48, 49, 44, 43, 42, 41, 40, 39, 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) 37, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const unsigned int sd1_4bit_pins0[] = { 48, 49, 44, 43, 42, 41, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const unsigned int sd1_4bit_pins1[] = { 48, 49, 40, 39, 38, 37, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const unsigned int sd2_basic_pins[] = { 31, 32, 33, 34, 35, 36, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const unsigned int sd2_cdb_pins0[] = { 124, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static const unsigned int sd2_cdb_pins1[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const unsigned int sd2_wpb_pins0[] = { 123, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const unsigned int sd2_wpb_pins1[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const unsigned int sd3_9_pins[] = { 85, 86, 87, 88, 89, 90, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const unsigned int sd5_pins[] = { 91, 92, 93, 94, 95, 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const unsigned int sd6_pins0[] = { 79, 78, 74, 75, 76, 77, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const unsigned int sd6_pins1[] = { 101, 99, 100, 110, 109, 111, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const unsigned int sp0_ext_ldo_on_pins[] = { 4, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const unsigned int sp0_qspi_pins[] = { 12, 13, 14, 15, 16, 17, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const unsigned int sp1_spi_pins[] = { 19, 20, 21, 18, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const unsigned int tpiu_trace_pins[] = { 53, 56, 57, 58, 59, 60, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const unsigned int uart0_pins[] = { 121, 120, 134, 133, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const unsigned int uart0_nopause_pins[] = { 134, 133, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const unsigned int uart1_pins[] = { 136, 135, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const unsigned int uart2_cts_pins0[] = { 132, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const unsigned int uart2_cts_pins1[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const unsigned int uart2_rts_pins0[] = { 131, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const unsigned int uart2_rts_pins1[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const unsigned int uart2_rxd_pins0[] = { 11, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const unsigned int uart2_rxd_pins1[] = { 160, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const unsigned int uart2_rxd_pins2[] = { 130, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const unsigned int uart2_txd_pins0[] = { 10, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const unsigned int uart2_txd_pins1[] = { 159, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const unsigned int uart2_txd_pins2[] = { 129, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned int uart3_cts_pins0[] = { 125, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const unsigned int uart3_cts_pins1[] = { 111, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const unsigned int uart3_cts_pins2[] = { 140, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const unsigned int uart3_rts_pins0[] = { 126, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const unsigned int uart3_rts_pins1[] = { 109, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const unsigned int uart3_rts_pins2[] = { 139, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const unsigned int uart3_rxd_pins0[] = { 138, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const unsigned int uart3_rxd_pins1[] = { 84, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const unsigned int uart3_rxd_pins2[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const unsigned int uart3_txd_pins0[] = { 137, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const unsigned int uart3_txd_pins1[] = { 83, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const unsigned int uart3_txd_pins2[] = { 161, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const unsigned int uart4_basic_pins[] = { 140, 139, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const unsigned int uart4_cts_pins0[] = { 122, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const unsigned int uart4_cts_pins1[] = { 100, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const unsigned int uart4_cts_pins2[] = { 117, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const unsigned int uart4_rts_pins0[] = { 123, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const unsigned int uart4_rts_pins1[] = { 99, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const unsigned int uart4_rts_pins2[] = { 116, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const unsigned int usb0_drvvbus_pins0[] = { 51, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const unsigned int usb0_drvvbus_pins1[] = { 162, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const unsigned int usb1_drvvbus_pins0[] = { 134, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const unsigned int usb1_drvvbus_pins1[] = { 163, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const unsigned int visbus_dout_pins[] = { 57, 58, 59, 60, 61, 62, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) 64, 65, 66, 67, 68, 69, 70, 71, 72, 53, 54, 55, 56, 85, 86,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const unsigned int vi_vip1_pins[] = { 74, 75, 76, 77, 78, 79, 80, 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) 82, 83, 84, 103, 104, 105, 106, 107, 102, 97, 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const unsigned int vi_vip1_ext_pins[] = { 74, 75, 76, 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) 81, 82, 83, 84, 108, 103, 104, 105, 106, 107, 102, 97, 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) 99, 100, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const unsigned int vi_vip1_low8bit_pins[] = { 74, 75, 76, 77, 78, 79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) 80, 81, 82, 83, 84, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const unsigned int vi_vip1_high8bit_pins[] = { 82, 83, 84, 103, 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) 105, 106, 107, 102, 97, 98, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* definition of pin group table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static struct atlas7_pin_group altas7_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GROUP("gnss_gpio_grp", gnss_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GROUP("lcd_vip_gpio_grp", lcd_vip_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) GROUP("sdio_i2s_gpio_grp", sdio_i2s_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GROUP("sp_rgmii_gpio_grp", sp_rgmii_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GROUP("lvds_gpio_grp", lvds_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GROUP("jtag_uart_nand_gpio_grp", jtag_uart_nand_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GROUP("rtc_gpio_grp", rtc_gpio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GROUP("audio_ac97_grp", audio_ac97_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GROUP("audio_digmic_grp0", audio_digmic_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GROUP("audio_digmic_grp1", audio_digmic_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GROUP("audio_digmic_grp2", audio_digmic_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GROUP("audio_func_dbg_grp", audio_func_dbg_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GROUP("audio_i2s_grp", audio_i2s_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GROUP("audio_i2s_2ch_grp", audio_i2s_2ch_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GROUP("audio_i2s_extclk_grp", audio_i2s_extclk_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GROUP("audio_spdif_out_grp0", audio_spdif_out_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GROUP("audio_spdif_out_grp1", audio_spdif_out_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GROUP("audio_spdif_out_grp2", audio_spdif_out_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GROUP("audio_uart0_basic_grp", audio_uart0_basic_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GROUP("audio_uart0_urfs_grp0", audio_uart0_urfs_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GROUP("audio_uart0_urfs_grp1", audio_uart0_urfs_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) GROUP("audio_uart0_urfs_grp2", audio_uart0_urfs_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GROUP("audio_uart0_urfs_grp3", audio_uart0_urfs_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GROUP("audio_uart1_basic_grp", audio_uart1_basic_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GROUP("audio_uart1_urfs_grp0", audio_uart1_urfs_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GROUP("audio_uart1_urfs_grp1", audio_uart1_urfs_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GROUP("audio_uart1_urfs_grp2", audio_uart1_urfs_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GROUP("audio_uart2_urfs_grp0", audio_uart2_urfs_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GROUP("audio_uart2_urfs_grp1", audio_uart2_urfs_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GROUP("audio_uart2_urfs_grp2", audio_uart2_urfs_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GROUP("audio_uart2_urxd_grp0", audio_uart2_urxd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) GROUP("audio_uart2_urxd_grp1", audio_uart2_urxd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GROUP("audio_uart2_urxd_grp2", audio_uart2_urxd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GROUP("audio_uart2_usclk_grp0", audio_uart2_usclk_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GROUP("audio_uart2_usclk_grp1", audio_uart2_usclk_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GROUP("audio_uart2_usclk_grp2", audio_uart2_usclk_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GROUP("audio_uart2_utfs_grp0", audio_uart2_utfs_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GROUP("audio_uart2_utfs_grp1", audio_uart2_utfs_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GROUP("audio_uart2_utfs_grp2", audio_uart2_utfs_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GROUP("audio_uart2_utxd_grp0", audio_uart2_utxd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GROUP("audio_uart2_utxd_grp1", audio_uart2_utxd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GROUP("audio_uart2_utxd_grp2", audio_uart2_utxd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GROUP("c_can_trnsvr_en_grp0", c_can_trnsvr_en_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) GROUP("c_can_trnsvr_en_grp1", c_can_trnsvr_en_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GROUP("c_can_trnsvr_intr_grp", c_can_trnsvr_intr_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GROUP("c_can_trnsvr_stb_n_grp", c_can_trnsvr_stb_n_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GROUP("c0_can_rxd_trnsv0_grp", c0_can_rxd_trnsv0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) GROUP("c0_can_rxd_trnsv1_grp", c0_can_rxd_trnsv1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) GROUP("c0_can_txd_trnsv0_grp", c0_can_txd_trnsv0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) GROUP("c0_can_txd_trnsv1_grp", c0_can_txd_trnsv1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GROUP("c1_can_rxd_grp0", c1_can_rxd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) GROUP("c1_can_rxd_grp1", c1_can_rxd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) GROUP("c1_can_rxd_grp2", c1_can_rxd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GROUP("c1_can_rxd_grp3", c1_can_rxd_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) GROUP("c1_can_txd_grp0", c1_can_txd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GROUP("c1_can_txd_grp1", c1_can_txd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) GROUP("c1_can_txd_grp2", c1_can_txd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GROUP("c1_can_txd_grp3", c1_can_txd_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GROUP("ca_audio_lpc_grp", ca_audio_lpc_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GROUP("ca_bt_lpc_grp", ca_bt_lpc_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) GROUP("ca_coex_grp", ca_coex_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GROUP("ca_curator_lpc_grp", ca_curator_lpc_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GROUP("ca_pcm_debug_grp", ca_pcm_debug_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GROUP("ca_pio_grp", ca_pio_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) GROUP("ca_sdio_debug_grp", ca_sdio_debug_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GROUP("ca_spi_grp", ca_spi_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GROUP("ca_trb_grp", ca_trb_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) GROUP("ca_uart_debug_grp", ca_uart_debug_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) GROUP("clkc_grp0", clkc_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GROUP("clkc_grp1", clkc_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) GROUP("gn_gnss_i2c_grp", gn_gnss_i2c_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) GROUP("gn_gnss_uart_nopause_grp", gn_gnss_uart_nopause_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) GROUP("gn_gnss_uart_grp", gn_gnss_uart_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) GROUP("gn_trg_spi_grp0", gn_trg_spi_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) GROUP("gn_trg_spi_grp1", gn_trg_spi_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) GROUP("cvbs_dbg_grp", cvbs_dbg_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) GROUP("cvbs_dbg_test_grp0", cvbs_dbg_test_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) GROUP("cvbs_dbg_test_grp1", cvbs_dbg_test_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) GROUP("cvbs_dbg_test_grp2", cvbs_dbg_test_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) GROUP("cvbs_dbg_test_grp3", cvbs_dbg_test_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GROUP("cvbs_dbg_test_grp4", cvbs_dbg_test_pins4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) GROUP("cvbs_dbg_test_grp5", cvbs_dbg_test_pins5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) GROUP("cvbs_dbg_test_grp6", cvbs_dbg_test_pins6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) GROUP("cvbs_dbg_test_grp7", cvbs_dbg_test_pins7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) GROUP("cvbs_dbg_test_grp8", cvbs_dbg_test_pins8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) GROUP("cvbs_dbg_test_grp9", cvbs_dbg_test_pins9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) GROUP("cvbs_dbg_test_grp10", cvbs_dbg_test_pins10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) GROUP("cvbs_dbg_test_grp11", cvbs_dbg_test_pins11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) GROUP("cvbs_dbg_test_grp12", cvbs_dbg_test_pins12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) GROUP("cvbs_dbg_test_grp13", cvbs_dbg_test_pins13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) GROUP("cvbs_dbg_test_grp14", cvbs_dbg_test_pins14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) GROUP("cvbs_dbg_test_grp15", cvbs_dbg_test_pins15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) GROUP("gn_gnss_power_grp", gn_gnss_power_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) GROUP("gn_gnss_sw_status_grp", gn_gnss_sw_status_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) GROUP("gn_gnss_eclk_grp", gn_gnss_eclk_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) GROUP("gn_gnss_irq1_grp0", gn_gnss_irq1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) GROUP("gn_gnss_irq2_grp0", gn_gnss_irq2_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) GROUP("gn_gnss_tm_grp", gn_gnss_tm_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) GROUP("gn_gnss_tsync_grp", gn_gnss_tsync_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) GROUP("gn_io_gnsssys_sw_cfg_grp", gn_io_gnsssys_sw_cfg_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GROUP("gn_trg_grp0", gn_trg_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GROUP("gn_trg_grp1", gn_trg_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GROUP("gn_trg_shutdown_grp0", gn_trg_shutdown_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) GROUP("gn_trg_shutdown_grp1", gn_trg_shutdown_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) GROUP("gn_trg_shutdown_grp2", gn_trg_shutdown_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) GROUP("gn_trg_shutdown_grp3", gn_trg_shutdown_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) GROUP("i2c0_grp", i2c0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) GROUP("i2c1_grp", i2c1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) GROUP("i2s0_grp", i2s0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) GROUP("i2s1_basic_grp", i2s1_basic_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) GROUP("i2s1_rxd0_grp0", i2s1_rxd0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) GROUP("i2s1_rxd0_grp1", i2s1_rxd0_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) GROUP("i2s1_rxd0_grp2", i2s1_rxd0_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) GROUP("i2s1_rxd0_grp3", i2s1_rxd0_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) GROUP("i2s1_rxd0_grp4", i2s1_rxd0_pins4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) GROUP("i2s1_rxd1_grp0", i2s1_rxd1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) GROUP("i2s1_rxd1_grp1", i2s1_rxd1_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) GROUP("i2s1_rxd1_grp2", i2s1_rxd1_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) GROUP("i2s1_rxd1_grp3", i2s1_rxd1_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) GROUP("i2s1_rxd1_grp4", i2s1_rxd1_pins4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) GROUP("jtag_jt_dbg_nsrst_grp", jtag_jt_dbg_nsrst_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) GROUP("jtag_ntrst_grp0", jtag_ntrst_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) GROUP("jtag_ntrst_grp1", jtag_ntrst_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) GROUP("jtag_swdiotms_grp0", jtag_swdiotms_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) GROUP("jtag_swdiotms_grp1", jtag_swdiotms_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) GROUP("jtag_tck_grp0", jtag_tck_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) GROUP("jtag_tck_grp1", jtag_tck_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) GROUP("jtag_tdi_grp0", jtag_tdi_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) GROUP("jtag_tdi_grp1", jtag_tdi_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) GROUP("jtag_tdo_grp0", jtag_tdo_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) GROUP("jtag_tdo_grp1", jtag_tdo_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GROUP("ks_kas_spi_grp0", ks_kas_spi_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) GROUP("ld_ldd_grp", ld_ldd_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) GROUP("ld_ldd_16bit_grp", ld_ldd_16bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) GROUP("ld_ldd_fck_grp", ld_ldd_fck_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GROUP("ld_ldd_lck_grp", ld_ldd_lck_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) GROUP("lr_lcdrom_grp", lr_lcdrom_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) GROUP("lvds_analog_grp", lvds_analog_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) GROUP("nd_df_basic_grp", nd_df_basic_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) GROUP("nd_df_wp_grp", nd_df_wp_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) GROUP("nd_df_cs_grp", nd_df_cs_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) GROUP("ps_grp", ps_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) GROUP("ps_no_dir_grp", ps_no_dir_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) GROUP("pwc_core_on_grp", pwc_core_on_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) GROUP("pwc_ext_on_grp", pwc_ext_on_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) GROUP("pwc_gpio3_clk_grp", pwc_gpio3_clk_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) GROUP("pwc_io_on_grp", pwc_io_on_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) GROUP("pwc_lowbatt_b_grp0", pwc_lowbatt_b_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) GROUP("pwc_mem_on_grp", pwc_mem_on_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) GROUP("pwc_on_key_b_grp0", pwc_on_key_b_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) GROUP("pwc_wakeup_src0_grp", pwc_wakeup_src0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) GROUP("pwc_wakeup_src1_grp", pwc_wakeup_src1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) GROUP("pwc_wakeup_src2_grp", pwc_wakeup_src2_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) GROUP("pwc_wakeup_src3_grp", pwc_wakeup_src3_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) GROUP("pw_cko0_grp0", pw_cko0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) GROUP("pw_cko0_grp1", pw_cko0_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) GROUP("pw_cko0_grp2", pw_cko0_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) GROUP("pw_cko0_grp3", pw_cko0_pins3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) GROUP("pw_cko1_grp0", pw_cko1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) GROUP("pw_cko1_grp1", pw_cko1_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) GROUP("pw_cko1_grp2", pw_cko1_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) GROUP("pw_i2s01_clk_grp0", pw_i2s01_clk_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) GROUP("pw_i2s01_clk_grp1", pw_i2s01_clk_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) GROUP("pw_i2s01_clk_grp2", pw_i2s01_clk_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) GROUP("pw_pwm0_grp0", pw_pwm0_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) GROUP("pw_pwm0_grp1", pw_pwm0_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) GROUP("pw_pwm1_grp0", pw_pwm1_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) GROUP("pw_pwm1_grp1", pw_pwm1_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) GROUP("pw_pwm1_grp2", pw_pwm1_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) GROUP("pw_pwm2_grp0", pw_pwm2_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) GROUP("pw_pwm2_grp1", pw_pwm2_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) GROUP("pw_pwm2_grp2", pw_pwm2_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) GROUP("pw_pwm3_grp0", pw_pwm3_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) GROUP("pw_pwm3_grp1", pw_pwm3_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) GROUP("pw_pwm_cpu_vol_grp0", pw_pwm_cpu_vol_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) GROUP("pw_pwm_cpu_vol_grp1", pw_pwm_cpu_vol_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) GROUP("pw_pwm_cpu_vol_grp2", pw_pwm_cpu_vol_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) GROUP("pw_backlight_grp0", pw_backlight_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) GROUP("pw_backlight_grp1", pw_backlight_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) GROUP("rg_eth_mac_grp", rg_eth_mac_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) GROUP("rg_gmac_phy_intr_n_grp", rg_gmac_phy_intr_n_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) GROUP("rg_rgmii_mac_grp", rg_rgmii_mac_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) GROUP("rg_rgmii_phy_ref_clk_grp0", rg_rgmii_phy_ref_clk_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) GROUP("rg_rgmii_phy_ref_clk_grp1", rg_rgmii_phy_ref_clk_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) GROUP("sd0_grp", sd0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) GROUP("sd0_4bit_grp", sd0_4bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) GROUP("sd1_grp", sd1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) GROUP("sd1_4bit_grp0", sd1_4bit_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) GROUP("sd1_4bit_grp1", sd1_4bit_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) GROUP("sd2_basic_grp", sd2_basic_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) GROUP("sd2_cdb_grp0", sd2_cdb_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) GROUP("sd2_cdb_grp1", sd2_cdb_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) GROUP("sd2_wpb_grp0", sd2_wpb_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) GROUP("sd2_wpb_grp1", sd2_wpb_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) GROUP("sd3_9_grp", sd3_9_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) GROUP("sd5_grp", sd5_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) GROUP("sd6_grp0", sd6_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) GROUP("sd6_grp1", sd6_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) GROUP("sp0_ext_ldo_on_grp", sp0_ext_ldo_on_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) GROUP("sp0_qspi_grp", sp0_qspi_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) GROUP("sp1_spi_grp", sp1_spi_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) GROUP("tpiu_trace_grp", tpiu_trace_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) GROUP("uart0_grp", uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) GROUP("uart0_nopause_grp", uart0_nopause_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) GROUP("uart1_grp", uart1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) GROUP("uart2_cts_grp0", uart2_cts_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) GROUP("uart2_cts_grp1", uart2_cts_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) GROUP("uart2_rts_grp0", uart2_rts_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) GROUP("uart2_rts_grp1", uart2_rts_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) GROUP("uart2_rxd_grp0", uart2_rxd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) GROUP("uart2_rxd_grp1", uart2_rxd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) GROUP("uart2_rxd_grp2", uart2_rxd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) GROUP("uart2_txd_grp0", uart2_txd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) GROUP("uart2_txd_grp1", uart2_txd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) GROUP("uart2_txd_grp2", uart2_txd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) GROUP("uart3_cts_grp0", uart3_cts_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) GROUP("uart3_cts_grp1", uart3_cts_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) GROUP("uart3_cts_grp2", uart3_cts_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) GROUP("uart3_rts_grp0", uart3_rts_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) GROUP("uart3_rts_grp1", uart3_rts_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) GROUP("uart3_rts_grp2", uart3_rts_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) GROUP("uart3_rxd_grp0", uart3_rxd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) GROUP("uart3_rxd_grp1", uart3_rxd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) GROUP("uart3_rxd_grp2", uart3_rxd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) GROUP("uart3_txd_grp0", uart3_txd_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) GROUP("uart3_txd_grp1", uart3_txd_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) GROUP("uart3_txd_grp2", uart3_txd_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) GROUP("uart4_basic_grp", uart4_basic_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) GROUP("uart4_cts_grp0", uart4_cts_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) GROUP("uart4_cts_grp1", uart4_cts_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) GROUP("uart4_cts_grp2", uart4_cts_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) GROUP("uart4_rts_grp0", uart4_rts_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) GROUP("uart4_rts_grp1", uart4_rts_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) GROUP("uart4_rts_grp2", uart4_rts_pins2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) GROUP("usb0_drvvbus_grp0", usb0_drvvbus_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) GROUP("usb0_drvvbus_grp1", usb0_drvvbus_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) GROUP("usb1_drvvbus_grp0", usb1_drvvbus_pins0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) GROUP("usb1_drvvbus_grp1", usb1_drvvbus_pins1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) GROUP("visbus_dout_grp", visbus_dout_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) GROUP("vi_vip1_grp", vi_vip1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) GROUP("vi_vip1_ext_grp", vi_vip1_ext_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) GROUP("vi_vip1_low8bit_grp", vi_vip1_low8bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) GROUP("vi_vip1_high8bit_grp", vi_vip1_high8bit_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* How many groups that a function can use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const char * const gnss_gpio_grp[] = { "gnss_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static const char * const lcd_vip_gpio_grp[] = { "lcd_vip_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const char * const sdio_i2s_gpio_grp[] = { "sdio_i2s_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static const char * const sp_rgmii_gpio_grp[] = { "sp_rgmii_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const char * const lvds_gpio_grp[] = { "lvds_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static const char * const jtag_uart_nand_gpio_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "jtag_uart_nand_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static const char * const rtc_gpio_grp[] = { "rtc_gpio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const char * const audio_ac97_grp[] = { "audio_ac97_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static const char * const audio_digmic_grp0[] = { "audio_digmic_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static const char * const audio_digmic_grp1[] = { "audio_digmic_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static const char * const audio_digmic_grp2[] = { "audio_digmic_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const char * const audio_func_dbg_grp[] = { "audio_func_dbg_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const char * const audio_i2s_grp[] = { "audio_i2s_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const char * const audio_i2s_2ch_grp[] = { "audio_i2s_2ch_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static const char * const audio_i2s_extclk_grp[] = { "audio_i2s_extclk_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static const char * const audio_spdif_out_grp0[] = { "audio_spdif_out_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const char * const audio_spdif_out_grp1[] = { "audio_spdif_out_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const char * const audio_spdif_out_grp2[] = { "audio_spdif_out_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const char * const audio_uart0_basic_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) "audio_uart0_basic_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const char * const audio_uart0_urfs_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) "audio_uart0_urfs_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const char * const audio_uart0_urfs_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) "audio_uart0_urfs_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static const char * const audio_uart0_urfs_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) "audio_uart0_urfs_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const char * const audio_uart0_urfs_grp3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "audio_uart0_urfs_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static const char * const audio_uart1_basic_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "audio_uart1_basic_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const char * const audio_uart1_urfs_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) "audio_uart1_urfs_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static const char * const audio_uart1_urfs_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) "audio_uart1_urfs_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const char * const audio_uart1_urfs_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) "audio_uart1_urfs_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static const char * const audio_uart2_urfs_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) "audio_uart2_urfs_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const char * const audio_uart2_urfs_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "audio_uart2_urfs_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static const char * const audio_uart2_urfs_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "audio_uart2_urfs_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const char * const audio_uart2_urxd_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) "audio_uart2_urxd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const char * const audio_uart2_urxd_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "audio_uart2_urxd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static const char * const audio_uart2_urxd_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) "audio_uart2_urxd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const char * const audio_uart2_usclk_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) "audio_uart2_usclk_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static const char * const audio_uart2_usclk_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) "audio_uart2_usclk_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static const char * const audio_uart2_usclk_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) "audio_uart2_usclk_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static const char * const audio_uart2_utfs_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) "audio_uart2_utfs_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const char * const audio_uart2_utfs_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "audio_uart2_utfs_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const char * const audio_uart2_utfs_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "audio_uart2_utfs_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const char * const audio_uart2_utxd_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "audio_uart2_utxd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const char * const audio_uart2_utxd_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) "audio_uart2_utxd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static const char * const audio_uart2_utxd_grp2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "audio_uart2_utxd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const char * const c_can_trnsvr_en_grp0[] = { "c_can_trnsvr_en_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const char * const c_can_trnsvr_en_grp1[] = { "c_can_trnsvr_en_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static const char * const c_can_trnsvr_intr_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "c_can_trnsvr_intr_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static const char * const c_can_trnsvr_stb_n_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "c_can_trnsvr_stb_n_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static const char * const c0_can_rxd_trnsv0_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) "c0_can_rxd_trnsv0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static const char * const c0_can_rxd_trnsv1_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) "c0_can_rxd_trnsv1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const char * const c0_can_txd_trnsv0_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "c0_can_txd_trnsv0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static const char * const c0_can_txd_trnsv1_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "c0_can_txd_trnsv1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static const char * const c1_can_rxd_grp0[] = { "c1_can_rxd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static const char * const c1_can_rxd_grp1[] = { "c1_can_rxd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static const char * const c1_can_rxd_grp2[] = { "c1_can_rxd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static const char * const c1_can_rxd_grp3[] = { "c1_can_rxd_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const char * const c1_can_txd_grp0[] = { "c1_can_txd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static const char * const c1_can_txd_grp1[] = { "c1_can_txd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const char * const c1_can_txd_grp2[] = { "c1_can_txd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static const char * const c1_can_txd_grp3[] = { "c1_can_txd_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static const char * const ca_audio_lpc_grp[] = { "ca_audio_lpc_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static const char * const ca_bt_lpc_grp[] = { "ca_bt_lpc_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const char * const ca_coex_grp[] = { "ca_coex_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const char * const ca_curator_lpc_grp[] = { "ca_curator_lpc_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static const char * const ca_pcm_debug_grp[] = { "ca_pcm_debug_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const char * const ca_pio_grp[] = { "ca_pio_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static const char * const ca_sdio_debug_grp[] = { "ca_sdio_debug_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static const char * const ca_spi_grp[] = { "ca_spi_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static const char * const ca_trb_grp[] = { "ca_trb_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const char * const ca_uart_debug_grp[] = { "ca_uart_debug_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const char * const clkc_grp0[] = { "clkc_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static const char * const clkc_grp1[] = { "clkc_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) static const char * const gn_gnss_i2c_grp[] = { "gn_gnss_i2c_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static const char * const gn_gnss_uart_nopause_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) "gn_gnss_uart_nopause_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const char * const gn_gnss_uart_grp[] = { "gn_gnss_uart_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const char * const gn_trg_spi_grp0[] = { "gn_trg_spi_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const char * const gn_trg_spi_grp1[] = { "gn_trg_spi_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static const char * const cvbs_dbg_grp[] = { "cvbs_dbg_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const char * const cvbs_dbg_test_grp0[] = { "cvbs_dbg_test_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static const char * const cvbs_dbg_test_grp1[] = { "cvbs_dbg_test_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static const char * const cvbs_dbg_test_grp2[] = { "cvbs_dbg_test_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static const char * const cvbs_dbg_test_grp3[] = { "cvbs_dbg_test_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const char * const cvbs_dbg_test_grp4[] = { "cvbs_dbg_test_grp4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static const char * const cvbs_dbg_test_grp5[] = { "cvbs_dbg_test_grp5", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static const char * const cvbs_dbg_test_grp6[] = { "cvbs_dbg_test_grp6", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static const char * const cvbs_dbg_test_grp7[] = { "cvbs_dbg_test_grp7", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static const char * const cvbs_dbg_test_grp8[] = { "cvbs_dbg_test_grp8", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static const char * const cvbs_dbg_test_grp9[] = { "cvbs_dbg_test_grp9", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const char * const cvbs_dbg_test_grp10[] = { "cvbs_dbg_test_grp10", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static const char * const cvbs_dbg_test_grp11[] = { "cvbs_dbg_test_grp11", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static const char * const cvbs_dbg_test_grp12[] = { "cvbs_dbg_test_grp12", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const char * const cvbs_dbg_test_grp13[] = { "cvbs_dbg_test_grp13", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static const char * const cvbs_dbg_test_grp14[] = { "cvbs_dbg_test_grp14", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static const char * const cvbs_dbg_test_grp15[] = { "cvbs_dbg_test_grp15", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static const char * const gn_gnss_power_grp[] = { "gn_gnss_power_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static const char * const gn_gnss_sw_status_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) "gn_gnss_sw_status_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static const char * const gn_gnss_eclk_grp[] = { "gn_gnss_eclk_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const char * const gn_gnss_irq1_grp0[] = { "gn_gnss_irq1_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static const char * const gn_gnss_irq2_grp0[] = { "gn_gnss_irq2_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static const char * const gn_gnss_tm_grp[] = { "gn_gnss_tm_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static const char * const gn_gnss_tsync_grp[] = { "gn_gnss_tsync_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static const char * const gn_io_gnsssys_sw_cfg_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) "gn_io_gnsssys_sw_cfg_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static const char * const gn_trg_grp0[] = { "gn_trg_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const char * const gn_trg_grp1[] = { "gn_trg_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const char * const gn_trg_shutdown_grp0[] = { "gn_trg_shutdown_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) static const char * const gn_trg_shutdown_grp1[] = { "gn_trg_shutdown_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static const char * const gn_trg_shutdown_grp2[] = { "gn_trg_shutdown_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static const char * const gn_trg_shutdown_grp3[] = { "gn_trg_shutdown_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static const char * const i2c0_grp[] = { "i2c0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const char * const i2c1_grp[] = { "i2c1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static const char * const i2s0_grp[] = { "i2s0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const char * const i2s1_basic_grp[] = { "i2s1_basic_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const char * const i2s1_rxd0_grp0[] = { "i2s1_rxd0_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static const char * const i2s1_rxd0_grp1[] = { "i2s1_rxd0_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static const char * const i2s1_rxd0_grp2[] = { "i2s1_rxd0_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static const char * const i2s1_rxd0_grp3[] = { "i2s1_rxd0_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static const char * const i2s1_rxd0_grp4[] = { "i2s1_rxd0_grp4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const char * const i2s1_rxd1_grp0[] = { "i2s1_rxd1_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static const char * const i2s1_rxd1_grp1[] = { "i2s1_rxd1_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static const char * const i2s1_rxd1_grp2[] = { "i2s1_rxd1_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static const char * const i2s1_rxd1_grp3[] = { "i2s1_rxd1_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const char * const i2s1_rxd1_grp4[] = { "i2s1_rxd1_grp4", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static const char * const jtag_jt_dbg_nsrst_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) "jtag_jt_dbg_nsrst_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static const char * const jtag_ntrst_grp0[] = { "jtag_ntrst_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static const char * const jtag_ntrst_grp1[] = { "jtag_ntrst_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static const char * const jtag_swdiotms_grp0[] = { "jtag_swdiotms_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static const char * const jtag_swdiotms_grp1[] = { "jtag_swdiotms_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const char * const jtag_tck_grp0[] = { "jtag_tck_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) static const char * const jtag_tck_grp1[] = { "jtag_tck_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const char * const jtag_tdi_grp0[] = { "jtag_tdi_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static const char * const jtag_tdi_grp1[] = { "jtag_tdi_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static const char * const jtag_tdo_grp0[] = { "jtag_tdo_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const char * const jtag_tdo_grp1[] = { "jtag_tdo_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static const char * const ks_kas_spi_grp0[] = { "ks_kas_spi_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const char * const ld_ldd_grp[] = { "ld_ldd_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static const char * const ld_ldd_16bit_grp[] = { "ld_ldd_16bit_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static const char * const ld_ldd_fck_grp[] = { "ld_ldd_fck_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static const char * const ld_ldd_lck_grp[] = { "ld_ldd_lck_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static const char * const lr_lcdrom_grp[] = { "lr_lcdrom_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const char * const lvds_analog_grp[] = { "lvds_analog_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static const char * const nd_df_basic_grp[] = { "nd_df_basic_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const char * const nd_df_wp_grp[] = { "nd_df_wp_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static const char * const nd_df_cs_grp[] = { "nd_df_cs_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const char * const ps_grp[] = { "ps_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static const char * const ps_no_dir_grp[] = { "ps_no_dir_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static const char * const pwc_core_on_grp[] = { "pwc_core_on_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static const char * const pwc_ext_on_grp[] = { "pwc_ext_on_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const char * const pwc_gpio3_clk_grp[] = { "pwc_gpio3_clk_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const char * const pwc_io_on_grp[] = { "pwc_io_on_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static const char * const pwc_lowbatt_b_grp0[] = { "pwc_lowbatt_b_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static const char * const pwc_mem_on_grp[] = { "pwc_mem_on_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static const char * const pwc_on_key_b_grp0[] = { "pwc_on_key_b_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const char * const pwc_wakeup_src0_grp[] = { "pwc_wakeup_src0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static const char * const pwc_wakeup_src1_grp[] = { "pwc_wakeup_src1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const char * const pwc_wakeup_src2_grp[] = { "pwc_wakeup_src2_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static const char * const pwc_wakeup_src3_grp[] = { "pwc_wakeup_src3_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static const char * const pw_cko0_grp0[] = { "pw_cko0_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static const char * const pw_cko0_grp1[] = { "pw_cko0_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) static const char * const pw_cko0_grp2[] = { "pw_cko0_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static const char * const pw_cko0_grp3[] = { "pw_cko0_grp3", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static const char * const pw_cko1_grp0[] = { "pw_cko1_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const char * const pw_cko1_grp1[] = { "pw_cko1_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static const char * const pw_cko1_grp2[] = { "pw_cko1_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static const char * const pw_i2s01_clk_grp0[] = { "pw_i2s01_clk_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static const char * const pw_i2s01_clk_grp1[] = { "pw_i2s01_clk_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static const char * const pw_i2s01_clk_grp2[] = { "pw_i2s01_clk_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static const char * const pw_pwm0_grp0[] = { "pw_pwm0_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static const char * const pw_pwm0_grp1[] = { "pw_pwm0_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static const char * const pw_pwm1_grp0[] = { "pw_pwm1_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static const char * const pw_pwm1_grp1[] = { "pw_pwm1_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const char * const pw_pwm1_grp2[] = { "pw_pwm1_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) static const char * const pw_pwm2_grp0[] = { "pw_pwm2_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static const char * const pw_pwm2_grp1[] = { "pw_pwm2_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static const char * const pw_pwm2_grp2[] = { "pw_pwm2_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static const char * const pw_pwm3_grp0[] = { "pw_pwm3_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static const char * const pw_pwm3_grp1[] = { "pw_pwm3_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static const char * const pw_pwm_cpu_vol_grp0[] = { "pw_pwm_cpu_vol_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const char * const pw_pwm_cpu_vol_grp1[] = { "pw_pwm_cpu_vol_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static const char * const pw_pwm_cpu_vol_grp2[] = { "pw_pwm_cpu_vol_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const char * const pw_backlight_grp0[] = { "pw_backlight_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const char * const pw_backlight_grp1[] = { "pw_backlight_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static const char * const rg_eth_mac_grp[] = { "rg_eth_mac_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static const char * const rg_gmac_phy_intr_n_grp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) "rg_gmac_phy_intr_n_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const char * const rg_rgmii_mac_grp[] = { "rg_rgmii_mac_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static const char * const rg_rgmii_phy_ref_clk_grp0[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) "rg_rgmii_phy_ref_clk_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const char * const rg_rgmii_phy_ref_clk_grp1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) "rg_rgmii_phy_ref_clk_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static const char * const sd0_grp[] = { "sd0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const char * const sd0_4bit_grp[] = { "sd0_4bit_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const char * const sd1_grp[] = { "sd1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) static const char * const sd1_4bit_grp0[] = { "sd1_4bit_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const char * const sd1_4bit_grp1[] = { "sd1_4bit_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static const char * const sd2_basic_grp[] = { "sd2_basic_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const char * const sd2_cdb_grp0[] = { "sd2_cdb_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static const char * const sd2_cdb_grp1[] = { "sd2_cdb_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static const char * const sd2_wpb_grp0[] = { "sd2_wpb_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const char * const sd2_wpb_grp1[] = { "sd2_wpb_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const char * const sd3_9_grp[] = { "sd3_9_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const char * const sd5_grp[] = { "sd5_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static const char * const sd6_grp0[] = { "sd6_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static const char * const sd6_grp1[] = { "sd6_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const char * const sp0_ext_ldo_on_grp[] = { "sp0_ext_ldo_on_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static const char * const sp0_qspi_grp[] = { "sp0_qspi_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static const char * const sp1_spi_grp[] = { "sp1_spi_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static const char * const tpiu_trace_grp[] = { "tpiu_trace_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const char * const uart0_grp[] = { "uart0_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static const char * const uart0_nopause_grp[] = { "uart0_nopause_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) static const char * const uart1_grp[] = { "uart1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static const char * const uart2_cts_grp0[] = { "uart2_cts_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const char * const uart2_cts_grp1[] = { "uart2_cts_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static const char * const uart2_rts_grp0[] = { "uart2_rts_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static const char * const uart2_rts_grp1[] = { "uart2_rts_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static const char * const uart2_rxd_grp0[] = { "uart2_rxd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static const char * const uart2_rxd_grp1[] = { "uart2_rxd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static const char * const uart2_rxd_grp2[] = { "uart2_rxd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static const char * const uart2_txd_grp0[] = { "uart2_txd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static const char * const uart2_txd_grp1[] = { "uart2_txd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const char * const uart2_txd_grp2[] = { "uart2_txd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static const char * const uart3_cts_grp0[] = { "uart3_cts_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const char * const uart3_cts_grp1[] = { "uart3_cts_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static const char * const uart3_cts_grp2[] = { "uart3_cts_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static const char * const uart3_rts_grp0[] = { "uart3_rts_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static const char * const uart3_rts_grp1[] = { "uart3_rts_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const char * const uart3_rts_grp2[] = { "uart3_rts_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static const char * const uart3_rxd_grp0[] = { "uart3_rxd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static const char * const uart3_rxd_grp1[] = { "uart3_rxd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const char * const uart3_rxd_grp2[] = { "uart3_rxd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const char * const uart3_txd_grp0[] = { "uart3_txd_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static const char * const uart3_txd_grp1[] = { "uart3_txd_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static const char * const uart3_txd_grp2[] = { "uart3_txd_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const char * const uart4_basic_grp[] = { "uart4_basic_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const char * const uart4_cts_grp0[] = { "uart4_cts_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const char * const uart4_cts_grp1[] = { "uart4_cts_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const char * const uart4_cts_grp2[] = { "uart4_cts_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const char * const uart4_rts_grp0[] = { "uart4_rts_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static const char * const uart4_rts_grp1[] = { "uart4_rts_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static const char * const uart4_rts_grp2[] = { "uart4_rts_grp2", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const char * const usb0_drvvbus_grp0[] = { "usb0_drvvbus_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static const char * const usb0_drvvbus_grp1[] = { "usb0_drvvbus_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static const char * const usb1_drvvbus_grp0[] = { "usb1_drvvbus_grp0", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const char * const usb1_drvvbus_grp1[] = { "usb1_drvvbus_grp1", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static const char * const visbus_dout_grp[] = { "visbus_dout_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static const char * const vi_vip1_grp[] = { "vi_vip1_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const char * const vi_vip1_ext_grp[] = { "vi_vip1_ext_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static const char * const vi_vip1_low8bit_grp[] = { "vi_vip1_low8bit_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const char * const vi_vip1_high8bit_grp[] = { "vi_vip1_high8bit_grp", };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static struct atlas7_pad_mux gnss_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MUX(1, 119, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) MUX(1, 120, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) MUX(1, 121, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) MUX(1, 122, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) MUX(1, 123, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MUX(1, 124, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MUX(1, 125, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) MUX(1, 126, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) MUX(1, 127, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) MUX(1, 128, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) MUX(1, 22, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) MUX(1, 23, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) MUX(1, 24, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) MUX(1, 25, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) MUX(1, 26, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) MUX(1, 27, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MUX(1, 28, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) MUX(1, 29, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MUX(1, 30, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static struct atlas7_grp_mux gnss_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .pad_mux_count = ARRAY_SIZE(gnss_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .pad_mux_list = gnss_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static struct atlas7_pad_mux lcd_vip_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) MUX(1, 74, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) MUX(1, 75, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) MUX(1, 76, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) MUX(1, 77, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) MUX(1, 78, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) MUX(1, 79, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) MUX(1, 80, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) MUX(1, 81, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) MUX(1, 82, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) MUX(1, 83, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MUX(1, 84, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) MUX(1, 53, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) MUX(1, 54, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) MUX(1, 55, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) MUX(1, 56, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) MUX(1, 57, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) MUX(1, 58, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) MUX(1, 59, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) MUX(1, 60, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) MUX(1, 61, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) MUX(1, 62, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) MUX(1, 63, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) MUX(1, 64, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) MUX(1, 65, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) MUX(1, 66, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) MUX(1, 67, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) MUX(1, 68, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) MUX(1, 69, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) MUX(1, 70, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) MUX(1, 71, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) MUX(1, 72, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) MUX(1, 73, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) static struct atlas7_grp_mux lcd_vip_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .pad_mux_count = ARRAY_SIZE(lcd_vip_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .pad_mux_list = lcd_vip_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static struct atlas7_pad_mux sdio_i2s_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) MUX(1, 31, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) MUX(1, 32, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) MUX(1, 33, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) MUX(1, 34, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) MUX(1, 35, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) MUX(1, 36, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) MUX(1, 85, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) MUX(1, 86, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) MUX(1, 87, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) MUX(1, 88, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) MUX(1, 89, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) MUX(1, 90, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) MUX(1, 129, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) MUX(1, 130, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) MUX(1, 131, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) MUX(1, 132, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) MUX(1, 91, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) MUX(1, 92, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) MUX(1, 93, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) MUX(1, 94, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) MUX(1, 95, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) MUX(1, 96, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) MUX(1, 112, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) MUX(1, 113, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) MUX(1, 114, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) MUX(1, 115, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) MUX(1, 116, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) MUX(1, 117, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) MUX(1, 118, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static struct atlas7_grp_mux sdio_i2s_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .pad_mux_count = ARRAY_SIZE(sdio_i2s_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .pad_mux_list = sdio_i2s_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static struct atlas7_pad_mux sp_rgmii_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) MUX(1, 97, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) MUX(1, 98, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) MUX(1, 99, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) MUX(1, 100, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) MUX(1, 101, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) MUX(1, 102, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) MUX(1, 103, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) MUX(1, 104, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) MUX(1, 105, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) MUX(1, 106, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MUX(1, 107, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) MUX(1, 108, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) MUX(1, 109, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) MUX(1, 110, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) MUX(1, 111, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) MUX(1, 18, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) MUX(1, 19, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) MUX(1, 20, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) MUX(1, 21, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) MUX(1, 141, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) MUX(1, 142, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) MUX(1, 143, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) MUX(1, 144, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) MUX(1, 145, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) MUX(1, 146, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) MUX(1, 147, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) MUX(1, 148, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static struct atlas7_grp_mux sp_rgmii_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .pad_mux_count = ARRAY_SIZE(sp_rgmii_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .pad_mux_list = sp_rgmii_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static struct atlas7_pad_mux lvds_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) MUX(1, 157, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) MUX(1, 158, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) MUX(1, 155, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) MUX(1, 156, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) MUX(1, 153, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) MUX(1, 154, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) MUX(1, 151, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) MUX(1, 152, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) MUX(1, 149, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) MUX(1, 150, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static struct atlas7_grp_mux lvds_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .pad_mux_count = ARRAY_SIZE(lvds_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .pad_mux_list = lvds_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static struct atlas7_pad_mux jtag_uart_nand_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) MUX(1, 44, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) MUX(1, 43, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) MUX(1, 42, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) MUX(1, 41, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) MUX(1, 40, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) MUX(1, 39, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) MUX(1, 38, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) MUX(1, 37, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) MUX(1, 46, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) MUX(1, 47, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) MUX(1, 48, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) MUX(1, 49, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) MUX(1, 50, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) MUX(1, 52, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) MUX(1, 51, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) MUX(1, 45, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) MUX(1, 133, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) MUX(1, 134, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) MUX(1, 135, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) MUX(1, 136, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) MUX(1, 137, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) MUX(1, 138, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) MUX(1, 139, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) MUX(1, 140, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) MUX(1, 159, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) MUX(1, 160, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) MUX(1, 161, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) MUX(1, 162, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) MUX(1, 163, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static struct atlas7_grp_mux jtag_uart_nand_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .pad_mux_count = ARRAY_SIZE(jtag_uart_nand_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .pad_mux_list = jtag_uart_nand_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static struct atlas7_pad_mux rtc_gpio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) MUX(0, 0, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) MUX(0, 1, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) MUX(0, 2, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) MUX(0, 3, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) MUX(0, 4, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) MUX(0, 10, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) MUX(0, 11, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) MUX(0, 12, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) MUX(0, 13, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) MUX(0, 14, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) MUX(0, 15, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) MUX(0, 16, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) MUX(0, 17, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) MUX(0, 9, 0, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static struct atlas7_grp_mux rtc_gpio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .pad_mux_count = ARRAY_SIZE(rtc_gpio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .pad_mux_list = rtc_gpio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static struct atlas7_pad_mux audio_ac97_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) MUX(1, 113, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) MUX(1, 118, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) MUX(1, 115, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) MUX(1, 114, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static struct atlas7_grp_mux audio_ac97_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) .pad_mux_count = ARRAY_SIZE(audio_ac97_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) .pad_mux_list = audio_ac97_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static struct atlas7_pad_mux audio_digmic_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) MUX(1, 51, 3, 0xa10, 20, 0xa90, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static struct atlas7_grp_mux audio_digmic_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) .pad_mux_count = ARRAY_SIZE(audio_digmic_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) .pad_mux_list = audio_digmic_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static struct atlas7_pad_mux audio_digmic_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) MUX(1, 122, 5, 0xa10, 20, 0xa90, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static struct atlas7_grp_mux audio_digmic_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .pad_mux_count = ARRAY_SIZE(audio_digmic_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .pad_mux_list = audio_digmic_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static struct atlas7_pad_mux audio_digmic_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) MUX(1, 161, 7, 0xa10, 20, 0xa90, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static struct atlas7_grp_mux audio_digmic_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) .pad_mux_count = ARRAY_SIZE(audio_digmic_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) .pad_mux_list = audio_digmic_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static struct atlas7_pad_mux audio_func_dbg_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) MUX(1, 141, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) MUX(1, 144, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) MUX(1, 44, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) MUX(1, 43, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) MUX(1, 42, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) MUX(1, 41, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) MUX(1, 40, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) MUX(1, 39, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) MUX(1, 38, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) MUX(1, 37, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) MUX(1, 74, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) MUX(1, 75, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) MUX(1, 76, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) MUX(1, 77, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) MUX(1, 78, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) MUX(1, 79, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) MUX(1, 81, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) MUX(1, 113, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) MUX(1, 114, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) MUX(1, 118, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) MUX(1, 115, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) MUX(1, 49, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) MUX(1, 50, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) MUX(1, 142, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) MUX(1, 143, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) MUX(1, 80, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static struct atlas7_grp_mux audio_func_dbg_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .pad_mux_count = ARRAY_SIZE(audio_func_dbg_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .pad_mux_list = audio_func_dbg_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static struct atlas7_pad_mux audio_i2s_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) MUX(1, 118, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) MUX(1, 115, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) MUX(1, 116, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) MUX(1, 117, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) MUX(1, 112, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) MUX(1, 113, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) MUX(1, 114, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static struct atlas7_grp_mux audio_i2s_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .pad_mux_count = ARRAY_SIZE(audio_i2s_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .pad_mux_list = audio_i2s_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static struct atlas7_pad_mux audio_i2s_2ch_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) MUX(1, 118, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) MUX(1, 115, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) MUX(1, 112, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) MUX(1, 113, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) MUX(1, 114, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static struct atlas7_grp_mux audio_i2s_2ch_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .pad_mux_count = ARRAY_SIZE(audio_i2s_2ch_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .pad_mux_list = audio_i2s_2ch_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static struct atlas7_pad_mux audio_i2s_extclk_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) MUX(1, 112, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static struct atlas7_grp_mux audio_i2s_extclk_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .pad_mux_count = ARRAY_SIZE(audio_i2s_extclk_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .pad_mux_list = audio_i2s_extclk_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static struct atlas7_pad_mux audio_spdif_out_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) MUX(1, 112, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static struct atlas7_grp_mux audio_spdif_out_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .pad_mux_list = audio_spdif_out_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static struct atlas7_pad_mux audio_spdif_out_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) MUX(1, 116, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static struct atlas7_grp_mux audio_spdif_out_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .pad_mux_list = audio_spdif_out_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static struct atlas7_pad_mux audio_spdif_out_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) MUX(1, 142, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static struct atlas7_grp_mux audio_spdif_out_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .pad_mux_count = ARRAY_SIZE(audio_spdif_out_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .pad_mux_list = audio_spdif_out_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static struct atlas7_pad_mux audio_uart0_basic_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) MUX(1, 143, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) MUX(1, 142, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) MUX(1, 141, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) MUX(1, 144, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static struct atlas7_grp_mux audio_uart0_basic_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .pad_mux_count = ARRAY_SIZE(audio_uart0_basic_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .pad_mux_list = audio_uart0_basic_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static struct atlas7_pad_mux audio_uart0_urfs_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) MUX(1, 117, 5, 0xa10, 28, 0xa90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static struct atlas7_grp_mux audio_uart0_urfs_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) .pad_mux_list = audio_uart0_urfs_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static struct atlas7_pad_mux audio_uart0_urfs_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) MUX(1, 139, 3, 0xa10, 28, 0xa90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static struct atlas7_grp_mux audio_uart0_urfs_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .pad_mux_list = audio_uart0_urfs_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static struct atlas7_pad_mux audio_uart0_urfs_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) MUX(1, 163, 3, 0xa10, 28, 0xa90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static struct atlas7_grp_mux audio_uart0_urfs_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) .pad_mux_list = audio_uart0_urfs_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static struct atlas7_pad_mux audio_uart0_urfs_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) MUX(1, 162, 6, 0xa10, 28, 0xa90, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static struct atlas7_grp_mux audio_uart0_urfs_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) .pad_mux_count = ARRAY_SIZE(audio_uart0_urfs_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) .pad_mux_list = audio_uart0_urfs_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static struct atlas7_pad_mux audio_uart1_basic_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) MUX(1, 147, 1, 0xa10, 24, 0xa90, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) MUX(1, 146, 1, 0xa10, 25, 0xa90, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) MUX(1, 145, 1, 0xa10, 23, 0xa90, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) MUX(1, 148, 1, 0xa10, 22, 0xa90, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static struct atlas7_grp_mux audio_uart1_basic_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) .pad_mux_count = ARRAY_SIZE(audio_uart1_basic_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) .pad_mux_list = audio_uart1_basic_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) static struct atlas7_pad_mux audio_uart1_urfs_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) MUX(1, 117, 6, 0xa10, 29, 0xa90, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static struct atlas7_grp_mux audio_uart1_urfs_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) .pad_mux_list = audio_uart1_urfs_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static struct atlas7_pad_mux audio_uart1_urfs_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) MUX(1, 140, 3, 0xa10, 29, 0xa90, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static struct atlas7_grp_mux audio_uart1_urfs_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) .pad_mux_list = audio_uart1_urfs_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) static struct atlas7_pad_mux audio_uart1_urfs_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) MUX(1, 163, 4, 0xa10, 29, 0xa90, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static struct atlas7_grp_mux audio_uart1_urfs_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .pad_mux_count = ARRAY_SIZE(audio_uart1_urfs_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) .pad_mux_list = audio_uart1_urfs_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static struct atlas7_pad_mux audio_uart2_urfs_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) MUX(1, 139, 4, 0xa10, 30, 0xa90, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static struct atlas7_grp_mux audio_uart2_urfs_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) .pad_mux_list = audio_uart2_urfs_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static struct atlas7_pad_mux audio_uart2_urfs_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) MUX(1, 163, 6, 0xa10, 30, 0xa90, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static struct atlas7_grp_mux audio_uart2_urfs_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) .pad_mux_list = audio_uart2_urfs_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static struct atlas7_pad_mux audio_uart2_urfs_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) MUX(1, 96, 3, 0xa10, 30, 0xa90, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static struct atlas7_grp_mux audio_uart2_urfs_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) .pad_mux_count = ARRAY_SIZE(audio_uart2_urfs_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) .pad_mux_list = audio_uart2_urfs_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static struct atlas7_pad_mux audio_uart2_urxd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) MUX(1, 20, 2, 0xa00, 24, 0xa80, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static struct atlas7_grp_mux audio_uart2_urxd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .pad_mux_list = audio_uart2_urxd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static struct atlas7_pad_mux audio_uart2_urxd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) MUX(1, 109, 2, 0xa00, 24, 0xa80, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static struct atlas7_grp_mux audio_uart2_urxd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) .pad_mux_list = audio_uart2_urxd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static struct atlas7_pad_mux audio_uart2_urxd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) MUX(1, 93, 3, 0xa00, 24, 0xa80, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) static struct atlas7_grp_mux audio_uart2_urxd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) .pad_mux_count = ARRAY_SIZE(audio_uart2_urxd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) .pad_mux_list = audio_uart2_urxd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static struct atlas7_pad_mux audio_uart2_usclk_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) MUX(1, 19, 2, 0xa00, 23, 0xa80, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static struct atlas7_grp_mux audio_uart2_usclk_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .pad_mux_list = audio_uart2_usclk_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static struct atlas7_pad_mux audio_uart2_usclk_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) MUX(1, 101, 2, 0xa00, 23, 0xa80, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static struct atlas7_grp_mux audio_uart2_usclk_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) .pad_mux_list = audio_uart2_usclk_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static struct atlas7_pad_mux audio_uart2_usclk_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) MUX(1, 91, 3, 0xa00, 23, 0xa80, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static struct atlas7_grp_mux audio_uart2_usclk_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .pad_mux_count = ARRAY_SIZE(audio_uart2_usclk_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .pad_mux_list = audio_uart2_usclk_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static struct atlas7_pad_mux audio_uart2_utfs_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) MUX(1, 18, 2, 0xa00, 22, 0xa80, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static struct atlas7_grp_mux audio_uart2_utfs_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .pad_mux_list = audio_uart2_utfs_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static struct atlas7_pad_mux audio_uart2_utfs_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) MUX(1, 111, 2, 0xa00, 22, 0xa80, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static struct atlas7_grp_mux audio_uart2_utfs_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .pad_mux_list = audio_uart2_utfs_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static struct atlas7_pad_mux audio_uart2_utfs_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) MUX(1, 94, 3, 0xa00, 22, 0xa80, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static struct atlas7_grp_mux audio_uart2_utfs_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) .pad_mux_count = ARRAY_SIZE(audio_uart2_utfs_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) .pad_mux_list = audio_uart2_utfs_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static struct atlas7_pad_mux audio_uart2_utxd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) MUX(1, 21, 2, 0xa00, 25, 0xa80, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static struct atlas7_grp_mux audio_uart2_utxd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) .pad_mux_list = audio_uart2_utxd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static struct atlas7_pad_mux audio_uart2_utxd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) MUX(1, 110, 2, 0xa00, 25, 0xa80, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static struct atlas7_grp_mux audio_uart2_utxd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .pad_mux_list = audio_uart2_utxd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static struct atlas7_pad_mux audio_uart2_utxd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) MUX(1, 92, 3, 0xa00, 25, 0xa80, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static struct atlas7_grp_mux audio_uart2_utxd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) .pad_mux_count = ARRAY_SIZE(audio_uart2_utxd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) .pad_mux_list = audio_uart2_utxd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static struct atlas7_pad_mux c_can_trnsvr_en_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) MUX(0, 2, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static struct atlas7_grp_mux c_can_trnsvr_en_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .pad_mux_list = c_can_trnsvr_en_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static struct atlas7_pad_mux c_can_trnsvr_en_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) MUX(0, 0, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static struct atlas7_grp_mux c_can_trnsvr_en_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_en_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .pad_mux_list = c_can_trnsvr_en_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static struct atlas7_pad_mux c_can_trnsvr_intr_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) MUX(0, 1, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) static struct atlas7_grp_mux c_can_trnsvr_intr_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_intr_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .pad_mux_list = c_can_trnsvr_intr_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static struct atlas7_pad_mux c_can_trnsvr_stb_n_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) MUX(0, 3, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static struct atlas7_grp_mux c_can_trnsvr_stb_n_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .pad_mux_count = ARRAY_SIZE(c_can_trnsvr_stb_n_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) .pad_mux_list = c_can_trnsvr_stb_n_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static struct atlas7_pad_mux c0_can_rxd_trnsv0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) MUX(0, 11, 1, 0xa08, 9, 0xa88, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static struct atlas7_grp_mux c0_can_rxd_trnsv0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) .pad_mux_list = c0_can_rxd_trnsv0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static struct atlas7_pad_mux c0_can_rxd_trnsv1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) MUX(0, 2, 5, 0xa10, 9, 0xa90, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static struct atlas7_grp_mux c0_can_rxd_trnsv1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) .pad_mux_count = ARRAY_SIZE(c0_can_rxd_trnsv1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) .pad_mux_list = c0_can_rxd_trnsv1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static struct atlas7_pad_mux c0_can_txd_trnsv0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) MUX(0, 10, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static struct atlas7_grp_mux c0_can_txd_trnsv0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) .pad_mux_list = c0_can_txd_trnsv0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static struct atlas7_pad_mux c0_can_txd_trnsv1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) MUX(0, 3, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static struct atlas7_grp_mux c0_can_txd_trnsv1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .pad_mux_count = ARRAY_SIZE(c0_can_txd_trnsv1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .pad_mux_list = c0_can_txd_trnsv1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) static struct atlas7_pad_mux c1_can_rxd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) MUX(1, 138, 2, 0xa00, 4, 0xa80, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static struct atlas7_grp_mux c1_can_rxd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) .pad_mux_list = c1_can_rxd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static struct atlas7_pad_mux c1_can_rxd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) MUX(1, 147, 2, 0xa00, 4, 0xa80, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static struct atlas7_grp_mux c1_can_rxd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .pad_mux_list = c1_can_rxd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static struct atlas7_pad_mux c1_can_rxd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) MUX(0, 2, 2, 0xa00, 4, 0xa80, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) static struct atlas7_grp_mux c1_can_rxd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .pad_mux_list = c1_can_rxd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static struct atlas7_pad_mux c1_can_rxd_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) MUX(1, 162, 4, 0xa00, 4, 0xa80, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static struct atlas7_grp_mux c1_can_rxd_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) .pad_mux_count = ARRAY_SIZE(c1_can_rxd_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) .pad_mux_list = c1_can_rxd_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static struct atlas7_pad_mux c1_can_txd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) MUX(1, 137, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static struct atlas7_grp_mux c1_can_txd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) .pad_mux_list = c1_can_txd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static struct atlas7_pad_mux c1_can_txd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) MUX(1, 146, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static struct atlas7_grp_mux c1_can_txd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .pad_mux_list = c1_can_txd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static struct atlas7_pad_mux c1_can_txd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) MUX(0, 3, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static struct atlas7_grp_mux c1_can_txd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) .pad_mux_list = c1_can_txd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static struct atlas7_pad_mux c1_can_txd_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) MUX(1, 161, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) static struct atlas7_grp_mux c1_can_txd_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .pad_mux_count = ARRAY_SIZE(c1_can_txd_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .pad_mux_list = c1_can_txd_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static struct atlas7_pad_mux ca_audio_lpc_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) MUX(1, 62, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) MUX(1, 63, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) MUX(1, 64, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) MUX(1, 65, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) MUX(1, 66, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) MUX(1, 67, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) MUX(1, 68, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) MUX(1, 69, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) MUX(1, 70, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) MUX(1, 71, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static struct atlas7_grp_mux ca_audio_lpc_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .pad_mux_count = ARRAY_SIZE(ca_audio_lpc_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .pad_mux_list = ca_audio_lpc_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) static struct atlas7_pad_mux ca_bt_lpc_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) MUX(1, 85, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) MUX(1, 86, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) MUX(1, 87, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) MUX(1, 88, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) MUX(1, 89, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) MUX(1, 90, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static struct atlas7_grp_mux ca_bt_lpc_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .pad_mux_count = ARRAY_SIZE(ca_bt_lpc_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .pad_mux_list = ca_bt_lpc_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static struct atlas7_pad_mux ca_coex_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) MUX(1, 129, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) MUX(1, 130, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) MUX(1, 131, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) MUX(1, 132, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) static struct atlas7_grp_mux ca_coex_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .pad_mux_count = ARRAY_SIZE(ca_coex_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .pad_mux_list = ca_coex_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static struct atlas7_pad_mux ca_curator_lpc_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) MUX(1, 57, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) MUX(1, 58, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) MUX(1, 59, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) MUX(1, 60, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static struct atlas7_grp_mux ca_curator_lpc_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .pad_mux_count = ARRAY_SIZE(ca_curator_lpc_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .pad_mux_list = ca_curator_lpc_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static struct atlas7_pad_mux ca_pcm_debug_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) MUX(1, 91, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) MUX(1, 93, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) MUX(1, 94, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) MUX(1, 92, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static struct atlas7_grp_mux ca_pcm_debug_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .pad_mux_count = ARRAY_SIZE(ca_pcm_debug_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .pad_mux_list = ca_pcm_debug_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static struct atlas7_pad_mux ca_pio_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) MUX(1, 121, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) MUX(1, 122, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) MUX(1, 125, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) MUX(1, 126, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) MUX(1, 38, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) MUX(1, 37, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) MUX(1, 47, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) MUX(1, 49, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) MUX(1, 50, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) MUX(1, 54, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) MUX(1, 55, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) MUX(1, 56, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static struct atlas7_grp_mux ca_pio_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .pad_mux_count = ARRAY_SIZE(ca_pio_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .pad_mux_list = ca_pio_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static struct atlas7_pad_mux ca_sdio_debug_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) MUX(1, 40, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) MUX(1, 39, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) MUX(1, 44, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) MUX(1, 43, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) MUX(1, 42, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) MUX(1, 41, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static struct atlas7_grp_mux ca_sdio_debug_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .pad_mux_count = ARRAY_SIZE(ca_sdio_debug_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .pad_mux_list = ca_sdio_debug_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) static struct atlas7_pad_mux ca_spi_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) MUX(1, 82, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) MUX(1, 79, 5, 0xa08, 6, 0xa88, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) MUX(1, 80, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) MUX(1, 81, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) static struct atlas7_grp_mux ca_spi_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .pad_mux_count = ARRAY_SIZE(ca_spi_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .pad_mux_list = ca_spi_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) static struct atlas7_pad_mux ca_trb_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) MUX(1, 91, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) MUX(1, 93, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) MUX(1, 94, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) MUX(1, 95, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) MUX(1, 96, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) MUX(1, 78, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) MUX(1, 74, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) MUX(1, 75, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) MUX(1, 76, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) MUX(1, 77, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) static struct atlas7_grp_mux ca_trb_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) .pad_mux_count = ARRAY_SIZE(ca_trb_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) .pad_mux_list = ca_trb_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static struct atlas7_pad_mux ca_uart_debug_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) MUX(1, 136, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) MUX(1, 135, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) MUX(1, 134, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) MUX(1, 133, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static struct atlas7_grp_mux ca_uart_debug_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) .pad_mux_count = ARRAY_SIZE(ca_uart_debug_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .pad_mux_list = ca_uart_debug_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static struct atlas7_pad_mux clkc_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) MUX(1, 30, 2, 0xa08, 14, 0xa88, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) MUX(1, 47, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) static struct atlas7_grp_mux clkc_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .pad_mux_count = ARRAY_SIZE(clkc_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .pad_mux_list = clkc_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) static struct atlas7_pad_mux clkc_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) MUX(1, 78, 3, 0xa08, 14, 0xa88, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) MUX(1, 54, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static struct atlas7_grp_mux clkc_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .pad_mux_count = ARRAY_SIZE(clkc_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) .pad_mux_list = clkc_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static struct atlas7_pad_mux gn_gnss_i2c_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) MUX(1, 128, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) MUX(1, 127, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) static struct atlas7_grp_mux gn_gnss_i2c_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) .pad_mux_count = ARRAY_SIZE(gn_gnss_i2c_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) .pad_mux_list = gn_gnss_i2c_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static struct atlas7_pad_mux gn_gnss_uart_nopause_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) MUX(1, 134, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) MUX(1, 133, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static struct atlas7_grp_mux gn_gnss_uart_nopause_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_nopause_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) .pad_mux_list = gn_gnss_uart_nopause_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static struct atlas7_pad_mux gn_gnss_uart_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) MUX(1, 134, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) MUX(1, 133, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) MUX(1, 136, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) MUX(1, 135, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static struct atlas7_grp_mux gn_gnss_uart_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .pad_mux_count = ARRAY_SIZE(gn_gnss_uart_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) .pad_mux_list = gn_gnss_uart_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static struct atlas7_pad_mux gn_trg_spi_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) MUX(1, 22, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) MUX(1, 25, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) MUX(1, 23, 1, 0xa00, 10, 0xa80, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) MUX(1, 24, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static struct atlas7_grp_mux gn_trg_spi_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .pad_mux_list = gn_trg_spi_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) static struct atlas7_pad_mux gn_trg_spi_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) MUX(1, 82, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) MUX(1, 79, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) MUX(1, 80, 3, 0xa00, 10, 0xa80, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) MUX(1, 81, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) static struct atlas7_grp_mux gn_trg_spi_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .pad_mux_count = ARRAY_SIZE(gn_trg_spi_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) .pad_mux_list = gn_trg_spi_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static struct atlas7_pad_mux cvbs_dbg_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) MUX(1, 54, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) MUX(1, 53, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) MUX(1, 82, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) MUX(1, 74, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) MUX(1, 75, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) MUX(1, 76, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) MUX(1, 77, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) MUX(1, 78, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) MUX(1, 79, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) MUX(1, 80, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) MUX(1, 81, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) MUX(1, 83, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) MUX(1, 84, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) MUX(1, 73, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) MUX(1, 55, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) MUX(1, 56, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static struct atlas7_grp_mux cvbs_dbg_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) .pad_mux_list = cvbs_dbg_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static struct atlas7_pad_mux cvbs_dbg_test_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) MUX(1, 57, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static struct atlas7_grp_mux cvbs_dbg_test_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .pad_mux_list = cvbs_dbg_test_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) static struct atlas7_pad_mux cvbs_dbg_test_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) MUX(1, 58, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static struct atlas7_grp_mux cvbs_dbg_test_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .pad_mux_list = cvbs_dbg_test_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) static struct atlas7_pad_mux cvbs_dbg_test_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) MUX(1, 59, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static struct atlas7_grp_mux cvbs_dbg_test_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .pad_mux_list = cvbs_dbg_test_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static struct atlas7_pad_mux cvbs_dbg_test_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) MUX(1, 60, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static struct atlas7_grp_mux cvbs_dbg_test_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .pad_mux_list = cvbs_dbg_test_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) static struct atlas7_pad_mux cvbs_dbg_test_grp4_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) MUX(1, 61, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) static struct atlas7_grp_mux cvbs_dbg_test_grp4_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp4_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .pad_mux_list = cvbs_dbg_test_grp4_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) static struct atlas7_pad_mux cvbs_dbg_test_grp5_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) MUX(1, 62, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) static struct atlas7_grp_mux cvbs_dbg_test_grp5_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp5_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .pad_mux_list = cvbs_dbg_test_grp5_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) static struct atlas7_pad_mux cvbs_dbg_test_grp6_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) MUX(1, 63, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) static struct atlas7_grp_mux cvbs_dbg_test_grp6_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp6_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .pad_mux_list = cvbs_dbg_test_grp6_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) static struct atlas7_pad_mux cvbs_dbg_test_grp7_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) MUX(1, 64, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static struct atlas7_grp_mux cvbs_dbg_test_grp7_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp7_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .pad_mux_list = cvbs_dbg_test_grp7_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static struct atlas7_pad_mux cvbs_dbg_test_grp8_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) MUX(1, 65, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) static struct atlas7_grp_mux cvbs_dbg_test_grp8_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp8_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .pad_mux_list = cvbs_dbg_test_grp8_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static struct atlas7_pad_mux cvbs_dbg_test_grp9_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) MUX(1, 66, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static struct atlas7_grp_mux cvbs_dbg_test_grp9_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp9_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) .pad_mux_list = cvbs_dbg_test_grp9_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static struct atlas7_pad_mux cvbs_dbg_test_grp10_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) MUX(1, 67, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static struct atlas7_grp_mux cvbs_dbg_test_grp10_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp10_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .pad_mux_list = cvbs_dbg_test_grp10_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static struct atlas7_pad_mux cvbs_dbg_test_grp11_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) MUX(1, 68, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) static struct atlas7_grp_mux cvbs_dbg_test_grp11_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp11_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .pad_mux_list = cvbs_dbg_test_grp11_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static struct atlas7_pad_mux cvbs_dbg_test_grp12_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) MUX(1, 69, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) static struct atlas7_grp_mux cvbs_dbg_test_grp12_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp12_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) .pad_mux_list = cvbs_dbg_test_grp12_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static struct atlas7_pad_mux cvbs_dbg_test_grp13_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) MUX(1, 70, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) static struct atlas7_grp_mux cvbs_dbg_test_grp13_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp13_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .pad_mux_list = cvbs_dbg_test_grp13_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) static struct atlas7_pad_mux cvbs_dbg_test_grp14_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) MUX(1, 71, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) static struct atlas7_grp_mux cvbs_dbg_test_grp14_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp14_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) .pad_mux_list = cvbs_dbg_test_grp14_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static struct atlas7_pad_mux cvbs_dbg_test_grp15_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) MUX(1, 72, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static struct atlas7_grp_mux cvbs_dbg_test_grp15_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .pad_mux_count = ARRAY_SIZE(cvbs_dbg_test_grp15_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .pad_mux_list = cvbs_dbg_test_grp15_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) static struct atlas7_pad_mux gn_gnss_power_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) MUX(1, 123, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) MUX(1, 124, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) MUX(1, 121, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) MUX(1, 122, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) MUX(1, 125, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) MUX(1, 120, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static struct atlas7_grp_mux gn_gnss_power_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) .pad_mux_count = ARRAY_SIZE(gn_gnss_power_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) .pad_mux_list = gn_gnss_power_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) static struct atlas7_pad_mux gn_gnss_sw_status_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) MUX(1, 57, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) MUX(1, 58, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) MUX(1, 59, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) MUX(1, 60, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) MUX(1, 61, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) MUX(1, 62, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) MUX(1, 63, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) MUX(1, 64, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) MUX(1, 65, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) MUX(1, 66, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) MUX(1, 67, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) MUX(1, 68, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) MUX(1, 69, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) MUX(1, 70, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) MUX(1, 71, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) MUX(1, 72, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) MUX(1, 53, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) MUX(1, 55, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) MUX(1, 56, 7, 0xa08, 12, 0xa88, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) MUX(1, 54, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) static struct atlas7_grp_mux gn_gnss_sw_status_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) .pad_mux_count = ARRAY_SIZE(gn_gnss_sw_status_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .pad_mux_list = gn_gnss_sw_status_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static struct atlas7_pad_mux gn_gnss_eclk_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) MUX(1, 113, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static struct atlas7_grp_mux gn_gnss_eclk_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .pad_mux_count = ARRAY_SIZE(gn_gnss_eclk_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .pad_mux_list = gn_gnss_eclk_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) static struct atlas7_pad_mux gn_gnss_irq1_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) MUX(1, 112, 4, 0xa08, 10, 0xa88, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static struct atlas7_grp_mux gn_gnss_irq1_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) .pad_mux_count = ARRAY_SIZE(gn_gnss_irq1_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) .pad_mux_list = gn_gnss_irq1_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static struct atlas7_pad_mux gn_gnss_irq2_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) MUX(1, 118, 4, 0xa08, 11, 0xa88, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static struct atlas7_grp_mux gn_gnss_irq2_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .pad_mux_count = ARRAY_SIZE(gn_gnss_irq2_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .pad_mux_list = gn_gnss_irq2_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static struct atlas7_pad_mux gn_gnss_tm_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) MUX(1, 115, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static struct atlas7_grp_mux gn_gnss_tm_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .pad_mux_count = ARRAY_SIZE(gn_gnss_tm_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) .pad_mux_list = gn_gnss_tm_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static struct atlas7_pad_mux gn_gnss_tsync_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) MUX(1, 114, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static struct atlas7_grp_mux gn_gnss_tsync_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .pad_mux_count = ARRAY_SIZE(gn_gnss_tsync_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .pad_mux_list = gn_gnss_tsync_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) static struct atlas7_pad_mux gn_io_gnsssys_sw_cfg_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) MUX(1, 44, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) MUX(1, 43, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) MUX(1, 42, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) MUX(1, 41, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) MUX(1, 40, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) MUX(1, 39, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) MUX(1, 38, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) MUX(1, 37, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) MUX(1, 49, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) MUX(1, 50, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) MUX(1, 91, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) MUX(1, 92, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) MUX(1, 93, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) MUX(1, 94, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) MUX(1, 95, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) MUX(1, 96, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static struct atlas7_grp_mux gn_io_gnsssys_sw_cfg_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .pad_mux_count = ARRAY_SIZE(gn_io_gnsssys_sw_cfg_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .pad_mux_list = gn_io_gnsssys_sw_cfg_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static struct atlas7_pad_mux gn_trg_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) MUX(1, 29, 1, 0xa00, 6, 0xa80, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) MUX(1, 28, 1, 0xa00, 7, 0xa80, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) MUX(1, 26, 1, 0xa00, 8, 0xa80, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) MUX(1, 27, 1, 0xa00, 9, 0xa80, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) static struct atlas7_grp_mux gn_trg_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .pad_mux_count = ARRAY_SIZE(gn_trg_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .pad_mux_list = gn_trg_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static struct atlas7_pad_mux gn_trg_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) MUX(1, 77, 3, 0xa00, 6, 0xa80, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) MUX(1, 76, 3, 0xa00, 7, 0xa80, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) MUX(1, 74, 3, 0xa00, 8, 0xa80, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) MUX(1, 75, 3, 0xa00, 9, 0xa80, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) static struct atlas7_grp_mux gn_trg_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) .pad_mux_count = ARRAY_SIZE(gn_trg_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) .pad_mux_list = gn_trg_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) static struct atlas7_pad_mux gn_trg_shutdown_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) MUX(1, 30, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) static struct atlas7_grp_mux gn_trg_shutdown_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .pad_mux_list = gn_trg_shutdown_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) static struct atlas7_pad_mux gn_trg_shutdown_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) MUX(1, 83, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static struct atlas7_grp_mux gn_trg_shutdown_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .pad_mux_list = gn_trg_shutdown_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) static struct atlas7_pad_mux gn_trg_shutdown_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) MUX(1, 117, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static struct atlas7_grp_mux gn_trg_shutdown_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .pad_mux_list = gn_trg_shutdown_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) static struct atlas7_pad_mux gn_trg_shutdown_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) MUX(1, 123, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) static struct atlas7_grp_mux gn_trg_shutdown_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .pad_mux_count = ARRAY_SIZE(gn_trg_shutdown_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) .pad_mux_list = gn_trg_shutdown_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) static struct atlas7_pad_mux i2c0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) MUX(1, 128, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) MUX(1, 127, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) static struct atlas7_grp_mux i2c0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) .pad_mux_count = ARRAY_SIZE(i2c0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) .pad_mux_list = i2c0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) static struct atlas7_pad_mux i2c1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) MUX(1, 126, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) MUX(1, 125, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static struct atlas7_grp_mux i2c1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .pad_mux_count = ARRAY_SIZE(i2c1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) .pad_mux_list = i2c1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static struct atlas7_pad_mux i2s0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) MUX(1, 91, 2, 0xa10, 12, 0xa90, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) MUX(1, 93, 2, 0xa10, 13, 0xa90, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) MUX(1, 94, 2, 0xa10, 14, 0xa90, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) MUX(1, 92, 2, 0xa10, 15, 0xa90, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static struct atlas7_grp_mux i2s0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) .pad_mux_count = ARRAY_SIZE(i2s0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .pad_mux_list = i2s0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) static struct atlas7_pad_mux i2s1_basic_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) MUX(1, 95, 2, 0xa10, 16, 0xa90, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) MUX(1, 96, 2, 0xa10, 19, 0xa90, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) static struct atlas7_grp_mux i2s1_basic_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) .pad_mux_count = ARRAY_SIZE(i2s1_basic_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) .pad_mux_list = i2s1_basic_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) static struct atlas7_pad_mux i2s1_rxd0_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) MUX(1, 61, 4, 0xa10, 17, 0xa90, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static struct atlas7_grp_mux i2s1_rxd0_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .pad_mux_list = i2s1_rxd0_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static struct atlas7_pad_mux i2s1_rxd0_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) MUX(1, 131, 4, 0xa10, 17, 0xa90, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) static struct atlas7_grp_mux i2s1_rxd0_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .pad_mux_list = i2s1_rxd0_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static struct atlas7_pad_mux i2s1_rxd0_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) MUX(1, 129, 2, 0xa10, 17, 0xa90, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static struct atlas7_grp_mux i2s1_rxd0_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) .pad_mux_list = i2s1_rxd0_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) static struct atlas7_pad_mux i2s1_rxd0_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) MUX(1, 117, 7, 0xa10, 17, 0xa90, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static struct atlas7_grp_mux i2s1_rxd0_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .pad_mux_list = i2s1_rxd0_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) static struct atlas7_pad_mux i2s1_rxd0_grp4_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) MUX(1, 83, 4, 0xa10, 17, 0xa90, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) static struct atlas7_grp_mux i2s1_rxd0_grp4_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) .pad_mux_count = ARRAY_SIZE(i2s1_rxd0_grp4_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .pad_mux_list = i2s1_rxd0_grp4_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) static struct atlas7_pad_mux i2s1_rxd1_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) MUX(1, 72, 4, 0xa10, 18, 0xa90, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) static struct atlas7_grp_mux i2s1_rxd1_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .pad_mux_list = i2s1_rxd1_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) static struct atlas7_pad_mux i2s1_rxd1_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) MUX(1, 132, 4, 0xa10, 18, 0xa90, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static struct atlas7_grp_mux i2s1_rxd1_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) .pad_mux_list = i2s1_rxd1_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) static struct atlas7_pad_mux i2s1_rxd1_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) MUX(1, 130, 2, 0xa10, 18, 0xa90, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) static struct atlas7_grp_mux i2s1_rxd1_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .pad_mux_list = i2s1_rxd1_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) static struct atlas7_pad_mux i2s1_rxd1_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) MUX(1, 118, 7, 0xa10, 18, 0xa90, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static struct atlas7_grp_mux i2s1_rxd1_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) .pad_mux_list = i2s1_rxd1_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) static struct atlas7_pad_mux i2s1_rxd1_grp4_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) MUX(1, 84, 4, 0xa10, 18, 0xa90, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) static struct atlas7_grp_mux i2s1_rxd1_grp4_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .pad_mux_count = ARRAY_SIZE(i2s1_rxd1_grp4_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) .pad_mux_list = i2s1_rxd1_grp4_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) static struct atlas7_pad_mux jtag_jt_dbg_nsrst_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) MUX(1, 125, 5, 0xa08, 2, 0xa88, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) static struct atlas7_grp_mux jtag_jt_dbg_nsrst_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .pad_mux_count = ARRAY_SIZE(jtag_jt_dbg_nsrst_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .pad_mux_list = jtag_jt_dbg_nsrst_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) static struct atlas7_pad_mux jtag_ntrst_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) MUX(0, 4, 3, 0xa08, 3, 0xa88, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) static struct atlas7_grp_mux jtag_ntrst_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .pad_mux_list = jtag_ntrst_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static struct atlas7_pad_mux jtag_ntrst_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) MUX(1, 163, 1, 0xa08, 3, 0xa88, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) static struct atlas7_grp_mux jtag_ntrst_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .pad_mux_count = ARRAY_SIZE(jtag_ntrst_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .pad_mux_list = jtag_ntrst_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static struct atlas7_pad_mux jtag_swdiotms_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) MUX(0, 2, 3, 0xa10, 10, 0xa90, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static struct atlas7_grp_mux jtag_swdiotms_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .pad_mux_list = jtag_swdiotms_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static struct atlas7_pad_mux jtag_swdiotms_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) MUX(1, 160, 1, 0xa10, 10, 0xa90, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) static struct atlas7_grp_mux jtag_swdiotms_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .pad_mux_count = ARRAY_SIZE(jtag_swdiotms_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .pad_mux_list = jtag_swdiotms_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static struct atlas7_pad_mux jtag_tck_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) MUX(0, 0, 3, 0xa10, 11, 0xa90, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) static struct atlas7_grp_mux jtag_tck_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) .pad_mux_count = ARRAY_SIZE(jtag_tck_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) .pad_mux_list = jtag_tck_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static struct atlas7_pad_mux jtag_tck_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) MUX(1, 161, 1, 0xa10, 11, 0xa90, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) static struct atlas7_grp_mux jtag_tck_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .pad_mux_count = ARRAY_SIZE(jtag_tck_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .pad_mux_list = jtag_tck_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) static struct atlas7_pad_mux jtag_tdi_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) MUX(0, 1, 3, 0xa10, 31, 0xa90, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) static struct atlas7_grp_mux jtag_tdi_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .pad_mux_list = jtag_tdi_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) static struct atlas7_pad_mux jtag_tdi_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) MUX(1, 162, 1, 0xa10, 31, 0xa90, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static struct atlas7_grp_mux jtag_tdi_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .pad_mux_count = ARRAY_SIZE(jtag_tdi_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .pad_mux_list = jtag_tdi_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) static struct atlas7_pad_mux jtag_tdo_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) MUX(0, 3, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) static struct atlas7_grp_mux jtag_tdo_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .pad_mux_list = jtag_tdo_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) static struct atlas7_pad_mux jtag_tdo_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) MUX(1, 159, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static struct atlas7_grp_mux jtag_tdo_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) .pad_mux_count = ARRAY_SIZE(jtag_tdo_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .pad_mux_list = jtag_tdo_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) static struct atlas7_pad_mux ks_kas_spi_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) MUX(1, 141, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) MUX(1, 144, 2, 0xa08, 8, 0xa88, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) MUX(1, 143, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) MUX(1, 142, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static struct atlas7_grp_mux ks_kas_spi_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) .pad_mux_count = ARRAY_SIZE(ks_kas_spi_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) .pad_mux_list = ks_kas_spi_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) static struct atlas7_pad_mux ld_ldd_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) MUX(1, 57, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) MUX(1, 58, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) MUX(1, 59, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) MUX(1, 60, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) MUX(1, 61, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) MUX(1, 62, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) MUX(1, 63, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) MUX(1, 64, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) MUX(1, 65, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) MUX(1, 66, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) MUX(1, 67, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) MUX(1, 68, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) MUX(1, 69, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) MUX(1, 70, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) MUX(1, 71, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) MUX(1, 72, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) MUX(1, 74, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) MUX(1, 75, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) MUX(1, 76, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) MUX(1, 77, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) MUX(1, 78, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) MUX(1, 79, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) MUX(1, 80, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) MUX(1, 81, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) MUX(1, 56, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) MUX(1, 53, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) static struct atlas7_grp_mux ld_ldd_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) .pad_mux_count = ARRAY_SIZE(ld_ldd_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) .pad_mux_list = ld_ldd_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static struct atlas7_pad_mux ld_ldd_16bit_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) MUX(1, 57, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) MUX(1, 58, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) MUX(1, 59, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) MUX(1, 60, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) MUX(1, 61, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) MUX(1, 62, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) MUX(1, 63, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) MUX(1, 64, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) MUX(1, 65, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) MUX(1, 66, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) MUX(1, 67, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) MUX(1, 68, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) MUX(1, 69, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) MUX(1, 70, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) MUX(1, 71, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) MUX(1, 72, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) MUX(1, 56, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) MUX(1, 53, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) static struct atlas7_grp_mux ld_ldd_16bit_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) .pad_mux_count = ARRAY_SIZE(ld_ldd_16bit_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) .pad_mux_list = ld_ldd_16bit_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static struct atlas7_pad_mux ld_ldd_fck_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) MUX(1, 55, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) static struct atlas7_grp_mux ld_ldd_fck_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) .pad_mux_count = ARRAY_SIZE(ld_ldd_fck_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) .pad_mux_list = ld_ldd_fck_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) static struct atlas7_pad_mux ld_ldd_lck_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) MUX(1, 54, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) static struct atlas7_grp_mux ld_ldd_lck_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) .pad_mux_count = ARRAY_SIZE(ld_ldd_lck_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) .pad_mux_list = ld_ldd_lck_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static struct atlas7_pad_mux lr_lcdrom_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) MUX(1, 73, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) MUX(1, 54, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) MUX(1, 57, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) MUX(1, 58, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) MUX(1, 59, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) MUX(1, 60, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) MUX(1, 61, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) MUX(1, 62, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) MUX(1, 63, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) MUX(1, 64, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) MUX(1, 65, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) MUX(1, 66, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) MUX(1, 67, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) MUX(1, 68, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) MUX(1, 69, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) MUX(1, 70, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) MUX(1, 71, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) MUX(1, 72, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) MUX(1, 56, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) MUX(1, 53, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) MUX(1, 55, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) static struct atlas7_grp_mux lr_lcdrom_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) .pad_mux_count = ARRAY_SIZE(lr_lcdrom_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) .pad_mux_list = lr_lcdrom_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static struct atlas7_pad_mux lvds_analog_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) MUX(1, 149, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) MUX(1, 150, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) MUX(1, 151, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) MUX(1, 152, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) MUX(1, 153, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) MUX(1, 154, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) MUX(1, 155, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) MUX(1, 156, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) MUX(1, 157, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) MUX(1, 158, 8, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) static struct atlas7_grp_mux lvds_analog_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) .pad_mux_count = ARRAY_SIZE(lvds_analog_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .pad_mux_list = lvds_analog_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) static struct atlas7_pad_mux nd_df_basic_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) MUX(1, 44, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) MUX(1, 43, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) MUX(1, 42, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) MUX(1, 41, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) MUX(1, 40, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) MUX(1, 39, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) MUX(1, 38, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) MUX(1, 37, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) MUX(1, 47, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) MUX(1, 46, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) MUX(1, 52, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) MUX(1, 45, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) MUX(1, 49, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) MUX(1, 50, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) MUX(1, 48, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) static struct atlas7_grp_mux nd_df_basic_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) .pad_mux_count = ARRAY_SIZE(nd_df_basic_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) .pad_mux_list = nd_df_basic_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) static struct atlas7_pad_mux nd_df_wp_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) MUX(1, 124, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) static struct atlas7_grp_mux nd_df_wp_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) .pad_mux_count = ARRAY_SIZE(nd_df_wp_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) .pad_mux_list = nd_df_wp_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) static struct atlas7_pad_mux nd_df_cs_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) MUX(1, 51, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) static struct atlas7_grp_mux nd_df_cs_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) .pad_mux_count = ARRAY_SIZE(nd_df_cs_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) .pad_mux_list = nd_df_cs_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) static struct atlas7_pad_mux ps_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) MUX(1, 120, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) MUX(1, 119, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) MUX(1, 121, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) static struct atlas7_grp_mux ps_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) .pad_mux_count = ARRAY_SIZE(ps_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) .pad_mux_list = ps_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) static struct atlas7_pad_mux ps_no_dir_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) MUX(1, 119, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) static struct atlas7_grp_mux ps_no_dir_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) .pad_mux_count = ARRAY_SIZE(ps_no_dir_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) .pad_mux_list = ps_no_dir_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) static struct atlas7_pad_mux pwc_core_on_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) MUX(0, 8, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) static struct atlas7_grp_mux pwc_core_on_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) .pad_mux_count = ARRAY_SIZE(pwc_core_on_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) .pad_mux_list = pwc_core_on_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) static struct atlas7_pad_mux pwc_ext_on_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) MUX(0, 6, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) static struct atlas7_grp_mux pwc_ext_on_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) .pad_mux_count = ARRAY_SIZE(pwc_ext_on_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) .pad_mux_list = pwc_ext_on_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) static struct atlas7_pad_mux pwc_gpio3_clk_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) MUX(0, 3, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) static struct atlas7_grp_mux pwc_gpio3_clk_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) .pad_mux_count = ARRAY_SIZE(pwc_gpio3_clk_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) .pad_mux_list = pwc_gpio3_clk_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) static struct atlas7_pad_mux pwc_io_on_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) MUX(0, 9, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) static struct atlas7_grp_mux pwc_io_on_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) .pad_mux_count = ARRAY_SIZE(pwc_io_on_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) .pad_mux_list = pwc_io_on_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static struct atlas7_pad_mux pwc_lowbatt_b_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) MUX(0, 4, 1, 0xa08, 4, 0xa88, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) static struct atlas7_grp_mux pwc_lowbatt_b_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) .pad_mux_count = ARRAY_SIZE(pwc_lowbatt_b_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) .pad_mux_list = pwc_lowbatt_b_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) static struct atlas7_pad_mux pwc_mem_on_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) MUX(0, 7, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) static struct atlas7_grp_mux pwc_mem_on_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) .pad_mux_count = ARRAY_SIZE(pwc_mem_on_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) .pad_mux_list = pwc_mem_on_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) static struct atlas7_pad_mux pwc_on_key_b_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) MUX(0, 5, 1, 0xa08, 5, 0xa88, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) static struct atlas7_grp_mux pwc_on_key_b_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .pad_mux_count = ARRAY_SIZE(pwc_on_key_b_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) .pad_mux_list = pwc_on_key_b_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) static struct atlas7_pad_mux pwc_wakeup_src0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) MUX(0, 0, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static struct atlas7_grp_mux pwc_wakeup_src0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) .pad_mux_list = pwc_wakeup_src0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) static struct atlas7_pad_mux pwc_wakeup_src1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) MUX(0, 1, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) static struct atlas7_grp_mux pwc_wakeup_src1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) .pad_mux_list = pwc_wakeup_src1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static struct atlas7_pad_mux pwc_wakeup_src2_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) MUX(0, 2, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static struct atlas7_grp_mux pwc_wakeup_src2_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src2_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) .pad_mux_list = pwc_wakeup_src2_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) static struct atlas7_pad_mux pwc_wakeup_src3_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) MUX(0, 3, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) static struct atlas7_grp_mux pwc_wakeup_src3_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) .pad_mux_count = ARRAY_SIZE(pwc_wakeup_src3_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) .pad_mux_list = pwc_wakeup_src3_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) static struct atlas7_pad_mux pw_cko0_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) MUX(1, 123, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) static struct atlas7_grp_mux pw_cko0_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) .pad_mux_count = ARRAY_SIZE(pw_cko0_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) .pad_mux_list = pw_cko0_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) static struct atlas7_pad_mux pw_cko0_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) MUX(1, 101, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) static struct atlas7_grp_mux pw_cko0_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) .pad_mux_count = ARRAY_SIZE(pw_cko0_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) .pad_mux_list = pw_cko0_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) static struct atlas7_pad_mux pw_cko0_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) MUX(1, 82, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) static struct atlas7_grp_mux pw_cko0_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) .pad_mux_count = ARRAY_SIZE(pw_cko0_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) .pad_mux_list = pw_cko0_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) static struct atlas7_pad_mux pw_cko0_grp3_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) MUX(1, 162, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) static struct atlas7_grp_mux pw_cko0_grp3_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) .pad_mux_count = ARRAY_SIZE(pw_cko0_grp3_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) .pad_mux_list = pw_cko0_grp3_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static struct atlas7_pad_mux pw_cko1_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) MUX(1, 124, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) static struct atlas7_grp_mux pw_cko1_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) .pad_mux_count = ARRAY_SIZE(pw_cko1_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) .pad_mux_list = pw_cko1_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static struct atlas7_pad_mux pw_cko1_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) MUX(1, 110, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) static struct atlas7_grp_mux pw_cko1_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) .pad_mux_count = ARRAY_SIZE(pw_cko1_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) .pad_mux_list = pw_cko1_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) static struct atlas7_pad_mux pw_cko1_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) MUX(1, 163, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) static struct atlas7_grp_mux pw_cko1_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) .pad_mux_count = ARRAY_SIZE(pw_cko1_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) .pad_mux_list = pw_cko1_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) static struct atlas7_pad_mux pw_i2s01_clk_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) MUX(1, 125, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) static struct atlas7_grp_mux pw_i2s01_clk_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) .pad_mux_list = pw_i2s01_clk_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) static struct atlas7_pad_mux pw_i2s01_clk_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) MUX(1, 117, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) static struct atlas7_grp_mux pw_i2s01_clk_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) .pad_mux_list = pw_i2s01_clk_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) static struct atlas7_pad_mux pw_i2s01_clk_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) MUX(1, 132, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) static struct atlas7_grp_mux pw_i2s01_clk_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) .pad_mux_count = ARRAY_SIZE(pw_i2s01_clk_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) .pad_mux_list = pw_i2s01_clk_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) static struct atlas7_pad_mux pw_pwm0_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) MUX(1, 119, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) static struct atlas7_grp_mux pw_pwm0_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) .pad_mux_list = pw_pwm0_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) static struct atlas7_pad_mux pw_pwm0_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) MUX(1, 159, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) static struct atlas7_grp_mux pw_pwm0_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .pad_mux_count = ARRAY_SIZE(pw_pwm0_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .pad_mux_list = pw_pwm0_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) static struct atlas7_pad_mux pw_pwm1_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) MUX(1, 120, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) static struct atlas7_grp_mux pw_pwm1_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) .pad_mux_list = pw_pwm1_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) static struct atlas7_pad_mux pw_pwm1_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) MUX(1, 160, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) static struct atlas7_grp_mux pw_pwm1_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) .pad_mux_list = pw_pwm1_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) static struct atlas7_pad_mux pw_pwm1_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) MUX(1, 131, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) static struct atlas7_grp_mux pw_pwm1_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) .pad_mux_count = ARRAY_SIZE(pw_pwm1_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) .pad_mux_list = pw_pwm1_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) static struct atlas7_pad_mux pw_pwm2_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) MUX(1, 121, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) static struct atlas7_grp_mux pw_pwm2_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) .pad_mux_list = pw_pwm2_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) static struct atlas7_pad_mux pw_pwm2_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) MUX(1, 98, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) static struct atlas7_grp_mux pw_pwm2_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) .pad_mux_list = pw_pwm2_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) static struct atlas7_pad_mux pw_pwm2_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) MUX(1, 161, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) static struct atlas7_grp_mux pw_pwm2_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) .pad_mux_count = ARRAY_SIZE(pw_pwm2_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) .pad_mux_list = pw_pwm2_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) static struct atlas7_pad_mux pw_pwm3_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) MUX(1, 122, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) static struct atlas7_grp_mux pw_pwm3_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) .pad_mux_list = pw_pwm3_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) static struct atlas7_pad_mux pw_pwm3_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) MUX(1, 73, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) static struct atlas7_grp_mux pw_pwm3_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) .pad_mux_count = ARRAY_SIZE(pw_pwm3_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) .pad_mux_list = pw_pwm3_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) static struct atlas7_pad_mux pw_pwm_cpu_vol_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) MUX(1, 121, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) static struct atlas7_grp_mux pw_pwm_cpu_vol_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) .pad_mux_list = pw_pwm_cpu_vol_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) static struct atlas7_pad_mux pw_pwm_cpu_vol_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) MUX(1, 98, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) static struct atlas7_grp_mux pw_pwm_cpu_vol_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) .pad_mux_list = pw_pwm_cpu_vol_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) static struct atlas7_pad_mux pw_pwm_cpu_vol_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) MUX(1, 161, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) static struct atlas7_grp_mux pw_pwm_cpu_vol_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) .pad_mux_count = ARRAY_SIZE(pw_pwm_cpu_vol_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) .pad_mux_list = pw_pwm_cpu_vol_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) static struct atlas7_pad_mux pw_backlight_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) MUX(1, 122, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) static struct atlas7_grp_mux pw_backlight_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) .pad_mux_count = ARRAY_SIZE(pw_backlight_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) .pad_mux_list = pw_backlight_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) static struct atlas7_pad_mux pw_backlight_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) MUX(1, 73, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) static struct atlas7_grp_mux pw_backlight_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) .pad_mux_count = ARRAY_SIZE(pw_backlight_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) .pad_mux_list = pw_backlight_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) static struct atlas7_pad_mux rg_eth_mac_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) MUX(1, 108, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) MUX(1, 103, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) MUX(1, 104, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) MUX(1, 105, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) MUX(1, 106, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) MUX(1, 107, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) MUX(1, 102, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) MUX(1, 97, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) MUX(1, 98, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) MUX(1, 99, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) MUX(1, 100, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) MUX(1, 101, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) static struct atlas7_grp_mux rg_eth_mac_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) .pad_mux_count = ARRAY_SIZE(rg_eth_mac_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) .pad_mux_list = rg_eth_mac_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) static struct atlas7_pad_mux rg_gmac_phy_intr_n_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) MUX(1, 111, 1, 0xa08, 13, 0xa88, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) static struct atlas7_grp_mux rg_gmac_phy_intr_n_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) .pad_mux_count = ARRAY_SIZE(rg_gmac_phy_intr_n_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) .pad_mux_list = rg_gmac_phy_intr_n_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) static struct atlas7_pad_mux rg_rgmii_mac_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) MUX(1, 109, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) MUX(1, 110, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) static struct atlas7_grp_mux rg_rgmii_mac_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) .pad_mux_count = ARRAY_SIZE(rg_rgmii_mac_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) .pad_mux_list = rg_rgmii_mac_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) MUX(1, 111, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) .pad_mux_list = rg_rgmii_phy_ref_clk_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) static struct atlas7_pad_mux rg_rgmii_phy_ref_clk_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) MUX(1, 53, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) static struct atlas7_grp_mux rg_rgmii_phy_ref_clk_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) .pad_mux_count = ARRAY_SIZE(rg_rgmii_phy_ref_clk_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) .pad_mux_list = rg_rgmii_phy_ref_clk_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) static struct atlas7_pad_mux sd0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) MUX(1, 46, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) MUX(1, 47, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) MUX(1, 44, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) MUX(1, 43, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) MUX(1, 42, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) MUX(1, 41, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) MUX(1, 40, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) MUX(1, 39, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) MUX(1, 38, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) MUX(1, 37, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) static struct atlas7_grp_mux sd0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) .pad_mux_count = ARRAY_SIZE(sd0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .pad_mux_list = sd0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) static struct atlas7_pad_mux sd0_4bit_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) MUX(1, 46, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) MUX(1, 47, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) MUX(1, 44, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) MUX(1, 43, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) MUX(1, 42, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) MUX(1, 41, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) static struct atlas7_grp_mux sd0_4bit_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) .pad_mux_count = ARRAY_SIZE(sd0_4bit_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) .pad_mux_list = sd0_4bit_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) static struct atlas7_pad_mux sd1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) MUX(1, 48, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) MUX(1, 49, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) MUX(1, 40, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) MUX(1, 39, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) MUX(1, 38, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) MUX(1, 37, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) static struct atlas7_grp_mux sd1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) .pad_mux_count = ARRAY_SIZE(sd1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) .pad_mux_list = sd1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) static struct atlas7_pad_mux sd1_4bit_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) MUX(1, 48, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) MUX(1, 49, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) MUX(1, 44, 3, 0xa00, 0, 0xa80, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) MUX(1, 43, 3, 0xa00, 1, 0xa80, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) MUX(1, 42, 3, 0xa00, 2, 0xa80, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) MUX(1, 41, 3, 0xa00, 3, 0xa80, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) static struct atlas7_grp_mux sd1_4bit_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) .pad_mux_list = sd1_4bit_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) static struct atlas7_pad_mux sd1_4bit_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) MUX(1, 48, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) MUX(1, 49, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) MUX(1, 40, 4, 0xa00, 0, 0xa80, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) MUX(1, 39, 4, 0xa00, 1, 0xa80, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) MUX(1, 38, 4, 0xa00, 2, 0xa80, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) MUX(1, 37, 4, 0xa00, 3, 0xa80, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) static struct atlas7_grp_mux sd1_4bit_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) .pad_mux_count = ARRAY_SIZE(sd1_4bit_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) .pad_mux_list = sd1_4bit_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) static struct atlas7_pad_mux sd2_basic_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) MUX(1, 31, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) MUX(1, 32, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) MUX(1, 33, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) MUX(1, 34, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) MUX(1, 35, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) MUX(1, 36, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) static struct atlas7_grp_mux sd2_basic_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) .pad_mux_count = ARRAY_SIZE(sd2_basic_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) .pad_mux_list = sd2_basic_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) static struct atlas7_pad_mux sd2_cdb_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) MUX(1, 124, 2, 0xa08, 7, 0xa88, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) static struct atlas7_grp_mux sd2_cdb_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) .pad_mux_list = sd2_cdb_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) static struct atlas7_pad_mux sd2_cdb_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) MUX(1, 161, 6, 0xa08, 7, 0xa88, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static struct atlas7_grp_mux sd2_cdb_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) .pad_mux_count = ARRAY_SIZE(sd2_cdb_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) .pad_mux_list = sd2_cdb_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) static struct atlas7_pad_mux sd2_wpb_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) MUX(1, 123, 2, 0xa10, 6, 0xa90, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) static struct atlas7_grp_mux sd2_wpb_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) .pad_mux_list = sd2_wpb_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) static struct atlas7_pad_mux sd2_wpb_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) MUX(1, 163, 7, 0xa10, 6, 0xa90, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) static struct atlas7_grp_mux sd2_wpb_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) .pad_mux_count = ARRAY_SIZE(sd2_wpb_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) .pad_mux_list = sd2_wpb_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) static struct atlas7_pad_mux sd3_9_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) MUX(1, 85, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) MUX(1, 86, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) MUX(1, 87, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) MUX(1, 88, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) MUX(1, 89, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) MUX(1, 90, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) static struct atlas7_grp_mux sd3_9_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) .pad_mux_count = ARRAY_SIZE(sd3_9_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) .pad_mux_list = sd3_9_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) static struct atlas7_pad_mux sd5_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) MUX(1, 91, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) MUX(1, 92, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) MUX(1, 93, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) MUX(1, 94, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) MUX(1, 95, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) MUX(1, 96, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) static struct atlas7_grp_mux sd5_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) .pad_mux_count = ARRAY_SIZE(sd5_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) .pad_mux_list = sd5_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) static struct atlas7_pad_mux sd6_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) MUX(1, 79, 4, 0xa00, 27, 0xa80, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) MUX(1, 78, 4, 0xa00, 26, 0xa80, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) MUX(1, 74, 4, 0xa00, 28, 0xa80, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) MUX(1, 75, 4, 0xa00, 29, 0xa80, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) MUX(1, 76, 4, 0xa00, 30, 0xa80, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) MUX(1, 77, 4, 0xa00, 31, 0xa80, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) static struct atlas7_grp_mux sd6_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) .pad_mux_count = ARRAY_SIZE(sd6_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) .pad_mux_list = sd6_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) static struct atlas7_pad_mux sd6_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) MUX(1, 101, 3, 0xa00, 27, 0xa80, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) MUX(1, 99, 3, 0xa00, 26, 0xa80, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) MUX(1, 100, 3, 0xa00, 28, 0xa80, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) MUX(1, 110, 3, 0xa00, 29, 0xa80, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) MUX(1, 109, 3, 0xa00, 30, 0xa80, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) MUX(1, 111, 3, 0xa00, 31, 0xa80, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) static struct atlas7_grp_mux sd6_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) .pad_mux_count = ARRAY_SIZE(sd6_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) .pad_mux_list = sd6_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) static struct atlas7_pad_mux sp0_ext_ldo_on_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) MUX(0, 4, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) static struct atlas7_grp_mux sp0_ext_ldo_on_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) .pad_mux_count = ARRAY_SIZE(sp0_ext_ldo_on_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) .pad_mux_list = sp0_ext_ldo_on_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) static struct atlas7_pad_mux sp0_qspi_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) MUX(0, 12, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) MUX(0, 13, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) MUX(0, 14, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) MUX(0, 15, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) MUX(0, 16, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) MUX(0, 17, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) static struct atlas7_grp_mux sp0_qspi_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) .pad_mux_count = ARRAY_SIZE(sp0_qspi_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) .pad_mux_list = sp0_qspi_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) static struct atlas7_pad_mux sp1_spi_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) MUX(1, 19, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) MUX(1, 20, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) MUX(1, 21, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) MUX(1, 18, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) static struct atlas7_grp_mux sp1_spi_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) .pad_mux_count = ARRAY_SIZE(sp1_spi_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) .pad_mux_list = sp1_spi_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) static struct atlas7_pad_mux tpiu_trace_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) MUX(1, 53, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) MUX(1, 56, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) MUX(1, 57, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) MUX(1, 58, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) MUX(1, 59, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) MUX(1, 60, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) MUX(1, 61, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) MUX(1, 62, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) MUX(1, 63, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) MUX(1, 64, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) MUX(1, 65, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) MUX(1, 66, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) MUX(1, 67, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) MUX(1, 68, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) MUX(1, 69, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) MUX(1, 70, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) MUX(1, 71, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) MUX(1, 72, 5, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) static struct atlas7_grp_mux tpiu_trace_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) .pad_mux_count = ARRAY_SIZE(tpiu_trace_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) .pad_mux_list = tpiu_trace_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) static struct atlas7_pad_mux uart0_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) MUX(1, 121, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) MUX(1, 120, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) MUX(1, 134, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) MUX(1, 133, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) static struct atlas7_grp_mux uart0_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) .pad_mux_count = ARRAY_SIZE(uart0_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) .pad_mux_list = uart0_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) static struct atlas7_pad_mux uart0_nopause_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) MUX(1, 134, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) MUX(1, 133, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) static struct atlas7_grp_mux uart0_nopause_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) .pad_mux_count = ARRAY_SIZE(uart0_nopause_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) .pad_mux_list = uart0_nopause_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) static struct atlas7_pad_mux uart1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) MUX(1, 136, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) MUX(1, 135, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) static struct atlas7_grp_mux uart1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) .pad_mux_count = ARRAY_SIZE(uart1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) .pad_mux_list = uart1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) static struct atlas7_pad_mux uart2_cts_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) MUX(1, 132, 3, 0xa10, 2, 0xa90, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) static struct atlas7_grp_mux uart2_cts_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) .pad_mux_count = ARRAY_SIZE(uart2_cts_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) .pad_mux_list = uart2_cts_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) static struct atlas7_pad_mux uart2_cts_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) MUX(1, 162, 2, 0xa10, 2, 0xa90, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) static struct atlas7_grp_mux uart2_cts_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) .pad_mux_count = ARRAY_SIZE(uart2_cts_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) .pad_mux_list = uart2_cts_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) static struct atlas7_pad_mux uart2_rts_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) MUX(1, 131, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) static struct atlas7_grp_mux uart2_rts_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) .pad_mux_count = ARRAY_SIZE(uart2_rts_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) .pad_mux_list = uart2_rts_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) static struct atlas7_pad_mux uart2_rts_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) MUX(1, 161, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) static struct atlas7_grp_mux uart2_rts_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) .pad_mux_count = ARRAY_SIZE(uart2_rts_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) .pad_mux_list = uart2_rts_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) static struct atlas7_pad_mux uart2_rxd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) MUX(0, 11, 2, 0xa10, 5, 0xa90, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) static struct atlas7_grp_mux uart2_rxd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) .pad_mux_list = uart2_rxd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) static struct atlas7_pad_mux uart2_rxd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) MUX(1, 160, 2, 0xa10, 5, 0xa90, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) static struct atlas7_grp_mux uart2_rxd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) .pad_mux_list = uart2_rxd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) static struct atlas7_pad_mux uart2_rxd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) MUX(1, 130, 3, 0xa10, 5, 0xa90, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) static struct atlas7_grp_mux uart2_rxd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) .pad_mux_count = ARRAY_SIZE(uart2_rxd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) .pad_mux_list = uart2_rxd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) static struct atlas7_pad_mux uart2_txd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) MUX(0, 10, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) static struct atlas7_grp_mux uart2_txd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) .pad_mux_count = ARRAY_SIZE(uart2_txd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) .pad_mux_list = uart2_txd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) static struct atlas7_pad_mux uart2_txd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) MUX(1, 159, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) static struct atlas7_grp_mux uart2_txd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) .pad_mux_count = ARRAY_SIZE(uart2_txd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) .pad_mux_list = uart2_txd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) static struct atlas7_pad_mux uart2_txd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) MUX(1, 129, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) static struct atlas7_grp_mux uart2_txd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) .pad_mux_count = ARRAY_SIZE(uart2_txd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) .pad_mux_list = uart2_txd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) static struct atlas7_pad_mux uart3_cts_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) MUX(1, 125, 2, 0xa08, 0, 0xa88, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) static struct atlas7_grp_mux uart3_cts_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) .pad_mux_count = ARRAY_SIZE(uart3_cts_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) .pad_mux_list = uart3_cts_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) static struct atlas7_pad_mux uart3_cts_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) MUX(1, 111, 4, 0xa08, 0, 0xa88, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) static struct atlas7_grp_mux uart3_cts_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) .pad_mux_count = ARRAY_SIZE(uart3_cts_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) .pad_mux_list = uart3_cts_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) static struct atlas7_pad_mux uart3_cts_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) MUX(1, 140, 2, 0xa08, 0, 0xa88, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) static struct atlas7_grp_mux uart3_cts_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) .pad_mux_count = ARRAY_SIZE(uart3_cts_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) .pad_mux_list = uart3_cts_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) static struct atlas7_pad_mux uart3_rts_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) MUX(1, 126, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) static struct atlas7_grp_mux uart3_rts_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) .pad_mux_count = ARRAY_SIZE(uart3_rts_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) .pad_mux_list = uart3_rts_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) static struct atlas7_pad_mux uart3_rts_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) MUX(1, 109, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) static struct atlas7_grp_mux uart3_rts_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) .pad_mux_count = ARRAY_SIZE(uart3_rts_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) .pad_mux_list = uart3_rts_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) static struct atlas7_pad_mux uart3_rts_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) MUX(1, 139, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) static struct atlas7_grp_mux uart3_rts_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) .pad_mux_count = ARRAY_SIZE(uart3_rts_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) .pad_mux_list = uart3_rts_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) static struct atlas7_pad_mux uart3_rxd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) MUX(1, 138, 1, 0xa00, 5, 0xa80, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) static struct atlas7_grp_mux uart3_rxd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) .pad_mux_list = uart3_rxd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) static struct atlas7_pad_mux uart3_rxd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) MUX(1, 84, 2, 0xa00, 5, 0xa80, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) static struct atlas7_grp_mux uart3_rxd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) .pad_mux_list = uart3_rxd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) static struct atlas7_pad_mux uart3_rxd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) MUX(1, 162, 3, 0xa00, 5, 0xa80, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) static struct atlas7_grp_mux uart3_rxd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) .pad_mux_count = ARRAY_SIZE(uart3_rxd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) .pad_mux_list = uart3_rxd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) static struct atlas7_pad_mux uart3_txd_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) MUX(1, 137, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) static struct atlas7_grp_mux uart3_txd_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) .pad_mux_count = ARRAY_SIZE(uart3_txd_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) .pad_mux_list = uart3_txd_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) static struct atlas7_pad_mux uart3_txd_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) MUX(1, 83, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) static struct atlas7_grp_mux uart3_txd_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) .pad_mux_count = ARRAY_SIZE(uart3_txd_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) .pad_mux_list = uart3_txd_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) static struct atlas7_pad_mux uart3_txd_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) MUX(1, 161, 3, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) static struct atlas7_grp_mux uart3_txd_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) .pad_mux_count = ARRAY_SIZE(uart3_txd_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) .pad_mux_list = uart3_txd_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) static struct atlas7_pad_mux uart4_basic_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) MUX(1, 140, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) MUX(1, 139, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) static struct atlas7_grp_mux uart4_basic_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) .pad_mux_count = ARRAY_SIZE(uart4_basic_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) .pad_mux_list = uart4_basic_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) static struct atlas7_pad_mux uart4_cts_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) MUX(1, 122, 4, 0xa08, 1, 0xa88, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) static struct atlas7_grp_mux uart4_cts_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) .pad_mux_count = ARRAY_SIZE(uart4_cts_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) .pad_mux_list = uart4_cts_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) static struct atlas7_pad_mux uart4_cts_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) MUX(1, 100, 4, 0xa08, 1, 0xa88, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) static struct atlas7_grp_mux uart4_cts_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) .pad_mux_count = ARRAY_SIZE(uart4_cts_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) .pad_mux_list = uart4_cts_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) static struct atlas7_pad_mux uart4_cts_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) MUX(1, 117, 2, 0xa08, 1, 0xa88, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) static struct atlas7_grp_mux uart4_cts_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) .pad_mux_count = ARRAY_SIZE(uart4_cts_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) .pad_mux_list = uart4_cts_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) static struct atlas7_pad_mux uart4_rts_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) MUX(1, 123, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) static struct atlas7_grp_mux uart4_rts_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) .pad_mux_count = ARRAY_SIZE(uart4_rts_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) .pad_mux_list = uart4_rts_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) static struct atlas7_pad_mux uart4_rts_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) MUX(1, 99, 4, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) static struct atlas7_grp_mux uart4_rts_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) .pad_mux_count = ARRAY_SIZE(uart4_rts_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) .pad_mux_list = uart4_rts_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) static struct atlas7_pad_mux uart4_rts_grp2_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) MUX(1, 116, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) static struct atlas7_grp_mux uart4_rts_grp2_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) .pad_mux_count = ARRAY_SIZE(uart4_rts_grp2_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) .pad_mux_list = uart4_rts_grp2_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) static struct atlas7_pad_mux usb0_drvvbus_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) MUX(1, 51, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) static struct atlas7_grp_mux usb0_drvvbus_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) .pad_mux_list = usb0_drvvbus_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) static struct atlas7_pad_mux usb0_drvvbus_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) MUX(1, 162, 7, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) static struct atlas7_grp_mux usb0_drvvbus_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) .pad_mux_count = ARRAY_SIZE(usb0_drvvbus_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) .pad_mux_list = usb0_drvvbus_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) static struct atlas7_pad_mux usb1_drvvbus_grp0_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) MUX(1, 134, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) static struct atlas7_grp_mux usb1_drvvbus_grp0_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp0_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) .pad_mux_list = usb1_drvvbus_grp0_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) static struct atlas7_pad_mux usb1_drvvbus_grp1_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) MUX(1, 163, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) static struct atlas7_grp_mux usb1_drvvbus_grp1_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) .pad_mux_count = ARRAY_SIZE(usb1_drvvbus_grp1_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) .pad_mux_list = usb1_drvvbus_grp1_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) static struct atlas7_pad_mux visbus_dout_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) MUX(1, 57, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) MUX(1, 58, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) MUX(1, 59, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) MUX(1, 60, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) MUX(1, 61, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) MUX(1, 62, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) MUX(1, 63, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) MUX(1, 64, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) MUX(1, 65, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) MUX(1, 66, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) MUX(1, 67, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) MUX(1, 68, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) MUX(1, 69, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) MUX(1, 70, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) MUX(1, 71, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) MUX(1, 72, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) MUX(1, 53, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) MUX(1, 54, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) MUX(1, 55, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) MUX(1, 56, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) MUX(1, 85, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) MUX(1, 86, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) MUX(1, 87, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) MUX(1, 88, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) MUX(1, 89, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) MUX(1, 90, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) MUX(1, 91, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) MUX(1, 92, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) MUX(1, 93, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) MUX(1, 94, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) MUX(1, 95, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) MUX(1, 96, 6, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) static struct atlas7_grp_mux visbus_dout_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) .pad_mux_count = ARRAY_SIZE(visbus_dout_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) .pad_mux_list = visbus_dout_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) static struct atlas7_pad_mux vi_vip1_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) MUX(1, 74, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) MUX(1, 75, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) MUX(1, 76, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) MUX(1, 77, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) MUX(1, 78, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) MUX(1, 79, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) MUX(1, 80, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) MUX(1, 81, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) MUX(1, 82, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) MUX(1, 83, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) MUX(1, 84, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) MUX(1, 103, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) MUX(1, 104, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) MUX(1, 105, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) MUX(1, 106, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) MUX(1, 107, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) MUX(1, 102, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) MUX(1, 97, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) MUX(1, 98, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) static struct atlas7_grp_mux vi_vip1_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) .pad_mux_count = ARRAY_SIZE(vi_vip1_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) .pad_mux_list = vi_vip1_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) static struct atlas7_pad_mux vi_vip1_ext_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) MUX(1, 74, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) MUX(1, 75, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) MUX(1, 76, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) MUX(1, 77, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) MUX(1, 78, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) MUX(1, 79, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) MUX(1, 80, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) MUX(1, 81, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) MUX(1, 82, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) MUX(1, 83, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) MUX(1, 84, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) MUX(1, 108, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) MUX(1, 103, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) MUX(1, 104, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) MUX(1, 105, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) MUX(1, 106, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) MUX(1, 107, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) MUX(1, 102, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) MUX(1, 97, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) MUX(1, 98, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) MUX(1, 99, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) MUX(1, 100, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) static struct atlas7_grp_mux vi_vip1_ext_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) .pad_mux_count = ARRAY_SIZE(vi_vip1_ext_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) .pad_mux_list = vi_vip1_ext_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) static struct atlas7_pad_mux vi_vip1_low8bit_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) MUX(1, 74, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) MUX(1, 75, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) MUX(1, 76, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) MUX(1, 77, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) MUX(1, 78, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) MUX(1, 79, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) MUX(1, 80, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) MUX(1, 81, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) MUX(1, 82, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) MUX(1, 83, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) MUX(1, 84, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) static struct atlas7_grp_mux vi_vip1_low8bit_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) .pad_mux_count = ARRAY_SIZE(vi_vip1_low8bit_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) .pad_mux_list = vi_vip1_low8bit_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) static struct atlas7_pad_mux vi_vip1_high8bit_grp_pad_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) MUX(1, 82, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) MUX(1, 83, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) MUX(1, 84, 1, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) MUX(1, 103, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) MUX(1, 104, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) MUX(1, 105, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) MUX(1, 106, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) MUX(1, 107, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) MUX(1, 102, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) MUX(1, 97, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) MUX(1, 98, 2, N, N, N, N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) static struct atlas7_grp_mux vi_vip1_high8bit_grp_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) .pad_mux_count = ARRAY_SIZE(vi_vip1_high8bit_grp_pad_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) .pad_mux_list = vi_vip1_high8bit_grp_pad_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) static struct atlas7_pmx_func atlas7_pmx_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) FUNCTION("gnss_gpio", gnss_gpio_grp, &gnss_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) FUNCTION("lcd_vip_gpio", lcd_vip_gpio_grp, &lcd_vip_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) FUNCTION("sdio_i2s_gpio", sdio_i2s_gpio_grp, &sdio_i2s_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) FUNCTION("sp_rgmii_gpio", sp_rgmii_gpio_grp, &sp_rgmii_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) FUNCTION("lvds_gpio", lvds_gpio_grp, &lvds_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) FUNCTION("jtag_uart_nand_gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) jtag_uart_nand_gpio_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) &jtag_uart_nand_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) FUNCTION("rtc_gpio", rtc_gpio_grp, &rtc_gpio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) FUNCTION("audio_ac97", audio_ac97_grp, &audio_ac97_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) FUNCTION("audio_digmic_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) audio_digmic_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) &audio_digmic_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) FUNCTION("audio_digmic_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) audio_digmic_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) &audio_digmic_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) FUNCTION("audio_digmic_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) audio_digmic_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) &audio_digmic_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) FUNCTION("audio_func_dbg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) audio_func_dbg_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) &audio_func_dbg_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) FUNCTION("audio_i2s", audio_i2s_grp, &audio_i2s_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) FUNCTION("audio_i2s_2ch", audio_i2s_2ch_grp, &audio_i2s_2ch_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) FUNCTION("audio_i2s_extclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) audio_i2s_extclk_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) &audio_i2s_extclk_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) FUNCTION("audio_spdif_out_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) audio_spdif_out_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) &audio_spdif_out_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) FUNCTION("audio_spdif_out_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) audio_spdif_out_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) &audio_spdif_out_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) FUNCTION("audio_spdif_out_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) audio_spdif_out_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) &audio_spdif_out_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) FUNCTION("audio_uart0_basic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) audio_uart0_basic_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) &audio_uart0_basic_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) FUNCTION("audio_uart0_urfs_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) audio_uart0_urfs_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) &audio_uart0_urfs_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) FUNCTION("audio_uart0_urfs_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) audio_uart0_urfs_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) &audio_uart0_urfs_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) FUNCTION("audio_uart0_urfs_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) audio_uart0_urfs_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) &audio_uart0_urfs_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) FUNCTION("audio_uart0_urfs_m3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) audio_uart0_urfs_grp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) &audio_uart0_urfs_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) FUNCTION("audio_uart1_basic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) audio_uart1_basic_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) &audio_uart1_basic_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) FUNCTION("audio_uart1_urfs_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) audio_uart1_urfs_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) &audio_uart1_urfs_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) FUNCTION("audio_uart1_urfs_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) audio_uart1_urfs_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) &audio_uart1_urfs_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) FUNCTION("audio_uart1_urfs_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) audio_uart1_urfs_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) &audio_uart1_urfs_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) FUNCTION("audio_uart2_urfs_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) audio_uart2_urfs_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) &audio_uart2_urfs_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) FUNCTION("audio_uart2_urfs_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) audio_uart2_urfs_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) &audio_uart2_urfs_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) FUNCTION("audio_uart2_urfs_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) audio_uart2_urfs_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) &audio_uart2_urfs_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) FUNCTION("audio_uart2_urxd_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) audio_uart2_urxd_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) &audio_uart2_urxd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) FUNCTION("audio_uart2_urxd_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) audio_uart2_urxd_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) &audio_uart2_urxd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) FUNCTION("audio_uart2_urxd_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) audio_uart2_urxd_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) &audio_uart2_urxd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) FUNCTION("audio_uart2_usclk_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) audio_uart2_usclk_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) &audio_uart2_usclk_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) FUNCTION("audio_uart2_usclk_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) audio_uart2_usclk_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) &audio_uart2_usclk_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) FUNCTION("audio_uart2_usclk_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) audio_uart2_usclk_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) &audio_uart2_usclk_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) FUNCTION("audio_uart2_utfs_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) audio_uart2_utfs_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) &audio_uart2_utfs_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) FUNCTION("audio_uart2_utfs_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) audio_uart2_utfs_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) &audio_uart2_utfs_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) FUNCTION("audio_uart2_utfs_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) audio_uart2_utfs_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) &audio_uart2_utfs_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) FUNCTION("audio_uart2_utxd_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) audio_uart2_utxd_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) &audio_uart2_utxd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) FUNCTION("audio_uart2_utxd_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) audio_uart2_utxd_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) &audio_uart2_utxd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) FUNCTION("audio_uart2_utxd_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) audio_uart2_utxd_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) &audio_uart2_utxd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) FUNCTION("c_can_trnsvr_en_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) c_can_trnsvr_en_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) &c_can_trnsvr_en_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) FUNCTION("c_can_trnsvr_en_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) c_can_trnsvr_en_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) &c_can_trnsvr_en_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) FUNCTION("c_can_trnsvr_intr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) c_can_trnsvr_intr_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) &c_can_trnsvr_intr_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) FUNCTION("c_can_trnsvr_stb_n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) c_can_trnsvr_stb_n_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) &c_can_trnsvr_stb_n_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) FUNCTION("c0_can_rxd_trnsv0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) c0_can_rxd_trnsv0_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) &c0_can_rxd_trnsv0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) FUNCTION("c0_can_rxd_trnsv1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) c0_can_rxd_trnsv1_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) &c0_can_rxd_trnsv1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) FUNCTION("c0_can_txd_trnsv0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) c0_can_txd_trnsv0_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) &c0_can_txd_trnsv0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) FUNCTION("c0_can_txd_trnsv1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) c0_can_txd_trnsv1_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) &c0_can_txd_trnsv1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) FUNCTION("c1_can_rxd_m0", c1_can_rxd_grp0, &c1_can_rxd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) FUNCTION("c1_can_rxd_m1", c1_can_rxd_grp1, &c1_can_rxd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) FUNCTION("c1_can_rxd_m2", c1_can_rxd_grp2, &c1_can_rxd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) FUNCTION("c1_can_rxd_m3", c1_can_rxd_grp3, &c1_can_rxd_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) FUNCTION("c1_can_txd_m0", c1_can_txd_grp0, &c1_can_txd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) FUNCTION("c1_can_txd_m1", c1_can_txd_grp1, &c1_can_txd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) FUNCTION("c1_can_txd_m2", c1_can_txd_grp2, &c1_can_txd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) FUNCTION("c1_can_txd_m3", c1_can_txd_grp3, &c1_can_txd_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) FUNCTION("ca_audio_lpc", ca_audio_lpc_grp, &ca_audio_lpc_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) FUNCTION("ca_bt_lpc", ca_bt_lpc_grp, &ca_bt_lpc_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) FUNCTION("ca_coex", ca_coex_grp, &ca_coex_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) FUNCTION("ca_curator_lpc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) ca_curator_lpc_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) &ca_curator_lpc_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) FUNCTION("ca_pcm_debug", ca_pcm_debug_grp, &ca_pcm_debug_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) FUNCTION("ca_pio", ca_pio_grp, &ca_pio_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) FUNCTION("ca_sdio_debug", ca_sdio_debug_grp, &ca_sdio_debug_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) FUNCTION("ca_spi", ca_spi_grp, &ca_spi_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) FUNCTION("ca_trb", ca_trb_grp, &ca_trb_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) FUNCTION("ca_uart_debug", ca_uart_debug_grp, &ca_uart_debug_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) FUNCTION("clkc_m0", clkc_grp0, &clkc_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) FUNCTION("clkc_m1", clkc_grp1, &clkc_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) FUNCTION("gn_gnss_i2c", gn_gnss_i2c_grp, &gn_gnss_i2c_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) FUNCTION("gn_gnss_uart_nopause",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) gn_gnss_uart_nopause_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) &gn_gnss_uart_nopause_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) FUNCTION("gn_gnss_uart", gn_gnss_uart_grp, &gn_gnss_uart_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) FUNCTION("gn_trg_spi_m0", gn_trg_spi_grp0, &gn_trg_spi_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) FUNCTION("gn_trg_spi_m1", gn_trg_spi_grp1, &gn_trg_spi_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) FUNCTION("cvbs_dbg", cvbs_dbg_grp, &cvbs_dbg_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) FUNCTION("cvbs_dbg_test_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) cvbs_dbg_test_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) &cvbs_dbg_test_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) FUNCTION("cvbs_dbg_test_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) cvbs_dbg_test_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) &cvbs_dbg_test_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) FUNCTION("cvbs_dbg_test_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) cvbs_dbg_test_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) &cvbs_dbg_test_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) FUNCTION("cvbs_dbg_test_m3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) cvbs_dbg_test_grp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) &cvbs_dbg_test_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) FUNCTION("cvbs_dbg_test_m4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) cvbs_dbg_test_grp4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) &cvbs_dbg_test_grp4_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) FUNCTION("cvbs_dbg_test_m5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) cvbs_dbg_test_grp5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) &cvbs_dbg_test_grp5_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) FUNCTION("cvbs_dbg_test_m6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) cvbs_dbg_test_grp6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) &cvbs_dbg_test_grp6_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) FUNCTION("cvbs_dbg_test_m7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) cvbs_dbg_test_grp7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) &cvbs_dbg_test_grp7_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) FUNCTION("cvbs_dbg_test_m8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) cvbs_dbg_test_grp8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) &cvbs_dbg_test_grp8_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) FUNCTION("cvbs_dbg_test_m9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) cvbs_dbg_test_grp9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) &cvbs_dbg_test_grp9_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) FUNCTION("cvbs_dbg_test_m10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) cvbs_dbg_test_grp10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) &cvbs_dbg_test_grp10_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) FUNCTION("cvbs_dbg_test_m11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) cvbs_dbg_test_grp11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) &cvbs_dbg_test_grp11_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) FUNCTION("cvbs_dbg_test_m12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) cvbs_dbg_test_grp12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) &cvbs_dbg_test_grp12_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) FUNCTION("cvbs_dbg_test_m13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) cvbs_dbg_test_grp13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) &cvbs_dbg_test_grp13_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) FUNCTION("cvbs_dbg_test_m14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) cvbs_dbg_test_grp14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) &cvbs_dbg_test_grp14_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) FUNCTION("cvbs_dbg_test_m15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) cvbs_dbg_test_grp15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) &cvbs_dbg_test_grp15_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) FUNCTION("gn_gnss_power", gn_gnss_power_grp, &gn_gnss_power_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) FUNCTION("gn_gnss_sw_status",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) gn_gnss_sw_status_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) &gn_gnss_sw_status_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) FUNCTION("gn_gnss_eclk", gn_gnss_eclk_grp, &gn_gnss_eclk_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) FUNCTION("gn_gnss_irq1_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) gn_gnss_irq1_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) &gn_gnss_irq1_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) FUNCTION("gn_gnss_irq2_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) gn_gnss_irq2_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) &gn_gnss_irq2_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) FUNCTION("gn_gnss_tm", gn_gnss_tm_grp, &gn_gnss_tm_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) FUNCTION("gn_gnss_tsync", gn_gnss_tsync_grp, &gn_gnss_tsync_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) FUNCTION("gn_io_gnsssys_sw_cfg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) gn_io_gnsssys_sw_cfg_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) &gn_io_gnsssys_sw_cfg_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) FUNCTION("gn_trg_m0", gn_trg_grp0, &gn_trg_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) FUNCTION("gn_trg_m1", gn_trg_grp1, &gn_trg_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) FUNCTION("gn_trg_shutdown_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) gn_trg_shutdown_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) &gn_trg_shutdown_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) FUNCTION("gn_trg_shutdown_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) gn_trg_shutdown_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) &gn_trg_shutdown_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) FUNCTION("gn_trg_shutdown_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) gn_trg_shutdown_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) &gn_trg_shutdown_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) FUNCTION("gn_trg_shutdown_m3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) gn_trg_shutdown_grp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) &gn_trg_shutdown_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) FUNCTION("i2c0", i2c0_grp, &i2c0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) FUNCTION("i2c1", i2c1_grp, &i2c1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) FUNCTION("i2s0", i2s0_grp, &i2s0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) FUNCTION("i2s1_basic", i2s1_basic_grp, &i2s1_basic_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) FUNCTION("i2s1_rxd0_m0", i2s1_rxd0_grp0, &i2s1_rxd0_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) FUNCTION("i2s1_rxd0_m1", i2s1_rxd0_grp1, &i2s1_rxd0_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) FUNCTION("i2s1_rxd0_m2", i2s1_rxd0_grp2, &i2s1_rxd0_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) FUNCTION("i2s1_rxd0_m3", i2s1_rxd0_grp3, &i2s1_rxd0_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) FUNCTION("i2s1_rxd0_m4", i2s1_rxd0_grp4, &i2s1_rxd0_grp4_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) FUNCTION("i2s1_rxd1_m0", i2s1_rxd1_grp0, &i2s1_rxd1_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) FUNCTION("i2s1_rxd1_m1", i2s1_rxd1_grp1, &i2s1_rxd1_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) FUNCTION("i2s1_rxd1_m2", i2s1_rxd1_grp2, &i2s1_rxd1_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) FUNCTION("i2s1_rxd1_m3", i2s1_rxd1_grp3, &i2s1_rxd1_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) FUNCTION("i2s1_rxd1_m4", i2s1_rxd1_grp4, &i2s1_rxd1_grp4_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) FUNCTION("jtag_jt_dbg_nsrst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) jtag_jt_dbg_nsrst_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) &jtag_jt_dbg_nsrst_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) FUNCTION("jtag_ntrst_m0", jtag_ntrst_grp0, &jtag_ntrst_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) FUNCTION("jtag_ntrst_m1", jtag_ntrst_grp1, &jtag_ntrst_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) FUNCTION("jtag_swdiotms_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) jtag_swdiotms_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) &jtag_swdiotms_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) FUNCTION("jtag_swdiotms_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) jtag_swdiotms_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) &jtag_swdiotms_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) FUNCTION("jtag_tck_m0", jtag_tck_grp0, &jtag_tck_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) FUNCTION("jtag_tck_m1", jtag_tck_grp1, &jtag_tck_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) FUNCTION("jtag_tdi_m0", jtag_tdi_grp0, &jtag_tdi_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) FUNCTION("jtag_tdi_m1", jtag_tdi_grp1, &jtag_tdi_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) FUNCTION("jtag_tdo_m0", jtag_tdo_grp0, &jtag_tdo_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) FUNCTION("jtag_tdo_m1", jtag_tdo_grp1, &jtag_tdo_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) FUNCTION("ks_kas_spi_m0", ks_kas_spi_grp0, &ks_kas_spi_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) FUNCTION("ld_ldd", ld_ldd_grp, &ld_ldd_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) FUNCTION("ld_ldd_16bit", ld_ldd_16bit_grp, &ld_ldd_16bit_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) FUNCTION("ld_ldd_fck", ld_ldd_fck_grp, &ld_ldd_fck_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) FUNCTION("ld_ldd_lck", ld_ldd_lck_grp, &ld_ldd_lck_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) FUNCTION("lr_lcdrom", lr_lcdrom_grp, &lr_lcdrom_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) FUNCTION("lvds_analog", lvds_analog_grp, &lvds_analog_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) FUNCTION("nd_df_basic", nd_df_basic_grp, &nd_df_basic_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) FUNCTION("nd_df_wp", nd_df_wp_grp, &nd_df_wp_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) FUNCTION("nd_df_cs", nd_df_cs_grp, &nd_df_cs_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) FUNCTION("ps", ps_grp, &ps_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) FUNCTION("ps_no_dir", ps_no_dir_grp, &ps_no_dir_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) FUNCTION("pwc_core_on", pwc_core_on_grp, &pwc_core_on_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) FUNCTION("pwc_ext_on", pwc_ext_on_grp, &pwc_ext_on_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) FUNCTION("pwc_gpio3_clk", pwc_gpio3_clk_grp, &pwc_gpio3_clk_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) FUNCTION("pwc_io_on", pwc_io_on_grp, &pwc_io_on_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) FUNCTION("pwc_lowbatt_b_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) pwc_lowbatt_b_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) &pwc_lowbatt_b_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) FUNCTION("pwc_mem_on", pwc_mem_on_grp, &pwc_mem_on_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) FUNCTION("pwc_on_key_b_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) pwc_on_key_b_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) &pwc_on_key_b_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) FUNCTION("pwc_wakeup_src0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) pwc_wakeup_src0_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) &pwc_wakeup_src0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) FUNCTION("pwc_wakeup_src1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) pwc_wakeup_src1_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) &pwc_wakeup_src1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) FUNCTION("pwc_wakeup_src2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) pwc_wakeup_src2_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) &pwc_wakeup_src2_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) FUNCTION("pwc_wakeup_src3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) pwc_wakeup_src3_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) &pwc_wakeup_src3_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) FUNCTION("pw_cko0_m0", pw_cko0_grp0, &pw_cko0_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) FUNCTION("pw_cko0_m1", pw_cko0_grp1, &pw_cko0_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) FUNCTION("pw_cko0_m2", pw_cko0_grp2, &pw_cko0_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) FUNCTION("pw_cko0_m3", pw_cko0_grp3, &pw_cko0_grp3_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) FUNCTION("pw_cko1_m0", pw_cko1_grp0, &pw_cko1_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) FUNCTION("pw_cko1_m1", pw_cko1_grp1, &pw_cko1_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) FUNCTION("pw_cko1_m2", pw_cko1_grp2, &pw_cko1_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) FUNCTION("pw_i2s01_clk_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) pw_i2s01_clk_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) &pw_i2s01_clk_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) FUNCTION("pw_i2s01_clk_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) pw_i2s01_clk_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) &pw_i2s01_clk_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) FUNCTION("pw_i2s01_clk_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) pw_i2s01_clk_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) &pw_i2s01_clk_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) FUNCTION("pw_pwm0_m0", pw_pwm0_grp0, &pw_pwm0_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) FUNCTION("pw_pwm0_m1", pw_pwm0_grp1, &pw_pwm0_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) FUNCTION("pw_pwm1_m0", pw_pwm1_grp0, &pw_pwm1_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) FUNCTION("pw_pwm1_m1", pw_pwm1_grp1, &pw_pwm1_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) FUNCTION("pw_pwm1_m2", pw_pwm1_grp2, &pw_pwm1_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) FUNCTION("pw_pwm2_m0", pw_pwm2_grp0, &pw_pwm2_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) FUNCTION("pw_pwm2_m1", pw_pwm2_grp1, &pw_pwm2_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) FUNCTION("pw_pwm2_m2", pw_pwm2_grp2, &pw_pwm2_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) FUNCTION("pw_pwm3_m0", pw_pwm3_grp0, &pw_pwm3_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) FUNCTION("pw_pwm3_m1", pw_pwm3_grp1, &pw_pwm3_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) FUNCTION("pw_pwm_cpu_vol_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) pw_pwm_cpu_vol_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) &pw_pwm_cpu_vol_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) FUNCTION("pw_pwm_cpu_vol_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) pw_pwm_cpu_vol_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) &pw_pwm_cpu_vol_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) FUNCTION("pw_pwm_cpu_vol_m2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) pw_pwm_cpu_vol_grp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) &pw_pwm_cpu_vol_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) FUNCTION("pw_backlight_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) pw_backlight_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) &pw_backlight_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) FUNCTION("pw_backlight_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) pw_backlight_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) &pw_backlight_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) FUNCTION("rg_eth_mac", rg_eth_mac_grp, &rg_eth_mac_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) FUNCTION("rg_gmac_phy_intr_n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) rg_gmac_phy_intr_n_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) &rg_gmac_phy_intr_n_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) FUNCTION("rg_rgmii_mac", rg_rgmii_mac_grp, &rg_rgmii_mac_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) FUNCTION("rg_rgmii_phy_ref_clk_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) rg_rgmii_phy_ref_clk_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) &rg_rgmii_phy_ref_clk_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) FUNCTION("rg_rgmii_phy_ref_clk_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) rg_rgmii_phy_ref_clk_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) &rg_rgmii_phy_ref_clk_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) FUNCTION("sd0", sd0_grp, &sd0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) FUNCTION("sd0_4bit", sd0_4bit_grp, &sd0_4bit_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) FUNCTION("sd1", sd1_grp, &sd1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) FUNCTION("sd1_4bit_m0", sd1_4bit_grp0, &sd1_4bit_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) FUNCTION("sd1_4bit_m1", sd1_4bit_grp1, &sd1_4bit_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) FUNCTION("sd2_basic", sd2_basic_grp, &sd2_basic_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) FUNCTION("sd2_cdb_m0", sd2_cdb_grp0, &sd2_cdb_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) FUNCTION("sd2_cdb_m1", sd2_cdb_grp1, &sd2_cdb_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) FUNCTION("sd2_wpb_m0", sd2_wpb_grp0, &sd2_wpb_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) FUNCTION("sd2_wpb_m1", sd2_wpb_grp1, &sd2_wpb_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) FUNCTION("sd3", sd3_9_grp, &sd3_9_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) FUNCTION("sd5", sd5_grp, &sd5_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) FUNCTION("sd6_m0", sd6_grp0, &sd6_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) FUNCTION("sd6_m1", sd6_grp1, &sd6_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) FUNCTION("sd9", sd3_9_grp, &sd3_9_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) FUNCTION("sp0_ext_ldo_on",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) sp0_ext_ldo_on_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) &sp0_ext_ldo_on_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) FUNCTION("sp0_qspi", sp0_qspi_grp, &sp0_qspi_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) FUNCTION("sp1_spi", sp1_spi_grp, &sp1_spi_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) FUNCTION("tpiu_trace", tpiu_trace_grp, &tpiu_trace_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) FUNCTION("uart0", uart0_grp, &uart0_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) FUNCTION("uart0_nopause", uart0_nopause_grp, &uart0_nopause_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) FUNCTION("uart1", uart1_grp, &uart1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) FUNCTION("uart2_cts_m0", uart2_cts_grp0, &uart2_cts_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) FUNCTION("uart2_cts_m1", uart2_cts_grp1, &uart2_cts_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) FUNCTION("uart2_rts_m0", uart2_rts_grp0, &uart2_rts_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) FUNCTION("uart2_rts_m1", uart2_rts_grp1, &uart2_rts_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) FUNCTION("uart2_rxd_m0", uart2_rxd_grp0, &uart2_rxd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) FUNCTION("uart2_rxd_m1", uart2_rxd_grp1, &uart2_rxd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) FUNCTION("uart2_rxd_m2", uart2_rxd_grp2, &uart2_rxd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) FUNCTION("uart2_txd_m0", uart2_txd_grp0, &uart2_txd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) FUNCTION("uart2_txd_m1", uart2_txd_grp1, &uart2_txd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) FUNCTION("uart2_txd_m2", uart2_txd_grp2, &uart2_txd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) FUNCTION("uart3_cts_m0", uart3_cts_grp0, &uart3_cts_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) FUNCTION("uart3_cts_m1", uart3_cts_grp1, &uart3_cts_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) FUNCTION("uart3_cts_m2", uart3_cts_grp2, &uart3_cts_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) FUNCTION("uart3_rts_m0", uart3_rts_grp0, &uart3_rts_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) FUNCTION("uart3_rts_m1", uart3_rts_grp1, &uart3_rts_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) FUNCTION("uart3_rts_m2", uart3_rts_grp2, &uart3_rts_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) FUNCTION("uart3_rxd_m0", uart3_rxd_grp0, &uart3_rxd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) FUNCTION("uart3_rxd_m1", uart3_rxd_grp1, &uart3_rxd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) FUNCTION("uart3_rxd_m2", uart3_rxd_grp2, &uart3_rxd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) FUNCTION("uart3_txd_m0", uart3_txd_grp0, &uart3_txd_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) FUNCTION("uart3_txd_m1", uart3_txd_grp1, &uart3_txd_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) FUNCTION("uart3_txd_m2", uart3_txd_grp2, &uart3_txd_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) FUNCTION("uart4_basic", uart4_basic_grp, &uart4_basic_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) FUNCTION("uart4_cts_m0", uart4_cts_grp0, &uart4_cts_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) FUNCTION("uart4_cts_m1", uart4_cts_grp1, &uart4_cts_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) FUNCTION("uart4_cts_m2", uart4_cts_grp2, &uart4_cts_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) FUNCTION("uart4_rts_m0", uart4_rts_grp0, &uart4_rts_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) FUNCTION("uart4_rts_m1", uart4_rts_grp1, &uart4_rts_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) FUNCTION("uart4_rts_m2", uart4_rts_grp2, &uart4_rts_grp2_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) FUNCTION("usb0_drvvbus_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) usb0_drvvbus_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) &usb0_drvvbus_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) FUNCTION("usb0_drvvbus_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) usb0_drvvbus_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) &usb0_drvvbus_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) FUNCTION("usb1_drvvbus_m0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) usb1_drvvbus_grp0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) &usb1_drvvbus_grp0_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) FUNCTION("usb1_drvvbus_m1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) usb1_drvvbus_grp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) &usb1_drvvbus_grp1_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) FUNCTION("visbus_dout", visbus_dout_grp, &visbus_dout_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) FUNCTION("vi_vip1", vi_vip1_grp, &vi_vip1_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) FUNCTION("vi_vip1_ext", vi_vip1_ext_grp, &vi_vip1_ext_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) FUNCTION("vi_vip1_low8bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) vi_vip1_low8bit_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) &vi_vip1_low8bit_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) FUNCTION("vi_vip1_high8bit",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) vi_vip1_high8bit_grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) &vi_vip1_high8bit_grp_mux),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) static struct atlas7_pinctrl_data atlas7_ioc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) .pads = (struct pinctrl_pin_desc *)atlas7_ioc_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) .pads_cnt = ARRAY_SIZE(atlas7_ioc_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) .grps = (struct atlas7_pin_group *)altas7_pin_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) .grps_cnt = ARRAY_SIZE(altas7_pin_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) .funcs = (struct atlas7_pmx_func *)atlas7_pmx_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) .funcs_cnt = ARRAY_SIZE(atlas7_pmx_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) .confs = (struct atlas7_pad_config *)atlas7_ioc_pad_confs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) .confs_cnt = ARRAY_SIZE(atlas7_ioc_pad_confs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) /* Simple map data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) struct map_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) u8 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) u8 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) * struct atlas7_pull_info - Atlas7 Pad pull info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) * @pad_type: The type of this Pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) * @mask: The mas value of this pin's pull bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) * @v2s: The map of pull register value to pull status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) * @s2v: The map of pull status to pull register value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) struct atlas7_pull_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) u8 pad_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) const struct map_data *v2s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) const struct map_data *s2v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) /* Pull Register value map to status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) static const struct map_data p4we_pull_v2s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) { P4WE_PULL_UP, PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) { P4WE_HIGH_HYSTERESIS, HIGH_HYSTERESIS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) { P4WE_HIGH_Z, HIGH_Z },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) { P4WE_PULL_DOWN, PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) static const struct map_data p16st_pull_v2s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) { P16ST_PULL_UP, PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) { PD, PULL_UNKNOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) { P16ST_HIGH_Z, HIGH_Z },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) { P16ST_PULL_DOWN, PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) static const struct map_data pm31_pull_v2s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) { PM31_PULL_DISABLED, PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) { PM31_PULL_ENABLED, PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) static const struct map_data pangd_pull_v2s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) { PANGD_PULL_UP, PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) { PD, PULL_UNKNOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) { PANGD_HIGH_Z, HIGH_Z },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) { PANGD_PULL_DOWN, PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) /* Pull status map to register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) static const struct map_data p4we_pull_s2v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) { PULL_UP, P4WE_PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) { HIGH_HYSTERESIS, P4WE_HIGH_HYSTERESIS },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) { HIGH_Z, P4WE_HIGH_Z },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) { PULL_DOWN, P4WE_PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) { PULL_DISABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) { PULL_ENABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) static const struct map_data p16st_pull_s2v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) { PULL_UP, P16ST_PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) { HIGH_HYSTERESIS, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) { HIGH_Z, P16ST_HIGH_Z },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) { PULL_DOWN, P16ST_PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) { PULL_DISABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) { PULL_ENABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) static const struct map_data pm31_pull_s2v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) { PULL_UP, PM31_PULL_ENABLED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) { HIGH_HYSTERESIS, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) { HIGH_Z, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) { PULL_DOWN, PM31_PULL_DISABLED },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) { PULL_DISABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) { PULL_ENABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) static const struct map_data pangd_pull_s2v[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) { PULL_UP, PANGD_PULL_UP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) { HIGH_HYSTERESIS, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) { HIGH_Z, PANGD_HIGH_Z },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) { PULL_DOWN, PANGD_PULL_DOWN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) { PULL_DISABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) { PULL_ENABLE, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) static const struct atlas7_pull_info atlas7_pull_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) { PAD_T_4WE_PD, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) { PAD_T_4WE_PU, P4WE_PULL_MASK, p4we_pull_v2s, p4we_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) { PAD_T_16ST, P16ST_PULL_MASK, p16st_pull_v2s, p16st_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) { PAD_T_M31_0204_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) { PAD_T_M31_0204_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) { PAD_T_M31_0610_PD, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) { PAD_T_M31_0610_PU, PM31_PULL_MASK, pm31_pull_v2s, pm31_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) { PAD_T_AD, PANGD_PULL_MASK, pangd_pull_v2s, pangd_pull_s2v },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) * struct atlas7_ds_ma_info - Atlas7 Pad DriveStrength & currents info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) * @ma: The Drive Strength in current value .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) * @ds_16st: The correspond raw value of 16st pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) * @ds_4we: The correspond raw value of 4we pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) * @ds_0204m31: The correspond raw value of 0204m31 pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) * @ds_0610m31: The correspond raw value of 0610m31 pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) struct atlas7_ds_ma_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) u32 ma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) u32 ds_16st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) u32 ds_4we;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) u32 ds_0204m31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) u32 ds_0610m31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) static const struct atlas7_ds_ma_info atlas7_ma2ds_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) { 2, DS_16ST_0, DS_4WE_0, DS_M31_0, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) { 4, DS_16ST_1, DS_NULL, DS_M31_1, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) { 6, DS_16ST_2, DS_NULL, DS_NULL, DS_M31_0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) { 8, DS_16ST_3, DS_4WE_1, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) { 10, DS_16ST_4, DS_NULL, DS_NULL, DS_M31_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) { 12, DS_16ST_5, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) { 14, DS_16ST_6, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) { 16, DS_16ST_7, DS_4WE_2, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) { 18, DS_16ST_8, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) { 20, DS_16ST_9, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) { 22, DS_16ST_10, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) { 24, DS_16ST_11, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) { 26, DS_16ST_12, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) { 28, DS_16ST_13, DS_4WE_3, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) { 30, DS_16ST_14, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) { 32, DS_16ST_15, DS_NULL, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) * struct atlas7_ds_info - Atlas7 Pad DriveStrength info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) * @type: The type of this Pad.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) * @mask: The mask value of this pin's pull bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) * @imval: The immediate value of drives trength register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) * @reserved: Reserved space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) struct atlas7_ds_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) u8 imval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) u8 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) static const struct atlas7_ds_info atlas7_ds_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) { PAD_T_4WE_PD, DS_2BIT_MASK, DS_2BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) { PAD_T_4WE_PU, DS_2BIT_MASK, DS_2BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) { PAD_T_16ST, DS_4BIT_MASK, DS_4BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) { PAD_T_M31_0204_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) { PAD_T_M31_0204_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) { PAD_T_M31_0610_PD, DS_1BIT_MASK, DS_1BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) { PAD_T_M31_0610_PU, DS_1BIT_MASK, DS_1BIT_IM_VAL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) { PAD_T_AD, DS_NULL, DS_NULL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) static inline u32 atlas7_pin_to_bank(u32 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) return (pin >= ATLAS7_PINCTRL_BANK_0_PINS) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) static int atlas7_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) return pmx->pctl_data->funcs_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) static const char *atlas7_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) u32 selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) return pmx->pctl_data->funcs[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) static int atlas7_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) u32 selector, const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) u32 * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) *groups = pmx->pctl_data->funcs[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) *num_groups = pmx->pctl_data->funcs[selector].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) static void __atlas7_pmx_pin_input_disable_set(struct atlas7_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) const struct atlas7_pad_mux *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) /* Set Input Disable to avoid input glitches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) * All Input-Disable Control registers are located on IOCRTC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) * So the regs bank is always 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) if (mux->dinput_reg && mux->dinput_val_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) writel(DI_MASK << mux->dinput_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) writel(DI_DISABLE << mux->dinput_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) pmx->regs[BANK_DS] + mux->dinput_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) writel(DIV_MASK << mux->dinput_val_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) writel(DIV_DISABLE << mux->dinput_val_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) pmx->regs[BANK_DS] + mux->dinput_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) static void __atlas7_pmx_pin_input_disable_clr(struct atlas7_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) const struct atlas7_pad_mux *mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) /* Clear Input Disable to avoid input glitches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) if (mux->dinput_reg && mux->dinput_val_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) writel(DI_MASK << mux->dinput_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) pmx->regs[BANK_DS] + CLR_REG(mux->dinput_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) writel(DI_ENABLE << mux->dinput_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) pmx->regs[BANK_DS] + mux->dinput_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) writel(DIV_MASK << mux->dinput_val_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) pmx->regs[BANK_DS] + CLR_REG(mux->dinput_val_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) writel(DIV_ENABLE << mux->dinput_val_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) pmx->regs[BANK_DS] + mux->dinput_val_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) static int __atlas7_pmx_pin_ad_sel(struct atlas7_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) struct atlas7_pad_config *conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) u32 bank, u32 ad_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) unsigned long regv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) /* Write to clear register to clear A/D selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) writel(ANA_CLEAR_MASK << conf->ad_ctrl_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) pmx->regs[bank] + CLR_REG(conf->ad_ctrl_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) /* Set target pad A/D selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) regv &= ~(ANA_CLEAR_MASK << conf->ad_ctrl_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) writel(regv | (ad_sel << conf->ad_ctrl_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) pmx->regs[bank] + conf->ad_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) bank, conf->ad_ctrl_reg, regv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) static int __atlas7_pmx_pin_analog_enable(struct atlas7_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) struct atlas7_pad_config *conf, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) /* Only PAD_T_AD pins can change between Analogue&Digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) if (conf->type != PAD_T_AD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) static int __atlas7_pmx_pin_digital_enable(struct atlas7_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) struct atlas7_pad_config *conf, u32 bank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) /* Other type pads are always digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) if (conf->type != PAD_T_AD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) return __atlas7_pmx_pin_ad_sel(pmx, conf, bank, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) static int __atlas7_pmx_pin_enable(struct atlas7_pmx *pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) u32 pin, u32 func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) struct atlas7_pad_config *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) unsigned long regv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) pr_debug("PMX DUMP ### pin#%d func:%d #### START >>>\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) pin, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) /* Get this Pad's descriptor from PINCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) conf = &pmx->pctl_data->confs[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) bank = atlas7_pin_to_bank(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) /* Just enable the analog function of this pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) if (FUNC_ANALOGUE == func) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) ret = __atlas7_pmx_pin_analog_enable(pmx, conf, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) "Convert pad#%d to analog failed, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) pin, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) /* Set Pads from analog to digital */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) ret = __atlas7_pmx_pin_digital_enable(pmx, conf, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) "Convert pad#%d to digital failed, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) pin, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) /* Write to clear register to clear current function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) writel(FUNC_CLEAR_MASK << conf->mux_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) pmx->regs[bank] + CLR_REG(conf->mux_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) /* Set target pad mux function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) regv = readl(pmx->regs[bank] + conf->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) regv &= ~(FUNC_CLEAR_MASK << conf->mux_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) writel(regv | (func << conf->mux_bit),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) pmx->regs[bank] + conf->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) regv = readl(pmx->regs[bank] + conf->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) pr_debug("bank:%d reg:0x%04x val:0x%08lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) bank, conf->mux_reg, regv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) static int atlas7_pmx_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) u32 func_selector, u32 group_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) struct atlas7_pmx_func *pmx_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) struct atlas7_pin_group *pin_grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) const struct atlas7_grp_mux *grp_mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) const struct atlas7_pad_mux *mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) pmx_func = &pmx->pctl_data->funcs[func_selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) pin_grp = &pmx->pctl_data->grps[group_selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### START >>>\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) pmx_func->name, pin_grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) /* the sd3 and sd9 pin select by SYS2PCI_SDIO9SEL register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) if (pin_grp->pins == (unsigned int *)&sd3_9_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) if (!strcmp(pmx_func->name, "sd9"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) writel(1, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) writel(0, pmx->sys2pci_base + SYS2PCI_SDIO9SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) grp_mux = pmx_func->grpmux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) for (idx = 0; idx < grp_mux->pad_mux_count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) mux = &grp_mux->pad_mux_list[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) __atlas7_pmx_pin_input_disable_set(pmx, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) ret = __atlas7_pmx_pin_enable(pmx, mux->pin, mux->func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) "FUNC:%s GRP:%s PIN#%d.%d failed, ret=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) pmx_func->name, pin_grp->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) mux->pin, mux->func, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) __atlas7_pmx_pin_input_disable_clr(pmx, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) pr_debug("PMX DUMP ### Function:[%s] Group:[%s] #### END <<<\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) pmx_func->name, pin_grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) static u32 convert_current_to_drive_strength(u32 type, u32 ma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) for (idx = 0; idx < ARRAY_SIZE(atlas7_ma2ds_map); idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) if (atlas7_ma2ds_map[idx].ma != ma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) if (type == PAD_T_4WE_PD || type == PAD_T_4WE_PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) return atlas7_ma2ds_map[idx].ds_4we;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) else if (type == PAD_T_16ST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) return atlas7_ma2ds_map[idx].ds_16st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) else if (type == PAD_T_M31_0204_PD || type == PAD_T_M31_0204_PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) return atlas7_ma2ds_map[idx].ds_0204m31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) else if (type == PAD_T_M31_0610_PD || type == PAD_T_M31_0610_PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) return atlas7_ma2ds_map[idx].ds_0610m31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) return DS_NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) static int altas7_pinctrl_set_pull_sel(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) u32 pin, u32 sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) const struct atlas7_pull_info *pull_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) unsigned long regv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) void __iomem *pull_sel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) bank = atlas7_pin_to_bank(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) pull_info = &atlas7_pull_map[conf->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) pull_sel_reg = pmx->regs[bank] + conf->pupd_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) /* Retrieve correspond register value from table by sel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) regv = pull_info->s2v[sel].data & pull_info->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) /* Clear & Set new value to pull register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) writel(pull_info->mask << conf->pupd_bit, CLR_REG(pull_sel_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) writel(regv << conf->pupd_bit, pull_sel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) pr_debug("PIN_CFG ### SET PIN#%d PULL SELECTOR:%d == OK ####\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) pin, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) static int __altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) u32 pin, u32 sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) const struct atlas7_ds_info *ds_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) void __iomem *ds_sel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) ds_info = &atlas7_ds_map[conf->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) if (sel & (~(ds_info->mask)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) goto unsupport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) bank = atlas7_pin_to_bank(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) ds_sel_reg = pmx->regs[bank] + conf->drvstr_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) writel(ds_info->imval << conf->drvstr_bit, CLR_REG(ds_sel_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) writel(sel << conf->drvstr_bit, ds_sel_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) unsupport:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) pr_err("Pad#%d type[%d] doesn't support ds code[%d]!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) pin, conf->type, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) static int altas7_pinctrl_set_drive_strength_sel(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) u32 pin, u32 ma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) struct atlas7_pad_config *conf = &pmx->pctl_data->confs[pin];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) u32 type = conf->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) u32 sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) sel = convert_current_to_drive_strength(conf->type, ma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) if (DS_NULL == sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) pr_err("Pad#%d type[%d] doesn't support ds current[%d]!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) pin, type, ma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) ret = __altas7_pinctrl_set_drive_strength_sel(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) pin, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) pr_debug("PIN_CFG ### SET PIN#%d DS:%d MA:%d == %s ####\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) pin, sel, ma, ret?"FAILED":"OK");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) static int atlas7_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) struct pinctrl_gpio_range *range, u32 pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) u32 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) dev_dbg(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) "atlas7_pmx_gpio_request_enable: pin=%d\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) for (idx = 0; idx < range->npins; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) if (pin == range->pins[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) if (idx >= range->npins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) dev_err(pmx->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) "The pin#%d could not be requested as GPIO!!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) __atlas7_pmx_pin_enable(pmx, pin, FUNC_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) static const struct pinmux_ops atlas7_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) .get_functions_count = atlas7_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) .get_function_name = atlas7_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) .get_function_groups = atlas7_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) .set_mux = atlas7_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) .gpio_request_enable = atlas7_pmx_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) static int atlas7_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) return pmx->pctl_data->grps_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) static const char *atlas7_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) u32 group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) return pmx->pctl_data->grps[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) static int atlas7_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) u32 group, const u32 **pins, u32 *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) struct atlas7_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) *num_pins = pmx->pctl_data->grps[group].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) *pins = pmx->pctl_data->grps[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) static int atlas7_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) struct device_node *np_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) u32 *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) return pinconf_generic_dt_node_to_map(pctldev, np_config, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) num_maps, PIN_MAP_TYPE_INVALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) static void atlas7_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) struct pinctrl_map *map, u32 num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) static const struct pinctrl_ops atlas7_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) .get_groups_count = atlas7_pinctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) .get_group_name = atlas7_pinctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) .get_group_pins = atlas7_pinctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) .dt_node_to_map = atlas7_pinctrl_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) .dt_free_map = atlas7_pinctrl_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) static int atlas7_pin_config_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) unsigned pin, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) u16 param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) int idx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) for (idx = 0; idx < num_configs; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) param = pinconf_to_config_param(configs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) arg = pinconf_to_config_argument(configs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d >>>>>\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) pin, atlas7_ioc_pads[pin].name, param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) err = altas7_pinctrl_set_pull_sel(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) pin, PULL_UP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) err = altas7_pinctrl_set_pull_sel(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) pin, PULL_DOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) err = altas7_pinctrl_set_pull_sel(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) pin, HIGH_HYSTERESIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) err = altas7_pinctrl_set_pull_sel(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) pin, HIGH_Z);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) err = altas7_pinctrl_set_drive_strength_sel(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) pr_debug("PMX CFG###### ATLAS7 PIN#%d [%s] CONFIG PARAM:%d ARG:%d <<<<\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) pin, atlas7_ioc_pads[pin].name, param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) static int atlas7_pin_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) unsigned group, unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) ret = atlas7_pinctrl_get_group_pins(pctldev, group, &pins, &npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) if (atlas7_pin_config_set(pctldev, pins[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) configs, num_configs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) static const struct pinconf_ops atlas7_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) .pin_config_set = atlas7_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) .pin_config_group_set = atlas7_pin_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) static int atlas7_pinmux_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) struct atlas7_pmx *pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) u32 banks = ATLAS7_PINCTRL_REG_BANKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) struct device_node *sys2pci_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) /* Create state holders etc for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) if (!pmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) /* The sd3 and sd9 shared all pins, and the function select by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) * SYS2PCI_SDIO9SEL register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) sys2pci_np = of_find_node_by_name(NULL, "sys2pci");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) if (!sys2pci_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) ret = of_address_to_resource(sys2pci_np, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) of_node_put(sys2pci_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) pmx->sys2pci_base = devm_ioremap_resource(&pdev->dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) if (IS_ERR(pmx->sys2pci_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) pmx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) pmx->pctl_data = &atlas7_ioc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) pmx->pctl_desc.name = "pinctrl-atlas7";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) pmx->pctl_desc.pins = pmx->pctl_data->pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) pmx->pctl_desc.npins = pmx->pctl_data->pads_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) pmx->pctl_desc.pctlops = &atlas7_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) pmx->pctl_desc.pmxops = &atlas7_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) pmx->pctl_desc.confops = &atlas7_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) for (idx = 0; idx < banks; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) pmx->regs[idx] = of_iomap(np, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) if (!pmx->regs[idx]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) "can't map ioc bank#%d registers\n", idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) goto unmap_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) /* Now register the pin controller and all pins it handles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) pmx->pctl = pinctrl_register(&pmx->pctl_desc, &pdev->dev, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) if (IS_ERR(pmx->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) dev_err(&pdev->dev, "could not register atlas7 pinmux driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) ret = PTR_ERR(pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) goto unmap_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) platform_set_drvdata(pdev, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) dev_info(&pdev->dev, "initialized atlas7 pinmux driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) unmap_io:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) for (idx = 0; idx < banks; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) if (!pmx->regs[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) iounmap(pmx->regs[idx]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) static int atlas7_pinmux_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) struct atlas7_pmx *pmx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) struct atlas7_pad_status *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) struct atlas7_pad_config *conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) const struct atlas7_ds_info *ds_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) const struct atlas7_pull_info *pull_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) u32 bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) unsigned long regv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) /* Get this Pad's descriptor from PINCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) conf = &pmx->pctl_data->confs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) bank = atlas7_pin_to_bank(idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) status = &pmx->sleep_data[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) /* Save Function selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) regv = readl(pmx->regs[bank] + conf->mux_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) status->func = (regv >> conf->mux_bit) & FUNC_CLEAR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) /* Check if Pad is in Analogue selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) if (conf->ad_ctrl_reg == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) goto save_ds_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) regv = readl(pmx->regs[bank] + conf->ad_ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) if (!(regv & (conf->ad_ctrl_bit << ANA_CLEAR_MASK)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) status->func = FUNC_ANALOGUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) save_ds_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) if (conf->drvstr_reg == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) goto save_pull_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) /* Save Drive Strength selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) ds_info = &atlas7_ds_map[conf->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) regv = readl(pmx->regs[bank] + conf->drvstr_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) status->dstr = (regv >> conf->drvstr_bit) & ds_info->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) save_pull_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) /* Save Pull selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) pull_info = &atlas7_pull_map[conf->type];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) regv = readl(pmx->regs[bank] + conf->pupd_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) regv = (regv >> conf->pupd_bit) & pull_info->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) status->pull = pull_info->v2s[regv].data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) * Save disable input selector, this selector is not for Pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) * but for Mux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) pmx->status_ds[idx] = readl(pmx->regs[BANK_DS] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) IN_DISABLE_0_REG_SET + 0x8 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) pmx->status_dsv[idx] = readl(pmx->regs[BANK_DS] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) static int atlas7_pinmux_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) struct atlas7_pmx *pmx = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) struct atlas7_pad_status *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) for (idx = 0; idx < pmx->pctl_desc.npins; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) /* Get this Pad's descriptor from PINCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) status = &pmx->sleep_data[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) /* Restore Function selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) __atlas7_pmx_pin_enable(pmx, idx, (u32)status->func & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) if (FUNC_ANALOGUE == status->func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) goto restore_pull_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) /* Restore Drive Strength selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) __altas7_pinctrl_set_drive_strength_sel(pmx->pctl, idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) (u32)status->dstr & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) restore_pull_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) /* Restore Pull selector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) altas7_pinctrl_set_pull_sel(pmx->pctl, idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) (u32)status->pull & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) * Restore disable input selector, this selector is not for Pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) * but for Mux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) for (idx = 0; idx < NUM_OF_IN_DISABLE_REG; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) writel(~0, pmx->regs[BANK_DS] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) IN_DISABLE_0_REG_CLR + 0x8 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) writel(pmx->status_ds[idx], pmx->regs[BANK_DS] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) IN_DISABLE_0_REG_SET + 0x8 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) writel(~0, pmx->regs[BANK_DS] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) IN_DISABLE_VAL_0_REG_CLR + 0x8 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) writel(pmx->status_dsv[idx], pmx->regs[BANK_DS] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) IN_DISABLE_VAL_0_REG_SET + 0x8 * idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) static const struct dev_pm_ops atlas7_pinmux_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) .suspend_noirq = atlas7_pinmux_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) .resume_noirq = atlas7_pinmux_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) .freeze_noirq = atlas7_pinmux_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) .restore_noirq = atlas7_pinmux_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) static const struct of_device_id atlas7_pinmux_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) { .compatible = "sirf,atlas7-ioc",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) static struct platform_driver atlas7_pinmux_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) .name = "atlas7-ioc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) .of_match_table = atlas7_pinmux_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) .pm = &atlas7_pinmux_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) .probe = atlas7_pinmux_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) static int __init atlas7_pinmux_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) return platform_driver_register(&atlas7_pinmux_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) arch_initcall(atlas7_pinmux_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) * The Following is GPIO Code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) static inline struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) atlas7_gpio_bank *atlas7_gpio_to_bank(struct atlas7_gpio_chip *a7gc, u32 gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) return &a7gc->banks[GPIO_TO_BANK(gpio)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) static int __atlas7_gpio_to_pin(struct atlas7_gpio_chip *a7gc, u32 gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) u32 ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) bank = atlas7_gpio_to_bank(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) ofs = gpio - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) if (ofs >= bank->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) return bank->gpio_pins[ofs];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) static void atlas7_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) u32 val, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) pin_in_bank = d->hwirq - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) val = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) /* clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) writel(val, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) static void __atlas7_gpio_irq_mask(struct atlas7_gpio_chip *a7gc, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) u32 val, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) bank = atlas7_gpio_to_bank(a7gc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) pin_in_bank = idx - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) val = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) val &= ~(ATLAS7_GPIO_CTL_INTR_EN_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) ATLAS7_GPIO_CTL_INTR_STATUS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) writel(val, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) static void atlas7_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) __atlas7_gpio_irq_mask(a7gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) static void atlas7_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) u32 val, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) pin_in_bank = d->hwirq - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) val = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) val &= ~ATLAS7_GPIO_CTL_INTR_STATUS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) val |= ATLAS7_GPIO_CTL_INTR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) writel(val, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) static int atlas7_gpio_irq_type(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) u32 val, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) bank = atlas7_gpio_to_bank(a7gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) pin_in_bank = d->hwirq - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) val = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) val &= ~(ATLAS7_GPIO_CTL_INTR_STATUS_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) ATLAS7_GPIO_CTL_INTR_EN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) case IRQ_TYPE_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) val &= ~ATLAS7_GPIO_CTL_INTR_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) val &= ~ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) ATLAS7_GPIO_CTL_INTR_LOW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) ATLAS7_GPIO_CTL_INTR_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) val &= ~(ATLAS7_GPIO_CTL_INTR_HIGH_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) val |= ATLAS7_GPIO_CTL_INTR_LOW_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) val |= ATLAS7_GPIO_CTL_INTR_HIGH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) val &= ~(ATLAS7_GPIO_CTL_INTR_LOW_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) ATLAS7_GPIO_CTL_INTR_TYPE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) writel(val, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) static struct irq_chip atlas7_gpio_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) .name = "atlas7-gpio-irq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) .irq_ack = atlas7_gpio_irq_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) .irq_mask = atlas7_gpio_irq_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) .irq_unmask = atlas7_gpio_irq_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) .irq_set_type = atlas7_gpio_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) static void atlas7_gpio_handle_irq(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) struct atlas7_gpio_bank *bank = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) u32 status, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) int pin_in_bank = 0, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) unsigned int irq = irq_desc_get_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) for (idx = 0; idx < a7gc->nbank; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) bank = &a7gc->banks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) if (bank->irq == irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) BUG_ON(idx == a7gc->nbank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) status = readl(ATLAS7_GPIO_INT_STATUS(bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) pr_warn("%s: gpio [%s] status %#x no interrupt is flagged\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) __func__, gc->label, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) handle_bad_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) while (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) ctrl = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) * Here we must check whether the corresponding GPIO's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) * interrupt has been enabled, otherwise just skip it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) if ((status & 0x1) && (ctrl & ATLAS7_GPIO_CTL_INTR_EN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) pr_debug("%s: chip[%s] gpio:%d happens\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) __func__, gc->label,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) bank->gpio_offset + pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) generic_handle_irq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) irq_find_mapping(gc->irq.domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) bank->gpio_offset + pin_in_bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) if (++pin_in_bank >= bank->ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) status = status >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) static void __atlas7_gpio_set_input(struct atlas7_gpio_chip *a7gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) u32 val, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) bank = atlas7_gpio_to_bank(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) pin_in_bank = gpio - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) val = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) val &= ~ATLAS7_GPIO_CTL_OUT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) writel(val, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) static int atlas7_gpio_request(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) ret = __atlas7_gpio_to_pin(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) if (pinctrl_gpio_request(chip->base + gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) * default status:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) * set direction as input and mask irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) __atlas7_gpio_set_input(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) __atlas7_gpio_irq_mask(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) static void atlas7_gpio_free(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) __atlas7_gpio_irq_mask(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) __atlas7_gpio_set_input(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) pinctrl_gpio_free(chip->base + gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) static int atlas7_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) __atlas7_gpio_set_input(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) static void __atlas7_gpio_set_output(struct atlas7_gpio_chip *a7gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) u32 out_ctrl, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) bank = atlas7_gpio_to_bank(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) pin_in_bank = gpio - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) out_ctrl = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) out_ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) out_ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) out_ctrl &= ~ATLAS7_GPIO_CTL_INTR_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) out_ctrl |= ATLAS7_GPIO_CTL_OUT_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) writel(out_ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) static int atlas7_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) __atlas7_gpio_set_output(a7gc, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) static int atlas7_gpio_get_value(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) u32 val, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) bank = atlas7_gpio_to_bank(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) pin_in_bank = gpio - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) val = readl(ATLAS7_GPIO_CTRL(bank, pin_in_bank));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) return !!(val & ATLAS7_GPIO_CTL_DATAIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) static void atlas7_gpio_set_value(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) struct atlas7_gpio_chip *a7gc = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) u32 ctrl, pin_in_bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) bank = atlas7_gpio_to_bank(a7gc, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) pin_in_bank = gpio - bank->gpio_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin_in_bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) raw_spin_lock_irqsave(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) ctrl = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) ctrl |= ATLAS7_GPIO_CTL_DATAOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) ctrl &= ~ATLAS7_GPIO_CTL_DATAOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) writel(ctrl, ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) raw_spin_unlock_irqrestore(&a7gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) static const struct of_device_id atlas7_gpio_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) { .compatible = "sirf,atlas7-gpio", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) static int atlas7_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) struct atlas7_gpio_chip *a7gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) u32 nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) int ret, idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) ret = of_property_read_u32(np, "gpio-banks", &nbank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) "Could not find GPIO bank info,ret=%d!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) /* retrieve gpio descriptor data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) if (!a7gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) /* Get Gpio clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) a7gc->clk = of_clk_get(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) if (!IS_ERR(a7gc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) ret = clk_prepare_enable(a7gc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) "Could not enable clock!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) /* Get Gpio Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) a7gc->reg = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) if (!a7gc->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) dev_err(&pdev->dev, "Could not map GPIO Registers!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) a7gc->nbank = nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) raw_spin_lock_init(&a7gc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) /* Setup GPIO Chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) chip = &a7gc->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) chip->request = atlas7_gpio_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) chip->free = atlas7_gpio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) chip->direction_input = atlas7_gpio_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) chip->get = atlas7_gpio_get_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) chip->direction_output = atlas7_gpio_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) chip->set = atlas7_gpio_set_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) /* Each chip can support 32 pins at one bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) chip->ngpio = NGPIO_OF_BANK * nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) chip->label = kstrdup(np->name, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) chip->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) chip->of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) chip->parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) girq->chip = &atlas7_gpio_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) girq->parent_handler = atlas7_gpio_handle_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) girq->num_parents = nbank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) girq->parents = devm_kcalloc(&pdev->dev, nbank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) for (idx = 0; idx < nbank; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) bank = &a7gc->banks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) /* Set ctrl registers' base of this bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) bank->base = ATLAS7_GPIO_BASE(a7gc, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) bank->gpio_offset = idx * NGPIO_OF_BANK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) /* Get interrupt number from DTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) ret = of_irq_get(np, idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) "Unable to find IRQ number. ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) bank->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) girq->parents[idx] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) /* Add gpio chip to system */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) ret = gpiochip_add_data(chip, a7gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) "%pOF: error in probe function with status %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) np, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) goto failed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) platform_set_drvdata(pdev, a7gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) dev_info(&pdev->dev, "add to system.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) failed:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) static int atlas7_gpio_suspend_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) u32 idx, pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) for (idx = 0; idx < a7gc->nbank; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) bank = &a7gc->banks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) for (pin = 0; pin < bank->ngpio; pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) bank->sleep_data[pin] = readl(ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) static int atlas7_gpio_resume_noirq(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) struct atlas7_gpio_chip *a7gc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) struct atlas7_gpio_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) void __iomem *ctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) u32 idx, pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) for (idx = 0; idx < a7gc->nbank; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) bank = &a7gc->banks[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) for (pin = 0; pin < bank->ngpio; pin++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) ctrl_reg = ATLAS7_GPIO_CTRL(bank, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) writel(bank->sleep_data[pin], ctrl_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) static const struct dev_pm_ops atlas7_gpio_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) .suspend_noirq = atlas7_gpio_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) .resume_noirq = atlas7_gpio_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) .freeze_noirq = atlas7_gpio_suspend_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) .restore_noirq = atlas7_gpio_resume_noirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) static struct platform_driver atlas7_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) .name = "atlas7-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) .of_match_table = atlas7_gpio_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) .pm = &atlas7_gpio_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) .probe = atlas7_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) static int __init atlas7_gpio_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) return platform_driver_register(&atlas7_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) subsys_initcall(atlas7_gpio_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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