^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * http://www.linaro.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef __PINCTRL_SAMSUNG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define __PINCTRL_SAMSUNG_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * enum pincfg_type - possible pin configuration types supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @PINCFG_TYPE_FUNC: Function configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @PINCFG_TYPE_DAT: Pin value configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @PINCFG_TYPE_PUD: Pull up/down configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @PINCFG_TYPE_DRV: Drive strength configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @PINCFG_TYPE_CON_PDN: Pin function in power down mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @PINCFG_TYPE_PUD_PDN: Pull up/down configuration in power down mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) enum pincfg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINCFG_TYPE_FUNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PINCFG_TYPE_DAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PINCFG_TYPE_PUD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINCFG_TYPE_DRV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINCFG_TYPE_CON_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINCFG_TYPE_PUD_PDN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCFG_TYPE_NUM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * pin configuration (pull up/down and drive strength) type and its value are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * packed together into a 16-bits. The upper 8-bits represent the configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * type and the lower 8-bits hold the value of the configuration type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PINCFG_TYPE_MASK 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PINCFG_VALUE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PINCFG_VALUE_MASK (0xFF << PINCFG_VALUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PINCFG_PACK(type, value) (((value) << PINCFG_VALUE_SHIFT) | type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PINCFG_UNPACK_TYPE(cfg) ((cfg) & PINCFG_TYPE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PINCFG_UNPACK_VALUE(cfg) (((cfg) & PINCFG_VALUE_MASK) >> \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCFG_VALUE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * enum eint_type - possible external interrupt types.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @EINT_TYPE_NONE: bank does not support external interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @EINT_TYPE_GPIO: bank supportes external gpio interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @EINT_TYPE_WKUP: bank supportes external wakeup interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @EINT_TYPE_WKUP_MUX: bank supports multiplexed external wakeup interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Samsung GPIO controller groups all the available pins into banks. The pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * in a pin bank can support external gpio interrupts or external wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * interrupts or no interrupts at all. From a software perspective, the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * difference between external gpio and external wakeup interrupts is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * the wakeup interrupts can additionally wakeup the system if it is in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * suspended state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) enum eint_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) EINT_TYPE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) EINT_TYPE_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) EINT_TYPE_WKUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) EINT_TYPE_WKUP_MUX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* maximum length of a pin in pin descriptor (example: "gpa0-0") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PIN_NAME_LENGTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PIN_GROUP(n, p, f) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .pins = p, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .num_pins = ARRAY_SIZE(p), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .func = f \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PMX_FUNC(n, g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = n, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .groups = g, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .num_groups = ARRAY_SIZE(g), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct samsung_pinctrl_drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * struct samsung_pin_bank_type: pin bank type description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @fld_width: widths of configuration bitfields (0 if unavailable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @reg_offset: offsets of configuration registers (don't care of width is 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct samsung_pin_bank_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u8 fld_width[PINCFG_TYPE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 reg_offset[PINCFG_TYPE_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * struct samsung_pin_bank_data: represent a controller pin-bank (init data).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @type: type of the bank (register offsets and bitfield widths)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @pctl_offset: starting offset of the pin-bank registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @pctl_res_idx: index of base address for pin-bank registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @nr_pins: number of pins included in this bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @eint_func: function to set in CON register to configure pin as EINT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @eint_type: type of the external interrupt supported by the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @eint_mask: bit mask of pins which support EINT function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @name: name to be prefixed for each pin in this pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct samsung_pin_bank_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) const struct samsung_pin_bank_type *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 pctl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u8 pctl_res_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u8 nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 eint_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) enum eint_type eint_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 eint_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 eint_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * struct samsung_pin_bank: represent a controller pin-bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @type: type of the bank (register offsets and bitfield widths)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @pctl_base: base address of the pin-bank registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @pctl_offset: starting offset of the pin-bank registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @nr_pins: number of pins included in this bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @eint_base: base address of the pin-bank EINT registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @eint_func: function to set in CON register to configure pin as EINT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @eint_type: type of the external interrupt supported by the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @eint_mask: bit mask of pins which support EINT function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @eint_offset: SoC-specific EINT register or interrupt offset of bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @name: name to be prefixed for each pin in this pin bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @pin_base: starting pin number of the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @soc_priv: per-bank private data for SoC-specific code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @of_node: OF node of the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @drvdata: link to controller driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @irq_domain: IRQ domain of the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @gpio_chip: GPIO chip of the bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @grange: linux gpio pin range supported by this bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @irq_chip: link to irq chip for external gpio and wakeup interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @slock: spinlock protecting bank registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @pm_save: saved register values during suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct samsung_pin_bank {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const struct samsung_pin_bank_type *type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) void __iomem *pctl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 pctl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *eint_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 eint_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) enum eint_type eint_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 eint_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 eint_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) void *soc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct device_node *of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct samsung_pinctrl_drv_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct irq_domain *irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct gpio_chip gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct pinctrl_gpio_range grange;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct exynos_irq_chip *irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) spinlock_t slock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * struct samsung_retention_data: runtime pin-bank retention control data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @regs: array of PMU registers to control pad retention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @nr_regs: number of registers in @regs array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @value: value to store to registers to turn off retention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @refcnt: atomic counter if retention control affects more than one bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @priv: retention control code private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @enable: platform specific callback to enter retention mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @disable: platform specific callback to exit retention mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct samsung_retention_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const u32 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int nr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) atomic_t *refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void (*enable)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) void (*disable)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * struct samsung_retention_data: represent a pin-bank retention control data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @regs: array of PMU registers to control pad retention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @nr_regs: number of registers in @regs array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @value: value to store to registers to turn off retention.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @refcnt: atomic counter if retention control affects more than one bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @init: platform specific callback to initialize retention control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) **/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct samsung_retention_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) const u32 *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int nr_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) atomic_t *refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct samsung_retention_ctrl *(*init)(struct samsung_pinctrl_drv_data *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) const struct samsung_retention_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * struct samsung_pin_ctrl: represent a pin controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @pin_banks: list of pin banks included in this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @nr_banks: number of pin banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @nr_ext_resources: number of the extra base address for pin banks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @retention_data: configuration data for retention control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @eint_gpio_init: platform specific callback to setup the external gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * interrupts for the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @eint_wkup_init: platform specific callback to setup the external wakeup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * interrupts for the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @suspend: platform specific suspend callback, executed during pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * device suspend, see samsung_pinctrl_suspend()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @resume: platform specific resume callback, executed during pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * device suspend, see samsung_pinctrl_resume()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * External wakeup interrupts must define at least eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * retention_data and suspend in order for proper suspend/resume to work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct samsung_pin_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct samsung_pin_bank_data *pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) unsigned int nr_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned int nr_ext_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) const struct samsung_retention_data *retention_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) void (*suspend)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) void (*resume)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @node: global list node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @virt_base: register base address of the controller; this will be equal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * to each bank samsung_pin_bank->pctl_base and used on legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * platforms (like S3C24XX or S3C64XX) which has to access the base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * through samsung_pinctrl_drv_data, not samsung_pin_bank).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @dev: device instance representing the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @irq: interrpt number used by the controller to notify gpio interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @ctrl: pin controller instance managed by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @pctl: pin controller descriptor registered with the pinctrl subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @pctl_dev: cookie representing pinctrl device instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @pin_groups: list of pin groups available to the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @nr_groups: number of such pin groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @pmx_functions: list of pin functions available to the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @nr_function: number of such pin functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @pin_base: starting system wide pin number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @nr_pins: number of pins supported by the controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @retention_ctrl: retention control runtime data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @suspend: platform specific suspend callback, executed during pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * device suspend, see samsung_pinctrl_suspend()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @resume: platform specific resume callback, executed during pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * device suspend, see samsung_pinctrl_resume()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct samsung_pinctrl_drv_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void __iomem *virt_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct pinctrl_desc pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct pinctrl_dev *pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const struct samsung_pin_group *pin_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned int nr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct samsung_pmx_func *pmx_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int nr_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct samsung_pin_bank *pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int nr_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) unsigned int pin_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned int nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct samsung_retention_ctrl *retention_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void (*suspend)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) void (*resume)(struct samsung_pinctrl_drv_data *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * struct samsung_pinctrl_of_match_data: OF match device specific configuration data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @ctrl: array of pin controller data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @num_ctrl: size of array @ctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct samsung_pinctrl_of_match_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) const struct samsung_pin_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) unsigned int num_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * struct samsung_pin_group: represent group of pins of a pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @name: name of the pin group, used to lookup the group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @pins: the pins included in this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @num_pins: number of pins included in this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @func: the function number to be programmed when selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct samsung_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * struct samsung_pmx_func: represent a pin function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * @name: name of the pin function, used to lookup the function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @groups: one or more names of pin groups that provide this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * @num_groups: number of groups included in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct samsung_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* list of all exported SoC specific data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) extern const struct samsung_pinctrl_of_match_data exynos3250_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) extern const struct samsung_pinctrl_of_match_data exynos4210_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) extern const struct samsung_pinctrl_of_match_data exynos4x12_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) extern const struct samsung_pinctrl_of_match_data exynos5250_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) extern const struct samsung_pinctrl_of_match_data exynos5260_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) extern const struct samsung_pinctrl_of_match_data exynos5410_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) extern const struct samsung_pinctrl_of_match_data exynos5420_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) extern const struct samsung_pinctrl_of_match_data exynos5433_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) extern const struct samsung_pinctrl_of_match_data exynos7_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) extern const struct samsung_pinctrl_of_match_data s3c64xx_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) extern const struct samsung_pinctrl_of_match_data s3c2412_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) extern const struct samsung_pinctrl_of_match_data s3c2416_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) extern const struct samsung_pinctrl_of_match_data s3c2440_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) extern const struct samsung_pinctrl_of_match_data s3c2450_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) extern const struct samsung_pinctrl_of_match_data s5pv210_of_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif /* __PINCTRL_SAMSUNG_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags