^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // S3C24XX specific support for Samsung pinctrl/gpiolib driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // This file contains the SamsungS3C24XX specific information required by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Samsung pinctrl/gpiolib driver. It also includes the implementation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // external gpio and wakeup interrupt support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irqdomain.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/irqchip/chained_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define NUM_EINT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define NUM_EINT_IRQ 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EINT_MAX_PER_GROUP 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EINTPEND_REG 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EINTMASK_REG 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EINT_GROUP(i) ((int)((i) / EINT_MAX_PER_GROUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EINT_REG(i) ((EINT_GROUP(i) * 4) + 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EINT_OFFS(i) ((i) % EINT_MAX_PER_GROUP * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EINT_LEVEL_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EINT_LEVEL_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EINT_EDGE_FALLING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EINT_EDGE_RISING 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EINT_EDGE_BOTH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EINT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct samsung_pin_bank_type bank_type_1bit = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .fld_width = { 1, 1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .reg_offset = { 0x00, 0x04, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct samsung_pin_bank_type bank_type_2bit = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .fld_width = { 2, 1, 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .reg_offset = { 0x00, 0x04, 0x08, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PIN_BANK_A(pins, reg, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .type = &bank_type_1bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .eint_type = EINT_TYPE_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PIN_BANK_2BIT(pins, reg, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .type = &bank_type_2bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .eint_type = EINT_TYPE_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PIN_BANK_2BIT_EINTW(pins, reg, id, eoffs, emask)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .type = &bank_type_2bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .eint_type = EINT_TYPE_WKUP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .eint_func = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .eint_mask = emask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .eint_offset = eoffs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * struct s3c24xx_eint_data - EINT common data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @drvdata: pin controller driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @domains: IRQ domains of particular EINT interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @parents: mapped parent irqs in the main interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct s3c24xx_eint_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct samsung_pinctrl_drv_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct irq_domain *domains[NUM_EINT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int parents[NUM_EINT_IRQ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct s3c24xx_eint_domain_data - per irq-domain data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @bank: pin bank related to the domain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @eint_data: common data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @eint0_3_parent_only: live eints 0-3 only in the main intc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct s3c24xx_eint_domain_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct samsung_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct s3c24xx_eint_data *eint_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bool eint0_3_parent_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int s3c24xx_eint_get_trigger(unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return EINT_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return EINT_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return EINT_EDGE_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return EINT_LEVEL_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return EINT_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void s3c24xx_eint_set_handler(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Edge- and level-triggered interrupts need different handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (type & IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static void s3c24xx_eint_set_function(struct samsung_pinctrl_drv_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct samsung_pin_bank *bank, int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct samsung_pin_bank_type *bank_type = bank->type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Make sure that pin is configured as interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) reg = d->virt_base + bank->pctl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) shift = pin * bank_type->fld_width[PINCFG_TYPE_FUNC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mask = (1 << bank_type->fld_width[PINCFG_TYPE_FUNC]) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) spin_lock_irqsave(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) val &= ~(mask << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) val |= bank->eint_func << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) spin_unlock_irqrestore(&bank->slock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int s3c24xx_eint_type(struct irq_data *data, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int index = bank->eint_offset + data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) int trigger;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) trigger = s3c24xx_eint_get_trigger(type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (trigger < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(d->dev, "unsupported external interrupt type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) s3c24xx_eint_set_handler(data, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Set up interrupt trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) reg = d->virt_base + EINT_REG(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) shift = EINT_OFFS(index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) val = readl(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) val &= ~(EINT_MASK << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) val |= trigger << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) writel(val, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) s3c24xx_eint_set_function(d, bank, data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Handling of EINTs 0-3 on all except S3C2412 and S3C2413 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static void s3c2410_eint0_3_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct s3c24xx_eint_data *eint_data = ddata->eint_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int parent_irq = eint_data->parents[data->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct irq_chip *parent_chip = irq_get_chip(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) parent_chip->irq_ack(irq_get_irq_data(parent_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void s3c2410_eint0_3_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct s3c24xx_eint_data *eint_data = ddata->eint_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int parent_irq = eint_data->parents[data->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct irq_chip *parent_chip = irq_get_chip(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) parent_chip->irq_mask(irq_get_irq_data(parent_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static void s3c2410_eint0_3_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct s3c24xx_eint_domain_data *ddata = bank->irq_domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct s3c24xx_eint_data *eint_data = ddata->eint_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int parent_irq = eint_data->parents[data->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct irq_chip *parent_chip = irq_get_chip(parent_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) parent_chip->irq_unmask(irq_get_irq_data(parent_irq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct irq_chip s3c2410_eint0_3_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = "s3c2410-eint0_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .irq_ack = s3c2410_eint0_3_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .irq_mask = s3c2410_eint0_3_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .irq_unmask = s3c2410_eint0_3_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .irq_set_type = s3c24xx_eint_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void s3c2410_demux_eint0_3(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct irq_data *data = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* the first 4 eints have a simple 1 to 1 mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Something must be really wrong if an unmapped EINT is unmasked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) BUG_ON(!virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Handling of EINTs 0-3 on S3C2412 and S3C2413 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void s3c2412_eint0_3_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long bitval = 1UL << data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(bitval, d->virt_base + EINTPEND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void s3c2412_eint0_3_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mask = readl(d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mask |= (1UL << data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) writel(mask, d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void s3c2412_eint0_3_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mask = readl(d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mask &= ~(1UL << data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(mask, d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct irq_chip s3c2412_eint0_3_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .name = "s3c2412-eint0_3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .irq_ack = s3c2412_eint0_3_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .irq_mask = s3c2412_eint0_3_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .irq_unmask = s3c2412_eint0_3_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .irq_set_type = s3c24xx_eint_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static void s3c2412_demux_eint0_3(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct s3c24xx_eint_data *eint_data = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct irq_data *data = irq_desc_get_irq_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct irq_chip *chip = irq_data_get_irq_chip(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* the first 4 eints have a simple 1 to 1 mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) virq = irq_linear_revmap(eint_data->domains[data->hwirq], data->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Something must be really wrong if an unmapped EINT is unmasked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) BUG_ON(!virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* Handling of all other eints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void s3c24xx_eint_ack(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned char index = bank->eint_offset + data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) writel(1UL << index, d->virt_base + EINTPEND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static void s3c24xx_eint_mask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) unsigned char index = bank->eint_offset + data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mask = readl(d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) mask |= (1UL << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) writel(mask, d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static void s3c24xx_eint_unmask(struct irq_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct samsung_pinctrl_drv_data *d = bank->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) unsigned char index = bank->eint_offset + data->hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mask = readl(d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) mask &= ~(1UL << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) writel(mask, d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct irq_chip s3c24xx_eint_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .name = "s3c-eint",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .irq_ack = s3c24xx_eint_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .irq_mask = s3c24xx_eint_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .irq_unmask = s3c24xx_eint_unmask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .irq_set_type = s3c24xx_eint_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static inline void s3c24xx_demux_eint(struct irq_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 offset, u32 range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct s3c24xx_eint_data *data = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct samsung_pinctrl_drv_data *d = data->drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int pend, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) pend = readl(d->virt_base + EINTPEND_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mask = readl(d->virt_base + EINTMASK_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) pend &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) pend &= range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) while (pend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int virq, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq = __ffs(pend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pend &= ~(1 << irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) virq = irq_linear_revmap(data->domains[irq], irq - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Something is really wrong if an unmapped EINT is unmasked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) BUG_ON(!virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) generic_handle_irq(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static void s3c24xx_demux_eint4_7(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) s3c24xx_demux_eint(desc, 0, 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void s3c24xx_demux_eint8_23(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) s3c24xx_demux_eint(desc, 8, 0xffff00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static irq_flow_handler_t s3c2410_eint_handlers[NUM_EINT_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) s3c2410_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) s3c2410_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) s3c2410_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) s3c2410_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) s3c24xx_demux_eint4_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) s3c24xx_demux_eint8_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static irq_flow_handler_t s3c2412_eint_handlers[NUM_EINT_IRQ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) s3c2412_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) s3c2412_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) s3c2412_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) s3c2412_demux_eint0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) s3c24xx_demux_eint4_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) s3c24xx_demux_eint8_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int s3c24xx_gpf_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct s3c24xx_eint_domain_data *ddata = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct samsung_pin_bank *bank = ddata->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (hw <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (ddata->eint0_3_parent_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) irq_set_chip_and_handler(virq, &s3c2410_eint0_3_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) irq_set_chip_and_handler(virq, &s3c2412_eint0_3_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) irq_set_chip_and_handler(virq, &s3c24xx_eint_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) irq_set_chip_data(virq, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct irq_domain_ops s3c24xx_gpf_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .map = s3c24xx_gpf_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int s3c24xx_gpg_irq_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct s3c24xx_eint_domain_data *ddata = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct samsung_pin_bank *bank = ddata->bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!(bank->eint_mask & (1 << (bank->eint_offset + hw))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) irq_set_chip_and_handler(virq, &s3c24xx_eint_chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) irq_set_chip_data(virq, bank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct irq_domain_ops s3c24xx_gpg_irq_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .map = s3c24xx_gpg_irq_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .xlate = irq_domain_xlate_twocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct of_device_id s3c24xx_eint_irq_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { .compatible = "samsung,s3c2410-wakeup-eint", .data = (void *)1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { .compatible = "samsung,s3c2412-wakeup-eint", .data = (void *)0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static int s3c24xx_eint_init(struct samsung_pinctrl_drv_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct device *dev = d->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct device_node *eint_np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct samsung_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct s3c24xx_eint_data *eint_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) const struct irq_domain_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bool eint0_3_parent_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) irq_flow_handler_t *handlers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) for_each_child_of_node(dev->of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) match = of_match_node(s3c24xx_eint_irq_ids, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) eint_np = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) eint0_3_parent_only = (bool)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!eint_np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) eint_data = devm_kzalloc(dev, sizeof(*eint_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!eint_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) of_node_put(eint_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) eint_data->drvdata = d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) handlers = eint0_3_parent_only ? s3c2410_eint_handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) : s3c2412_eint_handlers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) for (i = 0; i < NUM_EINT_IRQ; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) irq = irq_of_parse_and_map(eint_np, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_err(dev, "failed to get wakeup EINT IRQ %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) of_node_put(eint_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) eint_data->parents[i] = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) irq_set_chained_handler_and_data(irq, handlers[i], eint_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) of_node_put(eint_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) bank = d->pin_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) for (i = 0; i < d->nr_banks; ++i, ++bank) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct s3c24xx_eint_domain_data *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (bank->eint_type != EINT_TYPE_WKUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ddata->bank = bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ddata->eint_data = eint_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ddata->eint0_3_parent_only = eint0_3_parent_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ops = (bank->eint_offset == 0) ? &s3c24xx_gpf_irq_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) : &s3c24xx_gpg_irq_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) bank->irq_domain = irq_domain_add_linear(bank->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) bank->nr_pins, ops, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!bank->irq_domain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dev_err(dev, "wkup irq domain add failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) irq = bank->eint_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mask = bank->eint_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (pin = 0; mask; ++pin, mask >>= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (irq >= NUM_EINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (!(mask & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) eint_data->domains[irq] = bank->irq_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ++irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const struct samsung_pin_bank_data s3c2412_pin_banks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PIN_BANK_A(23, 0x000, "gpa"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PIN_BANK_2BIT(11, 0x010, "gpb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PIN_BANK_2BIT(16, 0x020, "gpc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PIN_BANK_2BIT(16, 0x030, "gpd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PIN_BANK_2BIT(16, 0x040, "gpe"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PIN_BANK_2BIT(11, 0x070, "gph"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PIN_BANK_2BIT(13, 0x080, "gpj"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const struct samsung_pin_ctrl s3c2412_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .pin_banks = s3c2412_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .nr_banks = ARRAY_SIZE(s3c2412_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .eint_wkup_init = s3c24xx_eint_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) const struct samsung_pinctrl_of_match_data s3c2412_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .ctrl = s3c2412_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .num_ctrl = ARRAY_SIZE(s3c2412_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const struct samsung_pin_bank_data s3c2416_pin_banks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PIN_BANK_A(27, 0x000, "gpa"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PIN_BANK_2BIT(11, 0x010, "gpb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PIN_BANK_2BIT(16, 0x020, "gpc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PIN_BANK_2BIT(16, 0x030, "gpd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PIN_BANK_2BIT(16, 0x040, "gpe"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PIN_BANK_2BIT_EINTW(8, 0x060, "gpg", 8, 0xff00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PIN_BANK_2BIT(15, 0x070, "gph"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PIN_BANK_2BIT(16, 0x0e0, "gpk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PIN_BANK_2BIT(14, 0x0f0, "gpl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PIN_BANK_2BIT(2, 0x100, "gpm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct samsung_pin_ctrl s3c2416_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .pin_banks = s3c2416_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .nr_banks = ARRAY_SIZE(s3c2416_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .eint_wkup_init = s3c24xx_eint_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const struct samsung_pinctrl_of_match_data s3c2416_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .ctrl = s3c2416_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .num_ctrl = ARRAY_SIZE(s3c2416_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const struct samsung_pin_bank_data s3c2440_pin_banks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PIN_BANK_A(25, 0x000, "gpa"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PIN_BANK_2BIT(11, 0x010, "gpb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PIN_BANK_2BIT(16, 0x020, "gpc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PIN_BANK_2BIT(16, 0x030, "gpd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PIN_BANK_2BIT(16, 0x040, "gpe"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PIN_BANK_2BIT(11, 0x070, "gph"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PIN_BANK_2BIT(13, 0x0d0, "gpj"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const struct samsung_pin_ctrl s3c2440_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .pin_banks = s3c2440_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .nr_banks = ARRAY_SIZE(s3c2440_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .eint_wkup_init = s3c24xx_eint_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) const struct samsung_pinctrl_of_match_data s3c2440_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .ctrl = s3c2440_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .num_ctrl = ARRAY_SIZE(s3c2440_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct samsung_pin_bank_data s3c2450_pin_banks[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PIN_BANK_A(28, 0x000, "gpa"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PIN_BANK_2BIT(11, 0x010, "gpb"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PIN_BANK_2BIT(16, 0x020, "gpc"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PIN_BANK_2BIT(16, 0x030, "gpd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PIN_BANK_2BIT(16, 0x040, "gpe"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PIN_BANK_2BIT_EINTW(8, 0x050, "gpf", 0, 0xff),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PIN_BANK_2BIT_EINTW(16, 0x060, "gpg", 8, 0xffff00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PIN_BANK_2BIT(15, 0x070, "gph"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PIN_BANK_2BIT(16, 0x0d0, "gpj"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PIN_BANK_2BIT(16, 0x0e0, "gpk"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PIN_BANK_2BIT(15, 0x0f0, "gpl"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PIN_BANK_2BIT(2, 0x100, "gpm"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const struct samsung_pin_ctrl s3c2450_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .pin_banks = s3c2450_pin_banks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .nr_banks = ARRAY_SIZE(s3c2450_pin_banks),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .eint_wkup_init = s3c24xx_eint_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) const struct samsung_pinctrl_of_match_data s3c2450_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ctrl = s3c2450_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .num_ctrl = ARRAY_SIZE(s3c2450_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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