^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Exynos specific definitions for Samsung pinctrl and gpiolib driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2012 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * http://www.linaro.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This file contains the Exynos specific definitions for the Samsung
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * pinctrl/gpiolib interface drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef __PINCTRL_SAMSUNG_EXYNOS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define __PINCTRL_SAMSUNG_EXYNOS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* External GPIO and wakeup interrupt related definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EXYNOS_GPIO_ECON_OFFSET 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EXYNOS_GPIO_EFLTCON_OFFSET 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EXYNOS_GPIO_EMASK_OFFSET 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EXYNOS_GPIO_EPEND_OFFSET 0xA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EXYNOS_WKUP_ECON_OFFSET 0xE00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXYNOS_WKUP_EMASK_OFFSET 0xF00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EXYNOS_WKUP_EPEND_OFFSET 0xF40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EXYNOS7_WKUP_ECON_OFFSET 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EXYNOS7_WKUP_EMASK_OFFSET 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EXYNOS7_WKUP_EPEND_OFFSET 0xA00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EXYNOS_SVC_OFFSET 0xB08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* helpers to access interrupt service register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EXYNOS_SVC_GROUP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EXYNOS_SVC_GROUP_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EXYNOS_SVC_NUM_MASK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EXYNOS_SVC_GROUP(x) ((x >> EXYNOS_SVC_GROUP_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) EXYNOS_SVC_GROUP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Exynos specific external interrupt trigger types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EXYNOS_EINT_LEVEL_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EXYNOS_EINT_LEVEL_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EXYNOS_EINT_EDGE_FALLING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EXYNOS_EINT_EDGE_RISING 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EXYNOS_EINT_EDGE_BOTH 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EXYNOS_EINT_CON_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EXYNOS_EINT_CON_LEN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EXYNOS_EINT_MAX_PER_BANK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EXYNOS_EINT_NR_WKUP_EINT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .type = &bank_type_off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .eint_type = EINT_TYPE_NONE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EXYNOS_PIN_BANK_EINTG(pins, reg, id, offs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .type = &bank_type_off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .eint_type = EINT_TYPE_GPIO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .eint_offset = offs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EXYNOS_PIN_BANK_EINTW(pins, reg, id, offs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .type = &bank_type_alive, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .eint_type = EINT_TYPE_WKUP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .eint_offset = offs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EXYNOS5433_PIN_BANK_EINTG(pins, reg, id, offs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .type = &exynos5433_bank_type_off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .eint_type = EINT_TYPE_GPIO, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .eint_offset = offs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EXYNOS5433_PIN_BANK_EINTW(pins, reg, id, offs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .type = &exynos5433_bank_type_alive, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .eint_type = EINT_TYPE_WKUP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .eint_offset = offs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .name = id \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EXYNOS5433_PIN_BANK_EINTW_EXT(pins, reg, id, offs, pctl_idx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .type = &exynos5433_bank_type_off, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .pctl_offset = reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .nr_pins = pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .eint_type = EINT_TYPE_WKUP, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .eint_offset = offs, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .name = id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pctl_res_idx = pctl_idx, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * struct exynos_weint_data: irq specific data for all the wakeup interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * generated by the external wakeup interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @irq: interrupt number within the domain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @bank: bank responsible for this interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct exynos_weint_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct samsung_pin_bank *bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * struct exynos_muxed_weint_data: irq specific data for muxed wakeup interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * generated by the external wakeup interrupt controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @nr_banks: count of banks being part of the mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @banks: array of banks being part of the mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct exynos_muxed_weint_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int nr_banks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct samsung_pin_bank *banks[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct samsung_retention_ctrl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct samsung_retention_data *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* __PINCTRL_SAMSUNG_EXYNOS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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