^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // with eint support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (c) 2012 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // http://www.linaro.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // This file contains the Samsung Exynos specific information required by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // external gpio and wakeup interrupt support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pinctrl-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "pinctrl-exynos.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct samsung_pin_bank_type bank_type_off = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .fld_width = { 4, 1, 2, 2, 2, 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const struct samsung_pin_bank_type bank_type_alive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .fld_width = { 4, 1, 2, 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Exynos5433 has the 4bit widths for PINCFG_TYPE_DRV bitfields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const struct samsung_pin_bank_type exynos5433_bank_type_off = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .fld_width = { 4, 1, 2, 4, 2, 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct samsung_pin_bank_type exynos5433_bank_type_alive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .fld_width = { 4, 1, 2, 4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Pad retention control code for accessing PMU regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static atomic_t exynos_shared_retention_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* pin banks of exynos5433 pin-controller - ALIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const struct samsung_pin_bank_data exynos5433_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) EXYNOS5433_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) EXYNOS5433_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) EXYNOS5433_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EXYNOS5433_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x020, "gpf1", 0x1004, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x040, "gpf2", 0x1008, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) EXYNOS5433_PIN_BANK_EINTW_EXT(4, 0x060, "gpf3", 0x100c, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x080, "gpf4", 0x1010, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) EXYNOS5433_PIN_BANK_EINTW_EXT(8, 0x0a0, "gpf5", 0x1014, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* pin banks of exynos5433 pin-controller - AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const struct samsung_pin_bank_data exynos5433_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) EXYNOS5433_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) EXYNOS5433_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* pin banks of exynos5433 pin-controller - CPIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const struct samsung_pin_bank_data exynos5433_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EXYNOS5433_PIN_BANK_EINTG(2, 0x000, "gpv6", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* pin banks of exynos5433 pin-controller - eSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const struct samsung_pin_bank_data exynos5433_pin_banks3[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj2", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* pin banks of exynos5433 pin-controller - FINGER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static const struct samsung_pin_bank_data exynos5433_pin_banks4[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) EXYNOS5433_PIN_BANK_EINTG(4, 0x000, "gpd5", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* pin banks of exynos5433 pin-controller - FSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct samsung_pin_bank_data exynos5433_pin_banks5[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gph1", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EXYNOS5433_PIN_BANK_EINTG(7, 0x020, "gpr4", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EXYNOS5433_PIN_BANK_EINTG(5, 0x040, "gpr0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) EXYNOS5433_PIN_BANK_EINTG(8, 0x060, "gpr1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) EXYNOS5433_PIN_BANK_EINTG(2, 0x080, "gpr2", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpr3", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* pin banks of exynos5433 pin-controller - IMEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct samsung_pin_bank_data exynos5433_pin_banks6[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EXYNOS5433_PIN_BANK_EINTG(8, 0x000, "gpf0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* pin banks of exynos5433 pin-controller - NFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static const struct samsung_pin_bank_data exynos5433_pin_banks7[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* pin banks of exynos5433 pin-controller - PERIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct samsung_pin_bank_data exynos5433_pin_banks8[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EXYNOS5433_PIN_BANK_EINTG(6, 0x000, "gpv7", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EXYNOS5433_PIN_BANK_EINTG(5, 0x020, "gpb0", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXYNOS5433_PIN_BANK_EINTG(8, 0x040, "gpc0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXYNOS5433_PIN_BANK_EINTG(2, 0x060, "gpc1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EXYNOS5433_PIN_BANK_EINTG(6, 0x080, "gpc2", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EXYNOS5433_PIN_BANK_EINTG(8, 0x0a0, "gpc3", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXYNOS5433_PIN_BANK_EINTG(2, 0x0c0, "gpg0", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXYNOS5433_PIN_BANK_EINTG(4, 0x0e0, "gpd0", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXYNOS5433_PIN_BANK_EINTG(6, 0x100, "gpd1", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EXYNOS5433_PIN_BANK_EINTG(8, 0x120, "gpd2", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXYNOS5433_PIN_BANK_EINTG(5, 0x140, "gpd4", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EXYNOS5433_PIN_BANK_EINTG(2, 0x160, "gpd8", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXYNOS5433_PIN_BANK_EINTG(7, 0x180, "gpd6", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXYNOS5433_PIN_BANK_EINTG(3, 0x1a0, "gpd7", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EXYNOS5433_PIN_BANK_EINTG(5, 0x1c0, "gpg1", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXYNOS5433_PIN_BANK_EINTG(2, 0x1e0, "gpg2", 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) EXYNOS5433_PIN_BANK_EINTG(8, 0x200, "gpg3", 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* pin banks of exynos5433 pin-controller - TOUCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct samsung_pin_bank_data exynos5433_pin_banks9[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) EXYNOS5433_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* PMU pin retention groups registers for Exynos5433 (without audio & fsys) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const u32 exynos5433_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) EXYNOS5433_PAD_RETENTION_TOP_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) EXYNOS5433_PAD_RETENTION_UART_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EXYNOS5433_PAD_RETENTION_EBIA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) EXYNOS5433_PAD_RETENTION_EBIB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) EXYNOS5433_PAD_RETENTION_SPI_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) EXYNOS5433_PAD_RETENTION_MIF_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) EXYNOS5433_PAD_RETENTION_USBXTI_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) EXYNOS5433_PAD_RETENTION_BOOTLDO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXYNOS5433_PAD_RETENTION_UFS_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) EXYNOS5433_PAD_RETENTION_FSYSGENIO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct samsung_retention_data exynos5433_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .regs = exynos5433_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .nr_regs = ARRAY_SIZE(exynos5433_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .refcnt = &exynos_shared_retention_refcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* PMU retention control for audio pins can be tied to audio pin bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const u32 exynos5433_audio_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) EXYNOS5433_PAD_RETENTION_AUD_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct samsung_retention_data exynos5433_audio_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .regs = exynos5433_audio_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .nr_regs = ARRAY_SIZE(exynos5433_audio_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* PMU retention control for mmc pins can be tied to fsys pin bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const u32 exynos5433_fsys_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EXYNOS5433_PAD_RETENTION_MMC0_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) EXYNOS5433_PAD_RETENTION_MMC1_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) EXYNOS5433_PAD_RETENTION_MMC2_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct samsung_retention_data exynos5433_fsys_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .regs = exynos5433_fsys_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .nr_regs = ARRAY_SIZE(exynos5433_fsys_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Samsung pinctrl driver data for Exynos5433 SoC. Exynos5433 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * ten gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct samsung_pin_ctrl exynos5433_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .pin_banks = exynos5433_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .nr_ext_resources = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .pin_banks = exynos5433_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .retention_data = &exynos5433_audio_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .pin_banks = exynos5433_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* pin-controller instance 3 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .pin_banks = exynos5433_pin_banks3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* pin-controller instance 4 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .pin_banks = exynos5433_pin_banks4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* pin-controller instance 5 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .pin_banks = exynos5433_pin_banks5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .retention_data = &exynos5433_fsys_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* pin-controller instance 6 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .pin_banks = exynos5433_pin_banks6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* pin-controller instance 7 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .pin_banks = exynos5433_pin_banks7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* pin-controller instance 8 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .pin_banks = exynos5433_pin_banks8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* pin-controller instance 9 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .pin_banks = exynos5433_pin_banks9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .nr_banks = ARRAY_SIZE(exynos5433_pin_banks9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .retention_data = &exynos5433_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) const struct samsung_pinctrl_of_match_data exynos5433_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .ctrl = exynos5433_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .num_ctrl = ARRAY_SIZE(exynos5433_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* pin banks of exynos7 pin-controller - ALIVE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct samsung_pin_bank_data exynos7_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXYNOS_PIN_BANK_EINTW(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EXYNOS_PIN_BANK_EINTW(8, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) EXYNOS_PIN_BANK_EINTW(8, 0x040, "gpa2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) EXYNOS_PIN_BANK_EINTW(8, 0x060, "gpa3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* pin banks of exynos7 pin-controller - BUS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct samsung_pin_bank_data exynos7_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpb0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc0", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) EXYNOS_PIN_BANK_EINTG(2, 0x040, "gpc1", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EXYNOS_PIN_BANK_EINTG(6, 0x060, "gpc2", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpc3", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpd2", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpd4", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) EXYNOS_PIN_BANK_EINTG(4, 0x120, "gpd5", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EXYNOS_PIN_BANK_EINTG(6, 0x140, "gpd6", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EXYNOS_PIN_BANK_EINTG(3, 0x160, "gpd7", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EXYNOS_PIN_BANK_EINTG(2, 0x180, "gpd8", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) EXYNOS_PIN_BANK_EINTG(2, 0x1a0, "gpg0", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpg3", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* pin banks of exynos7 pin-controller - NFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const struct samsung_pin_bank_data exynos7_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* pin banks of exynos7 pin-controller - TOUCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct samsung_pin_bank_data exynos7_pin_banks3[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) EXYNOS_PIN_BANK_EINTG(3, 0x000, "gpj1", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* pin banks of exynos7 pin-controller - FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct samsung_pin_bank_data exynos7_pin_banks4[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpg4", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* pin banks of exynos7 pin-controller - ESE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const struct samsung_pin_bank_data exynos7_pin_banks5[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpv7", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* pin banks of exynos7 pin-controller - FSYS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct samsung_pin_bank_data exynos7_pin_banks6[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpr4", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* pin banks of exynos7 pin-controller - FSYS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct samsung_pin_bank_data exynos7_pin_banks7[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpr0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpr1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXYNOS_PIN_BANK_EINTG(5, 0x040, "gpr2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpr3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* pin banks of exynos7 pin-controller - BUS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct samsung_pin_bank_data exynos7_pin_banks8[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpf0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpf1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpf3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EXYNOS_PIN_BANK_EINTG(8, 0x0a0, "gpf4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpf5", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) EXYNOS_PIN_BANK_EINTG(5, 0x0e0, "gpg1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpg2", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) EXYNOS_PIN_BANK_EINTG(6, 0x120, "gph1", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) EXYNOS_PIN_BANK_EINTG(3, 0x140, "gpv6", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const struct samsung_pin_bank_data exynos7_pin_banks9[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct samsung_pin_ctrl exynos7_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* pin-controller instance 0 Alive data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .pin_banks = exynos7_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .nr_banks = ARRAY_SIZE(exynos7_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* pin-controller instance 1 BUS0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .pin_banks = exynos7_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .nr_banks = ARRAY_SIZE(exynos7_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* pin-controller instance 2 NFC data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .pin_banks = exynos7_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .nr_banks = ARRAY_SIZE(exynos7_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* pin-controller instance 3 TOUCH data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .pin_banks = exynos7_pin_banks3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .nr_banks = ARRAY_SIZE(exynos7_pin_banks3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* pin-controller instance 4 FF data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .pin_banks = exynos7_pin_banks4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .nr_banks = ARRAY_SIZE(exynos7_pin_banks4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* pin-controller instance 5 ESE data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .pin_banks = exynos7_pin_banks5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .nr_banks = ARRAY_SIZE(exynos7_pin_banks5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* pin-controller instance 6 FSYS0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .pin_banks = exynos7_pin_banks6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .nr_banks = ARRAY_SIZE(exynos7_pin_banks6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* pin-controller instance 7 FSYS1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .pin_banks = exynos7_pin_banks7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .nr_banks = ARRAY_SIZE(exynos7_pin_banks7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* pin-controller instance 8 BUS1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .pin_banks = exynos7_pin_banks8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .nr_banks = ARRAY_SIZE(exynos7_pin_banks8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* pin-controller instance 9 AUD data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .pin_banks = exynos7_pin_banks9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .nr_banks = ARRAY_SIZE(exynos7_pin_banks9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) const struct samsung_pinctrl_of_match_data exynos7_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .ctrl = exynos7_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .num_ctrl = ARRAY_SIZE(exynos7_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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