^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright (c) 2012 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright (c) 2012 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // http://www.linaro.org
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Author: Thomas Abraham <thomas.ab@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) // This file contains the Samsung Exynos specific information required by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // external gpio and wakeup interrupt support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/soc/samsung/exynos-regs-pmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "pinctrl-samsung.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinctrl-exynos.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct samsung_pin_bank_type bank_type_off = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .fld_width = { 4, 1, 2, 2, 2, 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static const struct samsung_pin_bank_type bank_type_alive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .fld_width = { 4, 1, 2, 2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Retention control for S5PV210 are located at the end of clock controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S5P_OTHERS 0xE000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define S5P_OTHERS_RET_IO (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S5P_OTHERS_RET_CF (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S5P_OTHERS_RET_MMC (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S5P_OTHERS_RET_UART (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) tmp = __raw_readl(clk_base + S5P_OTHERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) S5P_OTHERS_RET_UART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __raw_writel(tmp, clk_base + S5P_OTHERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static struct samsung_retention_ctrl *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) const struct samsung_retention_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct samsung_retention_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) void __iomem *clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pr_err("%s: failed to find clock controller DT node\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) clk_base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (!clk_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pr_err("%s: failed to map clock registers\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ctrl->priv = (void __force *)clk_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ctrl->disable = s5pv210_retention_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct samsung_retention_data s5pv210_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .init = s5pv210_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* pin banks of s5pv210 pin-controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .pin_banks = s5pv210_pin_bank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .retention_data = &s5pv210_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .ctrl = s5pv210_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Pad retention control code for accessing PMU regmap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static atomic_t exynos_shared_retention_refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* pin banks of exynos3250 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* pin banks of exynos3250 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * them all together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const u32 exynos3250_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) S5P_PAD_RET_MAUDIO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) S5P_PAD_RET_GPIO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) S5P_PAD_RET_UART_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) S5P_PAD_RET_MMCA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) S5P_PAD_RET_MMCB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) S5P_PAD_RET_EBIA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) S5P_PAD_RET_EBIB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) S5P_PAD_RET_MMC2_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) S5P_PAD_RET_SPI_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const struct samsung_retention_data exynos3250_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .regs = exynos3250_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .refcnt = &exynos_shared_retention_refcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * two gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .pin_banks = exynos3250_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .retention_data = &exynos3250_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .pin_banks = exynos3250_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .retention_data = &exynos3250_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .ctrl = exynos3250_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* pin banks of exynos4210 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* pin banks of exynos4210 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* pin banks of exynos4210 pin-controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* PMU pad retention groups registers for Exynos4 (without audio) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const u32 exynos4_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) S5P_PAD_RET_GPIO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) S5P_PAD_RET_UART_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) S5P_PAD_RET_MMCA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) S5P_PAD_RET_MMCB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) S5P_PAD_RET_EBIA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) S5P_PAD_RET_EBIB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const struct samsung_retention_data exynos4_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .regs = exynos4_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .refcnt = &exynos_shared_retention_refcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* PMU retention control for audio pins can be tied to audio pin bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const u32 exynos4_audio_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) S5P_PAD_RET_MAUDIO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .regs = exynos4_audio_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * three gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .pin_banks = exynos4210_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .retention_data = &exynos4_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .pin_banks = exynos4210_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .retention_data = &exynos4_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .pin_banks = exynos4210_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .retention_data = &exynos4_audio_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .ctrl = exynos4210_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* pin banks of exynos4x12 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* pin banks of exynos4x12 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* pin banks of exynos4x12 pin-controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* pin banks of exynos4x12 pin-controller 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * four gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .pin_banks = exynos4x12_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .retention_data = &exynos4_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .pin_banks = exynos4x12_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .retention_data = &exynos4_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .pin_banks = exynos4x12_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .retention_data = &exynos4_audio_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* pin-controller instance 3 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .pin_banks = exynos4x12_pin_banks3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .ctrl = exynos4x12_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* pin banks of exynos5250 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* pin banks of exynos5250 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* pin banks of exynos5250 pin-controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* pin banks of exynos5250 pin-controller 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * four gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .pin_banks = exynos5250_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .retention_data = &exynos4_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .pin_banks = exynos5250_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .retention_data = &exynos4_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .pin_banks = exynos5250_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* pin-controller instance 3 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .pin_banks = exynos5250_pin_banks3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .retention_data = &exynos4_audio_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .ctrl = exynos5250_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* pin banks of exynos5260 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* pin banks of exynos5260 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* pin banks of exynos5260 pin-controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * three gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .pin_banks = exynos5260_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .pin_banks = exynos5260_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .pin_banks = exynos5260_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .ctrl = exynos5260_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* pin banks of exynos5410 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* pin banks of exynos5410 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* pin banks of exynos5410 pin-controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* pin banks of exynos5410 pin-controller 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * four gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .pin_banks = exynos5410_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .pin_banks = exynos5410_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .pin_banks = exynos5410_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* pin-controller instance 3 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .pin_banks = exynos5410_pin_banks3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .ctrl = exynos5410_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* pin banks of exynos5420 pin-controller 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* pin banks of exynos5420 pin-controller 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* pin banks of exynos5420 pin-controller 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* pin banks of exynos5420 pin-controller 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* pin banks of exynos5420 pin-controller 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Must start with EINTG banks, ordered by EINT group number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* PMU pad retention groups registers for Exynos5420 (without audio) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const u32 exynos5420_retention_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) EXYNOS_PAD_RET_DRAM_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) EXYNOS_PAD_RET_JTAG_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) EXYNOS5420_PAD_RET_GPIO_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) EXYNOS5420_PAD_RET_UART_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) EXYNOS5420_PAD_RET_MMCA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) EXYNOS5420_PAD_RET_MMCB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) EXYNOS5420_PAD_RET_MMCC_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) EXYNOS5420_PAD_RET_HSI_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) EXYNOS_PAD_RET_EBIA_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) EXYNOS_PAD_RET_EBIB_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) EXYNOS5420_PAD_RET_SPI_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const struct samsung_retention_data exynos5420_retention_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .regs = exynos5420_retention_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .value = EXYNOS_WAKEUP_FROM_LOWPWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .refcnt = &exynos_shared_retention_refcnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .init = exynos_retention_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * four gpio/pin-mux/pinconfig controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* pin-controller instance 0 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .pin_banks = exynos5420_pin_banks0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .eint_wkup_init = exynos_eint_wkup_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .retention_data = &exynos5420_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* pin-controller instance 1 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .pin_banks = exynos5420_pin_banks1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .retention_data = &exynos5420_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* pin-controller instance 2 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .pin_banks = exynos5420_pin_banks2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .retention_data = &exynos5420_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* pin-controller instance 3 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .pin_banks = exynos5420_pin_banks3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .retention_data = &exynos5420_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* pin-controller instance 4 data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .pin_banks = exynos5420_pin_banks4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .eint_gpio_init = exynos_eint_gpio_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .suspend = exynos_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .resume = exynos_pinctrl_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .retention_data = &exynos4_audio_retention_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) .ctrl = exynos5420_pin_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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