^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SuperH Pin Function Controller pinmux support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define DRV_NAME "sh-pfc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) struct sh_pfc_pin_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) unsigned int mux_mark;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) bool mux_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) bool gpio_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct sh_pfc_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct pinctrl_desc pctl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct sh_pfc *pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct sh_pfc_pin_config *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) const char *func_prop_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const char *groups_prop_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) const char *pins_prop_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return pmx->pfc->info->nr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return pmx->pfc->info->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) const unsigned **pins, unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *pins = pmx->pfc->info->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *num_pins = pmx->pfc->info->groups[selector].nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) seq_puts(s, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int sh_pfc_map_add_config(struct pinctrl_map *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) const char *group_or_pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum pinctrl_map_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long *cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) cfgs = kmemdup(configs, num_configs * sizeof(*cfgs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (cfgs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) map->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) map->data.configs.group_or_pin = group_or_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) map->data.configs.configs = cfgs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) map->data.configs.num_configs = num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int sh_pfc_dt_subnode_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int *num_maps, unsigned int *index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device *dev = pmx->pfc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct pinctrl_map *maps = *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int nmaps = *num_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int idx = *index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int num_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) const char *function = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long *configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const char *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const char *pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Support both the old Renesas-specific properties and the new standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * properties. Mixing old and new properties isn't allowed, neither
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * inside a subnode nor across subnodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!pmx->func_prop_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (of_find_property(np, "groups", NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) of_find_property(np, "pins", NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pmx->func_prop_name = "function";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pmx->groups_prop_name = "groups";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pmx->pins_prop_name = "pins";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) pmx->func_prop_name = "renesas,function";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) pmx->groups_prop_name = "renesas,groups";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pmx->pins_prop_name = "renesas,pins";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Parse the function and configuration properties. At least a function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * or one configuration must be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) ret = of_property_read_string(np, pmx->func_prop_name, &function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (ret < 0 && ret != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_err(dev, "Invalid function in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (!function && num_configs == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) "DT node must contain at least a function or config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Count the number of pins and groups and reallocate mappings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = of_property_count_strings(np, pmx->pins_prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) if (ret == -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) num_pins = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dev_err(dev, "Invalid pins list in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) num_pins = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ret = of_property_count_strings(np, pmx->groups_prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ret == -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) num_groups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) } else if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dev_err(dev, "Invalid pin groups list in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) num_groups = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!num_pins && !num_groups) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dev_err(dev, "No pin or group provided in DT node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) nmaps += num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) nmaps += num_pins + num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) maps = krealloc(maps, sizeof(*maps) * nmaps, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (maps == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) *map = maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *num_maps = nmaps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Iterate over pins and groups and create the mappings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) of_property_for_each_string(np, pmx->groups_prop_name, prop, group) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (function) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) maps[idx].type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) maps[idx].data.mux.group = group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) maps[idx].data.mux.function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = sh_pfc_map_add_config(&maps[idx], group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PIN_MAP_TYPE_CONFIGS_GROUP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (!configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) of_property_for_each_string(np, pmx->pins_prop_name, prop, pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ret = sh_pfc_map_add_config(&maps[idx], pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PIN_MAP_TYPE_CONFIGS_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *index = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void sh_pfc_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct pinctrl_map *map, unsigned num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (map == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) for (i = 0; i < num_maps; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) kfree(map[i].data.configs.configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int sh_pfc_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct pinctrl_map **map, unsigned *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct device *dev = pmx->pfc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ret = sh_pfc_dt_subnode_to_map(pctldev, child, map, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) &index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* If no mapping has been found in child nodes try the config node. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (*num_maps == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ret = sh_pfc_dt_subnode_to_map(pctldev, np, map, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) &index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (*num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_err(dev, "no mapping found in node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) sh_pfc_dt_free_map(pctldev, *map, *num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif /* CONFIG_OF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .get_groups_count = sh_pfc_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .get_group_name = sh_pfc_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .get_group_pins = sh_pfc_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .pin_dbg_show = sh_pfc_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .dt_node_to_map = sh_pfc_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .dt_free_map = sh_pfc_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return pmx->pfc->info->nr_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return pmx->pfc->info->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *groups = pmx->pfc->info->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) *num_groups = pmx->pfc->info->functions[selector].nr_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static int sh_pfc_func_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct sh_pfc *pfc = pmx->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dev_dbg(pctldev->dev, "Configuring pin group %s\n", grp->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < grp->nr_pins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * This driver cannot manage both gpio and mux when the gpio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * pin is already enabled. So, this function fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (cfg->gpio_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* All group pins are configured, mark the pins as mux_set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < grp->nr_pins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) cfg->mux_set = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cfg->mux_mark = grp->mux[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct sh_pfc *pfc = pmx->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int idx = sh_pfc_get_pin_index(pfc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (!pfc->gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* If GPIOs are handled externally the pin mux type need to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * set to GPIO here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cfg->gpio_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct sh_pfc *pfc = pmx->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int idx = sh_pfc_get_pin_index(pfc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) cfg->gpio_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* If mux is already set, this configures it here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (cfg->mux_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) sh_pfc_config_mux(pfc, cfg->mux_mark, PINMUX_TYPE_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned offset, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct sh_pfc *pfc = pmx->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int idx = sh_pfc_get_pin_index(pfc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Check if the requested direction is supported by the pin. Not all SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * provide pin config data, so perform the check conditionally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (pin->configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!(pin->configs & dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static const struct pinmux_ops sh_pfc_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .get_functions_count = sh_pfc_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .get_function_name = sh_pfc_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .get_function_groups = sh_pfc_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .set_mux = sh_pfc_func_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .gpio_request_enable = sh_pfc_gpio_request_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .gpio_disable_free = sh_pfc_gpio_disable_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .gpio_set_direction = sh_pfc_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static u32 sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) unsigned int pin, unsigned int *offset, unsigned int *size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) const struct pinmux_drive_reg_field *field;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) const struct pinmux_drive_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) field = ®->fields[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (field->size && field->pin == pin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *offset = field->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *size = field->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return reg->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int sh_pfc_pinconf_get_drive_strength(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = sh_pfc_read(pfc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) val = (val >> offset) & GENMASK(size - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Convert the value to mA based on a full drive strength value of 24mA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * We can make the full value configurable later if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return (val + 1) * (size == 2 ? 6 : 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int pin, u16 strength)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) unsigned int step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) step = size == 2 ? 6 : 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (strength < step || strength > 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Convert the value from mA based on a full drive strength value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * 24mA. We can make the full value configurable later if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) strength = strength / step - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = sh_pfc_read(pfc, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val &= ~GENMASK(offset + size - 1, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) val |= strength << offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) sh_pfc_write(pfc, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Check whether the requested parameter is supported for a pin. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) enum pin_config_param param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) int idx = sh_pfc_get_pin_index(pfc, _pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return pin->configs & SH_PFC_PIN_CFG_PULL_UP_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case PIN_CONFIG_POWER_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct sh_pfc *pfc = pmx->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!sh_pfc_pinconf_validate(pfc, _pin, param))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) case PIN_CONFIG_BIAS_PULL_DOWN: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) if (!pfc->info->ops || !pfc->info->ops->get_bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) bias = pfc->info->ops->get_bias(pfc, _pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (bias != param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) case PIN_CONFIG_DRIVE_STRENGTH: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = sh_pfc_pinconf_get_drive_strength(pfc, _pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) arg = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case PIN_CONFIG_POWER_SOURCE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 pocctrl, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (WARN(bit < 0, "invalid pin %#x", _pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val = sh_pfc_read(pfc, pocctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) arg = (val & BIT(bit)) ? 3300 : 1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sh_pfc *pfc = pmx->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!sh_pfc_pinconf_validate(pfc, _pin, param))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (!pfc->info->ops || !pfc->info->ops->set_bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) pfc->info->ops->set_bias(pfc, _pin, param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case PIN_CONFIG_DRIVE_STRENGTH: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned int arg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case PIN_CONFIG_POWER_SOURCE: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int mV = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u32 pocctrl, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &pocctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (WARN(bit < 0, "invalid pin %#x", _pin))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (mV != 1800 && mV != 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val = sh_pfc_read(pfc, pocctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (mV == 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) sh_pfc_write(pfc, pocctrl, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned int num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) pins = pmx->pfc->info->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) num_pins = pmx->pfc->info->groups[group].nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) for (i = 0; i < num_pins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = sh_pfc_pinconf_set(pctldev, pins[i], configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct pinconf_ops sh_pfc_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .pin_config_get = sh_pfc_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .pin_config_set = sh_pfc_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .pin_config_group_set = sh_pfc_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .pin_config_config_dbg_show = pinconf_generic_dump_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* PFC ranges -> pinctrl pin descs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Allocate and initialize the pins and configs arrays. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) pmx->pins = devm_kcalloc(pfc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) pfc->info->nr_pins, sizeof(*pmx->pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (unlikely(!pmx->pins))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) pmx->configs = devm_kcalloc(pfc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) pfc->info->nr_pins, sizeof(*pmx->configs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (unlikely(!pmx->configs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) for (i = 0; i < pfc->info->nr_pins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) const struct sh_pfc_pin *info = &pfc->info->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct pinctrl_pin_desc *pin = &pmx->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* If the pin number is equal to -1 all pins are considered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) pin->number = info->pin != (u16)-1 ? info->pin : i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pin->name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct sh_pfc_pinctrl *pmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (unlikely(!pmx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pmx->pfc = pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = sh_pfc_map_pins(pfc, pmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pmx->pctl_desc.name = DRV_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) pmx->pctl_desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) pmx->pctl_desc.pins = pmx->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pmx->pctl_desc.npins = pfc->info->nr_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = devm_pinctrl_register_and_init(pfc->dev, &pmx->pctl_desc, pmx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) &pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(pfc->dev, "could not register: %i\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return pinctrl_enable(pmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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