^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2014-2018 Renesas Electronics Europe Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Phil Edworthy <phil.edworthy@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on a driver originally written by Michel Pollet at Renesas.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <dt-bindings/pinctrl/rzn1-pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Field positions and masks in the pinmux registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RZN1_L1_PIN_DRIVE_STRENGTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RZN1_L1_PIN_DRIVE_STRENGTH_4MA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RZN1_L1_PIN_DRIVE_STRENGTH_6MA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define RZN1_L1_PIN_DRIVE_STRENGTH_8MA 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RZN1_L1_PIN_DRIVE_STRENGTH_12MA 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define RZN1_L1_PIN_PULL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RZN1_L1_PIN_PULL_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RZN1_L1_PIN_PULL_UP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RZN1_L1_PIN_PULL_DOWN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RZN1_L1_FUNCTION 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RZN1_L1_FUNC_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RZN1_L1_FUNCTION_L2 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * The hardware manual describes two levels of multiplexing, but it's more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * logical to think of the hardware as three levels, with level 3 consisting of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * the multiplexing for Ethernet MDIO signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Level 1 functions go from 0 to 9, with level 1 function '15' (0xf) specifying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * that level 2 functions are used instead. Level 2 has a lot more options,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * going from 0 to 61. Level 3 allows selection of MDIO functions which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * floating, or one of seven internal peripherals. Unfortunately, there are two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * level 2 functions that can select MDIO, and two MDIO channels so we have four
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * sets of level 3 functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * For this driver, we've compounded the numbers together, so:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 0 to 9 is level 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 10 to 71 is 10 + level 2 number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * 72 to 79 is 72 + MDIO0 source for level 2 MDIO function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * 80 to 87 is 80 + MDIO0 source for level 2 MDIO_E1 function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 88 to 95 is 88 + MDIO1 source for level 2 MDIO function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 96 to 103 is 96 + MDIO1 source for level 2 MDIO_E1 function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Function 28 corresponds UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Function 73 corresponds to MDIO0 to GMAC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * There are 170 configurable pins (called PL_GPIO in the datasheet).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Structure detailing the HW registers on the RZ/N1 devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Both the Level 1 mux registers and Level 2 mux registers have the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * structure. The only difference is that Level 2 has additional MDIO registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct rzn1_pinctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 conf[170];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 pad0[86];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 status_protect; /* 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* MDIO mux registers, level2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u32 l2_mdio[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * struct rzn1_pmx_func - describes rzn1 pinmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @name: the name of this specific function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @groups: corresponding pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @num_groups: the number of groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct rzn1_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const char **groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * struct rzn1_pin_group - describes an rzn1 pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @name: the name of this specific pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @func: the name of the function selected by this group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @npins: the number of pins in this group array, i.e. the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * elements in .pins so we can iterate over that array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @pins: array of pins. Needed due to pinctrl_ops.get_group_pins()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @pin_ids: array of pin_ids, i.e. the value used to select the mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct rzn1_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 *pin_ids;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct rzn1_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct rzn1_pinctrl_regs __iomem *lev1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct rzn1_pinctrl_regs __iomem *lev2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 lev1_protect_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 lev2_protect_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int mdio_func[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct rzn1_pin_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct rzn1_pmx_func *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RZN1_PINS_PROP "pinmux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RZN1_PIN(pin) PINCTRL_PIN(pin, "pl_gpio"#pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const struct pinctrl_pin_desc rzn1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) RZN1_PIN(0), RZN1_PIN(1), RZN1_PIN(2), RZN1_PIN(3), RZN1_PIN(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) RZN1_PIN(5), RZN1_PIN(6), RZN1_PIN(7), RZN1_PIN(8), RZN1_PIN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) RZN1_PIN(10), RZN1_PIN(11), RZN1_PIN(12), RZN1_PIN(13), RZN1_PIN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) RZN1_PIN(15), RZN1_PIN(16), RZN1_PIN(17), RZN1_PIN(18), RZN1_PIN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) RZN1_PIN(20), RZN1_PIN(21), RZN1_PIN(22), RZN1_PIN(23), RZN1_PIN(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) RZN1_PIN(25), RZN1_PIN(26), RZN1_PIN(27), RZN1_PIN(28), RZN1_PIN(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) RZN1_PIN(30), RZN1_PIN(31), RZN1_PIN(32), RZN1_PIN(33), RZN1_PIN(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) RZN1_PIN(35), RZN1_PIN(36), RZN1_PIN(37), RZN1_PIN(38), RZN1_PIN(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) RZN1_PIN(40), RZN1_PIN(41), RZN1_PIN(42), RZN1_PIN(43), RZN1_PIN(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) RZN1_PIN(45), RZN1_PIN(46), RZN1_PIN(47), RZN1_PIN(48), RZN1_PIN(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) RZN1_PIN(50), RZN1_PIN(51), RZN1_PIN(52), RZN1_PIN(53), RZN1_PIN(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) RZN1_PIN(55), RZN1_PIN(56), RZN1_PIN(57), RZN1_PIN(58), RZN1_PIN(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) RZN1_PIN(60), RZN1_PIN(61), RZN1_PIN(62), RZN1_PIN(63), RZN1_PIN(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) RZN1_PIN(65), RZN1_PIN(66), RZN1_PIN(67), RZN1_PIN(68), RZN1_PIN(69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) RZN1_PIN(70), RZN1_PIN(71), RZN1_PIN(72), RZN1_PIN(73), RZN1_PIN(74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) RZN1_PIN(75), RZN1_PIN(76), RZN1_PIN(77), RZN1_PIN(78), RZN1_PIN(79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) RZN1_PIN(80), RZN1_PIN(81), RZN1_PIN(82), RZN1_PIN(83), RZN1_PIN(84),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) RZN1_PIN(85), RZN1_PIN(86), RZN1_PIN(87), RZN1_PIN(88), RZN1_PIN(89),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) RZN1_PIN(90), RZN1_PIN(91), RZN1_PIN(92), RZN1_PIN(93), RZN1_PIN(94),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) RZN1_PIN(95), RZN1_PIN(96), RZN1_PIN(97), RZN1_PIN(98), RZN1_PIN(99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) RZN1_PIN(100), RZN1_PIN(101), RZN1_PIN(102), RZN1_PIN(103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) RZN1_PIN(104), RZN1_PIN(105), RZN1_PIN(106), RZN1_PIN(107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) RZN1_PIN(108), RZN1_PIN(109), RZN1_PIN(110), RZN1_PIN(111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) RZN1_PIN(112), RZN1_PIN(113), RZN1_PIN(114), RZN1_PIN(115),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) RZN1_PIN(116), RZN1_PIN(117), RZN1_PIN(118), RZN1_PIN(119),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) RZN1_PIN(120), RZN1_PIN(121), RZN1_PIN(122), RZN1_PIN(123),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) RZN1_PIN(124), RZN1_PIN(125), RZN1_PIN(126), RZN1_PIN(127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) RZN1_PIN(128), RZN1_PIN(129), RZN1_PIN(130), RZN1_PIN(131),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) RZN1_PIN(132), RZN1_PIN(133), RZN1_PIN(134), RZN1_PIN(135),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) RZN1_PIN(136), RZN1_PIN(137), RZN1_PIN(138), RZN1_PIN(139),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) RZN1_PIN(140), RZN1_PIN(141), RZN1_PIN(142), RZN1_PIN(143),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) RZN1_PIN(144), RZN1_PIN(145), RZN1_PIN(146), RZN1_PIN(147),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) RZN1_PIN(148), RZN1_PIN(149), RZN1_PIN(150), RZN1_PIN(151),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) RZN1_PIN(152), RZN1_PIN(153), RZN1_PIN(154), RZN1_PIN(155),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) RZN1_PIN(156), RZN1_PIN(157), RZN1_PIN(158), RZN1_PIN(159),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) RZN1_PIN(160), RZN1_PIN(161), RZN1_PIN(162), RZN1_PIN(163),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) RZN1_PIN(164), RZN1_PIN(165), RZN1_PIN(166), RZN1_PIN(167),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) RZN1_PIN(168), RZN1_PIN(169),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) LOCK_LEVEL1 = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) LOCK_LEVEL2 = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) LOCK_ALL = LOCK_LEVEL1 | LOCK_LEVEL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static void rzn1_hw_set_lock(struct rzn1_pinctrl *ipctl, u8 lock, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * The pinmux configuration is locked by writing the physical address of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * the status_protect register to itself. It is unlocked by writing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * address | 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (lock & LOCK_LEVEL1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 val = ipctl->lev1_protect_phys | !(value & LOCK_LEVEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) writel(val, &ipctl->lev1->status_protect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (lock & LOCK_LEVEL2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 val = ipctl->lev2_protect_phys | !(value & LOCK_LEVEL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(val, &ipctl->lev2->status_protect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static void rzn1_pinctrl_mdio_select(struct rzn1_pinctrl *ipctl, int mdio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (ipctl->mdio_func[mdio] >= 0 && ipctl->mdio_func[mdio] != func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_warn(ipctl->dev, "conflicting setting for mdio%d!\n", mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ipctl->mdio_func[mdio] = func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dev_dbg(ipctl->dev, "setting mdio%d to %u\n", mdio, func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) writel(func, &ipctl->lev2->l2_mdio[mdio]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Using a composite pin description, set the hardware pinmux registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * with the corresponding values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Make sure to unlock write protection and reset it afterward.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * NOTE: There is no protection for potential concurrency, it is assumed these
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * calls are serialized already.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int rzn1_set_hw_pin_func(struct rzn1_pinctrl *ipctl, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 pin_config, u8 use_locks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 l1_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 l2_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 l1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Level 3 MDIO multiplexing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (pin_config >= RZN1_FUNC_MDIO0_HIGHZ &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) pin_config <= RZN1_FUNC_MDIO1_E1_SWITCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) int mdio_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 mdio_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (pin_config <= RZN1_FUNC_MDIO1_HIGHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mdio_channel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mdio_channel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Get MDIO func, and convert the func to the level 2 number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (pin_config <= RZN1_FUNC_MDIO0_SWITCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mdio_func = pin_config - RZN1_FUNC_MDIO0_HIGHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pin_config = RZN1_FUNC_ETH_MDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) } else if (pin_config <= RZN1_FUNC_MDIO0_E1_SWITCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mdio_func = pin_config - RZN1_FUNC_MDIO0_E1_HIGHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pin_config = RZN1_FUNC_ETH_MDIO_E1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else if (pin_config <= RZN1_FUNC_MDIO1_SWITCH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) mdio_func = pin_config - RZN1_FUNC_MDIO1_HIGHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pin_config = RZN1_FUNC_ETH_MDIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mdio_func = pin_config - RZN1_FUNC_MDIO1_E1_HIGHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) pin_config = RZN1_FUNC_ETH_MDIO_E1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) rzn1_pinctrl_mdio_select(ipctl, mdio_channel, mdio_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Note here, we do not allow anything past the MDIO Mux values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (pin >= ARRAY_SIZE(ipctl->lev1->conf) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pin_config >= RZN1_FUNC_MDIO0_HIGHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) l1 = readl(&ipctl->lev1->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) l1_cache = l1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) l2 = readl(&ipctl->lev2->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) l2_cache = l2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_dbg(ipctl->dev, "setting func for pin %u to %u\n", pin, pin_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) l1 &= ~(RZN1_L1_FUNC_MASK << RZN1_L1_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (pin_config < RZN1_FUNC_L2_OFFSET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) l1 |= (pin_config << RZN1_L1_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) l1 |= (RZN1_L1_FUNCTION_L2 << RZN1_L1_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) l2 = pin_config - RZN1_FUNC_L2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* If either configuration changes, we update both anyway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (l1 != l1_cache || l2 != l2_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) writel(l1, &ipctl->lev1->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) writel(l2, &ipctl->lev2->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const struct rzn1_pin_group *rzn1_pinctrl_find_group_by_name(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) const struct rzn1_pinctrl *ipctl, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) for (i = 0; i < ipctl->ngroups; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (!strcmp(ipctl->groups[i].name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return &ipctl->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int rzn1_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return ipctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const char *rzn1_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ipctl->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int rzn1_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int selector, const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int *npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (selector >= ipctl->ngroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *pins = ipctl->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) *npins = ipctl->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * This function is called for each pinctl 'Function' node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * Sub-nodes can be used to describe multiple 'Groups' for the 'Function'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * If there aren't any sub-nodes, the 'Group' is essentially the 'Function'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * Each 'Group' uses pinmux = <...> to detail the pins and data used to select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * the functionality. Each 'Group' has optional pin configurations that apply
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * to all pins in the 'Group'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int rzn1_dt_node_to_map_one(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const struct rzn1_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) unsigned long *configs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) unsigned int reserved_maps = *num_maps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) unsigned int num_configs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned int reserve = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_dbg(ipctl->dev, "processing node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) grp = rzn1_pinctrl_find_group_by_name(ipctl, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!grp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(ipctl->dev, "unable to find group for node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Get the group's pin configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) &num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) dev_err(ipctl->dev, "%pOF: could not parse property\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reserve++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Increase the number of maps to cover this group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reserve);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Associate the group with the function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = pinctrl_utils_add_map_mux(pctldev, map, &reserved_maps, num_maps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) grp->name, grp->func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (num_configs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Associate the group's pin configuration with the group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = pinctrl_utils_add_map_configs(pctldev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) &reserved_maps, num_maps, grp->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) configs, num_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PIN_MAP_TYPE_CONFIGS_GROUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev_dbg(pctldev->dev, "maps: function %s group %s (%d pins)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) grp->func, grp->name, grp->npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) kfree(configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int rzn1_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = rzn1_dt_node_to_map_one(pctldev, np, map, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ret = rzn1_dt_node_to_map_one(pctldev, child, map, num_maps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct pinctrl_ops rzn1_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .get_groups_count = rzn1_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .get_group_name = rzn1_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .get_group_pins = rzn1_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .dt_node_to_map = rzn1_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int rzn1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ipctl->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) static const char *rzn1_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ipctl->functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int rzn1_pmx_get_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *groups = ipctl->functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *num_groups = ipctl->functions[selector].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int rzn1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct rzn1_pin_group *grp = &ipctl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int i, grp_pins = grp->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_dbg(ipctl->dev, "set mux %s(%d) group %s(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ipctl->functions[selector].name, selector, grp->name, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) rzn1_hw_set_lock(ipctl, LOCK_ALL, LOCK_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) for (i = 0; i < grp_pins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) rzn1_set_hw_pin_func(ipctl, grp->pins[i], grp->pin_ids[i], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) rzn1_hw_set_lock(ipctl, LOCK_ALL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct pinmux_ops rzn1_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .get_functions_count = rzn1_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .get_function_name = rzn1_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .get_function_groups = rzn1_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .set_mux = rzn1_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int rzn1_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) enum pin_config_param param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const u32 reg_drive[4] = { 4, 6, 8, 12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 pull, drive, l1mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 l1, l2, arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) l1 = readl(&ipctl->lev1->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) l1mux = l1 & RZN1_L1_FUNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pull = (l1 >> RZN1_L1_PIN_PULL) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) drive = (l1 >> RZN1_L1_PIN_DRIVE_STRENGTH) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (pull != RZN1_L1_PIN_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (pull != RZN1_L1_PIN_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (pull != RZN1_L1_PIN_PULL_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) arg = reg_drive[drive];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) l2 = readl(&ipctl->lev2->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (l1mux == RZN1_L1_FUNCTION_L2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (l2 != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) } else if (l1mux != RZN1_FUNC_HIGHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int rzn1_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) unsigned long *configs, unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) enum pin_config_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 l1, l1_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (pin >= ARRAY_SIZE(ipctl->lev1->conf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) l1 = readl(&ipctl->lev1->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) l1_cache = l1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_dbg(ipctl->dev, "set pin %d pull up\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) l1 |= (RZN1_L1_PIN_PULL_UP << RZN1_L1_PIN_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_dbg(ipctl->dev, "set pin %d pull down\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) l1 |= (RZN1_L1_PIN_PULL_DOWN << RZN1_L1_PIN_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev_dbg(ipctl->dev, "set pin %d bias off\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) l1 &= ~(0x3 << RZN1_L1_PIN_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) l1 |= (RZN1_L1_PIN_PULL_NONE << RZN1_L1_PIN_PULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_dbg(ipctl->dev, "set pin %d drv %umA\n", pin, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) switch (arg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) drv = RZN1_L1_PIN_DRIVE_STRENGTH_4MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) drv = RZN1_L1_PIN_DRIVE_STRENGTH_6MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) drv = RZN1_L1_PIN_DRIVE_STRENGTH_8MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) drv = RZN1_L1_PIN_DRIVE_STRENGTH_12MA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "Drive strength %umA not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) l1 &= ~(0x3 << RZN1_L1_PIN_DRIVE_STRENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) l1 |= (drv << RZN1_L1_PIN_DRIVE_STRENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) dev_dbg(ipctl->dev, "set pin %d High-Z\n", pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) l1 &= ~RZN1_L1_FUNC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) l1 |= RZN1_FUNC_HIGHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (l1 != l1_cache) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, LOCK_LEVEL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) writel(l1, &ipctl->lev1->conf[pin]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) rzn1_hw_set_lock(ipctl, LOCK_LEVEL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int rzn1_pinconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct rzn1_pin_group *grp = &ipctl->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) unsigned long old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_dbg(ipctl->dev, "group get %s selector:%u\n", grp->name, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (rzn1_pinconf_get(pctldev, grp->pins[i], config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* configs do not match between two pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (i && (old != *config))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) old = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int rzn1_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct rzn1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct rzn1_pin_group *grp = &ipctl->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_dbg(ipctl->dev, "group set %s selector:%u configs:%p/%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) grp->name, selector, configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned int pin = grp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = rzn1_pinconf_set(pctldev, pin, configs, num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const struct pinconf_ops rzn1_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .pin_config_get = rzn1_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .pin_config_set = rzn1_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .pin_config_group_get = rzn1_pinconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .pin_config_group_set = rzn1_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .pin_config_config_dbg_show = pinconf_generic_dump_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static struct pinctrl_desc rzn1_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .pctlops = &rzn1_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .pmxops = &rzn1_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .confops = &rzn1_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int rzn1_pinctrl_parse_groups(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct rzn1_pin_group *grp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct rzn1_pinctrl *ipctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) const __be32 *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_dbg(ipctl->dev, "%s: %s\n", __func__, np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* Initialise group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) grp->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * The binding format is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * pinmux = <PIN_FUNC_ID CONFIG ...>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * do sanity check and calculate pins number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) list = of_get_property(np, RZN1_PINS_PROP, &size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "no " RZN1_PINS_PROP " property in node %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev_err(ipctl->dev, "Invalid " RZN1_PINS_PROP " in node %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) grp->npins = size / sizeof(list[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) grp->pin_ids = devm_kmalloc_array(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) grp->npins, sizeof(grp->pin_ids[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) grp->pins = devm_kmalloc_array(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) grp->npins, sizeof(grp->pins[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!grp->pin_ids || !grp->pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) for (i = 0; i < grp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) u32 pin_id = be32_to_cpu(*list++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) grp->pins[i] = pin_id & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) grp->pin_ids[i] = (pin_id >> 8) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return grp->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int rzn1_pinctrl_count_function_groups(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (of_property_count_u32_elems(child, RZN1_PINS_PROP) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int rzn1_pinctrl_parse_functions(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct rzn1_pinctrl *ipctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct rzn1_pmx_func *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct rzn1_pin_group *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) func = &ipctl->functions[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Initialise function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) func->name = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) func->num_groups = rzn1_pinctrl_count_function_groups(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (func->num_groups == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_dbg(ipctl->dev, "function %s has %d groups\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) np->name, func->num_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) func->groups = devm_kmalloc_array(ipctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) func->num_groups, sizeof(char *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!func->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (of_property_count_u32_elems(np, RZN1_PINS_PROP) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) func->groups[i] = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) grp = &ipctl->groups[ipctl->ngroups];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) grp->func = func->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ret = rzn1_pinctrl_parse_groups(np, grp, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ipctl->ngroups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) func->groups[i] = child->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) grp = &ipctl->groups[ipctl->ngroups];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) grp->func = func->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = rzn1_pinctrl_parse_groups(child, grp, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ipctl->ngroups++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_dbg(ipctl->dev, "function %s parsed %u/%u groups\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) np->name, i, func->num_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int rzn1_pinctrl_probe_dt(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct rzn1_pinctrl *ipctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int maxgroups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int nfuncs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) nfuncs = of_get_child_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (nfuncs <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ipctl->nfunctions = nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ipctl->functions = devm_kmalloc_array(&pdev->dev, nfuncs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) sizeof(*ipctl->functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (!ipctl->functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ipctl->ngroups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) for_each_child_of_node(np, child)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) maxgroups += rzn1_pinctrl_count_function_groups(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ipctl->groups = devm_kmalloc_array(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) maxgroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) sizeof(*ipctl->groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!ipctl->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = rzn1_pinctrl_parse_functions(child, ipctl, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int rzn1_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct rzn1_pinctrl *ipctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Create state holders etc for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) if (!ipctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ipctl->mdio_func[0] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) ipctl->mdio_func[1] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ipctl->lev1_protect_phys = (u32)res->start + 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ipctl->lev1 = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (IS_ERR(ipctl->lev1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) return PTR_ERR(ipctl->lev1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ipctl->lev2_protect_phys = (u32)res->start + 0x400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ipctl->lev2 = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (IS_ERR(ipctl->lev2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return PTR_ERR(ipctl->lev2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ipctl->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (IS_ERR(ipctl->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return PTR_ERR(ipctl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = clk_prepare_enable(ipctl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ipctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rzn1_pinctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) rzn1_pinctrl_desc.pins = rzn1_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) rzn1_pinctrl_desc.npins = ARRAY_SIZE(rzn1_pins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = rzn1_pinctrl_probe_dt(pdev, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_err(&pdev->dev, "fail to probe dt properties\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) platform_set_drvdata(pdev, ipctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ret = devm_pinctrl_register_and_init(&pdev->dev, &rzn1_pinctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ipctl, &ipctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dev_err(&pdev->dev, "could not register rzn1 pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = pinctrl_enable(ipctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dev_info(&pdev->dev, "probed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) clk_disable_unprepare(ipctl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int rzn1_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) struct rzn1_pinctrl *ipctl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) clk_disable_unprepare(ipctl->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const struct of_device_id rzn1_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) { .compatible = "renesas,rzn1-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) MODULE_DEVICE_TABLE(of, rzn1_pinctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static struct platform_driver rzn1_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .probe = rzn1_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .remove = rzn1_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .name = "rzn1-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .of_match_table = rzn1_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static int __init _pinctrl_drv_register(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return platform_driver_register(&rzn1_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) subsys_initcall(_pinctrl_drv_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) MODULE_DESCRIPTION("Renesas RZ/N1 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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