^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Combined GPIO and pin controller support for Renesas RZ/A2 (R7S9210) SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Chris Brandt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This pin controller/gpio combined driver supports Renesas devices of RZ/A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRIVER_NAME "pinctrl-rza2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RZA2_PINS_PER_PORT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define RZA2_PIN_ID_TO_PORT(id) ((id) / RZA2_PINS_PER_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define RZA2_PIN_ID_TO_PIN(id) ((id) % RZA2_PINS_PER_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Use 16 lower bits [15:0] for pin identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Use 16 higher bits [31:16] for pin mux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MUX_PIN_ID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MUX_FUNC_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MUX_FUNC_OFFS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MUX_FUNC(pinconf) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const char port_names[] = "0123456789ABCDEFGHJKLM";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct rza2_pinctrl_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct pinctrl_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct pinctrl_gpio_range gpio_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RZA2_PDR(port) (0x0000 + (port) * 2) /* Direction 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RZA2_PODR(port) (0x0040 + (port)) /* Output Data 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RZA2_PIDR(port) (0x0060 + (port)) /* Input Data 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RZA2_PMR(port) (0x0080 + (port)) /* Mode 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RZA2_DSCR(port) (0x0140 + (port) * 2) /* Drive 16-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RZA2_PFS(port, pin) (0x0200 + ((port) * 8) + (pin)) /* Fnct 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RZA2_PWPR 0x02ff /* Write Protect 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RZA2_PFENET 0x0820 /* Ethernet Pins 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RZA2_PPOC 0x0900 /* Dedicated Pins 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RZA2_PHMOMO 0x0980 /* Peripheral Pins 32-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RZA2_PCKIO 0x09d0 /* CKIO Drive 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RZA2_PDR_INPUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RZA2_PDR_OUTPUT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define RZA2_PDR_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PWPR_B0WI BIT(7) /* Bit Write Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PWPR_PFSWE BIT(6) /* PFS Register Write Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PFS_ISEL BIT(6) /* Interrupt Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static void rza2_set_pin_function(void __iomem *pfc_base, u8 port, u8 pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u16 mask16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u16 reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 reg8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Set pin to 'Non-use (Hi-z input protection)' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg16 = readw(pfc_base + RZA2_PDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mask16 = RZA2_PDR_MASK << (pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg16 &= ~mask16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) writew(reg16, pfc_base + RZA2_PDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Temporarily switch to GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) reg8 = readb(pfc_base + RZA2_PMR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) reg8 &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) writeb(reg8, pfc_base + RZA2_PMR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* PFS Register Write Protect : OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writeb(PWPR_PFSWE, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Set Pin function (interrupt disabled, ISEL=0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) writeb(func, pfc_base + RZA2_PFS(port, pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* PFS Register Write Protect : ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) writeb(0x00, pfc_base + RZA2_PWPR); /* B0WI=0, PFSWE=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) writeb(0x80, pfc_base + RZA2_PWPR); /* B0WI=1, PFSWE=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Port Mode : Peripheral module pin functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg8 = readb(pfc_base + RZA2_PMR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) reg8 |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) writeb(reg8, pfc_base + RZA2_PMR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void rza2_pin_to_gpio(void __iomem *pfc_base, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 port = RZA2_PIN_ID_TO_PORT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 pin = RZA2_PIN_ID_TO_PIN(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 mask16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg16 = readw(pfc_base + RZA2_PDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) mask16 = RZA2_PDR_MASK << (pin * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg16 &= ~mask16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg16 |= RZA2_PDR_INPUT << (pin * 2); /* pin as input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) reg16 |= RZA2_PDR_OUTPUT << (pin * 2); /* pin as output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writew(reg16, pfc_base + RZA2_PDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int rza2_chip_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 port = RZA2_PIN_ID_TO_PORT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 pin = RZA2_PIN_ID_TO_PIN(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 reg16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) reg16 = readw(priv->base + RZA2_PDR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) reg16 = (reg16 >> (pin * 2)) & RZA2_PDR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (reg16 == RZA2_PDR_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (reg16 == RZA2_PDR_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * This GPIO controller has a default Hi-Z state that is not input or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * output, so force the pin to input now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rza2_pin_to_gpio(priv->base, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int rza2_chip_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rza2_pin_to_gpio(priv->base, offset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int rza2_chip_get(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u8 port = RZA2_PIN_ID_TO_PORT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 pin = RZA2_PIN_ID_TO_PIN(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return !!(readb(priv->base + RZA2_PIDR(port)) & BIT(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void rza2_chip_set(struct gpio_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 port = RZA2_PIN_ID_TO_PORT(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 pin = RZA2_PIN_ID_TO_PIN(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 new_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) new_value = readb(priv->base + RZA2_PODR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) new_value |= BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) new_value &= ~BIT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writeb(new_value, priv->base + RZA2_PODR(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int rza2_chip_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int offset, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct rza2_pinctrl_priv *priv = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rza2_chip_set(chip, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rza2_pin_to_gpio(priv->base, offset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const char * const rza2_gpio_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "PA_0", "PA_1", "PA_2", "PA_3", "PA_4", "PA_5", "PA_6", "PA_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "PB_0", "PB_1", "PB_2", "PB_3", "PB_4", "PB_5", "PB_6", "PB_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "PC_0", "PC_1", "PC_2", "PC_3", "PC_4", "PC_5", "PC_6", "PC_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "PD_0", "PD_1", "PD_2", "PD_3", "PD_4", "PD_5", "PD_6", "PD_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "PE_0", "PE_1", "PE_2", "PE_3", "PE_4", "PE_5", "PE_6", "PE_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "PF_0", "PF_1", "PF_2", "PF_3", "PF_4", "PF_5", "PF_6", "PF_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "PG_0", "PG_1", "PG_2", "PG_3", "PG_4", "PG_5", "PG_6", "PG_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "PH_0", "PH_1", "PH_2", "PH_3", "PH_4", "PH_5", "PH_6", "PH_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* port I does not exist */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "PJ_0", "PJ_1", "PJ_2", "PJ_3", "PJ_4", "PJ_5", "PJ_6", "PJ_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "PK_0", "PK_1", "PK_2", "PK_3", "PK_4", "PK_5", "PK_6", "PK_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "PL_0", "PL_1", "PL_2", "PL_3", "PL_4", "PL_5", "PL_6", "PL_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "PM_0", "PM_1", "PM_2", "PM_3", "PM_4", "PM_5", "PM_6", "PM_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct gpio_chip chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .names = rza2_gpio_names,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .get_direction = rza2_chip_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .direction_input = rza2_chip_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .direction_output = rza2_chip_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .get = rza2_chip_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .set = rza2_chip_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int rza2_gpio_register(struct rza2_pinctrl_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct device_node *np = priv->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct of_phandle_args of_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) chip.label = devm_kasprintf(priv->dev, GFP_KERNEL, "%pOFn", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) chip.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) chip.parent = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) chip.ngpio = priv->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) &of_args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(priv->dev, "Unable to parse gpio-ranges\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if ((of_args.args[0] != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) (of_args.args[1] != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (of_args.args[2] != priv->npins)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(priv->dev, "gpio-ranges does not match selected SOC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) priv->gpio_range.id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) priv->gpio_range.pin_base = priv->gpio_range.base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) priv->gpio_range.npins = priv->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) priv->gpio_range.name = chip.label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) priv->gpio_range.gc = &chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Register our gpio chip with gpiolib */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ret = devm_gpiochip_add_data(priv->dev, &chip, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Register pin range with pinctrl core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pinctrl_add_gpio_range(priv->pctl, &priv->gpio_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_dbg(priv->dev, "Registered gpio controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int rza2_pinctrl_register(struct rza2_pinctrl_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pins = devm_kcalloc(priv->dev, priv->npins, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) priv->pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) priv->desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) priv->desc.npins = priv->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 0; i < priv->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pins[i].name = rza2_gpio_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ret = devm_pinctrl_register_and_init(priv->dev, &priv->desc, priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) &priv->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(priv->dev, "pinctrl registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = pinctrl_enable(priv->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) dev_err(priv->dev, "pinctrl enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = rza2_gpio_register(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) dev_err(priv->dev, "GPIO registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * For each DT node, create a single pin mapping. That pin mapping will only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * contain a single group of pins, and that group of pins will only have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * single function that can be selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int rza2_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int *pins, *psel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int i, ret, npins, gsel, fsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct property *of_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const char **pin_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Find out how many pins to map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) of_pins = of_find_property(np, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (!of_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dev_info(priv->dev, "Missing pinmux property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) npins = of_pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) pins = devm_kcalloc(priv->dev, npins, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) psel_val = devm_kcalloc(priv->dev, npins, sizeof(*psel_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pin_fn = devm_kzalloc(priv->dev, sizeof(*pin_fn), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!pins || !psel_val || !pin_fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Collect pin locations and mux settings from DT properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) for (i = 0; i < npins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = of_property_read_u32_index(np, "pinmux", i, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pins[i] = value & MUX_PIN_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) psel_val[i] = MUX_FUNC(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* Register a single pin group listing all the pins we read from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) gsel = pinctrl_generic_add_group(pctldev, np->name, pins, npins, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (gsel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return gsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * Register a single group function where the 'data' is an array PSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * register values read from DT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pin_fn[0] = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) fsel = pinmux_generic_add_function(pctldev, np->name, pin_fn, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) psel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (fsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = fsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) goto remove_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(priv->dev, "Parsed %pOF with %d pins\n", np, npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Create map where to retrieve function and mux settings from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *map = kzalloc(sizeof(**map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!*map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) goto remove_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) (*map)->data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) (*map)->data.mux.function = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) remove_function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) pinmux_generic_remove_function(pctldev, fsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) remove_group:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pinctrl_generic_remove_group(pctldev, gsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(priv->dev, "Unable to parse DT node %s\n", np->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static void rza2_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct pinctrl_map *map, unsigned int num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct pinctrl_ops rza2_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .dt_node_to_map = rza2_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .dt_free_map = rza2_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int rza2_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct rza2_pinctrl_priv *priv = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int i, *psel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) func = pinmux_generic_get_function(pctldev, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) psel_val = func->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) for (i = 0; i < grp->num_pins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) dev_dbg(priv->dev, "Setting P%c_%d to PSEL=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) port_names[RZA2_PIN_ID_TO_PORT(grp->pins[i])],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) RZA2_PIN_ID_TO_PIN(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) psel_val[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) rza2_set_pin_function(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) priv->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) RZA2_PIN_ID_TO_PORT(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RZA2_PIN_ID_TO_PIN(grp->pins[i]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) psel_val[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct pinmux_ops rza2_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .set_mux = rza2_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int rza2_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct rza2_pinctrl_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) priv->npins = (int)(uintptr_t)of_device_get_match_data(&pdev->dev) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) RZA2_PINS_PER_PORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) priv->desc.name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) priv->desc.pctlops = &rza2_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) priv->desc.pmxops = &rza2_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) priv->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = rza2_pinctrl_register(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_info(&pdev->dev, "Registered ports P0 - P%c\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) port_names[priv->desc.npins / RZA2_PINS_PER_PORT - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct of_device_id rza2_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { .compatible = "renesas,r7s9210-pinctrl", .data = (void *)22, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static struct platform_driver rza2_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .of_match_table = rza2_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .probe = rza2_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int __init rza2_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return platform_driver_register(&rza2_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) core_initcall(rza2_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MODULE_AUTHOR("Chris Brandt <chris.brandt@renesas.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/A2 SoC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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