^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Combined GPIO and pin controller support for Renesas RZ/A1 (r7s72100) SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Jacopo Mondi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This pin controller/gpio combined driver supports Renesas devices of RZ/A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This includes SoCs which are sub- or super- sets of this particular line,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * as RZ/A1H (r7s721000), RZ/A1M (r7s721010) and RZ/A1L (r7s721020).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "../devicetree.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../pinmux.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_NAME "pinctrl-rza1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RZA1_P_REG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RZA1_PPR_REG 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define RZA1_PM_REG 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RZA1_PMC_REG 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RZA1_PFC_REG 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RZA1_PFCE_REG 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RZA1_PFCEA_REG 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RZA1_PIBC_REG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RZA1_PBDC_REG 0x4100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RZA1_PIPC_REG 0x4200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RZA1_ADDR(mem, reg, port) ((mem) + (reg) + ((port) * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RZA1_NPORTS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RZA1_PINS_PER_PORT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RZA1_NPINS (RZA1_PINS_PER_PORT * RZA1_NPORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RZA1_PIN_ID_TO_PORT(id) ((id) / RZA1_PINS_PER_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RZA1_PIN_ID_TO_PIN(id) ((id) % RZA1_PINS_PER_PORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * Use 16 lower bits [15:0] for pin identifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Use 16 higher bits [31:16] for pin mux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MUX_PIN_ID_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MUX_FUNC_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MUX_FUNC_OFFS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MUX_FUNC(pinconf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ((pinconf & MUX_FUNC_MASK) >> MUX_FUNC_OFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MUX_FUNC_PFC_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MUX_FUNC_PFCE_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MUX_FUNC_PFCEA_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Pin mux flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MUX_FLAGS_BIDIR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MUX_FLAGS_SWIO_INPUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MUX_FLAGS_SWIO_OUTPUT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * RZ/A1 pinmux flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * rza1_bidir_pin - describe a single pin that needs bidir flag applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct rza1_bidir_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 pin: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 func: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * rza1_bidir_entry - describe a list of pins that needs bidir flag applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Each struct rza1_bidir_entry describes a port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct rza1_bidir_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const struct rza1_bidir_pin *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * rza1_swio_pin - describe a single pin that needs swio flag applied.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct rza1_swio_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u16 pin: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 port: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u16 func: 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u16 input: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * rza1_swio_entry - describe a list of pins that needs swio flag applied
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct rza1_swio_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) const struct rza1_swio_pin *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * rza1_pinmux_conf - group together bidir and swio pinmux flag tables
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct rza1_pinmux_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct rza1_bidir_entry *bidir_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) const struct rza1_swio_entry *swio_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * RZ/A1H (r7s72100) pinmux flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct rza1_bidir_pin rza1h_bidir_pins_p1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { .pin = 0, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { .pin = 1, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { .pin = 2, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { .pin = 3, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { .pin = 4, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { .pin = 5, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { .pin = 6, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { .pin = 7, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct rza1_bidir_pin rza1h_bidir_pins_p2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { .pin = 0, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { .pin = 1, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { .pin = 2, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { .pin = 3, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .pin = 4, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { .pin = 0, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { .pin = 1, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { .pin = 2, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { .pin = 3, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .pin = 5, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { .pin = 6, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { .pin = 7, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { .pin = 8, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { .pin = 9, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { .pin = 10, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { .pin = 11, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { .pin = 12, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { .pin = 13, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { .pin = 14, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { .pin = 15, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { .pin = 12, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { .pin = 13, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { .pin = 14, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { .pin = 15, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct rza1_bidir_pin rza1h_bidir_pins_p3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { .pin = 3, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { .pin = 10, .func = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { .pin = 11, .func = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { .pin = 13, .func = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { .pin = 14, .func = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { .pin = 15, .func = 7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .pin = 10, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { .pin = 11, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { .pin = 13, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { .pin = 14, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { .pin = 15, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct rza1_bidir_pin rza1h_bidir_pins_p4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { .pin = 0, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .pin = 1, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .pin = 2, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .pin = 3, .func = 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .pin = 10, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { .pin = 11, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { .pin = 13, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { .pin = 14, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { .pin = 15, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { .pin = 10, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { .pin = 11, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { .pin = 13, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { .pin = 14, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { .pin = 15, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { .pin = 12, .func = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { .pin = 13, .func = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { .pin = 14, .func = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { .pin = 15, .func = 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct rza1_bidir_pin rza1h_bidir_pins_p6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { .pin = 0, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { .pin = 1, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { .pin = 2, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { .pin = 3, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { .pin = 4, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { .pin = 5, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .pin = 6, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { .pin = 7, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { .pin = 8, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { .pin = 9, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { .pin = 10, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { .pin = 11, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { .pin = 12, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .pin = 13, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .pin = 14, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { .pin = 15, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const struct rza1_bidir_pin rza1h_bidir_pins_p7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { .pin = 13, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const struct rza1_bidir_pin rza1h_bidir_pins_p8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { .pin = 8, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { .pin = 9, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { .pin = 10, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { .pin = 11, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { .pin = 14, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { .pin = 15, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { .pin = 14, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { .pin = 15, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct rza1_bidir_pin rza1h_bidir_pins_p9[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { .pin = 0, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { .pin = 1, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { .pin = 4, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { .pin = 5, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { .pin = 6, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { .pin = 7, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const struct rza1_bidir_pin rza1h_bidir_pins_p11[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { .pin = 6, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { .pin = 7, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { .pin = 9, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { .pin = 6, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { .pin = 7, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { .pin = 9, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { .pin = 10, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .pin = 11, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { .pin = 10, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { .pin = 11, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { .pin = 12, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { .pin = 13, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { .pin = 14, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { .pin = 15, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct rza1_swio_pin rza1h_swio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { .port = 2, .pin = 7, .func = 4, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { .port = 2, .pin = 11, .func = 4, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { .port = 3, .pin = 7, .func = 3, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { .port = 3, .pin = 7, .func = 8, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { .port = 4, .pin = 7, .func = 5, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { .port = 4, .pin = 7, .func = 11, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { .port = 4, .pin = 15, .func = 6, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { .port = 5, .pin = 0, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { .port = 5, .pin = 1, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { .port = 5, .pin = 2, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { .port = 5, .pin = 3, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { .port = 5, .pin = 4, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { .port = 5, .pin = 5, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { .port = 5, .pin = 6, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { .port = 5, .pin = 7, .func = 1, .input = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { .port = 7, .pin = 4, .func = 6, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { .port = 7, .pin = 11, .func = 2, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { .port = 8, .pin = 10, .func = 8, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { .port = 10, .pin = 15, .func = 2, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct rza1_bidir_entry rza1h_bidir_entries[RZA1_NPORTS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [1] = { ARRAY_SIZE(rza1h_bidir_pins_p1), rza1h_bidir_pins_p1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [2] = { ARRAY_SIZE(rza1h_bidir_pins_p2), rza1h_bidir_pins_p2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [3] = { ARRAY_SIZE(rza1h_bidir_pins_p3), rza1h_bidir_pins_p3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) [4] = { ARRAY_SIZE(rza1h_bidir_pins_p4), rza1h_bidir_pins_p4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [6] = { ARRAY_SIZE(rza1h_bidir_pins_p6), rza1h_bidir_pins_p6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [7] = { ARRAY_SIZE(rza1h_bidir_pins_p7), rza1h_bidir_pins_p7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [8] = { ARRAY_SIZE(rza1h_bidir_pins_p8), rza1h_bidir_pins_p8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) [9] = { ARRAY_SIZE(rza1h_bidir_pins_p9), rza1h_bidir_pins_p9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [11] = { ARRAY_SIZE(rza1h_bidir_pins_p11), rza1h_bidir_pins_p11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct rza1_swio_entry rza1h_swio_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) [0] = { ARRAY_SIZE(rza1h_swio_pins), rza1h_swio_pins },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* RZ/A1H (r7s72100x) pinmux flags table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct rza1_pinmux_conf rza1h_pmx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .bidir_entries = rza1h_bidir_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .swio_entries = rza1h_swio_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * RZ/A1L (r7s72102) pinmux flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct rza1_bidir_pin rza1l_bidir_pins_p1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { .pin = 0, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { .pin = 1, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { .pin = 2, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { .pin = 3, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { .pin = 4, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { .pin = 5, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { .pin = 6, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { .pin = 7, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const struct rza1_bidir_pin rza1l_bidir_pins_p3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { .pin = 0, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { .pin = 1, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { .pin = 2, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { .pin = 4, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { .pin = 5, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { .pin = 10, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { .pin = 11, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .pin = 12, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { .pin = 13, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const struct rza1_bidir_pin rza1l_bidir_pins_p4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { .pin = 1, .func = 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { .pin = 2, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { .pin = 3, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { .pin = 6, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { .pin = 7, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct rza1_bidir_pin rza1l_bidir_pins_p5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { .pin = 0, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { .pin = 1, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { .pin = 2, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { .pin = 3, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { .pin = 4, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { .pin = 5, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { .pin = 6, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { .pin = 7, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { .pin = 8, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { .pin = 9, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { .pin = 10, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { .pin = 11, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { .pin = 12, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { .pin = 13, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { .pin = 14, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { .pin = 15, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { .pin = 0, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { .pin = 1, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { .pin = 2, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { .pin = 3, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct rza1_bidir_pin rza1l_bidir_pins_p6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .pin = 0, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .pin = 1, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .pin = 2, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .pin = 3, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .pin = 4, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .pin = 5, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { .pin = 6, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { .pin = 7, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { .pin = 8, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { .pin = 9, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { .pin = 10, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { .pin = 11, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { .pin = 12, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { .pin = 13, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { .pin = 14, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { .pin = 15, .func = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const struct rza1_bidir_pin rza1l_bidir_pins_p7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { .pin = 2, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { .pin = 3, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { .pin = 5, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { .pin = 6, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { .pin = 7, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { .pin = 2, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { .pin = 3, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { .pin = 5, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { .pin = 6, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { .pin = 7, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct rza1_bidir_pin rza1l_bidir_pins_p9[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { .pin = 1, .func = 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { .pin = 0, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { .pin = 1, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { .pin = 3, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { .pin = 4, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { .pin = 5, .func = 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct rza1_swio_pin rza1l_swio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { .port = 2, .pin = 8, .func = 2, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { .port = 5, .pin = 6, .func = 3, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { .port = 6, .pin = 6, .func = 3, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { .port = 6, .pin = 10, .func = 3, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { .port = 7, .pin = 10, .func = 2, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { .port = 8, .pin = 2, .func = 3, .input = 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const struct rza1_bidir_entry rza1l_bidir_entries[RZA1_NPORTS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [1] = { ARRAY_SIZE(rza1l_bidir_pins_p1), rza1l_bidir_pins_p1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) [3] = { ARRAY_SIZE(rza1l_bidir_pins_p3), rza1l_bidir_pins_p3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [4] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) [5] = { ARRAY_SIZE(rza1l_bidir_pins_p4), rza1l_bidir_pins_p5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) [6] = { ARRAY_SIZE(rza1l_bidir_pins_p6), rza1l_bidir_pins_p6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) [7] = { ARRAY_SIZE(rza1l_bidir_pins_p7), rza1l_bidir_pins_p7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) [9] = { ARRAY_SIZE(rza1l_bidir_pins_p9), rza1l_bidir_pins_p9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static const struct rza1_swio_entry rza1l_swio_entries[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) [0] = { ARRAY_SIZE(rza1l_swio_pins), rza1l_swio_pins },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* RZ/A1L (r7s72102x) pinmux flags table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const struct rza1_pinmux_conf rza1l_pmx_conf = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .bidir_entries = rza1l_bidir_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .swio_entries = rza1l_swio_entries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * RZ/A1 types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * struct rza1_mux_conf - describes a pin multiplexing operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @id: the pin identifier from 0 to RZA1_NPINS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @port: the port where pin sits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @pin: pin id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * @mux_func: alternate function id number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @mux_flags: alternate function flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @value: output value to set the pin to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct rza1_mux_conf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u16 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u8 pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u8 mux_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u8 mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * struct rza1_port - describes a pin port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * This is mostly useful to lock register writes per-bank and not globally.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * @lock: protect access to HW registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * @id: port number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * @base: logical address base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * @pins: pins sitting on this port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct rza1_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * struct rza1_pinctrl - RZ pincontroller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @dev: parent device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @mutex: protect [pinctrl|pinmux]_generic functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @base: logical address base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * @nport: number of pin controller ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * @ports: pin controller banks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * @pins: pin array for pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * @desc: pincontroller desc for pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * @pctl: pinctrl device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * @data: device specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct rza1_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) unsigned int nport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct rza1_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct pinctrl_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) const void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * RZ/A1 pinmux flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static inline bool rza1_pinmux_get_bidir(unsigned int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const struct rza1_bidir_entry *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) const struct rza1_bidir_entry *entry = &table[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) const struct rza1_bidir_pin *bidir_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (i = 0; i < entry->npins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) bidir_pin = &entry->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (bidir_pin->pin == pin && bidir_pin->func == func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static inline int rza1_pinmux_get_swio(unsigned int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) const struct rza1_swio_entry *table)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) const struct rza1_swio_pin *swio_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) for (i = 0; i < table->npins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) swio_pin = &table->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (swio_pin->port == port && swio_pin->pin == pin &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) swio_pin->func == func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return swio_pin->input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * rza1_pinmux_get_flags() - return pinmux flags associated to a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static unsigned int rza1_pinmux_get_flags(unsigned int port, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct rza1_pinctrl *rza1_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const struct rza1_pinmux_conf *pmx_conf = rza1_pctl->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) const struct rza1_bidir_entry *bidir_entries = pmx_conf->bidir_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) const struct rza1_swio_entry *swio_entries = pmx_conf->swio_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) unsigned int pmx_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (rza1_pinmux_get_bidir(port, pin, func, bidir_entries))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pmx_flags |= MUX_FLAGS_BIDIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ret = rza1_pinmux_get_swio(port, pin, func, swio_entries);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) pmx_flags |= MUX_FLAGS_SWIO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) else if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pmx_flags |= MUX_FLAGS_SWIO_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return pmx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * RZ/A1 SoC operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * rza1_set_bit() - un-locked set/clear a single bit in pin configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static inline void rza1_set_bit(struct rza1_port *port, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned int bit, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) u16 val = ioread16(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) val |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) val &= ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) iowrite16(val, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static inline unsigned int rza1_get_bit(struct rza1_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned int reg, unsigned int bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) void __iomem *mem = RZA1_ADDR(port->base, reg, port->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ioread16(mem) & BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * rza1_pin_reset() - reset a pin to default initial state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * Reset pin state disabling input buffer and bi-directional control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * and configure it as input port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * Note that pin is now configured with direction as input but with input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * buffer disabled. This implies the pin value cannot be read in this state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @port: port where pin sits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * @pin: pin offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void rza1_pin_reset(struct rza1_port *port, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) spin_lock_irqsave(&port->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) rza1_set_bit(port, RZA1_PIBC_REG, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) rza1_set_bit(port, RZA1_PM_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rza1_set_bit(port, RZA1_PMC_REG, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rza1_set_bit(port, RZA1_PIPC_REG, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) spin_unlock_irqrestore(&port->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * rza1_pin_set_direction() - set I/O direction on a pin in port mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * When running in output port mode keep PBDC enabled to allow reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * pin value from PPR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * @port: port where pin sits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * @pin: pin offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * @input: input enable/disable flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static inline void rza1_pin_set_direction(struct rza1_port *port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned int pin, bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) spin_lock_irqsave(&port->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) rza1_set_bit(port, RZA1_PIBC_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rza1_set_bit(port, RZA1_PM_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rza1_set_bit(port, RZA1_PBDC_REG, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rza1_set_bit(port, RZA1_PM_REG, pin, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) spin_unlock_irqrestore(&port->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static inline void rza1_pin_set(struct rza1_port *port, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned long irqflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spin_lock_irqsave(&port->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) rza1_set_bit(port, RZA1_P_REG, pin, !!value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) spin_unlock_irqrestore(&port->lock, irqflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static inline int rza1_pin_get(struct rza1_port *port, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return rza1_get_bit(port, RZA1_PPR_REG, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * rza1_pin_mux_single() - configure pin multiplexing on a single pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * @rza1_pctl: RZ/A1 pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * @mux_conf: pin multiplexing descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int rza1_pin_mux_single(struct rza1_pinctrl *rza1_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct rza1_mux_conf *mux_conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct rza1_port *port = &rza1_pctl->ports[mux_conf->port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int pin = mux_conf->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 mux_func = mux_conf->mux_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u8 mux_flags = mux_conf->mux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) u8 mux_flags_from_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) rza1_pin_reset(port, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* SWIO pinmux flags coming from DT are high precedence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mux_flags_from_table = rza1_pinmux_get_flags(port->id, pin, mux_func,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) rza1_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (mux_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) mux_flags |= (mux_flags_from_table & MUX_FLAGS_BIDIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mux_flags = mux_flags_from_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (mux_flags & MUX_FLAGS_BIDIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) rza1_set_bit(port, RZA1_PBDC_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Enable alternate function mode and select it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) * Be careful here: the pin mux sub-nodes in device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) * enumerate alternate functions from 1 to 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) * subtract 1 before using macros to match registers configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * which expects numbers from 0 to 7 instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * ----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * Alternate mode selection table:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * PMC PFC PFCE PFCAE (mux_func - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * 1 0 0 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * 1 1 0 0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * 1 0 1 0 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * 1 1 1 0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * 1 0 0 1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * 1 1 0 1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * 1 0 1 1 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * 1 1 1 1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * ----------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) mux_func -= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) rza1_set_bit(port, RZA1_PFC_REG, pin, mux_func & MUX_FUNC_PFC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) rza1_set_bit(port, RZA1_PFCE_REG, pin, mux_func & MUX_FUNC_PFCE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) rza1_set_bit(port, RZA1_PFCEA_REG, pin, mux_func & MUX_FUNC_PFCEA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * All alternate functions except a few need PIPCn = 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * If PIPCn has to stay disabled (SW IO mode), configure PMn according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * to I/O direction specified by pin configuration -after- PMC has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * set to one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (mux_flags & (MUX_FLAGS_SWIO_INPUT | MUX_FLAGS_SWIO_OUTPUT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) rza1_set_bit(port, RZA1_PM_REG, pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) mux_flags & MUX_FLAGS_SWIO_INPUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) rza1_set_bit(port, RZA1_PIPC_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) rza1_set_bit(port, RZA1_PMC_REG, pin, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * gpio operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * rza1_gpio_request() - configure pin in port mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Configure a pin as gpio (port mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * After reset, the pin is in input mode with input buffer disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * To use the pin as input or output, set_direction shall be called first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * @chip: gpio chip where the gpio sits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * @gpio: gpio offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int rza1_gpio_request(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) rza1_pin_reset(port, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * rza1_gpio_disable_free() - reset a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * Surprisingly, disable_free a gpio, is equivalent to request it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * Reset pin to port mode, with input buffer disabled. This overwrites all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * port direction settings applied with set_direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * @chip: gpio chip where the gpio sits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * @gpio: gpio offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void rza1_gpio_free(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) rza1_pin_reset(port, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int rza1_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (rza1_get_bit(port, RZA1_PM_REG, gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return GPIO_LINE_DIRECTION_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int rza1_gpio_direction_input(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) rza1_pin_set_direction(port, gpio, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int rza1_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Set value before driving pin direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) rza1_pin_set(port, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rza1_pin_set_direction(port, gpio, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * rza1_gpio_get() - read a gpio pin value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Read gpio pin value through PPR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Requires bi-directional mode to work when reading the value of a pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * in output mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * @chip: gpio chip where the gpio sits on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @gpio: gpio offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int rza1_gpio_get(struct gpio_chip *chip, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return rza1_pin_get(port, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static void rza1_gpio_set(struct gpio_chip *chip, unsigned int gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct rza1_port *port = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) rza1_pin_set(port, gpio, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct gpio_chip rza1_gpiochip_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .request = rza1_gpio_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .free = rza1_gpio_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .get_direction = rza1_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .direction_input = rza1_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .direction_output = rza1_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .get = rza1_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .set = rza1_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * pinctrl operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * rza1_dt_node_pin_count() - Count number of pins in a dt node or in all its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * children sub-nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * @np: device tree node to parse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static int rza1_dt_node_pin_count(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct property *of_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) of_pins = of_find_property(np, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (of_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return of_pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) npins = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) of_pins = of_find_property(child, "pinmux", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!of_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) npins += of_pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * rza1_parse_pmx_function() - parse a pin mux sub-node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * @rza1_pctl: RZ/A1 pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * @np: of pmx sub-node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * @mux_confs: array of pin mux configurations to fill with parsed info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * @grpins: array of pin ids to mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct rza1_mux_conf *mux_confs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned int *grpins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct pinctrl_dev *pctldev = rza1_pctl->pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) char const *prop_name = "pinmux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned long *pin_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unsigned int npin_configs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct property *of_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u8 pinmux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) of_pins = of_find_property(np, prop_name, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!of_pins) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dev_dbg(rza1_pctl->dev, "Missing %s property\n", prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) npins = of_pins->length / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * Collect pin configuration properties: they apply to all pins in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * this sub-node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ret = pinconf_generic_parse_dt_config(np, pctldev, &pin_configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) &npin_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev_err(rza1_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "Unable to parse pin configuration options for %pOFn\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Create a mask with pinmux flags from pin configuration;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * very few pins (TIOC[0-4][A|B|C|D] require SWIO direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * specified in device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) pinmux_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for (i = 0; i < npin_configs && pinmux_flags == 0; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) switch (pinconf_to_config_param(pin_configs[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pinmux_flags |= MUX_FLAGS_SWIO_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) case PIN_CONFIG_OUTPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) kfree(pin_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Collect pin positions and their mux settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) for (i = 0; i < npins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 of_pinconf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct rza1_mux_conf *mux_conf = &mux_confs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = of_property_read_u32_index(np, prop_name, i, &of_pinconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mux_conf->id = of_pinconf & MUX_PIN_ID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mux_conf->port = RZA1_PIN_ID_TO_PORT(mux_conf->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mux_conf->pin = RZA1_PIN_ID_TO_PIN(mux_conf->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mux_conf->mux_func = MUX_FUNC(of_pinconf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mux_conf->mux_flags = pinmux_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (mux_conf->port >= RZA1_NPORTS ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mux_conf->pin >= RZA1_PINS_PER_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) dev_err(rza1_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "Wrong port %u pin %u for %s property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mux_conf->port, mux_conf->pin, prop_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) grpins[i] = mux_conf->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * rza1_dt_node_to_map() - map a pin mux node to a function/group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * Parse and register a pin mux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * @pctldev: pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * @np: device tree node to parse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * @map: pointer to pin map (output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * @num_maps: number of collected maps (output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static int rza1_dt_node_to_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct pinctrl_map **map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned int *num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct rza1_mux_conf *mux_confs, *mux_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) unsigned int *grpins, *grpin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) const char *grpname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) const char **fngrps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int ret, npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) int gsel, fsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) npins = rza1_dt_node_pin_count(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (npins < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev_err(rza1_pctl->dev, "invalid pinmux node structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * Functions are made of 1 group only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * in fact, functions and groups are identical for this pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * except that functions carry an array of per-pin mux configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mux_confs = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*mux_confs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) grpins = devm_kcalloc(rza1_pctl->dev, npins, sizeof(*grpins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fngrps = devm_kzalloc(rza1_pctl->dev, sizeof(*fngrps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!mux_confs || !grpins || !fngrps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * Parse the pinmux node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * If the node does not contain "pinmux" property (-ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * that property shall be specified in all its children sub-nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mux_conf = &mux_confs[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) grpin = &grpins[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = rza1_parse_pinmux_node(rza1_pctl, np, mux_conf, grpin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret = rza1_parse_pinmux_node(rza1_pctl, child, mux_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) grpin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) grpin += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) mux_conf += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) else if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* Register pin group and function name to pinctrl_generic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) grpname = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) fngrps[0] = grpname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) mutex_lock(&rza1_pctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) gsel = pinctrl_generic_add_group(pctldev, grpname, grpins, npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (gsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_unlock(&rza1_pctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return gsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) fsel = pinmux_generic_add_function(pctldev, grpname, fngrps, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) mux_confs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (fsel < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = fsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto remove_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dev_info(rza1_pctl->dev, "Parsed function and group %s with %d pins\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) grpname, npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* Create map where to retrieve function and mux settings from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) *num_maps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) *map = kzalloc(sizeof(**map), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (!*map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) goto remove_function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) (*map)->data.mux.group = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) (*map)->data.mux.function = np->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) *num_maps = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mutex_unlock(&rza1_pctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) remove_function:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) pinmux_generic_remove_function(pctldev, fsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) remove_group:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pinctrl_generic_remove_group(pctldev, gsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mutex_unlock(&rza1_pctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) dev_info(rza1_pctl->dev, "Unable to parse function and group %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) grpname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static void rza1_dt_free_map(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct pinctrl_map *map, unsigned int num_maps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) kfree(map);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const struct pinctrl_ops rza1_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .get_groups_count = pinctrl_generic_get_group_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .get_group_name = pinctrl_generic_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .get_group_pins = pinctrl_generic_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .dt_node_to_map = rza1_dt_node_to_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) .dt_free_map = rza1_dt_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * pinmux operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * rza1_set_mux() - retrieve pins from a group and apply their mux settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * @pctldev: pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * @selector: function selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * @group: group selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int rza1_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct rza1_pinctrl *rza1_pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct rza1_mux_conf *mux_confs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct function_desc *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct group_desc *grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) grp = pinctrl_generic_get_group(pctldev, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!grp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) func = pinmux_generic_get_function(pctldev, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (!func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) mux_confs = (struct rza1_mux_conf *)func->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) for (i = 0; i < grp->num_pins; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) ret = rza1_pin_mux_single(rza1_pctl, &mux_confs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct pinmux_ops rza1_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .get_functions_count = pinmux_generic_get_function_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .get_function_name = pinmux_generic_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .get_function_groups = pinmux_generic_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .set_mux = rza1_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .strict = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* ----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * RZ/A1 pin controller driver operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static unsigned int rza1_count_gpio_chips(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) unsigned int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (!of_property_read_bool(child, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * rza1_parse_gpiochip() - parse and register a gpio chip and pin range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) * The gpio controller subnode shall provide a "gpio-ranges" list property as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) * defined by gpio device tree binding documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) * @rza1_pctl: RZ/A1 pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) * @np: of gpio-controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) * @chip: gpio chip to register to gpiolib
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * @range: pin range to register to pinctrl core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static int rza1_parse_gpiochip(struct rza1_pinctrl *rza1_pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct pinctrl_gpio_range *range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) const char *list_name = "gpio-ranges";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct of_phandle_args of_args;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) unsigned int gpioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) u32 pinctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = of_parse_phandle_with_fixed_args(np, list_name, 3, 0, &of_args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(rza1_pctl->dev, "Unable to parse %s list property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) list_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * Find out on which port this gpio-chip maps to by inspecting the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * second argument of the "gpio-ranges" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pinctrl_base = of_args.args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) gpioport = RZA1_PIN_ID_TO_PORT(pinctrl_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (gpioport >= RZA1_NPORTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_err(rza1_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "Invalid values in property %s\n", list_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) *chip = rza1_gpiochip_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) chip->label = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL, "%pOFn",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (!chip->label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) chip->ngpio = of_args.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) chip->of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) chip->parent = rza1_pctl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) range->id = gpioport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) range->name = chip->label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) range->pin_base = range->base = pinctrl_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) range->npins = of_args.args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) range->gc = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = devm_gpiochip_add_data(rza1_pctl->dev, chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) &rza1_pctl->ports[gpioport]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) pinctrl_add_gpio_range(rza1_pctl->pctl, range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev_dbg(rza1_pctl->dev, "Parsed gpiochip %s with %d pins\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) chip->label, chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * rza1_gpio_register() - parse DT to collect gpio-chips and gpio-ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * @rza1_pctl: RZ/A1 pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int rza1_gpio_register(struct rza1_pinctrl *rza1_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct device_node *np = rza1_pctl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct pinctrl_gpio_range *gpio_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct gpio_chip *gpio_chips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) unsigned int ngpiochips;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ngpiochips = rza1_count_gpio_chips(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (ngpiochips == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev_dbg(rza1_pctl->dev, "No gpiochip registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) gpio_chips = devm_kcalloc(rza1_pctl->dev, ngpiochips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) sizeof(*gpio_chips), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) gpio_ranges = devm_kcalloc(rza1_pctl->dev, ngpiochips,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) sizeof(*gpio_ranges), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (!gpio_chips || !gpio_ranges)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (!of_property_read_bool(child, "gpio-controller"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret = rza1_parse_gpiochip(rza1_pctl, child, &gpio_chips[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &gpio_ranges[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ++i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dev_info(rza1_pctl->dev, "Registered %u gpio controllers\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * rza1_pinctrl_register() - Enumerate pins, ports and gpiochips; register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * them to pinctrl and gpio cores.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * @rza1_pctl: RZ/A1 pin controller device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int rza1_pinctrl_register(struct rza1_pinctrl *rza1_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct rza1_port *ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pins = devm_kcalloc(rza1_pctl->dev, RZA1_NPINS, sizeof(*pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) ports = devm_kcalloc(rza1_pctl->dev, RZA1_NPORTS, sizeof(*ports),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (!pins || !ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) rza1_pctl->pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) rza1_pctl->desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) rza1_pctl->desc.npins = RZA1_NPINS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) rza1_pctl->ports = ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) for (i = 0; i < RZA1_NPINS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) unsigned int pin = RZA1_PIN_ID_TO_PIN(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) unsigned int port = RZA1_PIN_ID_TO_PORT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) pins[i].name = devm_kasprintf(rza1_pctl->dev, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) "P%u-%u", port, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!pins[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (i % RZA1_PINS_PER_PORT == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * Setup ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * they provide per-port lock and logical base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) unsigned int port_id = RZA1_PIN_ID_TO_PORT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ports[port_id].id = port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ports[port_id].base = rza1_pctl->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ports[port_id].pins = &pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) spin_lock_init(&ports[port_id].lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = devm_pinctrl_register_and_init(rza1_pctl->dev, &rza1_pctl->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) rza1_pctl, &rza1_pctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_err(rza1_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) "RZ/A1 pin controller registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = pinctrl_enable(rza1_pctl->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_err(rza1_pctl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) "RZ/A1 pin controller failed to start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = rza1_gpio_register(rza1_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_err(rza1_pctl->dev, "RZ/A1 GPIO registration failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static int rza1_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) struct rza1_pinctrl *rza1_pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) rza1_pctl = devm_kzalloc(&pdev->dev, sizeof(*rza1_pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (!rza1_pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) rza1_pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) rza1_pctl->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (IS_ERR(rza1_pctl->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return PTR_ERR(rza1_pctl->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) mutex_init(&rza1_pctl->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) platform_set_drvdata(pdev, rza1_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) rza1_pctl->desc.name = DRIVER_NAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) rza1_pctl->desc.pctlops = &rza1_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) rza1_pctl->desc.pmxops = &rza1_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) rza1_pctl->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) rza1_pctl->data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ret = rza1_pinctrl_register(rza1_pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) dev_info(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) "RZ/A1 pin controller and gpio successfully registered\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static const struct of_device_id rza1_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* RZ/A1H, RZ/A1M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .compatible = "renesas,r7s72100-ports",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .data = &rza1h_pmx_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* RZ/A1L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .compatible = "renesas,r7s72102-ports",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .data = &rza1l_pmx_conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static struct platform_driver rza1_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .of_match_table = rza1_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .probe = rza1_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static int __init rza1_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return platform_driver_register(&rza1_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) core_initcall(rza1_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) MODULE_AUTHOR("Jacopo Mondi <jacopo+renesas@jmondi.org");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) MODULE_DESCRIPTION("Pin and gpio controller driver for Reneas RZ/A1 SoC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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