^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SH7786 Pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008, 2009 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on SH7785 pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <cpu/sh7786.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PE7_DATA, PE6_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PG7_DATA, PG6_DATA, PG5_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PJ3_DATA, PJ2_DATA, PJ1_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINMUX_INPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PA7_IN, PA6_IN, PA5_IN, PA4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PA3_IN, PA2_IN, PA1_IN, PA0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PB7_IN, PB6_IN, PB5_IN, PB4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PB3_IN, PB2_IN, PB1_IN, PB0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PC7_IN, PC6_IN, PC5_IN, PC4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PC3_IN, PC2_IN, PC1_IN, PC0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PD7_IN, PD6_IN, PD5_IN, PD4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PD3_IN, PD2_IN, PD1_IN, PD0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PE7_IN, PE6_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PF7_IN, PF6_IN, PF5_IN, PF4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PF3_IN, PF2_IN, PF1_IN, PF0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PG7_IN, PG6_IN, PG5_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PH7_IN, PH6_IN, PH5_IN, PH4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PH3_IN, PH2_IN, PH1_IN, PH0_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PJ7_IN, PJ6_IN, PJ5_IN, PJ4_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PJ3_IN, PJ2_IN, PJ1_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINMUX_INPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINMUX_OUTPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PA7_OUT, PA6_OUT, PA5_OUT, PA4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PA3_OUT, PA2_OUT, PA1_OUT, PA0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PB7_OUT, PB6_OUT, PB5_OUT, PB4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PB3_OUT, PB2_OUT, PB1_OUT, PB0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PC7_OUT, PC6_OUT, PC5_OUT, PC4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PC3_OUT, PC2_OUT, PC1_OUT, PC0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PD7_OUT, PD6_OUT, PD5_OUT, PD4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PD3_OUT, PD2_OUT, PD1_OUT, PD0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PE7_OUT, PE6_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PF7_OUT, PF6_OUT, PF5_OUT, PF4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PF3_OUT, PF2_OUT, PF1_OUT, PF0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PG7_OUT, PG6_OUT, PG5_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PH7_OUT, PH6_OUT, PH5_OUT, PH4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PH3_OUT, PH2_OUT, PH1_OUT, PH0_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PJ7_OUT, PJ6_OUT, PJ5_OUT, PJ4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PJ3_OUT, PJ2_OUT, PJ1_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINMUX_OUTPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PA7_FN, PA6_FN, PA5_FN, PA4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PA3_FN, PA2_FN, PA1_FN, PA0_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PB7_FN, PB6_FN, PB5_FN, PB4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PB3_FN, PB2_FN, PB1_FN, PB0_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PC7_FN, PC6_FN, PC5_FN, PC4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PC3_FN, PC2_FN, PC1_FN, PC0_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PD7_FN, PD6_FN, PD5_FN, PD4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PD3_FN, PD2_FN, PD1_FN, PD0_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PE7_FN, PE6_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PF7_FN, PF6_FN, PF5_FN, PF4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PF3_FN, PF2_FN, PF1_FN, PF0_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PG7_FN, PG6_FN, PG5_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PH7_FN, PH6_FN, PH5_FN, PH4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PH3_FN, PH2_FN, PH1_FN, PH0_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PJ7_FN, PJ6_FN, PJ5_FN, PJ4_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PJ3_FN, PJ2_FN, PJ1_FN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) P1MSEL14_0, P1MSEL14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) P1MSEL13_0, P1MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) P1MSEL12_0, P1MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) P1MSEL11_0, P1MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) P1MSEL10_0, P1MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) P1MSEL9_0, P1MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) P1MSEL8_0, P1MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) P1MSEL7_0, P1MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) P1MSEL6_0, P1MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) P1MSEL5_0, P1MSEL5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) P1MSEL4_0, P1MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) P1MSEL3_0, P1MSEL3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) P1MSEL2_0, P1MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) P1MSEL1_0, P1MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) P1MSEL0_0, P1MSEL0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) P2MSEL15_0, P2MSEL15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) P2MSEL14_0, P2MSEL14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) P2MSEL13_0, P2MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) P2MSEL12_0, P2MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) P2MSEL11_0, P2MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) P2MSEL10_0, P2MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) P2MSEL9_0, P2MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) P2MSEL8_0, P2MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) P2MSEL7_0, P2MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) P2MSEL6_0, P2MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) P2MSEL5_0, P2MSEL5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) P2MSEL4_0, P2MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) P2MSEL3_0, P2MSEL3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) P2MSEL2_0, P2MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) P2MSEL1_0, P2MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) P2MSEL0_0, P2MSEL0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DCLKIN_MARK, DCLKOUT_MARK, ODDF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) VSYNC_MARK, HSYNC_MARK, CDE_MARK, DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DR0_MARK, DR1_MARK, DR2_MARK, DR3_MARK, DR4_MARK, DR5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DG0_MARK, DG1_MARK, DG2_MARK, DG3_MARK, DG4_MARK, DG5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DB0_MARK, DB1_MARK, DB2_MARK, DB3_MARK, DB4_MARK, DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ETH_MAGIC_MARK, ETH_LINK_MARK, ETH_TX_ER_MARK, ETH_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ETH_MDIO_MARK, ETH_RX_CLK_MARK, ETH_MDC_MARK, ETH_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ETH_TX_CLK_MARK, ETH_CRS_MARK, ETH_RX_DV_MARK, ETH_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ETH_TXD3_MARK, ETH_TXD2_MARK, ETH_TXD1_MARK, ETH_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ETH_RXD3_MARK, ETH_RXD2_MARK, ETH_RXD1_MARK, ETH_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) HSPI_CLK_MARK, HSPI_CS_MARK, HSPI_RX_MARK, HSPI_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SCIF0_CTS_MARK, SCIF0_RTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SCIF0_SCK_MARK, SCIF0_RXD_MARK, SCIF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SCIF1_SCK_MARK, SCIF1_RXD_MARK, SCIF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SCIF3_SCK_MARK, SCIF3_RXD_MARK, SCIF3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) SCIF4_SCK_MARK, SCIF4_RXD_MARK, SCIF4_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) SCIF5_SCK_MARK, SCIF5_RXD_MARK, SCIF5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) BREQ_MARK, IOIS16_MARK, CE2B_MARK, CE2A_MARK, BACK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FALE_MARK, FRB_MARK, FSTATUS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FSE_MARK, FCLE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DACK0_MARK, DACK1_MARK, DACK2_MARK, DACK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DREQ0_MARK, DREQ1_MARK, DREQ2_MARK, DREQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DRAK0_MARK, DRAK1_MARK, DRAK2_MARK, DRAK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) USB_OVC1_MARK, USB_OVC0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) USB_PENC1_MARK, USB_PENC0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) HAC_RES_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) HAC1_SDOUT_MARK, HAC1_SDIN_MARK, HAC1_SYNC_MARK, HAC1_BITCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) HAC0_SDOUT_MARK, HAC0_SDIN_MARK, HAC0_SYNC_MARK, HAC0_BITCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) SSI0_SDATA_MARK, SSI0_SCK_MARK, SSI0_WS_MARK, SSI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SSI1_SDATA_MARK, SSI1_SCK_MARK, SSI1_WS_MARK, SSI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) SSI2_SDATA_MARK, SSI2_SCK_MARK, SSI2_WS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SSI3_SDATA_MARK, SSI3_SCK_MARK, SSI3_WS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SDIF1CMD_MARK, SDIF1CD_MARK, SDIF1WP_MARK, SDIF1CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SDIF1D3_MARK, SDIF1D2_MARK, SDIF1D1_MARK, SDIF1D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SDIF0CMD_MARK, SDIF0CD_MARK, SDIF0WP_MARK, SDIF0CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SDIF0D3_MARK, SDIF0D2_MARK, SDIF0D1_MARK, SDIF0D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) TCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IRL7_MARK, IRL6_MARK, IRL5_MARK, IRL4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* PA GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINMUX_DATA(PA6_DATA, PA6_IN, PA6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINMUX_DATA(PA5_DATA, PA5_IN, PA5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINMUX_DATA(PA4_DATA, PA4_IN, PA4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINMUX_DATA(PA3_DATA, PA3_IN, PA3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINMUX_DATA(PA2_DATA, PA2_IN, PA2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINMUX_DATA(PA1_DATA, PA1_IN, PA1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINMUX_DATA(PA0_DATA, PA0_IN, PA0_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* PB GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINMUX_DATA(PB7_DATA, PB7_IN, PB7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINMUX_DATA(PB6_DATA, PB6_IN, PB6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINMUX_DATA(PB5_DATA, PB5_IN, PB5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINMUX_DATA(PB4_DATA, PB4_IN, PB4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINMUX_DATA(PB3_DATA, PB3_IN, PB3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINMUX_DATA(PB2_DATA, PB2_IN, PB2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINMUX_DATA(PB1_DATA, PB1_IN, PB1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINMUX_DATA(PB0_DATA, PB0_IN, PB0_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* PC GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINMUX_DATA(PC7_DATA, PC7_IN, PC7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINMUX_DATA(PC6_DATA, PC6_IN, PC6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINMUX_DATA(PC5_DATA, PC5_IN, PC5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINMUX_DATA(PC4_DATA, PC4_IN, PC4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINMUX_DATA(PC3_DATA, PC3_IN, PC3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINMUX_DATA(PC2_DATA, PC2_IN, PC2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINMUX_DATA(PC1_DATA, PC1_IN, PC1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINMUX_DATA(PC0_DATA, PC0_IN, PC0_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* PD GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINMUX_DATA(PD7_DATA, PD7_IN, PD7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINMUX_DATA(PD6_DATA, PD6_IN, PD6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINMUX_DATA(PD5_DATA, PD5_IN, PD5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINMUX_DATA(PD4_DATA, PD4_IN, PD4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINMUX_DATA(PD3_DATA, PD3_IN, PD3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINMUX_DATA(PD2_DATA, PD2_IN, PD2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINMUX_DATA(PD1_DATA, PD1_IN, PD1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINMUX_DATA(PD0_DATA, PD0_IN, PD0_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* PE GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINMUX_DATA(PE7_DATA, PE7_IN, PE7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINMUX_DATA(PE6_DATA, PE6_IN, PE6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* PF GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINMUX_DATA(PF7_DATA, PF7_IN, PF7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINMUX_DATA(PF6_DATA, PF6_IN, PF6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINMUX_DATA(PF5_DATA, PF5_IN, PF5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINMUX_DATA(PF4_DATA, PF4_IN, PF4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINMUX_DATA(PF3_DATA, PF3_IN, PF3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINMUX_DATA(PF2_DATA, PF2_IN, PF2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINMUX_DATA(PF1_DATA, PF1_IN, PF1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINMUX_DATA(PF0_DATA, PF0_IN, PF0_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* PG GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINMUX_DATA(PG7_DATA, PG7_IN, PG7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINMUX_DATA(PG6_DATA, PG6_IN, PG6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINMUX_DATA(PG5_DATA, PG5_IN, PG5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* PH GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINMUX_DATA(PH7_DATA, PH7_IN, PH7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINMUX_DATA(PH6_DATA, PH6_IN, PH6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINMUX_DATA(PH5_DATA, PH5_IN, PH5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINMUX_DATA(PH4_DATA, PH4_IN, PH4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINMUX_DATA(PH3_DATA, PH3_IN, PH3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINMUX_DATA(PH2_DATA, PH2_IN, PH2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINMUX_DATA(PH1_DATA, PH1_IN, PH1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINMUX_DATA(PH0_DATA, PH0_IN, PH0_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* PJ GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINMUX_DATA(PJ7_DATA, PJ7_IN, PJ7_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINMUX_DATA(PJ6_DATA, PJ6_IN, PJ6_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINMUX_DATA(PJ5_DATA, PJ5_IN, PJ5_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINMUX_DATA(PJ4_DATA, PJ4_IN, PJ4_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINMUX_DATA(PJ3_DATA, PJ3_IN, PJ3_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINMUX_DATA(PJ2_DATA, PJ2_IN, PJ2_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINMUX_DATA(PJ1_DATA, PJ1_IN, PJ1_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* PA FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINMUX_DATA(CDE_MARK, P1MSEL2_0, PA7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINMUX_DATA(DISP_MARK, P1MSEL2_0, PA6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINMUX_DATA(DR5_MARK, P1MSEL2_0, PA5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINMUX_DATA(DR4_MARK, P1MSEL2_0, PA4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINMUX_DATA(DR3_MARK, P1MSEL2_0, PA3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINMUX_DATA(DR2_MARK, P1MSEL2_0, PA2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINMUX_DATA(DR1_MARK, P1MSEL2_0, PA1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINMUX_DATA(DR0_MARK, P1MSEL2_0, PA0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINMUX_DATA(ETH_MAGIC_MARK, P1MSEL2_1, PA7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINMUX_DATA(ETH_LINK_MARK, P1MSEL2_1, PA6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINMUX_DATA(ETH_TX_ER_MARK, P1MSEL2_1, PA5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINMUX_DATA(ETH_TX_EN_MARK, P1MSEL2_1, PA4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINMUX_DATA(ETH_TXD3_MARK, P1MSEL2_1, PA3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINMUX_DATA(ETH_TXD2_MARK, P1MSEL2_1, PA2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINMUX_DATA(ETH_TXD1_MARK, P1MSEL2_1, PA1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINMUX_DATA(ETH_TXD0_MARK, P1MSEL2_1, PA0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* PB FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINMUX_DATA(VSYNC_MARK, P1MSEL3_0, PB7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINMUX_DATA(ODDF_MARK, P1MSEL3_0, PB6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINMUX_DATA(DG5_MARK, P1MSEL2_0, PB5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINMUX_DATA(DG4_MARK, P1MSEL2_0, PB4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINMUX_DATA(DG3_MARK, P1MSEL2_0, PB3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINMUX_DATA(DG2_MARK, P1MSEL2_0, PB2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINMUX_DATA(DG1_MARK, P1MSEL2_0, PB1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINMUX_DATA(DG0_MARK, P1MSEL2_0, PB0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINMUX_DATA(HSPI_CLK_MARK, P1MSEL3_1, PB7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINMUX_DATA(HSPI_CS_MARK, P1MSEL3_1, PB6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINMUX_DATA(ETH_MDIO_MARK, P1MSEL2_1, PB5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINMUX_DATA(ETH_RX_CLK_MARK, P1MSEL2_1, PB4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINMUX_DATA(ETH_MDC_MARK, P1MSEL2_1, PB3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINMUX_DATA(ETH_COL_MARK, P1MSEL2_1, PB2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINMUX_DATA(ETH_TX_CLK_MARK, P1MSEL2_1, PB1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINMUX_DATA(ETH_CRS_MARK, P1MSEL2_1, PB0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* PC FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINMUX_DATA(DCLKIN_MARK, P1MSEL3_0, PC7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINMUX_DATA(HSYNC_MARK, P1MSEL3_0, PC6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINMUX_DATA(DB5_MARK, P1MSEL2_0, PC5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINMUX_DATA(DB4_MARK, P1MSEL2_0, PC4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINMUX_DATA(DB3_MARK, P1MSEL2_0, PC3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINMUX_DATA(DB2_MARK, P1MSEL2_0, PC2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINMUX_DATA(DB1_MARK, P1MSEL2_0, PC1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINMUX_DATA(DB0_MARK, P1MSEL2_0, PC0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINMUX_DATA(HSPI_RX_MARK, P1MSEL3_1, PC7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINMUX_DATA(HSPI_TX_MARK, P1MSEL3_1, PC6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINMUX_DATA(ETH_RXD3_MARK, P1MSEL2_1, PC5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINMUX_DATA(ETH_RXD2_MARK, P1MSEL2_1, PC4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINMUX_DATA(ETH_RXD1_MARK, P1MSEL2_1, PC3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINMUX_DATA(ETH_RXD0_MARK, P1MSEL2_1, PC2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINMUX_DATA(ETH_RX_DV_MARK, P1MSEL2_1, PC1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINMUX_DATA(ETH_RX_ER_MARK, P1MSEL2_1, PC0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* PD FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINMUX_DATA(DCLKOUT_MARK, PD7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINMUX_DATA(SCIF1_SCK_MARK, PD6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINMUX_DATA(SCIF1_RXD_MARK, PD5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINMUX_DATA(SCIF1_TXD_MARK, PD4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINMUX_DATA(DACK1_MARK, P1MSEL13_1, P1MSEL12_0, PD3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINMUX_DATA(BACK_MARK, P1MSEL13_0, P1MSEL12_1, PD3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINMUX_DATA(FALE_MARK, P1MSEL13_0, P1MSEL12_0, PD3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINMUX_DATA(DACK0_MARK, P1MSEL14_1, PD2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINMUX_DATA(FCLE_MARK, P1MSEL14_0, PD2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINMUX_DATA(DREQ1_MARK, P1MSEL10_0, P1MSEL9_1, PD1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINMUX_DATA(BREQ_MARK, P1MSEL10_1, P1MSEL9_0, PD1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINMUX_DATA(USB_OVC1_MARK, P1MSEL10_0, P1MSEL9_0, PD1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINMUX_DATA(DREQ0_MARK, P1MSEL11_1, PD0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINMUX_DATA(USB_OVC0_MARK, P1MSEL11_0, PD0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* PE FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINMUX_DATA(USB_PENC1_MARK, PE7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINMUX_DATA(USB_PENC0_MARK, PE6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* PF FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINMUX_DATA(HAC1_SDOUT_MARK, P2MSEL15_0, P2MSEL14_0, PF7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINMUX_DATA(HAC1_SDIN_MARK, P2MSEL15_0, P2MSEL14_0, PF6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINMUX_DATA(HAC1_SYNC_MARK, P2MSEL15_0, P2MSEL14_0, PF5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINMUX_DATA(HAC1_BITCLK_MARK, P2MSEL15_0, P2MSEL14_0, PF4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINMUX_DATA(HAC0_SDOUT_MARK, P2MSEL13_0, P2MSEL12_0, PF3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINMUX_DATA(HAC0_SDIN_MARK, P2MSEL13_0, P2MSEL12_0, PF2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINMUX_DATA(HAC0_SYNC_MARK, P2MSEL13_0, P2MSEL12_0, PF1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINMUX_DATA(HAC0_BITCLK_MARK, P2MSEL13_0, P2MSEL12_0, PF0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINMUX_DATA(SSI1_SDATA_MARK, P2MSEL15_0, P2MSEL14_1, PF7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINMUX_DATA(SSI1_SCK_MARK, P2MSEL15_0, P2MSEL14_1, PF6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINMUX_DATA(SSI1_WS_MARK, P2MSEL15_0, P2MSEL14_1, PF5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINMUX_DATA(SSI1_CLK_MARK, P2MSEL15_0, P2MSEL14_1, PF4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINMUX_DATA(SSI0_SDATA_MARK, P2MSEL13_0, P2MSEL12_1, PF3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINMUX_DATA(SSI0_SCK_MARK, P2MSEL13_0, P2MSEL12_1, PF2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINMUX_DATA(SSI0_WS_MARK, P2MSEL13_0, P2MSEL12_1, PF1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINMUX_DATA(SSI0_CLK_MARK, P2MSEL13_0, P2MSEL12_1, PF0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINMUX_DATA(SDIF1CMD_MARK, P2MSEL15_1, P2MSEL14_0, PF7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINMUX_DATA(SDIF1CD_MARK, P2MSEL15_1, P2MSEL14_0, PF6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINMUX_DATA(SDIF1WP_MARK, P2MSEL15_1, P2MSEL14_0, PF5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINMUX_DATA(SDIF1CLK_MARK, P2MSEL15_1, P2MSEL14_0, PF4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINMUX_DATA(SDIF1D3_MARK, P2MSEL13_1, P2MSEL12_0, PF3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINMUX_DATA(SDIF1D2_MARK, P2MSEL13_1, P2MSEL12_0, PF2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINMUX_DATA(SDIF1D1_MARK, P2MSEL13_1, P2MSEL12_0, PF1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINMUX_DATA(SDIF1D0_MARK, P2MSEL13_1, P2MSEL12_0, PF0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* PG FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINMUX_DATA(SCIF3_SCK_MARK, P1MSEL8_0, PG7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINMUX_DATA(SSI2_SDATA_MARK, P1MSEL8_1, PG7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINMUX_DATA(SCIF3_RXD_MARK, P1MSEL7_0, P1MSEL6_0, PG6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINMUX_DATA(SSI2_SCK_MARK, P1MSEL7_1, P1MSEL6_0, PG6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINMUX_DATA(TCLK_MARK, P1MSEL7_0, P1MSEL6_1, PG6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINMUX_DATA(SCIF3_TXD_MARK, P1MSEL5_0, P1MSEL4_0, PG5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINMUX_DATA(SSI2_WS_MARK, P1MSEL5_1, P1MSEL4_0, PG5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINMUX_DATA(HAC_RES_MARK, P1MSEL5_0, P1MSEL4_1, PG5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* PH FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINMUX_DATA(DACK3_MARK, P2MSEL4_0, PH7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINMUX_DATA(SDIF0CMD_MARK, P2MSEL4_1, PH7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINMUX_DATA(DACK2_MARK, P2MSEL4_0, PH6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINMUX_DATA(SDIF0CD_MARK, P2MSEL4_1, PH6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINMUX_DATA(DREQ3_MARK, P2MSEL4_0, PH5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINMUX_DATA(SDIF0WP_MARK, P2MSEL4_1, PH5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINMUX_DATA(DREQ2_MARK, P2MSEL3_0, P2MSEL2_1, PH4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINMUX_DATA(SDIF0CLK_MARK, P2MSEL3_1, P2MSEL2_0, PH4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINMUX_DATA(SCIF0_CTS_MARK, P2MSEL3_0, P2MSEL2_0, PH4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINMUX_DATA(SDIF0D3_MARK, P2MSEL1_1, P2MSEL0_0, PH3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINMUX_DATA(SCIF0_RTS_MARK, P2MSEL1_0, P2MSEL0_0, PH3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINMUX_DATA(IRL7_MARK, P2MSEL1_0, P2MSEL0_1, PH3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINMUX_DATA(SDIF0D2_MARK, P2MSEL1_1, P2MSEL0_0, PH2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINMUX_DATA(SCIF0_SCK_MARK, P2MSEL1_0, P2MSEL0_0, PH2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINMUX_DATA(IRL6_MARK, P2MSEL1_0, P2MSEL0_1, PH2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINMUX_DATA(SDIF0D1_MARK, P2MSEL1_1, P2MSEL0_0, PH1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINMUX_DATA(SCIF0_RXD_MARK, P2MSEL1_0, P2MSEL0_0, PH1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINMUX_DATA(IRL5_MARK, P2MSEL1_0, P2MSEL0_1, PH1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINMUX_DATA(SDIF0D0_MARK, P2MSEL1_1, P2MSEL0_0, PH0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINMUX_DATA(SCIF0_TXD_MARK, P2MSEL1_0, P2MSEL0_0, PH0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINMUX_DATA(IRL4_MARK, P2MSEL1_0, P2MSEL0_1, PH0_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* PJ FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINMUX_DATA(SCIF5_SCK_MARK, P2MSEL11_1, PJ7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINMUX_DATA(FRB_MARK, P2MSEL11_0, PJ7_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINMUX_DATA(SCIF5_RXD_MARK, P2MSEL10_0, PJ6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINMUX_DATA(IOIS16_MARK, P2MSEL10_1, PJ6_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINMUX_DATA(SCIF5_TXD_MARK, P2MSEL10_0, PJ5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINMUX_DATA(CE2B_MARK, P2MSEL10_1, PJ5_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINMUX_DATA(DRAK3_MARK, P2MSEL7_0, PJ4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINMUX_DATA(CE2A_MARK, P2MSEL7_1, PJ4_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINMUX_DATA(SCIF4_SCK_MARK, P2MSEL9_0, P2MSEL8_0, PJ3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINMUX_DATA(DRAK2_MARK, P2MSEL9_0, P2MSEL8_1, PJ3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINMUX_DATA(SSI3_WS_MARK, P2MSEL9_1, P2MSEL8_0, PJ3_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINMUX_DATA(SCIF4_RXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINMUX_DATA(DRAK1_MARK, P2MSEL6_0, P2MSEL5_1, PJ2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINMUX_DATA(FSTATUS_MARK, P2MSEL6_0, P2MSEL5_0, PJ2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINMUX_DATA(SSI3_SDATA_MARK, P2MSEL6_1, P2MSEL5_1, PJ2_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINMUX_DATA(SCIF4_TXD_MARK, P2MSEL6_1, P2MSEL5_0, PJ1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINMUX_DATA(DRAK0_MARK, P2MSEL6_0, P2MSEL5_1, PJ1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINMUX_DATA(FSE_MARK, P2MSEL6_0, P2MSEL5_0, PJ1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* PA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINMUX_GPIO(PA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINMUX_GPIO(PA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINMUX_GPIO(PA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINMUX_GPIO(PA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINMUX_GPIO(PA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINMUX_GPIO(PA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINMUX_GPIO(PA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINMUX_GPIO(PA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* PB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINMUX_GPIO(PB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINMUX_GPIO(PB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINMUX_GPIO(PB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINMUX_GPIO(PB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINMUX_GPIO(PB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINMUX_GPIO(PB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINMUX_GPIO(PB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINMUX_GPIO(PB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* PC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINMUX_GPIO(PC7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINMUX_GPIO(PC6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINMUX_GPIO(PC5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINMUX_GPIO(PC4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINMUX_GPIO(PC3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINMUX_GPIO(PC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINMUX_GPIO(PC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINMUX_GPIO(PC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* PD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINMUX_GPIO(PD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINMUX_GPIO(PD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINMUX_GPIO(PD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINMUX_GPIO(PD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINMUX_GPIO(PD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINMUX_GPIO(PD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINMUX_GPIO(PD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINMUX_GPIO(PD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* PE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINMUX_GPIO(PE7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINMUX_GPIO(PE6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINMUX_GPIO(PF7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINMUX_GPIO(PF6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINMUX_GPIO(PF5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINMUX_GPIO(PF4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINMUX_GPIO(PF3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINMUX_GPIO(PF2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINMUX_GPIO(PF1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINMUX_GPIO(PF0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* PG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINMUX_GPIO(PG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_GPIO(PG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINMUX_GPIO(PG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* PH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINMUX_GPIO(PH7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINMUX_GPIO(PH6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_GPIO(PH5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINMUX_GPIO(PH4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINMUX_GPIO(PH3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINMUX_GPIO(PH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINMUX_GPIO(PH1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINMUX_GPIO(PH0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* PJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINMUX_GPIO(PJ7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINMUX_GPIO(PJ6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINMUX_GPIO(PJ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_GPIO(PJ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_GPIO(PJ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINMUX_GPIO(PJ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINMUX_GPIO(PJ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct pinmux_func pinmux_func_gpios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) GPIO_FN(CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) GPIO_FN(ETH_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) GPIO_FN(DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) GPIO_FN(ETH_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) GPIO_FN(DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) GPIO_FN(ETH_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) GPIO_FN(DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) GPIO_FN(ETH_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) GPIO_FN(DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) GPIO_FN(ETH_TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) GPIO_FN(DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) GPIO_FN(ETH_TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) GPIO_FN(DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GPIO_FN(ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) GPIO_FN(DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) GPIO_FN(ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) GPIO_FN(VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GPIO_FN(HSPI_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GPIO_FN(ODDF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) GPIO_FN(HSPI_CS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) GPIO_FN(DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) GPIO_FN(ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) GPIO_FN(DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) GPIO_FN(ETH_RX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) GPIO_FN(DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) GPIO_FN(ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GPIO_FN(DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) GPIO_FN(ETH_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GPIO_FN(DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) GPIO_FN(ETH_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GPIO_FN(DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) GPIO_FN(ETH_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GPIO_FN(DCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) GPIO_FN(HSPI_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) GPIO_FN(HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) GPIO_FN(HSPI_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GPIO_FN(DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) GPIO_FN(ETH_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) GPIO_FN(DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) GPIO_FN(ETH_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) GPIO_FN(DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) GPIO_FN(ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) GPIO_FN(DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) GPIO_FN(ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) GPIO_FN(DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) GPIO_FN(ETH_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) GPIO_FN(DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) GPIO_FN(ETH_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) GPIO_FN(DCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) GPIO_FN(SCIF1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) GPIO_FN(SCIF1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) GPIO_FN(SCIF1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) GPIO_FN(DACK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GPIO_FN(BACK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) GPIO_FN(FALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) GPIO_FN(DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) GPIO_FN(FCLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GPIO_FN(DREQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GPIO_FN(BREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) GPIO_FN(USB_OVC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) GPIO_FN(DREQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) GPIO_FN(USB_OVC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) GPIO_FN(USB_PENC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) GPIO_FN(USB_PENC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GPIO_FN(HAC1_SDOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) GPIO_FN(SSI1_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) GPIO_FN(SDIF1CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) GPIO_FN(HAC1_SDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) GPIO_FN(SSI1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) GPIO_FN(SDIF1CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) GPIO_FN(HAC1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) GPIO_FN(SSI1_WS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) GPIO_FN(SDIF1WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GPIO_FN(HAC1_BITCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) GPIO_FN(SSI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) GPIO_FN(SDIF1CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) GPIO_FN(HAC0_SDOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GPIO_FN(SSI0_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GPIO_FN(SDIF1D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GPIO_FN(HAC0_SDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) GPIO_FN(SSI0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GPIO_FN(SDIF1D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GPIO_FN(HAC0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GPIO_FN(SSI0_WS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GPIO_FN(SDIF1D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GPIO_FN(HAC0_BITCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GPIO_FN(SSI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GPIO_FN(SDIF1D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GPIO_FN(SCIF3_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GPIO_FN(SSI2_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GPIO_FN(SCIF3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GPIO_FN(TCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GPIO_FN(SSI2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GPIO_FN(SCIF3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GPIO_FN(HAC_RES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GPIO_FN(SSI2_WS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GPIO_FN(DACK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GPIO_FN(SDIF0CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GPIO_FN(DACK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GPIO_FN(SDIF0CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GPIO_FN(DREQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GPIO_FN(SDIF0WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GPIO_FN(SCIF0_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GPIO_FN(DREQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GPIO_FN(SDIF0CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GPIO_FN(SCIF0_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GPIO_FN(IRL7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GPIO_FN(SDIF0D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GPIO_FN(SCIF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GPIO_FN(IRL6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GPIO_FN(SDIF0D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GPIO_FN(SCIF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GPIO_FN(IRL5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GPIO_FN(SDIF0D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GPIO_FN(SCIF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GPIO_FN(IRL4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GPIO_FN(SDIF0D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GPIO_FN(SCIF5_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GPIO_FN(FRB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) GPIO_FN(SCIF5_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) GPIO_FN(IOIS16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) GPIO_FN(SCIF5_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) GPIO_FN(CE2B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) GPIO_FN(DRAK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) GPIO_FN(CE2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) GPIO_FN(SCIF4_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) GPIO_FN(DRAK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) GPIO_FN(SSI3_WS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) GPIO_FN(SCIF4_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) GPIO_FN(DRAK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) GPIO_FN(SSI3_SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GPIO_FN(FSTATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) GPIO_FN(SCIF4_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) GPIO_FN(DRAK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) GPIO_FN(SSI3_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) GPIO_FN(FSE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PA7_FN, PA7_OUT, PA7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PA6_FN, PA6_OUT, PA6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PA5_FN, PA5_OUT, PA5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PA4_FN, PA4_OUT, PA4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PA3_FN, PA3_OUT, PA3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PA2_FN, PA2_OUT, PA2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PA1_FN, PA1_OUT, PA1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PA0_FN, PA0_OUT, PA0_IN, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { PINMUX_CFG_REG("PBCR", 0xffcc0002, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PB7_FN, PB7_OUT, PB7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PB6_FN, PB6_OUT, PB6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PB5_FN, PB5_OUT, PB5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PB4_FN, PB4_OUT, PB4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PB3_FN, PB3_OUT, PB3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PB2_FN, PB2_OUT, PB2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PB1_FN, PB1_OUT, PB1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PB0_FN, PB0_OUT, PB0_IN, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { PINMUX_CFG_REG("PCCR", 0xffcc0004, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PC7_FN, PC7_OUT, PC7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PC6_FN, PC6_OUT, PC6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PC5_FN, PC5_OUT, PC5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PC4_FN, PC4_OUT, PC4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PC3_FN, PC3_OUT, PC3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PC2_FN, PC2_OUT, PC2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PC1_FN, PC1_OUT, PC1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PC0_FN, PC0_OUT, PC0_IN, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { PINMUX_CFG_REG("PDCR", 0xffcc0006, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PD7_FN, PD7_OUT, PD7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PD6_FN, PD6_OUT, PD6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PD5_FN, PD5_OUT, PD5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PD4_FN, PD4_OUT, PD4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PD3_FN, PD3_OUT, PD3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PD2_FN, PD2_OUT, PD2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PD1_FN, PD1_OUT, PD1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PD0_FN, PD0_OUT, PD0_IN, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { PINMUX_CFG_REG("PECR", 0xffcc0008, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PE7_FN, PE7_OUT, PE7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PE6_FN, PE6_OUT, PE6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { PINMUX_CFG_REG("PFCR", 0xffcc000a, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PF7_FN, PF7_OUT, PF7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PF6_FN, PF6_OUT, PF6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PF5_FN, PF5_OUT, PF5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PF4_FN, PF4_OUT, PF4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PF3_FN, PF3_OUT, PF3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PF2_FN, PF2_OUT, PF2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PF1_FN, PF1_OUT, PF1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PF0_FN, PF0_OUT, PF0_IN, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { PINMUX_CFG_REG("PGCR", 0xffcc000c, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PG7_FN, PG7_OUT, PG7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PG6_FN, PG6_OUT, PG6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PG5_FN, PG5_OUT, PG5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { PINMUX_CFG_REG("PHCR", 0xffcc000e, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PH7_FN, PH7_OUT, PH7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PH6_FN, PH6_OUT, PH6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PH5_FN, PH5_OUT, PH5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PH4_FN, PH4_OUT, PH4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PH3_FN, PH3_OUT, PH3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PH2_FN, PH2_OUT, PH2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PH1_FN, PH1_OUT, PH1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PH0_FN, PH0_OUT, PH0_IN, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { PINMUX_CFG_REG("PJCR", 0xffcc0010, 16, 2, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PJ7_FN, PJ7_OUT, PJ7_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PJ6_FN, PJ6_OUT, PJ6_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PJ5_FN, PJ5_OUT, PJ5_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PJ4_FN, PJ4_OUT, PJ4_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PJ3_FN, PJ3_OUT, PJ3_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PJ2_FN, PJ2_OUT, PJ2_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PJ1_FN, PJ1_OUT, PJ1_IN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { PINMUX_CFG_REG("P1MSELR", 0xffcc0080, 16, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) P1MSEL14_0, P1MSEL14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) P1MSEL13_0, P1MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) P1MSEL12_0, P1MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) P1MSEL11_0, P1MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) P1MSEL10_0, P1MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) P1MSEL9_0, P1MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) P1MSEL8_0, P1MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) P1MSEL7_0, P1MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) P1MSEL6_0, P1MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) P1MSEL5_0, P1MSEL5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) P1MSEL4_0, P1MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) P1MSEL3_0, P1MSEL3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) P1MSEL2_0, P1MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) P1MSEL1_0, P1MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) P1MSEL0_0, P1MSEL0_1 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { PINMUX_CFG_REG("P2MSELR", 0xffcc0082, 16, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) P2MSEL15_0, P2MSEL15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) P2MSEL14_0, P2MSEL14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) P2MSEL13_0, P2MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) P2MSEL12_0, P2MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) P2MSEL11_0, P2MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) P2MSEL10_0, P2MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) P2MSEL9_0, P2MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) P2MSEL8_0, P2MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) P2MSEL7_0, P2MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) P2MSEL6_0, P2MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) P2MSEL5_0, P2MSEL5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) P2MSEL4_0, P2MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) P2MSEL3_0, P2MSEL3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) P2MSEL2_0, P2MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) P2MSEL1_0, P2MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) P2MSEL0_0, P2MSEL0_1 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct pinmux_data_reg pinmux_data_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { PINMUX_DATA_REG("PADR", 0xffcc0020, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) { PINMUX_DATA_REG("PBDR", 0xffcc0022, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PB7_DATA, PB6_DATA, PB5_DATA, PB4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PB3_DATA, PB2_DATA, PB1_DATA, PB0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) { PINMUX_DATA_REG("PCDR", 0xffcc0024, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PC7_DATA, PC6_DATA, PC5_DATA, PC4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PC3_DATA, PC2_DATA, PC1_DATA, PC0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) { PINMUX_DATA_REG("PDDR", 0xffcc0026, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PD7_DATA, PD6_DATA, PD5_DATA, PD4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PD3_DATA, PD2_DATA, PD1_DATA, PD0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) { PINMUX_DATA_REG("PEDR", 0xffcc0028, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PE7_DATA, PE6_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 0, 0, 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) { PINMUX_DATA_REG("PFDR", 0xffcc002a, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PF7_DATA, PF6_DATA, PF5_DATA, PF4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PF3_DATA, PF2_DATA, PF1_DATA, PF0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) { PINMUX_DATA_REG("PGDR", 0xffcc002c, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PG7_DATA, PG6_DATA, PG5_DATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) { PINMUX_DATA_REG("PHDR", 0xffcc002e, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PH7_DATA, PH6_DATA, PH5_DATA, PH4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PH3_DATA, PH2_DATA, PH1_DATA, PH0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) { PINMUX_DATA_REG("PJDR", 0xffcc0030, 8, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PJ7_DATA, PJ6_DATA, PJ5_DATA, PJ4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PJ3_DATA, PJ2_DATA, PJ1_DATA, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) const struct sh_pfc_soc_info sh7786_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .name = "sh7786_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .func_gpios = pinmux_func_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .data_regs = pinmux_data_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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