^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SH7734 processor support - PFC hardware block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <cpu/sh7734.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PORT_GP_32(0, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PORT_GP_32(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PORT_GP_32(2, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_GP_32(3, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_GP_32(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_GP_12(5, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #undef _GP_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define _GP_DATA(bank, pin, name, sfx, cfg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define _GP_INDT(bank, pin, name, sfx, cfg) name##_DATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINMUX_INPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINMUX_INPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINMUX_OUTPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINMUX_OUTPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_USB_OVC0, FN_IP11_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FN_IP10_22, FN_IP10_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FN_IP10_27_26, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FN_IP10_29_28, /* 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FN_A25, FN_TX2_D, FN_ST1_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_A24, FN_RX2_D, FN_ST1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FN_A20, FN_ST1_REQ, FN_LCD_FLM_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FN_D12, FN_FWE_A, FN_ET0_ETXD5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FN_ET0_ETXD3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FN_ET0_ETXD2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FN_ET0_ETXD1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FN_ET0_GTX_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FN_ET0_MAGIC_C, FN_ET0_ETXD6_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FN_ET0_LINK_C, FN_ET0_ETXD5_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FN_EX_WAIT0, FN_TCLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FN_CS1_A26, FN_QIO3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FN_D15, FN_SCK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FN_SCK2_A, FN_VI0_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FN_RTS1_B, FN_VI0_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FN_CTS1_B, FN_VI0_DATA7_VI0_G1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FN_REF125CK, FN_ADTRG, FN_RX5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FN_REF50CK, FN_CTS1_E, FN_HCTS0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FN_DU0_DB4, FN_HIFINT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FN_DU0_DB5, FN_HIFDREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FN_DU0_DB6, FN_HIFRDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FN_CAN_CLK_A, FN_RX4_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FN_CAN1_RX_A, FN_IRQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FN_SCL1, FN_SCIF_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FN_SDA1, FN_RX1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FN_SDA0, FN_HIFEBL_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FN_SDSELF, FN_RTS1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FN_TX0_A, FN_HSPI_TX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FN_PRESETOUT, FN_ST_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* MOD_SEL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) FN_SEL_VIN1_0, FN_SEL_VIN1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FN_SEL_HIF_0, FN_SEL_HIF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FN_SEL_RSPI_0, FN_SEL_RSPI_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FN_SEL_LCDC_0, FN_SEL_LCDC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FN_SEL_ET0_0, FN_SEL_ET0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FN_SEL_RMII_0, FN_SEL_RMII_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FN_SEL_TMU_0, FN_SEL_TMU_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FN_SEL_SSI1_0, FN_SEL_SSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FN_SEL_SSI0_0, FN_SEL_SSI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FN_SEL_MMC_0, FN_SEL_MMC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FN_SEL_INTC_0, FN_SEL_INTC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* MOD_SEL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FN_SEL_SCIF3_3, FN_SEL_SCIF3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FN_SEL_SCIF2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FN_SEL_SCIF1_3, FN_SEL_SCIF1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) WE0_MARK, WE1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) SCL0_MARK, PENC0_MARK, USB_OVC0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) IRQ2_B_MARK, IRQ3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) A25_MARK, TX2_D_MARK, ST1_D2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) A24_MARK, RX2_D_MARK, ST1_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ET0_ETXD3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ET0_ETXD2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FCLE_A_MARK, ET0_ETXD1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FCE_A_MARK, ET0_GTX_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FD7_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FD6_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FD4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) ET0_LINK_C_MARK, ET0_ETXD5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) EX_WAIT0_MARK, TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ET0_ETXD3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ET0_ETXD2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ET0_ETXD1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ET0_GTX_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) ET0_ETXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) CS1_A26_MARK, QIO3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) D15_MARK, SCK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) SCK2_A_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) RTS1_B_MARK, VI0_G2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ET0_MDC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) RMII0_MDC_A_MARK, ET0_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) RMII0_CRS_DV_A_MARK, ET0_CRS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) RMII0_RXD1_A_MARK, ET0_ERXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) REF125CK_MARK, ADTRG_MARK, RX5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) TCLKA_A_MARK, HIFD00_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) TCLKB_A_MARK, HIFD01_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) TIOC1A_A_MARK, HIFD08_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) HIFD09_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) HIFD10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) HIFD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) HIFD12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) HIFD13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) HIFD14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) HIFD15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) HIFCS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) HIFRS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) HIFWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DU0_DB4_MARK, HIFINT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DU0_DB5_MARK, HIFDREQ_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DU0_DB6_MARK, HIFRDY_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) LCD_DATA15_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) FALE_B_MARK, LCD_DON_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) LCD_CL1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) LCD_CL2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) LCD_FLM_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) LCD_VEPWC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) LCD_M_DISP_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) CAN_CLK_A_MARK, RX4_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) CAN1_RX_A_MARK, IRQ1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SCL1_MARK, SCIF_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SDA1_MARK, RX1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SDA0_MARK, HIFEBL_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SDSELF_MARK, RTS1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ET0_ERXD4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ET0_ERXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) TX0_A_MARK, HSPI_TX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) IETX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) IERX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ET0_TX_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PRESETOUT_MARK, ST_CLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_SINGLE(CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_SINGLE(BS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_SINGLE(CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_SINGLE(EX_CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_SINGLE(RD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_SINGLE(WE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_SINGLE(WE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_SINGLE(SCL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_SINGLE(PENC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_SINGLE(USB_OVC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_SINGLE(IRQ2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_SINGLE(IRQ3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_GPSR(IP0_1_0, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_IPSR_GPSR(IP0_3_2, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_IPSR_GPSR(IP0_5_4, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_GPSR(IP0_7_6, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR_GPSR(IP0_9_8, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_IPSR_GPSR(IP0_11_10, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_GPSR(IP0_13_12, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_IPSR_GPSR(IP0_15_14, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_GPSR(IP0_17_16, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_IPSR_GPSR(IP0_19_18, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_GPSR(IP0_21_20, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_IPSR_GPSR(IP0_23_22, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_GPSR(IP0_25_24, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_IPSR_GPSR(IP0_27_26, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_GPSR(IP0_29_28, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_GPSR(IP0_31_30, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_GPSR(IP1_1_0, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP1_3_2, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_IPSR_GPSR(IP1_5_4, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_GPSR(IP1_7_6, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_GPSR(IP1_9_8, A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_GPSR(IP1_11_10, A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_GPSR(IP1_13_12, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_IPSR_GPSR(IP1_15_14, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_GPSR(IP1_17_16, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP1_19_18, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_GPSR(IP1_22_20, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_GPSR(IP1_25_23, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_IPSR_GPSR(IP1_28_26, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_IPSR_GPSR(IP1_31_29, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_GPSR(IP2_2_0, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_IPSR_GPSR(IP2_4_3, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_IPSR_GPSR(IP2_7_5, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_GPSR(IP2_10_8, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_GPSR(IP2_13_11, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_GPSR(IP2_16_14, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_GPSR(IP2_19_17, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_IPSR_GPSR(IP2_22_20, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP2_24_23, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_IPSR_GPSR(IP2_27_25, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_GPSR(IP2_30_28, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_IPSR_GPSR(IP3_1_0, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* IPSE10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_IPSR_GPSR(IP11_0, SCL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINMUX_IPSR_GPSR(IP11_1, SDA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINMUX_IPSR_GPSR(IP11_2, SDA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINMUX_IPSR_GPSR(IP11_3, SDSELF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const struct pinmux_func pinmux_func_gpios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) GPIO_FN(TCLKA_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) GPIO_FN(TCLKB_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) GPIO_FN(TCLKC_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) GPIO_FN(TCLKD_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) GPIO_FN(TIOC0A_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) GPIO_FN(TIOC0B_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) GPIO_FN(TIOC0C_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) GPIO_FN(TIOC0D_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) GPIO_FN(TIOC1A_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) GPIO_FN(TIOC1B_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) GPIO_FN(TIOC2A_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) GPIO_FN(TIOC2B_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) GPIO_FN(TIOC3D_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) GPIO_FN(TIOC4A_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) GPIO_FN(TIOC4B_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) GPIO_FN(TIOC4C_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) GPIO_FN(TIOC4D_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) GPIO_FN(ST1_D3), GPIO_FN(FD0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) GPIO_FN(ST1_D4), GPIO_FN(FD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) GPIO_FN(ST1_D5), GPIO_FN(FD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) GPIO_FN(ST1_D6), GPIO_FN(FD3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) GPIO_FN(FD4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) GPIO_FN(QSPCLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) GPIO_FN(FD6_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) GPIO_FN(FD7_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) GPIO_FN(ET0_ETXD3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) GPIO_FN(D15), GPIO_FN(SCK2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) GPIO_FN(CS1_A26), GPIO_FN(QIO3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) GPIO_FN(ET0_ETXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) GPIO_FN(ET0_GTX_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) GPIO_FN(ET0_ETXD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) GPIO_FN(ET0_ETXD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) GPIO_FN(ET0_ETXD3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) GPIO_FN(RD_WR), GPIO_FN(TCLK0), GPIO_FN(CAN_CLK_B), GPIO_FN(ET0_ETXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) GPIO_FN(ET0_ETXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) GPIO_FN(ET0_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) GPIO_FN(RTS1_B), GPIO_FN(VI0_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) GPIO_FN(SCK2_A), GPIO_FN(VI0_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) GPIO_FN(ET0_PHY_INT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) GPIO_FN(ET0_MAGIC_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) GPIO_FN(ET0_LINK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) GPIO_FN(ET0_MDIO_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) GPIO_FN(ET0_ERXD3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) GPIO_FN(ET0_ERXD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) GPIO_FN(ET0_RX_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) GPIO_FN(HIFD07),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) GPIO_FN(HIFD06),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) GPIO_FN(HIFD05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) GPIO_FN(HIFD04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) GPIO_FN(DU0_DB4), GPIO_FN(HIFINT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) GPIO_FN(ET0_ERXD3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) GPIO_FN(ET0_ERXD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) GPIO_FN(ET0_ERXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) GPIO_FN(ET0_ERXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) GPIO_FN(LCD_VCPWC_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) GPIO_FN(AUDIO_CLKA_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) GPIO_FN(SSI_SDATA1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) GPIO_FN(SSI_WS1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) GPIO_FN(SSI_SCK1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) GPIO_FN(SSI_SDATA0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) GPIO_FN(SSI_WS0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) GPIO_FN(LCD_DATA12_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) GPIO_FN(LCD_DATA11_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) GPIO_FN(ET0_RX_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) GPIO_FN(RX5_D), GPIO_FN(IERX_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) GPIO_FN(TX5_D), GPIO_FN(IETX_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) GPIO_FN(ET0_ERXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) GPIO_FN(SDSELF), GPIO_FN(RTS1_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) GPIO_FN(SDA0), GPIO_FN(HIFEBL_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) GPIO_FN(SDA1), GPIO_FN(RX1_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) GP_0_31_FN, FN_IP2_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) GP_0_30_FN, FN_IP1_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) GP_0_29_FN, FN_IP1_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) GP_0_28_FN, FN_IP1_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) GP_0_27_FN, FN_IP1_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) GP_0_26_FN, FN_IP1_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) GP_0_25_FN, FN_IP1_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) GP_0_24_FN, FN_IP0_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) GP_0_23_FN, FN_IP0_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) GP_0_22_FN, FN_IP0_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) GP_0_21_FN, FN_IP11_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) GP_0_20_FN, FN_IP1_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) GP_0_19_FN, FN_IP1_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) GP_0_18_FN, FN_IP1_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) GP_0_17_FN, FN_IP1_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) GP_0_16_FN, FN_IP0_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) GP_0_15_FN, FN_IP0_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) GP_0_14_FN, FN_IP0_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) GP_0_13_FN, FN_IP0_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) GP_0_12_FN, FN_IP0_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) GP_0_11_FN, FN_IP0_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) GP_0_10_FN, FN_IP0_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) GP_0_9_FN, FN_IP0_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) GP_0_8_FN, FN_IP0_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) GP_0_7_FN, FN_IP0_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) GP_0_6_FN, FN_IP0_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) GP_0_5_FN, FN_IP0_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) GP_0_4_FN, FN_IP0_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) GP_0_3_FN, FN_IP1_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) GP_0_2_FN, FN_IP1_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) GP_0_1_FN, FN_IP1_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) GP_0_0_FN, FN_IP1_9_8 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) GP_1_31_FN, FN_IP11_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) GP_1_30_FN, FN_IP2_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) GP_1_29_FN, FN_IP2_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) GP_1_28_FN, FN_IP2_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) GP_1_27_FN, FN_IP3_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) GP_1_26_FN, FN_IP3_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) GP_1_25_FN, FN_IP2_4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) GP_1_24_FN, FN_WE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) GP_1_23_FN, FN_WE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) GP_1_22_FN, FN_IP3_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) GP_1_21_FN, FN_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) GP_1_20_FN, FN_IP3_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) GP_1_19_FN, FN_IP3_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) GP_1_18_FN, FN_IP3_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) GP_1_17_FN, FN_IP3_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) GP_1_16_FN, FN_IP3_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) GP_1_15_FN, FN_EX_CS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) GP_1_14_FN, FN_IP3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) GP_1_13_FN, FN_CS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) GP_1_12_FN, FN_BS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) GP_1_11_FN, FN_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) GP_1_10_FN, FN_IP3_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) GP_1_9_FN, FN_IP2_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) GP_1_8_FN, FN_IP2_27_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) GP_1_7_FN, FN_IP2_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) GP_1_6_FN, FN_IP2_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) GP_1_5_FN, FN_IP2_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) GP_1_4_FN, FN_IP2_16_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) GP_1_3_FN, FN_IP11_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) GP_1_2_FN, FN_IP11_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) GP_1_1_FN, FN_IP3_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) GP_1_0_FN, FN_IP3_20 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) GP_2_31_FN, FN_IP4_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) GP_2_30_FN, FN_IP5_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) GP_2_29_FN, FN_IP5_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) GP_2_28_FN, FN_IP5_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) GP_2_27_FN, FN_IP5_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) GP_2_26_FN, FN_IP5_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) GP_2_25_FN, FN_IP5_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) GP_2_24_FN, FN_IP5_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) GP_2_23_FN, FN_IP5_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) GP_2_22_FN, FN_IP5_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) GP_2_21_FN, FN_IP5_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) GP_2_20_FN, FN_IP4_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) GP_2_19_FN, FN_IP4_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) GP_2_18_FN, FN_IP4_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) GP_2_17_FN, FN_IP4_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) GP_2_16_FN, FN_IP4_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) GP_2_15_FN, FN_IP4_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) GP_2_14_FN, FN_IP4_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) GP_2_13_FN, FN_IP4_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) GP_2_12_FN, FN_IP4_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) GP_2_11_FN, FN_IP4_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) GP_2_10_FN, FN_IP4_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) GP_2_9_FN, FN_IP8_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) GP_2_8_FN, FN_IP11_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) GP_2_7_FN, FN_IP8_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) GP_2_6_FN, FN_IP8_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) GP_2_5_FN, FN_IP11_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) GP_2_4_FN, FN_IP8_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) GP_2_3_FN, FN_IP4_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) GP_2_2_FN, FN_IP11_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) GP_2_1_FN, FN_IP11_9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) GP_2_0_FN, FN_IP11_6_4 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) GP_3_31_FN, FN_IP9_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) GP_3_30_FN, FN_IP8_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) GP_3_29_FN, FN_IP8_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) GP_3_28_FN, FN_IP8_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) GP_3_27_FN, FN_IP8_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) GP_3_26_FN, FN_IP8_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) GP_3_25_FN, FN_IP8_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) GP_3_24_FN, FN_IP8_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) GP_3_23_FN, FN_IP8_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) GP_3_22_FN, FN_IP8_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) GP_3_21_FN, FN_IP8_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) GP_3_20_FN, FN_IP7_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) GP_3_19_FN, FN_IP7_28_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) GP_3_18_FN, FN_IP7_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) GP_3_17_FN, FN_IP7_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) GP_3_16_FN, FN_IP7_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) GP_3_15_FN, FN_IP7_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) GP_3_14_FN, FN_IP7_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) GP_3_13_FN, FN_IP7_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) GP_3_12_FN, FN_IP7_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) GP_3_11_FN, FN_IP7_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) GP_3_10_FN, FN_IP7_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) GP_3_9_FN, FN_IP6_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) GP_3_8_FN, FN_IP6_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) GP_3_7_FN, FN_IP6_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) GP_3_6_FN, FN_IP6_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) GP_3_5_FN, FN_IP6_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) GP_3_4_FN, FN_IP6_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) GP_3_3_FN, FN_IP6_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) GP_3_2_FN, FN_IP6_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) GP_3_1_FN, FN_IP6_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) GP_3_0_FN, FN_IP6_2_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) GP_4_31_FN, FN_IP10_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) GP_4_30_FN, FN_IP10_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) GP_4_29_FN, FN_IP11_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) GP_4_28_FN, FN_USB_OVC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) GP_4_27_FN, FN_IP11_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) GP_4_26_FN, FN_PENC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) GP_4_25_FN, FN_IP11_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) GP_4_24_FN, FN_SCL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) GP_4_23_FN, FN_IP11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) GP_4_22_FN, FN_IP11_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) GP_4_21_FN, FN_IP10_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) GP_4_20_FN, FN_IP10_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) GP_4_19_FN, FN_IP10_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) GP_4_18_FN, FN_IP10_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) GP_4_17_FN, FN_IP10_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) GP_4_16_FN, FN_IP10_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) GP_4_15_FN, FN_IP10_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) GP_4_14_FN, FN_IP10_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) GP_4_13_FN, FN_IP9_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) GP_4_12_FN, FN_IP9_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) GP_4_11_FN, FN_IP9_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) GP_4_10_FN, FN_IP9_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) GP_4_9_FN, FN_IP9_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) GP_4_8_FN, FN_IP9_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) GP_4_7_FN, FN_IP9_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) GP_4_6_FN, FN_IP9_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) GP_4_5_FN, FN_IP9_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) GP_4_4_FN, FN_IP9_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) GP_4_3_FN, FN_IP9_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) GP_4_2_FN, FN_IP9_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) GP_4_1_FN, FN_IP9_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) GP_4_0_FN, FN_IP9_19_18 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) GP_5_11_FN, FN_IP10_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) GP_5_10_FN, FN_IP10_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) 0, 0, 0, 0, /* 5, 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) GP_5_3_FN, FN_IRQ3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) GP_5_2_FN, FN_IRQ2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) GP_5_1_FN, FN_IP11_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) GP_5_0_FN, FN_IP10_25 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* IP0_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) FN_TIOC3D_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* IP0_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* IP0_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* IP0_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) /* IP0_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) /* IP0_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) /* IP0_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* IP0_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* IP0_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* IP0_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* IP0_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* IP0_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* IP0_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* IP0_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* IP0_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* IP0_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) GROUP(3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* IP1_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) FN_FD3_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* IP1_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) FN_FD2_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* IP1_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) FN_FD1_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* IP1_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) FN_FD0_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* IP1_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) FN_A25, FN_TX2_D, FN_ST1_D2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* IP1_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) FN_A24, FN_RX2_D, FN_ST1_D1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* IP1_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* IP1_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* IP1_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* IP1_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) /* IP1_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* IP1_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* IP1_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* IP1_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) /* IP2_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* IP2_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) FN_D14, FN_TX2_B, 0, FN_FSE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) FN_ET0_TX_CLK_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* IP2_27_25 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) FN_D13, FN_RX2_B, 0, FN_FRB_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) FN_ET0_ETXD6_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* IP2_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* IP2_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) FN_FRE_A, FN_ET0_ETXD3_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* IP2_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) FN_FALE_A, FN_ET0_ETXD2_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* IP2_16_14 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) /* IP2_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* IP2_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) FN_FD7_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* IP2_7_5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) FN_FD6_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* IP2_4_3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* IP2_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) FN_FD4_A, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) GROUP(2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* IP3_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* IP3_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) FN_ET0_ETXD7, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* IP3_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* IP3_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) /* IP3_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) FN_EX_WAIT0, FN_TCLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* IP3_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /* IP3_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) FN_ET0_ETXD3_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* IP3_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) FN_ET0_ETXD2_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* IP3_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) FN_ET0_ETXD1_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* IP3_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) FN_ET0_GTX_CLK_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* IP3_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) FN_ET0_ETXD0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* IP3_2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) FN_CS1_A26, FN_QIO3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* IP3_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) FN_D15, FN_SCK2_B, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) GROUP(2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) /* IP4_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) 0, FN_SCK2_A, FN_VI0_G3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* IP4_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) 0, FN_RTS1_B, FN_VI0_G2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* IP4_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) /* IP4_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* IP4_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* IP4_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* IP4_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) /* IP4_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) FN_ET0_MDC, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* IP4_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) FN_ET0_COL, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) /* IP4_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) FN_ET0_CRS, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* IP4_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) FN_ET0_RX_ER, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* IP4_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) FN_ET0_RX_DV, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* IP4_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) FN_ET0_ERXD7, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) GROUP(1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* IP5_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* IP5_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* IP5_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* IP5_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* IP5_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* IP5_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* IP5_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) FN_REF125CK, FN_ADTRG, FN_RX5_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) /* IP5_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) /* IP5_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) 0, 0, 0, FN_ET0_PHY_INT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* IP5_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) 0, 0, 0, FN_ET0_MAGIC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) /* IP5_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) 0, 0, 0, FN_ET0_LINK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* IP5_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) 0, 0, 0, FN_ET0_MDIO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) /* IP5_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) 0, 0, 0, FN_ET0_ERXD3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* IP5_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) 0, 0, 0, FN_ET0_ERXD2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /* IP5_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) FN_ET0_RX_CLK_B, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 3, 3, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) 2, 2, 2, 2, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* IP5_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* IP6_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* IP6_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /* IP6_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* IP6_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* IP6_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* IP6_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* IP6_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* IP6_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) FN_HIFD09, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /* IP6_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) FN_TIOC1A_A, FN_HIFD08, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* IP6_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* IP6_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) /* IP6_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /* IP6_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* IP6_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /* IP6_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /* IP6_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) FN_TCLKB_A, FN_HIFD01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /* IP6_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) FN_TCLKA_A, FN_HIFD00, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) GROUP(1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* IP7_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /* IP7_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) FN_DU0_DB4, 0, FN_HIFINT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* IP7_28_27 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) /* IP7_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) FN_HIFWR, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* IP7_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) FN_HIFRS, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) /* IP7_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) FN_HIFCS, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /* IP7_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) FN_HIFD15, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /* IP7_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) FN_HIFD14, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /* IP7_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) FN_HIFD13, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /* IP7_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) FN_HIFD12, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* IP7_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) FN_HIFD11, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /* IP7_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) FN_HIFD10, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) /* IP9_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) /* IP8_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /* IP8_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* IP8_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) FN_ET0_ERXD1, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) /* IP8_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) FN_ET0_ERXD0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* IP8_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* IP8_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /* IP8_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) FN_SSI_SDATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* IP8_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /* IP8_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* IP8_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* IP8_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* IP8_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) /* IP8_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) FN_DU0_DB6, 0, FN_HIFRDY, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) /* IP8_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) FN_DU0_DB5, 0, FN_HIFDREQ, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* IP9_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* IP9_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /* IP9_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* IP9_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* IP9_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* IP9_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) /* IP9_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) /* IP9_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /* IP9_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) /* IP9_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) /* IP9_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) /* IP9_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* IP9_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* IP9_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) /* IP9_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* IP9_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) GROUP(2, 2, 2, 1, 2, 1, 3, 3, 1, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) /* IP9_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* IP10_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) /* IP10_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* IP10_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) FN_CAN1_RX_A, FN_IRQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /* IP10_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /* IP10_22 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) FN_CAN_CLK_A, FN_RX4_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) /* IP10_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) FN_AUDIO_CLKOUT, FN_TX1_E, 0, FN_HRTS0_C, FN_FSE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) FN_LCD_M_DISP_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* IP10_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) FN_AUDIO_CLKC, FN_SCK1_E, 0, FN_HCTS0_C, FN_FRB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) FN_LCD_VEPWC_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /* IP10_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) FN_AUDIO_CLKB_A, FN_LCD_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) /* IP10_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) FN_LCD_FLM_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* IP10_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) FN_SSI_SDATA3, FN_VI1_7_B, 0, FN_HTX0_C, FN_FWE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) FN_LCD_CL2_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* IP10_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) FN_SSI_SDATA2, FN_VI1_6_B, 0, FN_HRX0_C, FN_FRE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) FN_LCD_CL1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) /* IP10_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) FN_LCD_DON_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* IP10_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) FN_LCD_DATA15_B, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) GROUP(3, 1, 2, 3, 2, 2, 3, 3, 1, 2, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* IP11_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) /* IP11_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) FN_PRESETOUT, FN_ST_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) /* IP11_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) /* IP11_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) FN_ET0_TX_CLK_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /* IP11_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /* IP11_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) /* IP11_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) FN_IERX_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* IP11_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) FN_IETX_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) /* IP11_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) FN_TX0_A, FN_HSPI_TX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) /* IP11_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) /* IP11_9_7 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) FN_ET0_ERXD5, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) /* IP11_6_4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) FN_ET0_ERXD4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) /* IP11_3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) FN_SDSELF, FN_RTS1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) /* IP11_2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) FN_SDA0, FN_HIFEBL_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) /* IP11_1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) FN_SDA1, FN_RX1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) /* IP11_0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) FN_SCL1, FN_SCIF_CLK_C ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) GROUP(3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /* SEL1_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* SEL1_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) FN_SEL_IEBUS_0, FN_SEL_IEBUS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* SEL1_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) FN_SEL_RQSPI_0, FN_SEL_RQSPI_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) /* SEL1_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) FN_SEL_VIN1_0, FN_SEL_VIN1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) /* SEL1_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) FN_SEL_HIF_0, FN_SEL_HIF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* SEL1_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) FN_SEL_RSPI_0, FN_SEL_RSPI_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) /* SEL1_23 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) FN_SEL_LCDC_0, FN_SEL_LCDC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) /* SEL1_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* SEL1_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) FN_SEL_ET0_0, FN_SEL_ET0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /* SEL1_19 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) FN_SEL_RMII_0, FN_SEL_RMII_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* SEL1_18 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) FN_SEL_TMU_0, FN_SEL_TMU_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) /* SEL1_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* SEL1_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) /* SEL1_13 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) /* SEL1_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* SEL1_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) FN_SEL_RCAN0_0, FN_SEL_RCAN0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* SEL1_9 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) FN_SEL_SDHI2_0, FN_SEL_SDHI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) /* SEL1_8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) FN_SEL_SDHI1_0, FN_SEL_SDHI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) /* SEL1_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) FN_SEL_SDHI0_0, FN_SEL_SDHI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* SEL1_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) FN_SEL_SSI1_0, FN_SEL_SSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* SEL1_5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) FN_SEL_SSI0_0, FN_SEL_SSI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) /* SEL1_4 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /* SEL1_3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* SEL1_2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) FN_SEL_FLCTL_0, FN_SEL_FLCTL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /* SEL1_1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) FN_SEL_MMC_0, FN_SEL_MMC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) /* SEL1_0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) FN_SEL_INTC_0, FN_SEL_INTC_1 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) 2, 1, 2, 2, 3, 2, 3, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /* SEL2_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* SEL2_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* SEL2_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) /* SEL2_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /* SEL2_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /* SEL2_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* SEL2_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) /* SEL2_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) /* SEL2_23 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) /* SEL2_22 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* SEL2_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* SEL2_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) /* SEL2_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* SEL2_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) /* SEL2_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* SEL2_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) /* SEL2_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) FN_SEL_SCIF3_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /* SEL2_8_7 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /* SEL2_6_4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) FN_SEL_SCIF1_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /* SEL2_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) /* SEL2_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) /* GPIO 0 - 5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1, GROUP(GP_INOUTSEL(0)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1, GROUP(GP_INOUTSEL(1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1, GROUP(GP_INOUTSEL(2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1, GROUP(GP_INOUTSEL(3)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1, GROUP(GP_INOUTSEL(4)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) GP_5_11_IN, GP_5_11_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) GP_5_10_IN, GP_5_10_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) GP_5_9_IN, GP_5_9_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) GP_5_8_IN, GP_5_8_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) GP_5_7_IN, GP_5_7_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) GP_5_6_IN, GP_5_6_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) GP_5_5_IN, GP_5_5_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) GP_5_4_IN, GP_5_4_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) GP_5_3_IN, GP_5_3_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) GP_5_2_IN, GP_5_2_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) GP_5_1_IN, GP_5_1_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) GP_5_0_IN, GP_5_0_OUT ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static const struct pinmux_data_reg pinmux_data_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) /* GPIO 0 - 5*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32, GROUP(GP_INDT(0))) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32, GROUP(GP_INDT(1))) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32, GROUP(GP_INDT(2))) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32, GROUP(GP_INDT(3))) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32, GROUP(GP_INDT(4))) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) const struct sh_pfc_soc_info sh7734_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) .name = "sh7734_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) .unlock_reg = 0xFFFC0000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .func_gpios = pinmux_func_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .data_regs = pinmux_data_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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