^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sh73a0 processor support - PFC hardware block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2010 NISHIMOTO Hiroki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPU_ALL_PORT(fn, pfx, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_10(100, fn, pfx##10, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_1(118, fn, pfx##118, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_10(150, fn, pfx##15, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PORT_1(164, fn, pfx##164, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PORT_1(282, fn, pfx##282, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CPU_ALL_NOGP(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PIN_NOGP(A11, "F26", fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINMUX_INPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINMUX_INPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINMUX_OUTPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINMUX_OUTPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Hardware manual Table 25-1 (Function 0-7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) VBUS_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GPI0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) GPI1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GPI2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GPI3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GPI4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GPI5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GPI6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GPI7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) SCIFA7_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) SCIFA7_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GPO7_MARK, MFG0_OUT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GPO6_MARK, MFG1_OUT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) SCIFA7_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GPO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) GPO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) GPO2_MARK, STATUS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) GPO3_MARK, STATUS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) GPO4_MARK, STATUS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) VINT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) TCKON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MFG0_OUT1_MARK, PORT27_IROUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PORT28_TPU1TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) SIM_RST_MARK, PORT29_TPU1TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) SIM_D_MARK, PORT31_IROUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) SCIFA4_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) SCIFA4_RXD_MARK, XWUP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) SCIFA4_RTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) SCIFA4_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FSIBOBT_MARK, FSIBIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FSIBOLR_MARK, FSIBILR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FSIBOSLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FSIBISLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) VACK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) XTAL1L_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) SCIFA0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FSICISLD_MARK, FSIDISLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FSIAOSLD_MARK, BBIF2_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PORT53_FSICSPDIF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FSICCK_MARK, FSICOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FSIAISLD_MARK, TPU0TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) A0_MARK, BS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) A14_MARK, KEYOUT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) A15_MARK, KEYOUT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) A26_MARK, KEYIN6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) KEYIN7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) D0_NAF0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) D1_NAF1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) D2_NAF2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) D3_NAF3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) D4_NAF4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) D5_NAF5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) D6_NAF6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) D7_NAF7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) D8_NAF8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) D9_NAF9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) D10_NAF10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) D11_NAF11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) D12_NAF12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) D13_NAF13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) D14_NAF14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) D15_NAF15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) CS4__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) CS5A__MARK, PORT91_RDWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) CS5B__MARK, FCE1__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) CS6B__MARK, DACK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FCE0__MARK, CS6A__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) WAIT__MARK, DREQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) RD__FSC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) WE0__FWE_MARK, RDWR_FWE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) WE1__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FRB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CKO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) NBRSTOUT__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) NBRST__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) BBIF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) BBIF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) BBIF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) BBIF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) SCIFA3_CTS__MARK, MFG3_IN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SCIFA3_RXD_MARK, MFG3_IN1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) SCIFA3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) HSI_TX_READY_MARK, BBIF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PORT115_I2C_SCL3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PORT116_I2C_SDA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) HSI_TX_FLAG_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) VIO2_HD_MARK, LCD2D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PORT131_KEYOUT11_MARK, LCD2D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PORT132_KEYOUT10_MARK, LCD2D12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) VIO2_D5_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LCD2D18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) VIO_CKO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MFG0_IN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) LCDD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) LCDD6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) LCDD8_MARK, D16_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) LCDD9_MARK, D17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) LCDD10_MARK, D18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) LCDD11_MARK, D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) LCDD12_MARK, D20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) LCDD13_MARK, D21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) LCDD14_MARK, D22_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) LCDD17_MARK, D25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) LCDDCK_MARK, LCDWR__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PORT218_VIO_CKOR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) LCDVSYN_MARK, LCDVSYN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) SCIFA1_TXD_MARK, OVCN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) SCIFA1_RTS__MARK, IDIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) SCIFA1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) SCIFA1_CTS__MARK, MFG1_IN1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SCIFA6_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MSIOF2R_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MSIOF2R_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) TPU1TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) TPU3TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MSIOF2R_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SDHICLK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SDHICD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) SDHID0_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) SDHID0_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SDHID0_2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SDHID0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) SDHICMD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SDHIWP0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SDHICLK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) SDHID1_0_MARK, TS_SPSYNC2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SDHID1_1_MARK, TS_SDAT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SDHID1_2_MARK, TS_SDEN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) SDHID1_3_MARK, TS_SCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) SDHICMD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) SDHICLK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) SDHID2_0_MARK, TS_SPSYNC4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) SDHID2_1_MARK, TS_SDAT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SDHID2_2_MARK, TS_SDEN4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SDHID2_3_MARK, TS_SCK4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SDHICMD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MMCCLK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MMCD0_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MMCD0_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MMCD0_2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MMCD0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MMCD0_4_MARK, TS_SPSYNC5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MMCD0_5_MARK, TS_SDAT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MMCD0_6_MARK, TS_SDEN5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MMCD0_7_MARK, TS_SCK5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) MMCCMD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) RESETOUTS__MARK, EXTAL2OUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MCP_WAIT__MCP_FRB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MCP_CKO_MARK, MMCCLK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MCP_D15_MCP_NAF15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) MCP_D14_MCP_NAF14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MCP_D13_MCP_NAF13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MCP_D12_MCP_NAF12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MCP_D11_MCP_NAF11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MCP_D10_MCP_NAF10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MCP_D9_MCP_NAF9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MCP_NBRSTOUT__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* MSEL2 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) TSIF2_TS_XX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) TSIF2_TS_XX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) TSIF2_TS_XX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) TSIF2_TS_XX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) TSIF2_TS_XX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) TSIF1_TS_XX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) TSIF1_TS_XX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) TSIF1_TS_XX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) TSIF1_TS_XX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) TSIF1_TS_XX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) TSIF0_TS_XX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) TSIF0_TS_XX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) TSIF0_TS_XX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) TSIF0_TS_XX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) TSIF0_TS_XX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MST1_TS_XX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MST1_TS_XX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MST1_TS_XX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MST1_TS_XX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MST1_TS_XX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MST0_TS_XX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MST0_TS_XX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MST0_TS_XX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MST0_TS_XX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MST0_TS_XX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* MSEL3 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) SDHI0_VCCQ_MC0_ON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) SDHI0_VCCQ_MC0_OFF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DEBUG_MON_VIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DEBUG_MON_LCDD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) LCDC_LCDC0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) LCDC_LCDC1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* MSEL4 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) IRQ9_MEM_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) IRQ9_MCP_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) A11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) KEYOUT8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) TPU4TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RESETA_N_PU_ON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) RESETA_N_PU_OFF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) EDBGREQ_PD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) EDBGREQ_PU_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* specify valid pin states for each pin in GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINMUX_DATA_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Table 25-1 (Function 0-7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINMUX_DATA(GPI0_MARK, PORT1_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_DATA(GPI1_MARK, PORT2_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINMUX_DATA(GPI2_MARK, PORT3_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINMUX_DATA(GPI3_MARK, PORT4_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINMUX_DATA(GPI4_MARK, PORT5_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINMUX_DATA(GPI5_MARK, PORT6_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINMUX_DATA(GPI6_MARK, PORT7_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_DATA(GPI7_MARK, PORT8_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINMUX_DATA(GPO0_MARK, PORT20_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINMUX_DATA(GPO1_MARK, PORT21_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINMUX_DATA(VINT_MARK, PORT25_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINMUX_DATA(TCKON_MARK, PORT26_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MSEL2CR_MSEL16_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MSEL2CR_MSEL18_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MSEL2CR_MSEL16_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MSEL2CR_MSEL18_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINMUX_DATA(XWUP_MARK, PORT33_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_DATA(VACK_MARK, PORT40_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_DATA(A0_MARK, PORT57_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINMUX_DATA(BS__MARK, PORT57_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_DATA(A12_MARK, PORT58_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_DATA(A13_MARK, PORT59_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_DATA(A14_MARK, PORT60_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_DATA(A15_MARK, PORT61_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_DATA(A16_MARK, PORT62_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_DATA(A17_MARK, PORT63_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINMUX_DATA(A18_MARK, PORT64_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_DATA(A19_MARK, PORT65_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_DATA(A20_MARK, PORT66_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_DATA(A21_MARK, PORT67_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_DATA(A22_MARK, PORT68_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_DATA(A23_MARK, PORT69_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_DATA(A24_MARK, PORT70_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_DATA(A25_MARK, PORT71_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_DATA(A26_MARK, PORT72_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_DATA(CS4__MARK, PORT90_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_DATA(FCE1__MARK, PORT92_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_DATA(DACK0_MARK, PORT93_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_DATA(CS6A__MARK, PORT94_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_DATA(WE1__MARK, PORT98_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_DATA(FRB_MARK, PORT99_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_DATA(CKO_MARK, PORT100_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_DATA(NBRST__MARK, PORT102_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MSEL4CR_MSEL10_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_DATA(A27_MARK, PORT149_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) MSEL4CR_MSEL10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_DATA(DINT__MARK, PORT158_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_DATA(NMI_MARK, PORT159_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) MSEL4CR_MSEL20_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) MSEL4CR_MSEL20_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) MSEL4CR_MSEL20_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) MSEL4CR_MSEL20_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MSEL4CR_MSEL20_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_DATA(D16_MARK, PORT200_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_DATA(D17_MARK, PORT201_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_DATA(D18_MARK, PORT202_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_DATA(D19_MARK, PORT203_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_DATA(D20_MARK, PORT204_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_DATA(D21_MARK, PORT205_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_DATA(D22_MARK, PORT206_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_DATA(D23_MARK, PORT207_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_DATA(D24_MARK, PORT208_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_DATA(D25_MARK, PORT209_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_DATA(D26_MARK, PORT210_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_DATA(D27_MARK, PORT211_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_DATA(D28_MARK, PORT212_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_DATA(D29_MARK, PORT213_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_DATA(D30_MARK, PORT214_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_DATA(D31_MARK, PORT215_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) MSEL4CR_MSEL26_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MSEL4CR_MSEL26_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MSEL4CR_MSEL26_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MSEL4CR_MSEL26_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_DATA(IDIN_MARK, PORT227_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) MSEL4CR_MSEL26_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MSEL4CR_MSEL26_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) MSEL2CR_MSEL16_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) MSEL2CR_MSEL16_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MSEL4CR_MSEL26_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) MSEL4CR_MSEL26_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) MSEL4CR_MSEL20_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) MSEL4CR_MSEL20_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MSEL4CR_MSEL20_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) MSEL4CR_MSEL20_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MSEL4CR_MSEL20_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) MSEL2CR_MSEL18_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) MSEL2CR_MSEL18_0), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* MSEL2 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) MSEL2CR_MSEL12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) MSEL2CR_MSEL12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) MSEL2CR_MSEL12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) MSEL2CR_MSEL12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) MSEL2CR_MSEL12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) MSEL2CR_MSEL9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) MSEL2CR_MSEL9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) MSEL2CR_MSEL9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) MSEL2CR_MSEL9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) MSEL2CR_MSEL9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) MSEL2CR_MSEL6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) MSEL2CR_MSEL6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) MSEL2CR_MSEL6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) MSEL2CR_MSEL6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) MSEL2CR_MSEL6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) MSEL2CR_MSEL3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) MSEL2CR_MSEL3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MSEL2CR_MSEL3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) MSEL2CR_MSEL3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) MSEL2CR_MSEL3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) MSEL2CR_MSEL0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) MSEL2CR_MSEL0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) MSEL2CR_MSEL0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) MSEL2CR_MSEL0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) MSEL2CR_MSEL0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* MSEL3 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* MSEL4 special cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define __I (SH_PFC_PIN_CFG_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define __O (SH_PFC_PIN_CFG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define __PU (SH_PFC_PIN_CFG_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * Pins not associated with a GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PORT_ASSIGN_LAST(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Table 25-1 (I/O and Pull U/D) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) SH73A0_PIN_I_PD(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SH73A0_PIN_I_PU(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SH73A0_PIN_I_PU(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) SH73A0_PIN_I_PU(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) SH73A0_PIN_I_PU(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SH73A0_PIN_I_PU(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SH73A0_PIN_I_PU(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SH73A0_PIN_I_PU(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) SH73A0_PIN_I_PU(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SH73A0_PIN_I_PD(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SH73A0_PIN_I_PD(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SH73A0_PIN_I_PU_PD(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) SH73A0_PIN_IO_PU_PD(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) SH73A0_PIN_IO_PU_PD(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SH73A0_PIN_IO_PU_PD(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) SH73A0_PIN_IO_PU_PD(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SH73A0_PIN_IO_PD(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SH73A0_PIN_IO_PD(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SH73A0_PIN_IO_PU(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) SH73A0_PIN_IO_PU(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) SH73A0_PIN_O(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) SH73A0_PIN_O(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) SH73A0_PIN_O(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) SH73A0_PIN_O(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SH73A0_PIN_O(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SH73A0_PIN_I_PD(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SH73A0_PIN_I_PD(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) SH73A0_PIN_IO_PU(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) SH73A0_PIN_IO_PU(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) SH73A0_PIN_IO_PD(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) SH73A0_PIN_IO_PD(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) SH73A0_PIN_IO_PU(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SH73A0_PIN_IO_PD(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) SH73A0_PIN_I_PU_PD(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) SH73A0_PIN_IO_PD(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) SH73A0_PIN_I_PU_PD(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SH73A0_PIN_IO_PD(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) SH73A0_PIN_IO(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SH73A0_PIN_O(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SH73A0_PIN_I_PU(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SH73A0_PIN_I_PU_PD(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) SH73A0_PIN_O(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) SH73A0_PIN_IO_PD(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) SH73A0_PIN_IO_PU_PD(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) SH73A0_PIN_IO_PU_PD(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SH73A0_PIN_IO_PD(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SH73A0_PIN_IO_PD(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) SH73A0_PIN_IO_PD(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) SH73A0_PIN_I_PD(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) SH73A0_PIN_IO_PU_PD(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) SH73A0_PIN_IO_PD(50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SH73A0_PIN_IO_PD(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) SH73A0_PIN_O(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) SH73A0_PIN_IO_PU_PD(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) SH73A0_PIN_IO_PU_PD(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) SH73A0_PIN_IO_PD(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) SH73A0_PIN_I_PU_PD(56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SH73A0_PIN_IO(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) SH73A0_PIN_IO(58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) SH73A0_PIN_IO(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) SH73A0_PIN_IO(60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) SH73A0_PIN_IO(61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) SH73A0_PIN_IO_PD(62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) SH73A0_PIN_IO_PD(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) SH73A0_PIN_IO_PU_PD(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SH73A0_PIN_IO_PD(65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) SH73A0_PIN_IO_PU_PD(66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) SH73A0_PIN_IO_PU_PD(67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) SH73A0_PIN_IO_PU_PD(68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) SH73A0_PIN_IO_PU_PD(69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) SH73A0_PIN_IO_PU_PD(70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) SH73A0_PIN_IO_PU_PD(71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) SH73A0_PIN_IO_PU_PD(72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) SH73A0_PIN_I_PU_PD(73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) SH73A0_PIN_IO_PU(74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) SH73A0_PIN_IO_PU(75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) SH73A0_PIN_IO_PU(76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) SH73A0_PIN_IO_PU(77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) SH73A0_PIN_IO_PU(78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) SH73A0_PIN_IO_PU(79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) SH73A0_PIN_IO_PU(80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) SH73A0_PIN_IO_PU(81),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SH73A0_PIN_IO_PU(82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) SH73A0_PIN_IO_PU(83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) SH73A0_PIN_IO_PU(84),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) SH73A0_PIN_IO_PU(85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) SH73A0_PIN_IO_PU(86),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) SH73A0_PIN_IO_PU(87),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) SH73A0_PIN_IO_PU(88),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) SH73A0_PIN_IO_PU(89),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) SH73A0_PIN_O(90),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) SH73A0_PIN_IO_PU(91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) SH73A0_PIN_O(92),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) SH73A0_PIN_IO_PU(93),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) SH73A0_PIN_O(94),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) SH73A0_PIN_I_PU_PD(95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) SH73A0_PIN_IO(96),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) SH73A0_PIN_IO(97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) SH73A0_PIN_IO(98),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) SH73A0_PIN_I_PU(99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) SH73A0_PIN_O(100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) SH73A0_PIN_O(101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) SH73A0_PIN_I_PU(102),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SH73A0_PIN_IO_PD(103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) SH73A0_PIN_I_PU_PD(104),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) SH73A0_PIN_I_PD(105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) SH73A0_PIN_I_PD(106),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) SH73A0_PIN_I_PU_PD(107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) SH73A0_PIN_I_PU_PD(108),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) SH73A0_PIN_IO_PD(109),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) SH73A0_PIN_IO_PD(110),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) SH73A0_PIN_IO_PU_PD(111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SH73A0_PIN_IO_PU_PD(112),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) SH73A0_PIN_IO_PU_PD(113),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) SH73A0_PIN_IO_PD(114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) SH73A0_PIN_IO_PU(115),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) SH73A0_PIN_IO_PU(116),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) SH73A0_PIN_IO_PU_PD(117),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) SH73A0_PIN_IO_PU_PD(118),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) SH73A0_PIN_IO_PD(128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) SH73A0_PIN_IO_PD(129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) SH73A0_PIN_IO_PU_PD(130),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) SH73A0_PIN_IO_PD(131),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) SH73A0_PIN_IO_PD(132),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) SH73A0_PIN_IO_PD(133),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) SH73A0_PIN_IO_PU_PD(134),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) SH73A0_PIN_IO_PU_PD(135),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) SH73A0_PIN_IO_PU_PD(136),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) SH73A0_PIN_IO_PU_PD(137),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) SH73A0_PIN_IO_PD(138),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) SH73A0_PIN_IO_PD(139),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) SH73A0_PIN_IO_PD(140),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) SH73A0_PIN_IO_PD(141),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) SH73A0_PIN_IO_PD(142),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) SH73A0_PIN_IO_PD(143),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) SH73A0_PIN_IO_PU_PD(144),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) SH73A0_PIN_IO_PD(145),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) SH73A0_PIN_IO_PU_PD(146),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) SH73A0_PIN_IO_PU_PD(147),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) SH73A0_PIN_IO_PU_PD(148),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) SH73A0_PIN_IO_PU_PD(149),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) SH73A0_PIN_I_PU_PD(150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) SH73A0_PIN_IO_PU_PD(151),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) SH73A0_PIN_IO_PU_PD(152),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) SH73A0_PIN_IO_PD(153),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) SH73A0_PIN_IO_PD(154),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) SH73A0_PIN_I_PU_PD(155),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) SH73A0_PIN_IO_PU_PD(156),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SH73A0_PIN_I_PD(157),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) SH73A0_PIN_IO_PD(158),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) SH73A0_PIN_IO_PU_PD(159),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) SH73A0_PIN_IO_PU_PD(160),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) SH73A0_PIN_I_PU_PD(161),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) SH73A0_PIN_I_PU_PD(162),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) SH73A0_PIN_IO_PU_PD(163),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SH73A0_PIN_I_PU_PD(164),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) SH73A0_PIN_IO_PD(192),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) SH73A0_PIN_IO_PU_PD(193),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) SH73A0_PIN_IO_PD(194),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SH73A0_PIN_IO_PU_PD(195),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SH73A0_PIN_IO_PD(196),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) SH73A0_PIN_IO_PD(197),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) SH73A0_PIN_IO_PD(198),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) SH73A0_PIN_IO_PD(199),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) SH73A0_PIN_IO_PU_PD(200),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) SH73A0_PIN_IO_PU_PD(201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) SH73A0_PIN_IO_PU_PD(202),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) SH73A0_PIN_IO_PU_PD(203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) SH73A0_PIN_IO_PU_PD(204),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) SH73A0_PIN_IO_PU_PD(205),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) SH73A0_PIN_IO_PU_PD(206),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) SH73A0_PIN_IO_PD(207),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SH73A0_PIN_IO_PD(208),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SH73A0_PIN_IO_PD(209),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SH73A0_PIN_IO_PD(210),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) SH73A0_PIN_IO_PD(211),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) SH73A0_PIN_IO_PD(212),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SH73A0_PIN_IO_PD(213),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SH73A0_PIN_IO_PU_PD(214),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) SH73A0_PIN_IO_PU_PD(215),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) SH73A0_PIN_IO_PD(216),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) SH73A0_PIN_IO_PD(217),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) SH73A0_PIN_O(218),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) SH73A0_PIN_IO_PD(219),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) SH73A0_PIN_IO_PD(220),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) SH73A0_PIN_IO_PU_PD(221),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) SH73A0_PIN_IO_PU_PD(222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) SH73A0_PIN_I_PU_PD(223),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SH73A0_PIN_I_PU_PD(224),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) SH73A0_PIN_IO_PU_PD(225),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) SH73A0_PIN_O(226),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) SH73A0_PIN_IO_PU_PD(227),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) SH73A0_PIN_I_PU_PD(228),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) SH73A0_PIN_I_PD(229),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) SH73A0_PIN_IO(230),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) SH73A0_PIN_IO_PU_PD(231),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) SH73A0_PIN_IO_PU_PD(232),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) SH73A0_PIN_I_PU_PD(233),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) SH73A0_PIN_IO_PU_PD(234),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) SH73A0_PIN_IO_PU_PD(235),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) SH73A0_PIN_IO_PU_PD(236),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) SH73A0_PIN_IO_PD(237),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) SH73A0_PIN_IO_PU_PD(238),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) SH73A0_PIN_IO_PU_PD(239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) SH73A0_PIN_IO_PU_PD(240),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) SH73A0_PIN_O(241),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) SH73A0_PIN_I_PD(242),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) SH73A0_PIN_IO_PU_PD(243),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) SH73A0_PIN_IO_PU_PD(244),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) SH73A0_PIN_IO_PU_PD(245),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) SH73A0_PIN_IO_PU_PD(246),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) SH73A0_PIN_IO_PU_PD(247),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) SH73A0_PIN_IO_PU_PD(248),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) SH73A0_PIN_IO_PU_PD(249),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) SH73A0_PIN_IO_PU_PD(250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SH73A0_PIN_IO_PU_PD(251),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) SH73A0_PIN_IO_PU_PD(252),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) SH73A0_PIN_IO_PU_PD(253),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) SH73A0_PIN_IO_PU_PD(254),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) SH73A0_PIN_IO_PU_PD(255),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) SH73A0_PIN_IO_PU_PD(256),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) SH73A0_PIN_IO_PU_PD(257),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) SH73A0_PIN_IO_PU_PD(258),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) SH73A0_PIN_IO_PU_PD(259),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) SH73A0_PIN_IO_PU_PD(260),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) SH73A0_PIN_IO_PU_PD(261),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) SH73A0_PIN_IO_PU_PD(262),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) SH73A0_PIN_IO_PU_PD(263),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) SH73A0_PIN_IO_PU_PD(264),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) SH73A0_PIN_IO_PU_PD(265),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) SH73A0_PIN_IO_PU_PD(266),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) SH73A0_PIN_IO_PU_PD(267),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) SH73A0_PIN_IO_PU_PD(268),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SH73A0_PIN_IO_PU_PD(269),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) SH73A0_PIN_IO_PU_PD(270),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) SH73A0_PIN_IO_PU_PD(271),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) SH73A0_PIN_IO_PU_PD(272),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) SH73A0_PIN_IO_PU_PD(273),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) SH73A0_PIN_IO_PU_PD(274),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) SH73A0_PIN_IO_PU_PD(275),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) SH73A0_PIN_IO_PU_PD(276),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) SH73A0_PIN_IO_PU_PD(277),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) SH73A0_PIN_IO_PU_PD(278),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) SH73A0_PIN_IO_PU_PD(279),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) SH73A0_PIN_IO_PU_PD(280),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) SH73A0_PIN_O(281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) SH73A0_PIN_O(282),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) SH73A0_PIN_I_PU(288),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SH73A0_PIN_IO_PU_PD(289),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) SH73A0_PIN_IO_PU_PD(290),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) SH73A0_PIN_IO_PU_PD(291),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SH73A0_PIN_IO_PU_PD(292),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) SH73A0_PIN_IO_PU_PD(293),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SH73A0_PIN_IO_PU_PD(294),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) SH73A0_PIN_IO_PU_PD(295),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) SH73A0_PIN_IO_PU_PD(296),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) SH73A0_PIN_IO_PU_PD(297),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) SH73A0_PIN_IO_PU_PD(298),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) SH73A0_PIN_IO_PU_PD(299),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) SH73A0_PIN_IO_PU_PD(300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) SH73A0_PIN_IO_PU_PD(301),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) SH73A0_PIN_IO_PU_PD(302),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) SH73A0_PIN_IO_PU_PD(303),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) SH73A0_PIN_IO_PU_PD(304),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) SH73A0_PIN_IO_PU_PD(305),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) SH73A0_PIN_O(306),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) SH73A0_PIN_O(307),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) SH73A0_PIN_I_PU(308),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) SH73A0_PIN_O(309),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* Pins not associated with a GPIO port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINMUX_NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* - BSC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const unsigned int bsc_data_0_7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) 74, 75, 76, 77, 78, 79, 80, 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static const unsigned int bsc_data_0_7_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static const unsigned int bsc_data_8_15_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) /* D[8:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) 82, 83, 84, 85, 86, 87, 88, 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static const unsigned int bsc_data_8_15_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static const unsigned int bsc_cs4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const unsigned int bsc_cs4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) CS4__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const unsigned int bsc_cs5_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static const unsigned int bsc_cs5_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) CS5A__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const unsigned int bsc_cs5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static const unsigned int bsc_cs5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) CS5B__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned int bsc_cs6_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const unsigned int bsc_cs6_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) CS6A__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static const unsigned int bsc_cs6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static const unsigned int bsc_cs6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) CS6B__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const unsigned int bsc_rd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned int bsc_rd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) RD__FSC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const unsigned int bsc_rdwr_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* RDWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const unsigned int bsc_rdwr_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) PORT91_RDWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const unsigned int bsc_rdwr_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* RDWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const unsigned int bsc_rdwr_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) RDWR_FWE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const unsigned int bsc_rdwr_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* RDWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static const unsigned int bsc_rdwr_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) PORT149_RDWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static const unsigned int bsc_we0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* WE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) 97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static const unsigned int bsc_we0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) WE0__FWE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const unsigned int bsc_we1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* WE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static const unsigned int bsc_we1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) WE1__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* - FSIA ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const unsigned int fsia_mclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static const unsigned int fsia_mclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) FSIACK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static const unsigned int fsia_mclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* OMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) 49,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int fsia_mclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) FSIAOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const unsigned int fsia_sclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* ILR, IBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) 50, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static const unsigned int fsia_sclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) FSIAILR_MARK, FSIAIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static const unsigned int fsia_sclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* OLR, OBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) 50, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const unsigned int fsia_sclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) FSIAOLR_MARK, FSIAOBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const unsigned int fsia_data_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* ISLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const unsigned int fsia_data_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) FSIAISLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const unsigned int fsia_data_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* OSLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const unsigned int fsia_data_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) FSIAOSLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static const unsigned int fsia_spdif_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const unsigned int fsia_spdif_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) FSIASPDIF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* - FSIB ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static const unsigned int fsib_mclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static const unsigned int fsib_mclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) FSIBCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const unsigned int fsib_mclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* OMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static const unsigned int fsib_mclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) FSIBOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static const unsigned int fsib_sclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* ILR, IBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) 37, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static const unsigned int fsib_sclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) FSIBILR_MARK, FSIBIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const unsigned int fsib_sclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* OLR, OBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) 37, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static const unsigned int fsib_sclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) FSIBOLR_MARK, FSIBOBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const unsigned int fsib_data_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* ISLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static const unsigned int fsib_data_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) FSIBISLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static const unsigned int fsib_data_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* OSLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static const unsigned int fsib_data_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) FSIBOSLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static const unsigned int fsib_spdif_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const unsigned int fsib_spdif_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) FSIBSPDIF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* - FSIC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static const unsigned int fsic_mclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static const unsigned int fsic_mclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) FSICCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static const unsigned int fsic_mclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* OMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static const unsigned int fsic_mclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) FSICOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static const unsigned int fsic_sclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* ILR, IBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) 46, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static const unsigned int fsic_sclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) FSICILR_MARK, FSICIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static const unsigned int fsic_sclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* OLR, OBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) 46, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static const unsigned int fsic_sclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) FSICOLR_MARK, FSICOBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static const unsigned int fsic_data_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* ISLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned int fsic_data_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) FSICISLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static const unsigned int fsic_data_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) 47, 44, 42, 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static const unsigned int fsic_data_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static const unsigned int fsic_spdif_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const unsigned int fsic_spdif_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) PORT53_FSICSPDIF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static const unsigned int fsic_spdif_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static const unsigned int fsic_spdif_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) PORT47_FSICSPDIF_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* - FSID ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const unsigned int fsid_sclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* ILR, IBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) 46, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static const unsigned int fsid_sclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) FSIDILR_MARK, FSIDIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int fsid_sclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* OLR, OBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) 46, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const unsigned int fsid_sclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) FSIDOLR_MARK, FSIDOBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const unsigned int fsid_data_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* ISLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static const unsigned int fsid_data_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) FSIDISLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static const unsigned int i2c2_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) 237, 236,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static const unsigned int i2c2_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static const unsigned int i2c2_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) 27, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const unsigned int i2c2_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static const unsigned int i2c2_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) 115, 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static const unsigned int i2c2_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const unsigned int i2c3_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) 248, 249,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static const unsigned int i2c3_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static const unsigned int i2c3_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) 27, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static const unsigned int i2c3_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static const unsigned int i2c3_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) 115, 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const unsigned int i2c3_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* - IrDA ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static const unsigned int irda_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /* OUT, IN, FIRSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) 241, 242, 243,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const unsigned int irda_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static const unsigned int irda_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) /* OUT, IN, FIRSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) 49, 53, 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static const unsigned int irda_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* - KEYSC ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static const unsigned int keysc_in5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /* KEYIN[0:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) 66, 67, 68, 69, 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const unsigned int keysc_in5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) KEYIN4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static const unsigned int keysc_in6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) /* KEYIN[0:5] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) 66, 67, 68, 69, 70, 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const unsigned int keysc_in6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) KEYIN4_MARK, KEYIN5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static const unsigned int keysc_in7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* KEYIN[0:6] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) 66, 67, 68, 69, 70, 71, 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static const unsigned int keysc_in7_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) static const unsigned int keysc_in8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* KEYIN[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) 66, 67, 68, 69, 70, 71, 72, 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static const unsigned int keysc_in8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static const unsigned int keysc_out04_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* KEYOUT[0:4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) 65, 64, 63, 62, 61,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static const unsigned int keysc_out04_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static const unsigned int keysc_out5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /* KEYOUT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static const unsigned int keysc_out5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) KEYOUT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static const unsigned int keysc_out6_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* KEYOUT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static const unsigned int keysc_out6_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) PORT59_KEYOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static const unsigned int keysc_out6_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* KEYOUT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static const unsigned int keysc_out6_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) PORT131_KEYOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static const unsigned int keysc_out6_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* KEYOUT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static const unsigned int keysc_out6_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) PORT143_KEYOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static const unsigned int keysc_out7_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* KEYOUT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static const unsigned int keysc_out7_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) PORT58_KEYOUT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static const unsigned int keysc_out7_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* KEYOUT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const unsigned int keysc_out7_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) PORT132_KEYOUT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const unsigned int keysc_out7_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* KEYOUT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) 144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static const unsigned int keysc_out7_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) PORT144_KEYOUT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static const unsigned int keysc_out8_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* KEYOUT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) PIN_A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static const unsigned int keysc_out8_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) KEYOUT8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static const unsigned int keysc_out8_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* KEYOUT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) 136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static const unsigned int keysc_out8_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) PORT136_KEYOUT8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static const unsigned int keysc_out8_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* KEYOUT8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const unsigned int keysc_out8_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) PORT138_KEYOUT8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static const unsigned int keysc_out9_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* KEYOUT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const unsigned int keysc_out9_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) PORT137_KEYOUT9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static const unsigned int keysc_out9_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /* KEYOUT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const unsigned int keysc_out9_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) PORT139_KEYOUT9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) static const unsigned int keysc_out9_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /* KEYOUT9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static const unsigned int keysc_out9_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) PORT149_KEYOUT9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const unsigned int keysc_out10_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* KEYOUT10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static const unsigned int keysc_out10_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) PORT132_KEYOUT10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static const unsigned int keysc_out10_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /* KEYOUT10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static const unsigned int keysc_out10_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) PORT142_KEYOUT10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static const unsigned int keysc_out11_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* KEYOUT11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static const unsigned int keysc_out11_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) PORT131_KEYOUT11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const unsigned int keysc_out11_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* KEYOUT11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) 143,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static const unsigned int keysc_out11_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) PORT143_KEYOUT11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* - LCD -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static const unsigned int lcd_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) 192, 193, 194, 195, 196, 197, 198, 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) static const unsigned int lcd_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static const unsigned int lcd_data9_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) /* D[0:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) 192, 193, 194, 195, 196, 197, 198, 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static const unsigned int lcd_data9_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) LCDD8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static const unsigned int lcd_data12_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* D[0:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) 192, 193, 194, 195, 196, 197, 198, 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) 200, 201, 202, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const unsigned int lcd_data12_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static const unsigned int lcd_data16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) 192, 193, 194, 195, 196, 197, 198, 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) 200, 201, 202, 203, 204, 205, 206, 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static const unsigned int lcd_data16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static const unsigned int lcd_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* D[0:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) 192, 193, 194, 195, 196, 197, 198, 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) 200, 201, 202, 203, 204, 205, 206, 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) 208, 209,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static const unsigned int lcd_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) LCDD16_MARK, LCDD17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static const unsigned int lcd_data24_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* D[0:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) 192, 193, 194, 195, 196, 197, 198, 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) 200, 201, 202, 203, 204, 205, 206, 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) 208, 209, 210, 211, 212, 213, 214, 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static const unsigned int lcd_data24_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static const unsigned int lcd_display_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* DON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) 222,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static const unsigned int lcd_display_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) LCDDON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static const unsigned int lcd_lclk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* LCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) 221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) static const unsigned int lcd_lclk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) LCDLCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static const unsigned int lcd_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* VSYN, HSYN, DCK, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) 220, 218, 216, 219,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) static const unsigned int lcd_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static const unsigned int lcd_sys_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* CS, WR, RD, RS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) 218, 216, 217, 219,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static const unsigned int lcd_sys_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) /* - LCD2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static const unsigned int lcd2_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) 128, 129, 142, 143, 144, 145, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static const unsigned int lcd2_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const unsigned int lcd2_data9_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* D[0:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) 128, 129, 142, 143, 144, 145, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const unsigned int lcd2_data9_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) LCD2D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static const unsigned int lcd2_data12_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* D[0:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) 128, 129, 142, 143, 144, 145, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) 140, 141, 130, 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static const unsigned int lcd2_data12_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static const unsigned int lcd2_data16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) /* D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) 128, 129, 142, 143, 144, 145, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) 140, 141, 130, 131, 132, 133, 134, 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static const unsigned int lcd2_data16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static const unsigned int lcd2_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* D[0:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) 128, 129, 142, 143, 144, 145, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) 140, 141, 130, 131, 132, 133, 134, 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) 136, 137,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static const unsigned int lcd2_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) LCD2D16_MARK, LCD2D17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static const unsigned int lcd2_data24_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* D[0:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) 128, 129, 142, 143, 144, 145, 138, 139,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) 140, 141, 130, 131, 132, 133, 134, 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) 136, 137, 146, 147, 234, 235, 238, 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static const unsigned int lcd2_data24_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static const unsigned int lcd2_sync_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* VSYN, HSYN, DCK, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) 128, 129, 146, 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) static const unsigned int lcd2_sync_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static const unsigned int lcd2_sync_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /* VSYN, HSYN, DCK, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) 222, 221, 219, 217,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static const unsigned int lcd2_sync_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static const unsigned int lcd2_sys_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) /* CS, WR, RD, RS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) 129, 146, 147, 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static const unsigned int lcd2_sys_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) LCD2RD__MARK, PORT145_LCD2RS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) static const unsigned int lcd2_sys_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* CS, WR, RD, RS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) 221, 219, 147, 217,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) static const unsigned int lcd2_sys_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) LCD2RD__MARK, PORT217_LCD2RS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /* - MMCIF ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static const unsigned int mmc0_data1_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) 271,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) static const unsigned int mmc0_data1_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) MMCD0_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static const unsigned int mmc0_data4_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) 271, 272, 273, 274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static const unsigned int mmc0_data4_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static const unsigned int mmc0_data8_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) 271, 272, 273, 274, 275, 276, 277, 278,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static const unsigned int mmc0_data8_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static const unsigned int mmc0_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) 279, 270,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static const unsigned int mmc0_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) MMCCMD0_MARK, MMCCLK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static const unsigned int mmc0_data1_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) 305,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) static const unsigned int mmc0_data1_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) MMCD1_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static const unsigned int mmc0_data4_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) 305, 304, 303, 302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) static const unsigned int mmc0_data4_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) static const unsigned int mmc0_data8_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) 305, 304, 303, 302, 301, 300, 299, 298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static const unsigned int mmc0_data8_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static const unsigned int mmc0_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) 297, 289,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) static const unsigned int mmc0_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) MMCCMD1_MARK, MMCCLK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static const unsigned int msiof0_rsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) /* RSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static const unsigned int msiof0_rsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) MSIOF0_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) static const unsigned int msiof0_tsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) /* TSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static const unsigned int msiof0_tsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) MSIOF0_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static const unsigned int msiof0_rsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /* RSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const unsigned int msiof0_rsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) MSIOF0_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static const unsigned int msiof0_tsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) /* TSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static const unsigned int msiof0_tsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) MSIOF0_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) 62,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static const unsigned int msiof0_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) 70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) static const unsigned int msiof0_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static const unsigned int msiof0_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static const unsigned int msiof0_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static const unsigned int msiof0_mck0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* MSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static const unsigned int msiof0_mck0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) MSIOF0_MCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static const unsigned int msiof0_mck1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /* MSCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) 69,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static const unsigned int msiof0_mck1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) MSIOF0_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static const unsigned int msiof0l_rsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) /* RSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) 214,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) static const unsigned int msiof0l_rsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) MSIOF0L_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) static const unsigned int msiof0l_tsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) /* TSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) 219,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static const unsigned int msiof0l_tsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) MSIOF0L_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static const unsigned int msiof0l_rsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) /* RSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) 215,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) static const unsigned int msiof0l_rsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) MSIOF0L_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static const unsigned int msiof0l_tsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) /* TSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) 217,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static const unsigned int msiof0l_tsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) MSIOF0L_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static const unsigned int msiof0l_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static const unsigned int msiof0l_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) PORT207_MSIOF0L_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) static const unsigned int msiof0l_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) 210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static const unsigned int msiof0l_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) PORT210_MSIOF0L_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static const unsigned int msiof0l_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) 208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static const unsigned int msiof0l_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) PORT208_MSIOF0L_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) static const unsigned int msiof0l_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) 211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) static const unsigned int msiof0l_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) PORT211_MSIOF0L_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) static const unsigned int msiof0l_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) 221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static const unsigned int msiof0l_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) MSIOF0L_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) static const unsigned int msiof0l_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) 222,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) static const unsigned int msiof0l_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) MSIOF0L_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static const unsigned int msiof0l_mck0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /* MSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) 212,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static const unsigned int msiof0l_mck0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) MSIOF0L_MCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static const unsigned int msiof0l_mck1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* MSCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) 213,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static const unsigned int msiof0l_mck1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) MSIOF0L_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static const unsigned int msiof1_rsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* RSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) 234,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static const unsigned int msiof1_rsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) MSIOF1_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static const unsigned int msiof1_tsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* TSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) 232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static const unsigned int msiof1_tsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) MSIOF1_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static const unsigned int msiof1_rsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) /* RSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) 235,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static const unsigned int msiof1_rsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) MSIOF1_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static const unsigned int msiof1_tsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) /* TSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) 231,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static const unsigned int msiof1_tsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) MSIOF1_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) 238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) 239,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static const unsigned int msiof1_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) 233,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static const unsigned int msiof1_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static const unsigned int msiof1_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static const unsigned int msiof1_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) static const unsigned int msiof1_mck0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /* MSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) 236,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static const unsigned int msiof1_mck0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) MSIOF1_MCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) static const unsigned int msiof1_mck1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) /* MSCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) 237,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) static const unsigned int msiof1_mck1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) MSIOF1_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const unsigned int msiof2_rsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* RSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) 151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static const unsigned int msiof2_rsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) MSIOF2_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static const unsigned int msiof2_tsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* TSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) 135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static const unsigned int msiof2_tsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) MSIOF2_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static const unsigned int msiof2_rsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) /* RSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const unsigned int msiof2_rsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) MSIOF2_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static const unsigned int msiof2_tsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* TSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) 133,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const unsigned int msiof2_tsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) MSIOF2_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static const unsigned int msiof2_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) 131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const unsigned int msiof2_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) PORT131_MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static const unsigned int msiof2_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) 153,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) static const unsigned int msiof2_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) PORT153_MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static const unsigned int msiof2_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) 132,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static const unsigned int msiof2_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) PORT132_MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) static const unsigned int msiof2_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) 156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static const unsigned int msiof2_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) PORT156_MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static const unsigned int msiof2_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) static const unsigned int msiof2_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) PORT130_MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) static const unsigned int msiof2_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) 157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static const unsigned int msiof2_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) PORT157_MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) static const unsigned int msiof2_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static const unsigned int msiof2_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) static const unsigned int msiof2_mck0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* MSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static const unsigned int msiof2_mck0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) MSIOF2_MCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) static const unsigned int msiof2_mck1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* MSCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) 155,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static const unsigned int msiof2_mck1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) MSIOF2_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) static const unsigned int msiof2r_tsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /* TSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) 248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static const unsigned int msiof2r_tsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) MSIOF2R_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) static const unsigned int msiof2r_tsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) /* TSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) 249,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static const unsigned int msiof2r_tsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) MSIOF2R_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static const unsigned int msiof2r_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) 244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static const unsigned int msiof2r_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) MSIOF2R_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static const unsigned int msiof2r_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) 245,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static const unsigned int msiof2r_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) MSIOF2R_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static const unsigned int msiof3_rsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* RSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) 115,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static const unsigned int msiof3_rsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) BBIF1_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static const unsigned int msiof3_tsck_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) /* TSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) static const unsigned int msiof3_tsck_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) BBIF1_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) static const unsigned int msiof3_rsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* RSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static const unsigned int msiof3_rsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) BBIF1_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static const unsigned int msiof3_tsync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* TSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) static const unsigned int msiof3_tsync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) BBIF1_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static const unsigned int msiof3_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static const unsigned int msiof3_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) BBIF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static const unsigned int msiof3_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) static const unsigned int msiof3_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) BBIF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static const unsigned int msiof3_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static const unsigned int msiof3_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) BBIF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static const unsigned int msiof3_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static const unsigned int msiof3_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) BBIF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static const unsigned int msiof3_flow_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) /* FLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) static const unsigned int msiof3_flow_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) BBIF1_FLOW_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* - SCIFA0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static const unsigned int scifa0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) 43, 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) static const unsigned int scifa0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static const unsigned int scifa0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static const unsigned int scifa0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) SCIFA0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static const unsigned int scifa0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) 42, 44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static const unsigned int scifa0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* - SCIFA1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static const unsigned int scifa1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) 228, 225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static const unsigned int scifa1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static const unsigned int scifa1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) 226,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const unsigned int scifa1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) SCIFA1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static const unsigned int scifa1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) 227, 229,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static const unsigned int scifa1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /* - SCIFA2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static const unsigned int scifa2_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) 155, 154,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static const unsigned int scifa2_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static const unsigned int scifa2_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static const unsigned int scifa2_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) SCIFA2_SCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static const unsigned int scifa2_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) 156, 157,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static const unsigned int scifa2_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static const unsigned int scifa2_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) 233, 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static const unsigned int scifa2_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const unsigned int scifa2_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) 232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static const unsigned int scifa2_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) SCIFA2_SCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static const unsigned int scifa2_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) 234, 231,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static const unsigned int scifa2_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) /* - SCIFA3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static const unsigned int scifa3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) 108, 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static const unsigned int scifa3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static const unsigned int scifa3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) 109, 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) static const unsigned int scifa3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* - SCIFA4 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) static const unsigned int scifa4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) 33, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) static const unsigned int scifa4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static const unsigned int scifa4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) 34, 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) static const unsigned int scifa4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /* - SCIFA5 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) static const unsigned int scifa5_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) 246, 247,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) static const unsigned int scifa5_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) static const unsigned int scifa5_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) 248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) static const unsigned int scifa5_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) PORT248_SCIFA5_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) static const unsigned int scifa5_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) 245, 244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) static const unsigned int scifa5_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) static const unsigned int scifa5_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) 195, 196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static const unsigned int scifa5_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) static const unsigned int scifa5_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) 197,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) static const unsigned int scifa5_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) PORT197_SCIFA5_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static const unsigned int scifa5_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) 194, 193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) static const unsigned int scifa5_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) static const unsigned int scifa5_data_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) 162, 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) static const unsigned int scifa5_data_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) static const unsigned int scifa5_clk_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) 159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) static const unsigned int scifa5_clk_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) PORT159_SCIFA5_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) static const unsigned int scifa5_ctrl_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) 163, 161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) static const unsigned int scifa5_ctrl_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) /* - SCIFA6 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) static const unsigned int scifa6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static const unsigned int scifa6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) SCIFA6_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) /* - SCIFA7 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) static const unsigned int scifa7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) 12, 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) static const unsigned int scifa7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) static const unsigned int scifa7_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) 19, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static const unsigned int scifa7_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* - SCIFB ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static const unsigned int scifb_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) 162, 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) static const unsigned int scifb_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) static const unsigned int scifb_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) 159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) static const unsigned int scifb_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) PORT159_SCIFB_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static const unsigned int scifb_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) 163, 161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static const unsigned int scifb_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static const unsigned int scifb_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) 246, 247,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static const unsigned int scifb_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) static const unsigned int scifb_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) 248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) static const unsigned int scifb_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) PORT248_SCIFB_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) static const unsigned int scifb_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) 245, 244,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) static const unsigned int scifb_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) 252,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) SDHID0_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) 252, 253, 254, 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) 256, 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) SDHICMD0_MARK, SDHICLK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) 251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) SDHICD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) 257,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) SDHIWP0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) 259,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) SDHID1_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) 259, 260, 261, 262,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) 263, 258,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) SDHICMD1_MARK, SDHICLK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) 265,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) SDHID2_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) 265, 266, 267, 268,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) 269, 264,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) SDHICMD2_MARK, SDHICLK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) /* - TPU0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) static const unsigned int tpu0_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) 55,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) static const unsigned int tpu0_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) TPU0TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) static const unsigned int tpu0_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) 59,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static const unsigned int tpu0_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static const unsigned int tpu0_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) static const unsigned int tpu0_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) TPU0TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static const unsigned int tpu0_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) 141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) static const unsigned int tpu0_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) /* - TPU1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) static const unsigned int tpu1_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) 246,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) static const unsigned int tpu1_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) TPU1TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) static const unsigned int tpu1_to1_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) static const unsigned int tpu1_to1_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) PORT28_TPU1TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) static const unsigned int tpu1_to1_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static const unsigned int tpu1_to1_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) PORT29_TPU1TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) static const unsigned int tpu1_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) 153,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) static const unsigned int tpu1_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) TPU1TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static const unsigned int tpu1_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) 145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) static const unsigned int tpu1_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) TPU1TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) /* - TPU2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) static const unsigned int tpu2_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) 248,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static const unsigned int tpu2_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) TPU2TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static const unsigned int tpu2_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) 197,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) static const unsigned int tpu2_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) TPU2TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static const unsigned int tpu2_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static const unsigned int tpu2_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) TPU2TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) static const unsigned int tpu2_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static const unsigned int tpu2_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) TPU2TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) /* - TPU3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) static const unsigned int tpu3_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) 163,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) static const unsigned int tpu3_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) TPU3TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) static const unsigned int tpu3_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) 247,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) static const unsigned int tpu3_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) TPU3TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) static const unsigned int tpu3_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) 54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) static const unsigned int tpu3_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) TPU3TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) static const unsigned int tpu3_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static const unsigned int tpu3_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) TPU3TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /* - TPU4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) static const unsigned int tpu4_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) 241,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) static const unsigned int tpu4_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) TPU4TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) static const unsigned int tpu4_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) static const unsigned int tpu4_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) TPU4TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static const unsigned int tpu4_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) 58,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) static const unsigned int tpu4_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) TPU4TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static const unsigned int tpu4_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) PIN_A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static const unsigned int tpu4_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) TPU4TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) /* - USB -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) static const unsigned int usb_vbus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /* VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) static const unsigned int usb_vbus_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) VBUS_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) SH_PFC_PIN_GROUP(bsc_data_0_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) SH_PFC_PIN_GROUP(bsc_data_8_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) SH_PFC_PIN_GROUP(bsc_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) SH_PFC_PIN_GROUP(bsc_cs5_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) SH_PFC_PIN_GROUP(bsc_cs5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) SH_PFC_PIN_GROUP(bsc_cs6_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) SH_PFC_PIN_GROUP(bsc_cs6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) SH_PFC_PIN_GROUP(bsc_rd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) SH_PFC_PIN_GROUP(bsc_rdwr_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) SH_PFC_PIN_GROUP(bsc_rdwr_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) SH_PFC_PIN_GROUP(bsc_rdwr_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) SH_PFC_PIN_GROUP(bsc_we0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) SH_PFC_PIN_GROUP(bsc_we1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) SH_PFC_PIN_GROUP(fsia_mclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) SH_PFC_PIN_GROUP(fsia_mclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) SH_PFC_PIN_GROUP(fsia_sclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) SH_PFC_PIN_GROUP(fsia_sclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) SH_PFC_PIN_GROUP(fsia_data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) SH_PFC_PIN_GROUP(fsia_data_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) SH_PFC_PIN_GROUP(fsia_spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) SH_PFC_PIN_GROUP(fsib_mclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) SH_PFC_PIN_GROUP(fsib_mclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) SH_PFC_PIN_GROUP(fsib_sclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) SH_PFC_PIN_GROUP(fsib_sclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) SH_PFC_PIN_GROUP(fsib_data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) SH_PFC_PIN_GROUP(fsib_data_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) SH_PFC_PIN_GROUP(fsib_spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) SH_PFC_PIN_GROUP(fsic_mclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) SH_PFC_PIN_GROUP(fsic_mclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) SH_PFC_PIN_GROUP(fsic_sclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) SH_PFC_PIN_GROUP(fsic_sclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) SH_PFC_PIN_GROUP(fsic_data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) SH_PFC_PIN_GROUP(fsic_data_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) SH_PFC_PIN_GROUP(fsic_spdif_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) SH_PFC_PIN_GROUP(fsic_spdif_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) SH_PFC_PIN_GROUP(fsid_sclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) SH_PFC_PIN_GROUP(fsid_sclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) SH_PFC_PIN_GROUP(fsid_data_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) SH_PFC_PIN_GROUP(i2c2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) SH_PFC_PIN_GROUP(i2c2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) SH_PFC_PIN_GROUP(i2c2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) SH_PFC_PIN_GROUP(i2c3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) SH_PFC_PIN_GROUP(i2c3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) SH_PFC_PIN_GROUP(i2c3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) SH_PFC_PIN_GROUP(irda_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) SH_PFC_PIN_GROUP(irda_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) SH_PFC_PIN_GROUP(keysc_in5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) SH_PFC_PIN_GROUP(keysc_in6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) SH_PFC_PIN_GROUP(keysc_in7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) SH_PFC_PIN_GROUP(keysc_in8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) SH_PFC_PIN_GROUP(keysc_out04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) SH_PFC_PIN_GROUP(keysc_out5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) SH_PFC_PIN_GROUP(keysc_out6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) SH_PFC_PIN_GROUP(keysc_out6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) SH_PFC_PIN_GROUP(keysc_out6_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) SH_PFC_PIN_GROUP(keysc_out7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) SH_PFC_PIN_GROUP(keysc_out7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) SH_PFC_PIN_GROUP(keysc_out7_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) SH_PFC_PIN_GROUP(keysc_out8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) SH_PFC_PIN_GROUP(keysc_out8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) SH_PFC_PIN_GROUP(keysc_out8_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) SH_PFC_PIN_GROUP(keysc_out9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) SH_PFC_PIN_GROUP(keysc_out9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) SH_PFC_PIN_GROUP(keysc_out9_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) SH_PFC_PIN_GROUP(keysc_out10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) SH_PFC_PIN_GROUP(keysc_out10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) SH_PFC_PIN_GROUP(keysc_out11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) SH_PFC_PIN_GROUP(keysc_out11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) SH_PFC_PIN_GROUP(lcd_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) SH_PFC_PIN_GROUP(lcd_data9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) SH_PFC_PIN_GROUP(lcd_data12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) SH_PFC_PIN_GROUP(lcd_data16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) SH_PFC_PIN_GROUP(lcd_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) SH_PFC_PIN_GROUP(lcd_data24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) SH_PFC_PIN_GROUP(lcd_display),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) SH_PFC_PIN_GROUP(lcd_lclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) SH_PFC_PIN_GROUP(lcd_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) SH_PFC_PIN_GROUP(lcd_sys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) SH_PFC_PIN_GROUP(lcd2_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) SH_PFC_PIN_GROUP(lcd2_data9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) SH_PFC_PIN_GROUP(lcd2_data12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) SH_PFC_PIN_GROUP(lcd2_data16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) SH_PFC_PIN_GROUP(lcd2_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) SH_PFC_PIN_GROUP(lcd2_data24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) SH_PFC_PIN_GROUP(lcd2_sync_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) SH_PFC_PIN_GROUP(lcd2_sync_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) SH_PFC_PIN_GROUP(lcd2_sys_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) SH_PFC_PIN_GROUP(lcd2_sys_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) SH_PFC_PIN_GROUP(mmc0_data1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) SH_PFC_PIN_GROUP(mmc0_data4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) SH_PFC_PIN_GROUP(mmc0_data8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) SH_PFC_PIN_GROUP(mmc0_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) SH_PFC_PIN_GROUP(mmc0_data1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) SH_PFC_PIN_GROUP(mmc0_data4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) SH_PFC_PIN_GROUP(mmc0_data8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) SH_PFC_PIN_GROUP(mmc0_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) SH_PFC_PIN_GROUP(msiof0_rsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) SH_PFC_PIN_GROUP(msiof0_tsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) SH_PFC_PIN_GROUP(msiof0_rsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) SH_PFC_PIN_GROUP(msiof0_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) SH_PFC_PIN_GROUP(msiof0_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) SH_PFC_PIN_GROUP(msiof0_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) SH_PFC_PIN_GROUP(msiof0_mck0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) SH_PFC_PIN_GROUP(msiof0_mck1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) SH_PFC_PIN_GROUP(msiof0l_rsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) SH_PFC_PIN_GROUP(msiof0l_tsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) SH_PFC_PIN_GROUP(msiof0l_rsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) SH_PFC_PIN_GROUP(msiof0l_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) SH_PFC_PIN_GROUP(msiof0l_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) SH_PFC_PIN_GROUP(msiof0l_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) SH_PFC_PIN_GROUP(msiof0l_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) SH_PFC_PIN_GROUP(msiof0l_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) SH_PFC_PIN_GROUP(msiof0l_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) SH_PFC_PIN_GROUP(msiof0l_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) SH_PFC_PIN_GROUP(msiof0l_mck0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) SH_PFC_PIN_GROUP(msiof0l_mck1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) SH_PFC_PIN_GROUP(msiof1_rsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) SH_PFC_PIN_GROUP(msiof1_tsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) SH_PFC_PIN_GROUP(msiof1_rsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) SH_PFC_PIN_GROUP(msiof1_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) SH_PFC_PIN_GROUP(msiof1_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) SH_PFC_PIN_GROUP(msiof1_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) SH_PFC_PIN_GROUP(msiof1_mck0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) SH_PFC_PIN_GROUP(msiof1_mck1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) SH_PFC_PIN_GROUP(msiof2_rsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) SH_PFC_PIN_GROUP(msiof2_tsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) SH_PFC_PIN_GROUP(msiof2_rsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) SH_PFC_PIN_GROUP(msiof2_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) SH_PFC_PIN_GROUP(msiof2_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) SH_PFC_PIN_GROUP(msiof2_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) SH_PFC_PIN_GROUP(msiof2_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) SH_PFC_PIN_GROUP(msiof2_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) SH_PFC_PIN_GROUP(msiof2_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) SH_PFC_PIN_GROUP(msiof2_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) SH_PFC_PIN_GROUP(msiof2_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) SH_PFC_PIN_GROUP(msiof2_mck0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) SH_PFC_PIN_GROUP(msiof2_mck1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) SH_PFC_PIN_GROUP(msiof2r_tsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) SH_PFC_PIN_GROUP(msiof2r_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) SH_PFC_PIN_GROUP(msiof2r_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) SH_PFC_PIN_GROUP(msiof2r_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) SH_PFC_PIN_GROUP(msiof3_rsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) SH_PFC_PIN_GROUP(msiof3_tsck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) SH_PFC_PIN_GROUP(msiof3_rsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) SH_PFC_PIN_GROUP(msiof3_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) SH_PFC_PIN_GROUP(msiof3_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) SH_PFC_PIN_GROUP(msiof3_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) SH_PFC_PIN_GROUP(msiof3_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) SH_PFC_PIN_GROUP(msiof3_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) SH_PFC_PIN_GROUP(msiof3_flow),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) SH_PFC_PIN_GROUP(scifa0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) SH_PFC_PIN_GROUP(scifa0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) SH_PFC_PIN_GROUP(scifa0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) SH_PFC_PIN_GROUP(scifa1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) SH_PFC_PIN_GROUP(scifa1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) SH_PFC_PIN_GROUP(scifa1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) SH_PFC_PIN_GROUP(scifa2_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) SH_PFC_PIN_GROUP(scifa2_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) SH_PFC_PIN_GROUP(scifa2_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) SH_PFC_PIN_GROUP(scifa2_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) SH_PFC_PIN_GROUP(scifa2_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) SH_PFC_PIN_GROUP(scifa2_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) SH_PFC_PIN_GROUP(scifa3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) SH_PFC_PIN_GROUP(scifa3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) SH_PFC_PIN_GROUP(scifa4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) SH_PFC_PIN_GROUP(scifa4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) SH_PFC_PIN_GROUP(scifa5_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) SH_PFC_PIN_GROUP(scifa5_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) SH_PFC_PIN_GROUP(scifa5_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) SH_PFC_PIN_GROUP(scifa5_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) SH_PFC_PIN_GROUP(scifa5_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) SH_PFC_PIN_GROUP(scifa5_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) SH_PFC_PIN_GROUP(scifa5_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) SH_PFC_PIN_GROUP(scifa5_clk_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) SH_PFC_PIN_GROUP(scifa5_ctrl_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) SH_PFC_PIN_GROUP(scifa6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) SH_PFC_PIN_GROUP(scifa7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) SH_PFC_PIN_GROUP(scifa7_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) SH_PFC_PIN_GROUP(scifb_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) SH_PFC_PIN_GROUP(scifb_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) SH_PFC_PIN_GROUP(scifb_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) SH_PFC_PIN_GROUP(scifb_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) SH_PFC_PIN_GROUP(scifb_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) SH_PFC_PIN_GROUP(scifb_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) SH_PFC_PIN_GROUP(tpu0_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) SH_PFC_PIN_GROUP(tpu0_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) SH_PFC_PIN_GROUP(tpu0_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) SH_PFC_PIN_GROUP(tpu0_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) SH_PFC_PIN_GROUP(tpu1_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) SH_PFC_PIN_GROUP(tpu1_to1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) SH_PFC_PIN_GROUP(tpu1_to1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) SH_PFC_PIN_GROUP(tpu1_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) SH_PFC_PIN_GROUP(tpu1_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) SH_PFC_PIN_GROUP(tpu2_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) SH_PFC_PIN_GROUP(tpu2_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) SH_PFC_PIN_GROUP(tpu2_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) SH_PFC_PIN_GROUP(tpu2_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) SH_PFC_PIN_GROUP(tpu3_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) SH_PFC_PIN_GROUP(tpu3_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) SH_PFC_PIN_GROUP(tpu3_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) SH_PFC_PIN_GROUP(tpu3_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) SH_PFC_PIN_GROUP(tpu4_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) SH_PFC_PIN_GROUP(tpu4_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) SH_PFC_PIN_GROUP(tpu4_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) SH_PFC_PIN_GROUP(tpu4_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) SH_PFC_PIN_GROUP(usb_vbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) static const char * const bsc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) "bsc_data_0_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) "bsc_data_8_15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) "bsc_cs4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) "bsc_cs5_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) "bsc_cs5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) "bsc_cs6_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) "bsc_cs6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) "bsc_rd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) "bsc_rdwr_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) "bsc_rdwr_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) "bsc_rdwr_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) "bsc_we0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) "bsc_we1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) static const char * const fsia_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) "fsia_mclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) "fsia_mclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) "fsia_sclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) "fsia_sclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) "fsia_data_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) "fsia_data_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) "fsia_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) static const char * const fsib_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) "fsib_mclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) "fsib_mclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) "fsib_sclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) "fsib_sclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) "fsib_data_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) "fsib_data_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) "fsib_spdif",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) static const char * const fsic_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) "fsic_mclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) "fsic_mclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) "fsic_sclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) "fsic_sclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) "fsic_data_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) "fsic_data_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) "fsic_spdif_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) "fsic_spdif_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) static const char * const fsid_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) "fsid_sclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) "fsid_sclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) "fsid_data_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) "i2c2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) "i2c2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) "i2c2_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) "i2c3_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) "i2c3_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) "i2c3_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) static const char * const irda_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) "irda_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) "irda_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) static const char * const keysc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) "keysc_in5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) "keysc_in6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) "keysc_in7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) "keysc_in8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) "keysc_out04",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) "keysc_out5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) "keysc_out6_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) "keysc_out6_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) "keysc_out6_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) "keysc_out7_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) "keysc_out7_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) "keysc_out7_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) "keysc_out8_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) "keysc_out8_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) "keysc_out8_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) "keysc_out9_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) "keysc_out9_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) "keysc_out9_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) "keysc_out10_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) "keysc_out10_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) "keysc_out11_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) "keysc_out11_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) static const char * const lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) "lcd_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) "lcd_data9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) "lcd_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) "lcd_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) "lcd_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) "lcd_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) "lcd_display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) "lcd_lclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) "lcd_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) "lcd_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) static const char * const lcd2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) "lcd2_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) "lcd2_data9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) "lcd2_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) "lcd2_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) "lcd2_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) "lcd2_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) "lcd2_sync_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) "lcd2_sync_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) "lcd2_sys_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) "lcd2_sys_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) static const char * const mmc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) "mmc0_data1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) "mmc0_data4_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) "mmc0_data8_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) "mmc0_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) "mmc0_data1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) "mmc0_data4_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) "mmc0_data8_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) "mmc0_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) "msiof0_rsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) "msiof0_tsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) "msiof0_rsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) "msiof0_tsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) "msiof0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) "msiof0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) "msiof0_mck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) "msiof0_mck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) "msiof0l_rsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) "msiof0l_tsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) "msiof0l_rsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) "msiof0l_tsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) "msiof0l_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) "msiof0l_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) "msiof0l_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) "msiof0l_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) "msiof0l_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) "msiof0l_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) "msiof0l_mck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) "msiof0l_mck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) "msiof1_rsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) "msiof1_tsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) "msiof1_rsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) "msiof1_tsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) "msiof1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) "msiof1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) "msiof1_mck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) "msiof1_mck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) "msiof2_rsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) "msiof2_tsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) "msiof2_rsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) "msiof2_tsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) "msiof2_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) "msiof2_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) "msiof2_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) "msiof2_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) "msiof2_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) "msiof2_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) "msiof2_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) "msiof2_mck0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) "msiof2_mck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) "msiof2r_tsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) "msiof2r_tsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) "msiof2r_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) "msiof2r_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) "msiof3_rsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) "msiof3_tsck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) "msiof3_rsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) "msiof3_tsync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) "msiof3_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) "msiof3_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) "msiof3_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) "msiof3_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) "msiof3_flow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) static const char * const scifa0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) "scifa0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) "scifa0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) "scifa0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) static const char * const scifa1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) "scifa1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) "scifa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) "scifa1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) static const char * const scifa2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) "scifa2_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) "scifa2_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) "scifa2_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) "scifa2_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) "scifa2_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) "scifa2_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) static const char * const scifa3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) "scifa3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) "scifa3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) static const char * const scifa4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) "scifa4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) "scifa4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) static const char * const scifa5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) "scifa5_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) "scifa5_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) "scifa5_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) "scifa5_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) "scifa5_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) "scifa5_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) "scifa5_data_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) "scifa5_clk_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) "scifa5_ctrl_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) static const char * const scifa6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) "scifa6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) static const char * const scifa7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) "scifa7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) "scifa7_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) static const char * const scifb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) "scifb_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) "scifb_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) "scifb_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) "scifb_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) "scifb_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) "scifb_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static const char * const usb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) "usb_vbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) static const char * const tpu0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) "tpu0_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) "tpu0_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) "tpu0_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) "tpu0_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) static const char * const tpu1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) "tpu1_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) "tpu1_to1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) "tpu1_to1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) "tpu1_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) "tpu1_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) static const char * const tpu2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) "tpu2_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) "tpu2_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) "tpu2_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) "tpu2_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) static const char * const tpu3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) "tpu3_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) "tpu3_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) "tpu3_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) "tpu3_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) static const char * const tpu4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) "tpu4_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) "tpu4_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) "tpu4_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) "tpu4_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) SH_PFC_FUNCTION(bsc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) SH_PFC_FUNCTION(fsia),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) SH_PFC_FUNCTION(fsib),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) SH_PFC_FUNCTION(fsic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) SH_PFC_FUNCTION(fsid),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) SH_PFC_FUNCTION(irda),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) SH_PFC_FUNCTION(keysc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) SH_PFC_FUNCTION(lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) SH_PFC_FUNCTION(lcd2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) SH_PFC_FUNCTION(mmc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) SH_PFC_FUNCTION(scifa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) SH_PFC_FUNCTION(scifa1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) SH_PFC_FUNCTION(scifa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) SH_PFC_FUNCTION(scifa3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) SH_PFC_FUNCTION(scifa4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) SH_PFC_FUNCTION(scifa5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) SH_PFC_FUNCTION(scifa6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) SH_PFC_FUNCTION(scifa7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) SH_PFC_FUNCTION(scifb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) SH_PFC_FUNCTION(tpu0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) SH_PFC_FUNCTION(tpu1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) SH_PFC_FUNCTION(tpu2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) SH_PFC_FUNCTION(tpu3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) SH_PFC_FUNCTION(tpu4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) SH_PFC_FUNCTION(usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) PORTCR(0, 0xe6050000), /* PORT0CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) PORTCR(1, 0xe6050001), /* PORT1CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) PORTCR(2, 0xe6050002), /* PORT2CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) PORTCR(3, 0xe6050003), /* PORT3CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) PORTCR(4, 0xe6050004), /* PORT4CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) PORTCR(5, 0xe6050005), /* PORT5CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) PORTCR(6, 0xe6050006), /* PORT6CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) PORTCR(7, 0xe6050007), /* PORT7CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) PORTCR(8, 0xe6050008), /* PORT8CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) PORTCR(9, 0xe6050009), /* PORT9CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) PORTCR(10, 0xe605000a), /* PORT10CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) PORTCR(11, 0xe605000b), /* PORT11CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) PORTCR(12, 0xe605000c), /* PORT12CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) PORTCR(13, 0xe605000d), /* PORT13CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) PORTCR(14, 0xe605000e), /* PORT14CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) PORTCR(15, 0xe605000f), /* PORT15CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) PORTCR(16, 0xe6050010), /* PORT16CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) PORTCR(17, 0xe6050011), /* PORT17CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) PORTCR(18, 0xe6050012), /* PORT18CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) PORTCR(19, 0xe6050013), /* PORT19CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) PORTCR(20, 0xe6050014), /* PORT20CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) PORTCR(21, 0xe6050015), /* PORT21CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) PORTCR(22, 0xe6050016), /* PORT22CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) PORTCR(23, 0xe6050017), /* PORT23CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) PORTCR(24, 0xe6050018), /* PORT24CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) PORTCR(25, 0xe6050019), /* PORT25CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) PORTCR(26, 0xe605001a), /* PORT26CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) PORTCR(27, 0xe605001b), /* PORT27CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) PORTCR(28, 0xe605001c), /* PORT28CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) PORTCR(29, 0xe605001d), /* PORT29CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) PORTCR(30, 0xe605001e), /* PORT30CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) PORTCR(31, 0xe605001f), /* PORT31CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) PORTCR(32, 0xe6051020), /* PORT32CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) PORTCR(33, 0xe6051021), /* PORT33CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) PORTCR(34, 0xe6051022), /* PORT34CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) PORTCR(35, 0xe6051023), /* PORT35CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) PORTCR(36, 0xe6051024), /* PORT36CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) PORTCR(37, 0xe6051025), /* PORT37CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) PORTCR(38, 0xe6051026), /* PORT38CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) PORTCR(39, 0xe6051027), /* PORT39CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) PORTCR(40, 0xe6051028), /* PORT40CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) PORTCR(41, 0xe6051029), /* PORT41CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) PORTCR(42, 0xe605102a), /* PORT42CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) PORTCR(43, 0xe605102b), /* PORT43CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) PORTCR(44, 0xe605102c), /* PORT44CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) PORTCR(45, 0xe605102d), /* PORT45CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) PORTCR(46, 0xe605102e), /* PORT46CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) PORTCR(47, 0xe605102f), /* PORT47CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) PORTCR(48, 0xe6051030), /* PORT48CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) PORTCR(49, 0xe6051031), /* PORT49CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) PORTCR(50, 0xe6051032), /* PORT50CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) PORTCR(51, 0xe6051033), /* PORT51CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) PORTCR(52, 0xe6051034), /* PORT52CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) PORTCR(53, 0xe6051035), /* PORT53CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) PORTCR(54, 0xe6051036), /* PORT54CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) PORTCR(55, 0xe6051037), /* PORT55CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) PORTCR(56, 0xe6051038), /* PORT56CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) PORTCR(57, 0xe6051039), /* PORT57CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) PORTCR(58, 0xe605103a), /* PORT58CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) PORTCR(59, 0xe605103b), /* PORT59CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) PORTCR(60, 0xe605103c), /* PORT60CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) PORTCR(61, 0xe605103d), /* PORT61CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) PORTCR(62, 0xe605103e), /* PORT62CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) PORTCR(63, 0xe605103f), /* PORT63CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) PORTCR(64, 0xe6051040), /* PORT64CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) PORTCR(65, 0xe6051041), /* PORT65CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) PORTCR(66, 0xe6051042), /* PORT66CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) PORTCR(67, 0xe6051043), /* PORT67CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) PORTCR(68, 0xe6051044), /* PORT68CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) PORTCR(69, 0xe6051045), /* PORT69CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) PORTCR(70, 0xe6051046), /* PORT70CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) PORTCR(71, 0xe6051047), /* PORT71CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) PORTCR(72, 0xe6051048), /* PORT72CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) PORTCR(73, 0xe6051049), /* PORT73CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) PORTCR(74, 0xe605104a), /* PORT74CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) PORTCR(75, 0xe605104b), /* PORT75CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) PORTCR(76, 0xe605104c), /* PORT76CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) PORTCR(77, 0xe605104d), /* PORT77CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) PORTCR(78, 0xe605104e), /* PORT78CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) PORTCR(79, 0xe605104f), /* PORT79CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) PORTCR(80, 0xe6051050), /* PORT80CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) PORTCR(81, 0xe6051051), /* PORT81CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) PORTCR(82, 0xe6051052), /* PORT82CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) PORTCR(83, 0xe6051053), /* PORT83CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) PORTCR(84, 0xe6051054), /* PORT84CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) PORTCR(85, 0xe6051055), /* PORT85CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) PORTCR(86, 0xe6051056), /* PORT86CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) PORTCR(87, 0xe6051057), /* PORT87CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) PORTCR(88, 0xe6051058), /* PORT88CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) PORTCR(89, 0xe6051059), /* PORT89CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) PORTCR(90, 0xe605105a), /* PORT90CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) PORTCR(91, 0xe605105b), /* PORT91CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) PORTCR(92, 0xe605105c), /* PORT92CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) PORTCR(93, 0xe605105d), /* PORT93CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) PORTCR(94, 0xe605105e), /* PORT94CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) PORTCR(95, 0xe605105f), /* PORT95CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) PORTCR(96, 0xe6052060), /* PORT96CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) PORTCR(97, 0xe6052061), /* PORT97CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) PORTCR(98, 0xe6052062), /* PORT98CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) PORTCR(99, 0xe6052063), /* PORT99CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) PORTCR(100, 0xe6052064), /* PORT100CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) PORTCR(101, 0xe6052065), /* PORT101CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) PORTCR(102, 0xe6052066), /* PORT102CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) PORTCR(103, 0xe6052067), /* PORT103CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) PORTCR(104, 0xe6052068), /* PORT104CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) PORTCR(105, 0xe6052069), /* PORT105CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) PORTCR(106, 0xe605206a), /* PORT106CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) PORTCR(107, 0xe605206b), /* PORT107CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) PORTCR(108, 0xe605206c), /* PORT108CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) PORTCR(109, 0xe605206d), /* PORT109CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) PORTCR(110, 0xe605206e), /* PORT110CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) PORTCR(111, 0xe605206f), /* PORT111CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) PORTCR(112, 0xe6052070), /* PORT112CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) PORTCR(113, 0xe6052071), /* PORT113CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) PORTCR(114, 0xe6052072), /* PORT114CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) PORTCR(115, 0xe6052073), /* PORT115CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) PORTCR(116, 0xe6052074), /* PORT116CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) PORTCR(117, 0xe6052075), /* PORT117CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) PORTCR(118, 0xe6052076), /* PORT118CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) PORTCR(128, 0xe6052080), /* PORT128CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) PORTCR(129, 0xe6052081), /* PORT129CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) PORTCR(130, 0xe6052082), /* PORT130CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) PORTCR(131, 0xe6052083), /* PORT131CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) PORTCR(132, 0xe6052084), /* PORT132CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) PORTCR(133, 0xe6052085), /* PORT133CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) PORTCR(134, 0xe6052086), /* PORT134CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) PORTCR(135, 0xe6052087), /* PORT135CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) PORTCR(136, 0xe6052088), /* PORT136CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) PORTCR(137, 0xe6052089), /* PORT137CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) PORTCR(138, 0xe605208a), /* PORT138CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) PORTCR(139, 0xe605208b), /* PORT139CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) PORTCR(140, 0xe605208c), /* PORT140CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) PORTCR(141, 0xe605208d), /* PORT141CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) PORTCR(142, 0xe605208e), /* PORT142CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) PORTCR(143, 0xe605208f), /* PORT143CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) PORTCR(144, 0xe6052090), /* PORT144CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) PORTCR(145, 0xe6052091), /* PORT145CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) PORTCR(146, 0xe6052092), /* PORT146CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) PORTCR(147, 0xe6052093), /* PORT147CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) PORTCR(148, 0xe6052094), /* PORT148CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) PORTCR(149, 0xe6052095), /* PORT149CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) PORTCR(150, 0xe6052096), /* PORT150CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) PORTCR(151, 0xe6052097), /* PORT151CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) PORTCR(152, 0xe6052098), /* PORT152CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) PORTCR(153, 0xe6052099), /* PORT153CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) PORTCR(154, 0xe605209a), /* PORT154CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) PORTCR(155, 0xe605209b), /* PORT155CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) PORTCR(156, 0xe605209c), /* PORT156CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) PORTCR(157, 0xe605209d), /* PORT157CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) PORTCR(158, 0xe605209e), /* PORT158CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) PORTCR(159, 0xe605209f), /* PORT159CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) PORTCR(160, 0xe60520a0), /* PORT160CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) PORTCR(161, 0xe60520a1), /* PORT161CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) PORTCR(162, 0xe60520a2), /* PORT162CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) PORTCR(163, 0xe60520a3), /* PORT163CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) PORTCR(164, 0xe60520a4), /* PORT164CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) PORTCR(192, 0xe60520c0), /* PORT192CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) PORTCR(193, 0xe60520c1), /* PORT193CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) PORTCR(194, 0xe60520c2), /* PORT194CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) PORTCR(195, 0xe60520c3), /* PORT195CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) PORTCR(196, 0xe60520c4), /* PORT196CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) PORTCR(197, 0xe60520c5), /* PORT197CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) PORTCR(198, 0xe60520c6), /* PORT198CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) PORTCR(199, 0xe60520c7), /* PORT199CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) PORTCR(200, 0xe60520c8), /* PORT200CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) PORTCR(201, 0xe60520c9), /* PORT201CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) PORTCR(202, 0xe60520ca), /* PORT202CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) PORTCR(203, 0xe60520cb), /* PORT203CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) PORTCR(204, 0xe60520cc), /* PORT204CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) PORTCR(205, 0xe60520cd), /* PORT205CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) PORTCR(206, 0xe60520ce), /* PORT206CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) PORTCR(207, 0xe60520cf), /* PORT207CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) PORTCR(208, 0xe60520d0), /* PORT208CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) PORTCR(209, 0xe60520d1), /* PORT209CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) PORTCR(210, 0xe60520d2), /* PORT210CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) PORTCR(211, 0xe60520d3), /* PORT211CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) PORTCR(212, 0xe60520d4), /* PORT212CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) PORTCR(213, 0xe60520d5), /* PORT213CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) PORTCR(214, 0xe60520d6), /* PORT214CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) PORTCR(215, 0xe60520d7), /* PORT215CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) PORTCR(216, 0xe60520d8), /* PORT216CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) PORTCR(217, 0xe60520d9), /* PORT217CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) PORTCR(218, 0xe60520da), /* PORT218CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) PORTCR(219, 0xe60520db), /* PORT219CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) PORTCR(220, 0xe60520dc), /* PORT220CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) PORTCR(221, 0xe60520dd), /* PORT221CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) PORTCR(222, 0xe60520de), /* PORT222CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) PORTCR(223, 0xe60520df), /* PORT223CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) PORTCR(224, 0xe60530e0), /* PORT224CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) PORTCR(225, 0xe60530e1), /* PORT225CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) PORTCR(226, 0xe60530e2), /* PORT226CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) PORTCR(227, 0xe60530e3), /* PORT227CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) PORTCR(228, 0xe60530e4), /* PORT228CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) PORTCR(229, 0xe60530e5), /* PORT229CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) PORTCR(230, 0xe60530e6), /* PORT230CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) PORTCR(231, 0xe60530e7), /* PORT231CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) PORTCR(232, 0xe60530e8), /* PORT232CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) PORTCR(233, 0xe60530e9), /* PORT233CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) PORTCR(234, 0xe60530ea), /* PORT234CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) PORTCR(235, 0xe60530eb), /* PORT235CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) PORTCR(236, 0xe60530ec), /* PORT236CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) PORTCR(237, 0xe60530ed), /* PORT237CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) PORTCR(238, 0xe60530ee), /* PORT238CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) PORTCR(239, 0xe60530ef), /* PORT239CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) PORTCR(240, 0xe60530f0), /* PORT240CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) PORTCR(241, 0xe60530f1), /* PORT241CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) PORTCR(242, 0xe60530f2), /* PORT242CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) PORTCR(243, 0xe60530f3), /* PORT243CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) PORTCR(244, 0xe60530f4), /* PORT244CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) PORTCR(245, 0xe60530f5), /* PORT245CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) PORTCR(246, 0xe60530f6), /* PORT246CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) PORTCR(247, 0xe60530f7), /* PORT247CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) PORTCR(248, 0xe60530f8), /* PORT248CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) PORTCR(249, 0xe60530f9), /* PORT249CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) PORTCR(250, 0xe60530fa), /* PORT250CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) PORTCR(251, 0xe60530fb), /* PORT251CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) PORTCR(252, 0xe60530fc), /* PORT252CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) PORTCR(253, 0xe60530fd), /* PORT253CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) PORTCR(254, 0xe60530fe), /* PORT254CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) PORTCR(255, 0xe60530ff), /* PORT255CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) PORTCR(256, 0xe6053100), /* PORT256CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) PORTCR(257, 0xe6053101), /* PORT257CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) PORTCR(258, 0xe6053102), /* PORT258CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) PORTCR(259, 0xe6053103), /* PORT259CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) PORTCR(260, 0xe6053104), /* PORT260CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) PORTCR(261, 0xe6053105), /* PORT261CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) PORTCR(262, 0xe6053106), /* PORT262CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) PORTCR(263, 0xe6053107), /* PORT263CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) PORTCR(264, 0xe6053108), /* PORT264CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) PORTCR(265, 0xe6053109), /* PORT265CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) PORTCR(266, 0xe605310a), /* PORT266CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) PORTCR(267, 0xe605310b), /* PORT267CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) PORTCR(268, 0xe605310c), /* PORT268CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) PORTCR(269, 0xe605310d), /* PORT269CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) PORTCR(270, 0xe605310e), /* PORT270CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) PORTCR(271, 0xe605310f), /* PORT271CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) PORTCR(272, 0xe6053110), /* PORT272CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) PORTCR(273, 0xe6053111), /* PORT273CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) PORTCR(274, 0xe6053112), /* PORT274CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) PORTCR(275, 0xe6053113), /* PORT275CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) PORTCR(276, 0xe6053114), /* PORT276CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) PORTCR(277, 0xe6053115), /* PORT277CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) PORTCR(278, 0xe6053116), /* PORT278CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) PORTCR(279, 0xe6053117), /* PORT279CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) PORTCR(280, 0xe6053118), /* PORT280CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) PORTCR(281, 0xe6053119), /* PORT281CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) PORTCR(282, 0xe605311a), /* PORT282CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) PORTCR(288, 0xe6052120), /* PORT288CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) PORTCR(289, 0xe6052121), /* PORT289CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) PORTCR(290, 0xe6052122), /* PORT290CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) PORTCR(291, 0xe6052123), /* PORT291CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) PORTCR(292, 0xe6052124), /* PORT292CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) PORTCR(293, 0xe6052125), /* PORT293CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) PORTCR(294, 0xe6052126), /* PORT294CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) PORTCR(295, 0xe6052127), /* PORT295CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) PORTCR(296, 0xe6052128), /* PORT296CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) PORTCR(297, 0xe6052129), /* PORT297CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) PORTCR(298, 0xe605212a), /* PORT298CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) PORTCR(299, 0xe605212b), /* PORT299CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) PORTCR(300, 0xe605212c), /* PORT300CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) PORTCR(301, 0xe605212d), /* PORT301CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) PORTCR(302, 0xe605212e), /* PORT302CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) PORTCR(303, 0xe605212f), /* PORT303CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) PORTCR(304, 0xe6052130), /* PORT304CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) PORTCR(305, 0xe6052131), /* PORT305CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) PORTCR(306, 0xe6052132), /* PORT306CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) PORTCR(307, 0xe6052133), /* PORT307CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) PORTCR(308, 0xe6052134), /* PORT308CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) PORTCR(309, 0xe6052135), /* PORT309CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) static const struct pinmux_data_reg pinmux_data_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) 0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) 0, 0, 0, PORT164_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) 0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) 0, 0, PORT309_DATA, PORT308_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) static const struct pinmux_irq pinmux_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) PINMUX_IRQ(11), /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) PINMUX_IRQ(10), /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) PINMUX_IRQ(149), /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) PINMUX_IRQ(224), /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) PINMUX_IRQ(159), /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) PINMUX_IRQ(227), /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) PINMUX_IRQ(147), /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) PINMUX_IRQ(150), /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) PINMUX_IRQ(223), /* IRQ8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) PINMUX_IRQ(56, 308), /* IRQ9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) PINMUX_IRQ(54), /* IRQ10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) PINMUX_IRQ(238), /* IRQ11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) PINMUX_IRQ(156), /* IRQ12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) PINMUX_IRQ(239), /* IRQ13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) PINMUX_IRQ(251), /* IRQ14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) PINMUX_IRQ(0), /* IRQ15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) PINMUX_IRQ(249), /* IRQ16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) PINMUX_IRQ(234), /* IRQ17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) PINMUX_IRQ(13), /* IRQ18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) PINMUX_IRQ(9), /* IRQ19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) PINMUX_IRQ(14), /* IRQ20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) PINMUX_IRQ(15), /* IRQ21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) PINMUX_IRQ(40), /* IRQ22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) PINMUX_IRQ(53), /* IRQ23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) PINMUX_IRQ(118), /* IRQ24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) PINMUX_IRQ(164), /* IRQ25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) PINMUX_IRQ(115), /* IRQ26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) PINMUX_IRQ(116), /* IRQ27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) PINMUX_IRQ(117), /* IRQ28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) PINMUX_IRQ(28), /* IRQ29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) PINMUX_IRQ(27), /* IRQ30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) PINMUX_IRQ(26), /* IRQ31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) * VCCQ MC0 regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) struct sh_pfc *pfc = reg->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) void __iomem *addr = pfc->windows[1].virt + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) value = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) value |= BIT(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) value &= ~BIT(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) iowrite32(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) sh73a0_vccq_mc0_endisable(reg, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) sh73a0_vccq_mc0_endisable(reg, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) struct sh_pfc *pfc = reg->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) void __iomem *addr = pfc->windows[1].virt + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) value = ioread32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) return !!(value & BIT(28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) return 3300000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) static struct regulator_ops sh73a0_vccq_mc0_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) .enable = sh73a0_vccq_mc0_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) .disable = sh73a0_vccq_mc0_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) .is_enabled = sh73a0_vccq_mc0_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) .get_voltage = sh73a0_vccq_mc0_get_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) static const struct regulator_desc sh73a0_vccq_mc0_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) .name = "vccq_mc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) .ops = &sh73a0_vccq_mc0_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) .constraints = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) .valid_ops_mask = REGULATOR_CHANGE_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) .consumer_supplies = sh73a0_vccq_mc0_consumers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) * Pin bias
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) #define PORTnCR_PULMD_OFF (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) #define PORTnCR_PULMD_DOWN (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) #define PORTnCR_PULMD_UP (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) #define PORTnCR_PULMD_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) static const unsigned int sh73a0_portcr_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) void __iomem *addr = pfc->windows->virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) + sh73a0_portcr_offsets[pin >> 5] + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) case PORTnCR_PULMD_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) return PIN_CONFIG_BIAS_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) case PORTnCR_PULMD_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) return PIN_CONFIG_BIAS_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) case PORTnCR_PULMD_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) unsigned int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) void __iomem *addr = pfc->windows->virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) + sh73a0_portcr_offsets[pin >> 5] + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) switch (bias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) value |= PORTnCR_PULMD_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) value |= PORTnCR_PULMD_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) iowrite8(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) * SoC information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) struct regulator_config cfg = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) struct regulator_dev *vccq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) cfg.dev = pfc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) cfg.init_data = &sh73a0_vccq_mc0_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) cfg.driver_data = pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) vccq = devm_regulator_register(pfc->dev, &sh73a0_vccq_mc0_desc, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) if (IS_ERR(vccq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) ret = PTR_ERR(vccq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) static const struct sh_pfc_soc_operations sh73a0_pfc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) .init = sh73a0_pinmux_soc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) .get_bias = sh73a0_pinmux_get_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) .set_bias = sh73a0_pinmux_set_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) const struct sh_pfc_soc_info sh73a0_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) .name = "sh73a0_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) .ops = &sh73a0_pfc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) .data_regs = pinmux_data_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) .gpio_irq = pinmux_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags