^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A77995 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * R-Car Gen3 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_GP_9(0, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_GP_32(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_32(2, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_32(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_21(5, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_14(6, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * F_() : just information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * FM() : macro for FN_xxx / xxx_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPSR0_8 F_(MLB_SIG, IP0_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPSR0_7 F_(MLB_DAT, IP0_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPSR0_6 F_(MLB_CLK, IP0_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPSR0_2 F_(IRQ0_A, IP0_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPSR0_1 FM(USB0_OVC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPSR0_0 FM(USB0_PWEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPSR1_31 F_(QPOLB, IP4_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPSR1_30 F_(QPOLA, IP4_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPSR1_29 F_(DU_CDE, IP4_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPSR1_27 F_(DU_DISP, IP4_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPSR1_26 F_(DU_VSYNC, IP4_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPSR1_25 F_(DU_HSYNC, IP4_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPSR1_23 F_(DU_DR7, IP3_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPSR1_22 F_(DU_DR6, IP3_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPSR1_21 F_(DU_DR5, IP3_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPSR1_20 F_(DU_DR4, IP3_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GPSR1_19 F_(DU_DR3, IP3_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPSR1_18 F_(DU_DR2, IP3_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPSR1_17 F_(DU_DR1, IP3_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPSR1_16 F_(DU_DR0, IP2_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPSR1_15 F_(DU_DG7, IP2_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPSR1_14 F_(DU_DG6, IP2_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPSR1_13 F_(DU_DG5, IP2_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPSR1_12 F_(DU_DG4, IP2_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPSR1_11 F_(DU_DG3, IP2_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPSR1_10 F_(DU_DG2, IP2_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPSR1_9 F_(DU_DG1, IP2_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPSR1_8 F_(DU_DG0, IP1_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPSR1_7 F_(DU_DB7, IP1_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPSR1_6 F_(DU_DB6, IP1_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPSR1_5 F_(DU_DB5, IP1_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GPSR1_4 F_(DU_DB4, IP1_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPSR1_3 F_(DU_DB3, IP1_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPSR1_2 F_(DU_DB2, IP1_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPSR1_1 F_(DU_DB1, IP1_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPSR1_0 F_(DU_DB0, IP0_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPSR2_31 F_(NFCE_N, IP8_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPSR2_30 F_(NFCLE, IP8_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPSR2_29 F_(NFALE, IP8_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPSR2_27 F_(VI4_FIELD, IP8_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GPSR2_24 F_(VI4_DATA23, IP7_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GPSR2_23 F_(VI4_DATA22, IP7_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GPSR2_22 F_(VI4_DATA21, IP7_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPSR2_21 F_(VI4_DATA20, IP7_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPSR2_20 F_(VI4_DATA19, IP7_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GPSR2_19 F_(VI4_DATA18, IP7_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GPSR2_18 F_(VI4_DATA17, IP6_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPSR2_17 F_(VI4_DATA16, IP6_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GPSR2_16 F_(VI4_DATA15, IP6_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPSR2_15 F_(VI4_DATA14, IP6_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPSR2_14 F_(VI4_DATA13, IP6_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPSR2_13 F_(VI4_DATA12, IP6_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPSR2_12 F_(VI4_DATA11, IP6_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPSR2_11 F_(VI4_DATA10, IP6_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPSR2_10 F_(VI4_DATA9, IP5_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPSR2_9 F_(VI4_DATA8, IP5_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPSR2_8 F_(VI4_DATA7, IP5_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPSR2_7 F_(VI4_DATA6, IP5_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPSR2_6 F_(VI4_DATA5, IP5_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPSR2_5 FM(VI4_DATA4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GPSR2_4 F_(VI4_DATA3, IP5_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPSR2_3 F_(VI4_DATA2, IP5_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GPSR2_2 F_(VI4_DATA1, IP5_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPSR2_1 F_(VI4_DATA0, IP4_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPSR2_0 FM(VI4_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPSR3_9 F_(NFDATA7, IP9_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPSR3_8 F_(NFDATA6, IP9_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPSR3_7 F_(NFDATA5, IP9_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPSR3_6 F_(NFDATA4, IP9_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GPSR3_5 F_(NFDATA3, IP9_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPSR3_4 F_(NFDATA2, IP9_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GPSR3_3 F_(NFDATA1, IP9_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPSR3_2 F_(NFDATA0, IP9_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPSR3_1 F_(NFWE_N, IP8_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPSR3_0 F_(NFRE_N, IP8_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPSR4_27 FM(TX2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPSR4_26 FM(RX2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPSR4_25 F_(SCK2, IP12_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPSR4_24 F_(TX1_A, IP12_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPSR4_23 F_(RX1_A, IP12_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPSR4_22 F_(SCK1_A, IP11_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPSR4_21 F_(TX0_A, IP11_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPSR4_20 F_(RX0_A, IP11_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPSR4_19 F_(SCK0_A, IP11_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPSR4_15 FM(MSIOF0_RXD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPSR4_14 FM(MSIOF0_TXD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPSR4_13 FM(MSIOF0_SYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPSR4_12 FM(MSIOF0_SCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPSR4_11 F_(SDA1, IP11_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPSR4_10 F_(SCL1, IP10_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPSR4_9 FM(SDA0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPSR4_8 FM(SCL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GPSR4_4 F_(SSI_WS34, IP10_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GPSR4_2 F_(SSI_SCK34, IP10_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GPSR4_0 F_(NFRB_N, IP8_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPSR5_20 FM(AVB0_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPSR5_19 FM(AVB0_PHY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPSR5_18 FM(AVB0_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GPSR5_17 FM(AVB0_MDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GPSR5_16 FM(AVB0_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GPSR5_15 FM(AVB0_TXCREFCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GPSR5_14 FM(AVB0_TD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GPSR5_13 FM(AVB0_TD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GPSR5_12 FM(AVB0_TD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GPSR5_11 FM(AVB0_TD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GPSR5_10 FM(AVB0_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GPSR5_9 FM(AVB0_TX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GPSR5_8 FM(AVB0_RD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GPSR5_7 FM(AVB0_RD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GPSR5_6 FM(AVB0_RD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GPSR5_5 FM(AVB0_RD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GPSR5_4 FM(AVB0_RXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GPSR5_3 FM(AVB0_RX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GPSR5_2 F_(CAN_CLK, IP12_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* GPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GPSR6_13 FM(RPC_INT_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GPSR6_12 FM(RPC_RESET_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GPSR6_11 FM(QSPI1_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GPSR6_10 FM(QSPI1_IO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GPSR6_9 FM(QSPI1_IO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GPSR6_8 FM(QSPI1_MISO_IO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GPSR6_7 FM(QSPI1_MOSI_IO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPSR6_6 FM(QSPI1_SPCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GPSR6_5 FM(QSPI0_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GPSR6_4 FM(QSPI0_IO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GPSR6_3 FM(QSPI0_IO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GPSR6_2 FM(QSPI0_MISO_IO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GPSR6_1 FM(QSPI0_MOSI_IO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GPSR6_0 FM(QSPI0_SPCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PINMUX_GPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) GPSR1_31 GPSR2_31 GPSR4_31 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) GPSR1_30 GPSR2_30 GPSR4_30 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) GPSR1_29 GPSR2_29 GPSR4_29 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) GPSR1_28 GPSR2_28 GPSR4_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) GPSR1_27 GPSR2_27 GPSR4_27 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) GPSR1_26 GPSR2_26 GPSR4_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) GPSR1_25 GPSR2_25 GPSR4_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) GPSR1_24 GPSR2_24 GPSR4_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) GPSR1_23 GPSR2_23 GPSR4_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) GPSR1_22 GPSR2_22 GPSR4_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) GPSR1_21 GPSR2_21 GPSR4_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PINMUX_IPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FM(IP12_11_8) IP12_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FM(IP12_15_12) IP12_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FM(IP12_19_16) IP12_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FM(IP12_23_20) IP12_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FM(IP12_27_24) IP12_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FM(IP12_31_28) IP12_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* The bit numbering in MOD_SEL fields is reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PINMUX_MOD_SELS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MOD_SEL1_31 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) MOD_SEL0_30 MOD_SEL1_30 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MOD_SEL0_29 MOD_SEL1_29 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MOD_SEL0_28 MOD_SEL1_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MOD_SEL0_27 MOD_SEL1_27 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MOD_SEL0_26 MOD_SEL1_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MOD_SEL0_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MOD_SEL0_24_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MOD_SEL0_22_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MOD_SEL0_20_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MOD_SEL0_18_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) MOD_SEL0_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MOD_SEL0_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MOD_SEL0_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MOD_SEL0_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MOD_SEL0_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MOD_SEL0_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MOD_SEL0_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MOD_SEL0_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MOD_SEL0_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MOD_SEL0_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MOD_SEL0_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MOD_SEL0_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define FM(x) x##_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINMUX_DATA_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINMUX_SINGLE(USB0_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINMUX_SINGLE(USB0_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINMUX_SINGLE(VI4_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_SINGLE(VI4_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_SINGLE(TX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINMUX_SINGLE(RX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINMUX_SINGLE(AVB0_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINMUX_SINGLE(AVB0_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINMUX_SINGLE(AVB0_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINMUX_SINGLE(AVB0_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINMUX_SINGLE(AVB0_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINMUX_SINGLE(AVB0_TXCREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINMUX_SINGLE(AVB0_TD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINMUX_SINGLE(AVB0_TD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINMUX_SINGLE(AVB0_TD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINMUX_SINGLE(AVB0_TD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINMUX_SINGLE(AVB0_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINMUX_SINGLE(AVB0_TX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINMUX_SINGLE(AVB0_RD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINMUX_SINGLE(AVB0_RD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINMUX_SINGLE(AVB0_RD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINMUX_SINGLE(AVB0_RD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINMUX_SINGLE(AVB0_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINMUX_SINGLE(AVB0_RX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINMUX_SINGLE(RPC_INT_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINMUX_SINGLE(RPC_RESET_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINMUX_SINGLE(QSPI1_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINMUX_SINGLE(QSPI1_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINMUX_SINGLE(QSPI1_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINMUX_SINGLE(QSPI1_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINMUX_SINGLE(QSPI1_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINMUX_SINGLE(QSPI1_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINMUX_SINGLE(QSPI0_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINMUX_SINGLE(QSPI0_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINMUX_SINGLE(QSPI0_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINMUX_SINGLE(QSPI0_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINMUX_SINGLE(QSPI0_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINMUX_SINGLE(QSPI0_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINMUX_SINGLE(SCL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINMUX_SINGLE(SDA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINMUX_SINGLE(MSIOF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINMUX_SINGLE(MSIOF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINMUX_SINGLE(MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINMUX_SINGLE(MSIOF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_IPSR_GPSR(IP3_19_16, NMI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_GPSR(IP3_31_28, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_GPSR(IP4_23_20, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP4_27_24, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_IPSR_GPSR(IP8_11_8, NFALE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_GPSR(IP8_15_12, NFCLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_GPSR(IP10_19_16, HSCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_GPSR(IP10_23_20, HTX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_GPSR(IP10_27_24, HRX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_GPSR(IP10_31_28, SCL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_GPSR(IP11_3_0, SDA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_GPSR(IP12_11_8, SCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* - AUDIO CLOCK ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const unsigned int audio_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* CLK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const unsigned int audio_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const unsigned int audio_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* CLK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const unsigned int audio_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) AUDIO_CLKB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const unsigned int audio_clkout_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const unsigned int audio_clkout_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) AUDIO_CLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const unsigned int audio_clkout1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* CLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const unsigned int audio_clkout1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) AUDIO_CLKOUT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* - EtherAVB --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const unsigned int avb0_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* AVB0_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const unsigned int avb0_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) AVB0_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const unsigned int avb0_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* AVB0_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const unsigned int avb0_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) AVB0_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const unsigned int avb0_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* AVB0_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const unsigned int avb0_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) AVB0_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const unsigned int avb0_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* AVB0_MDC, AVB0_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const unsigned int avb0_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) AVB0_MDC_MARK, AVB0_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const unsigned int avb0_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * AVB0_TD1, AVB0_TD2, AVB0_TD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * AVB0_RD1, AVB0_RD2, AVB0_RD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) * AVB0_TXCREFCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static const unsigned int avb0_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) AVB0_TXCREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static const unsigned int avb0_avtp_pps_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* AVB0_AVTP_PPS_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const unsigned int avb0_avtp_pps_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) AVB0_AVTP_PPS_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const unsigned int avb0_avtp_match_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* AVB0_AVTP_MATCH_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const unsigned int avb0_avtp_match_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) AVB0_AVTP_MATCH_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static const unsigned int avb0_avtp_capture_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* AVB0_AVTP_CAPTURE_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const unsigned int avb0_avtp_capture_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) AVB0_AVTP_CAPTURE_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const unsigned int avb0_avtp_pps_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* AVB0_AVTP_PPS_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const unsigned int avb0_avtp_pps_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) AVB0_AVTP_PPS_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const unsigned int avb0_avtp_match_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* AVB0_AVTP_MATCH_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const unsigned int avb0_avtp_match_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) AVB0_AVTP_MATCH_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const unsigned int avb0_avtp_capture_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* AVB0_AVTP_CAPTURE_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static const unsigned int avb0_avtp_capture_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) AVB0_AVTP_CAPTURE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) /* - CAN ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const unsigned int can0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static const unsigned int can0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) CAN0_TX_A_MARK, CAN0_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const unsigned int can0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const unsigned int can0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) CAN0_TX_B_MARK, CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const unsigned int can1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const unsigned int can1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) CAN1_TX_A_MARK, CAN1_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const unsigned int can1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static const unsigned int can1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) CAN1_TX_B_MARK, CAN1_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* - CAN Clock -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const unsigned int can_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const unsigned int can_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* - CAN FD ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const unsigned int canfd0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const unsigned int canfd0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) CANFD0_TX_MARK, CANFD0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const unsigned int canfd1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const unsigned int canfd1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) CANFD1_TX_MARK, CANFD1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) DU_DR3_MARK, DU_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) DU_DG3_MARK, DU_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) DU_DB3_MARK, DU_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const unsigned int du_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const unsigned int du_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const unsigned int du_clk_in_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) RCAR_GP_PIN(1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const unsigned int du_clk_in_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) DU_DOTCLKIN1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static const unsigned int du_clk_out_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static const unsigned int du_clk_out_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) DU_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static const unsigned int du_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* VSYNC, HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const unsigned int du_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) DU_VSYNC_MARK, DU_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const unsigned int du_disp_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* DISP_CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) RCAR_GP_PIN(1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static const unsigned int du_disp_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) DU_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) RCAR_GP_PIN(1, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) DU_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static const unsigned int du_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) RCAR_GP_PIN(1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const unsigned int du_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) DU_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* - I2C -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) SCL0_MARK, SDA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const unsigned int i2c1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const unsigned int i2c1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SCL1_MARK, SDA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static const unsigned int i2c2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const unsigned int i2c2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) SCL2_A_MARK, SDA2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) SCL2_B_MARK, SDA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static const unsigned int i2c3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static const unsigned int i2c3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SCL3_A_MARK, SDA3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const unsigned int i2c3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const unsigned int i2c3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) SCL3_B_MARK, SDA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* - MMC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const unsigned int mmc_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const unsigned int mmc_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) MMC_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static const unsigned int mmc_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static const unsigned int mmc_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) MMC_D0_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static const unsigned int mmc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const unsigned int mmc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) MMC_D0_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) MMC_D4_MARK, MMC_D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) MMC_D6_MARK, MMC_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static const unsigned int mmc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static const unsigned int mmc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) MMC_CLK_MARK, MMC_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const unsigned int msiof0_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static const unsigned int msiof0_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static const unsigned int msiof0_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static const unsigned int msiof0_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static const unsigned int msiof1_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static const unsigned int msiof1_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static const unsigned int msiof1_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static const unsigned int msiof1_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const unsigned int msiof2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const unsigned int msiof2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const unsigned int msiof2_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static const unsigned int msiof2_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) MSIOF2_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const unsigned int msiof2_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const unsigned int msiof2_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) MSIOF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static const unsigned int msiof2_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const unsigned int msiof2_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const unsigned int msiof2_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const unsigned int msiof2_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static const unsigned int msiof2_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const unsigned int msiof2_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static const unsigned int msiof2_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const unsigned int msiof2_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* - MSIOF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static const unsigned int msiof3_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const unsigned int msiof3_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) MSIOF3_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const unsigned int msiof3_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static const unsigned int msiof3_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) MSIOF3_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const unsigned int msiof3_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const unsigned int msiof3_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) MSIOF3_SS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) static const unsigned int msiof3_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned int msiof3_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) MSIOF3_SS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const unsigned int msiof3_txd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static const unsigned int msiof3_txd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) MSIOF3_TXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static const unsigned int msiof3_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned int msiof3_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) MSIOF3_RXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const unsigned int msiof3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const unsigned int msiof3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) MSIOF3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static const unsigned int msiof3_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static const unsigned int msiof3_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) MSIOF3_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const unsigned int msiof3_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static const unsigned int msiof3_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) MSIOF3_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const unsigned int msiof3_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static const unsigned int msiof3_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) MSIOF3_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static const unsigned int msiof3_txd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static const unsigned int msiof3_txd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) MSIOF3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static const unsigned int msiof3_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static const unsigned int msiof3_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) MSIOF3_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* - PWM0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static const unsigned int pwm0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const unsigned int pwm0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) PWM0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static const unsigned int pwm0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) RCAR_GP_PIN(2, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static const unsigned int pwm0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) PWM0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* - PWM1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const unsigned int pwm1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static const unsigned int pwm1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) PWM1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) static const unsigned int pwm1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const unsigned int pwm1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) PWM1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* - PWM2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static const unsigned int pwm2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static const unsigned int pwm2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) PWM2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static const unsigned int pwm2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static const unsigned int pwm2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) PWM2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /* - PWM3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static const unsigned int pwm3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static const unsigned int pwm3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) PWM3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static const unsigned int pwm3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) RCAR_GP_PIN(1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static const unsigned int pwm3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) static const unsigned int pwm3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static const unsigned int pwm3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) PWM3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned int scif0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static const unsigned int scif0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) RX0_A_MARK, TX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static const unsigned int scif0_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const unsigned int scif0_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) SCK0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const unsigned int scif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static const unsigned int scif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) RX0_B_MARK, TX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static const unsigned int scif0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const unsigned int scif0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) SCK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const unsigned int scif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int scif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) RTS0_N_MARK, CTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const unsigned int scif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) static const unsigned int scif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) RX1_A_MARK, TX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static const unsigned int scif1_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static const unsigned int scif1_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) SCK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static const unsigned int scif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static const unsigned int scif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) SCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static const unsigned int scif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const unsigned int scif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) RTS1_N_MARK, CTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static const unsigned int scif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static const unsigned int scif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) RX2_MARK, TX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static const unsigned int scif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static const unsigned int scif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static const unsigned int scif3_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static const unsigned int scif3_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) RX3_A_MARK, TX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const unsigned int scif3_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static const unsigned int scif3_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) SCK3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static const unsigned int scif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static const unsigned int scif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) RX3_B_MARK, TX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const unsigned int scif3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) RCAR_GP_PIN(1, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static const unsigned int scif3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SCK3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const unsigned int scif4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const unsigned int scif4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) RX4_A_MARK, TX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const unsigned int scif4_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static const unsigned int scif4_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) SCK4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned int scif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static const unsigned int scif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) RX4_B_MARK, TX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static const unsigned int scif4_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static const unsigned int scif4_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SCK4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static const unsigned int scif5_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static const unsigned int scif5_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) RX5_A_MARK, TX5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const unsigned int scif5_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static const unsigned int scif5_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) SCK5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static const unsigned int scif5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const unsigned int scif5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) RX5_B_MARK, TX5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static const unsigned int scif5_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const unsigned int scif5_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SCK5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static const unsigned int scif_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static const unsigned int scif_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) SCIF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* - SSI ---------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const unsigned int ssi3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static const unsigned int ssi3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) SSI_SDATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static const unsigned int ssi34_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static const unsigned int ssi34_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) SSI_SCK34_MARK, SSI_WS34_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static const unsigned int ssi4_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static const unsigned int ssi4_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) SSI_SCK4_A_MARK, SSI_WS4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static const unsigned int ssi4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static const unsigned int ssi4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) SSI_SDATA4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const unsigned int ssi4_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static const unsigned int ssi4_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const unsigned int ssi4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const unsigned int ssi4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) SSI_SDATA4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static const unsigned int usb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static const unsigned int usb0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) USB0_PWEN_MARK, USB0_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* - VIN4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static const unsigned int vin4_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static const unsigned int vin4_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) VI4_DATA2_MARK, VI4_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) VI4_DATA4_MARK, VI4_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) VI4_DATA6_MARK, VI4_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) VI4_DATA10_MARK, VI4_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) VI4_DATA12_MARK, VI4_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) VI4_DATA14_MARK, VI4_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) VI4_DATA18_MARK, VI4_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) VI4_DATA20_MARK, VI4_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) VI4_DATA22_MARK, VI4_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const union vin_data vin4_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static const union vin_data vin4_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) VI4_DATA0_MARK, VI4_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) VI4_DATA2_MARK, VI4_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) VI4_DATA4_MARK, VI4_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) VI4_DATA6_MARK, VI4_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) VI4_DATA8_MARK, VI4_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) VI4_DATA10_MARK, VI4_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) VI4_DATA12_MARK, VI4_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) VI4_DATA14_MARK, VI4_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) VI4_DATA16_MARK, VI4_DATA17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) VI4_DATA18_MARK, VI4_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) VI4_DATA20_MARK, VI4_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) VI4_DATA22_MARK, VI4_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static const unsigned int vin4_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) /* HSYNC#, VSYNC# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static const unsigned int vin4_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static const unsigned int vin4_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static const unsigned int vin4_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) VI4_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static const unsigned int vin4_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* CLKENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) RCAR_GP_PIN(2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static const unsigned int vin4_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) VI4_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static const unsigned int vin4_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static const unsigned int vin4_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) VI4_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) SH_PFC_PIN_GROUP(audio_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) SH_PFC_PIN_GROUP(audio_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) SH_PFC_PIN_GROUP(audio_clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) SH_PFC_PIN_GROUP(audio_clkout1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) SH_PFC_PIN_GROUP(avb0_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) SH_PFC_PIN_GROUP(avb0_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) SH_PFC_PIN_GROUP(avb0_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) SH_PFC_PIN_GROUP(avb0_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) SH_PFC_PIN_GROUP(avb0_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) SH_PFC_PIN_GROUP(avb0_avtp_pps_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) SH_PFC_PIN_GROUP(avb0_avtp_match_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) SH_PFC_PIN_GROUP(avb0_avtp_capture_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) SH_PFC_PIN_GROUP(avb0_avtp_pps_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) SH_PFC_PIN_GROUP(avb0_avtp_match_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) SH_PFC_PIN_GROUP(avb0_avtp_capture_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) SH_PFC_PIN_GROUP(can0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) SH_PFC_PIN_GROUP(can0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) SH_PFC_PIN_GROUP(can1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) SH_PFC_PIN_GROUP(can1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) SH_PFC_PIN_GROUP(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) SH_PFC_PIN_GROUP(canfd0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) SH_PFC_PIN_GROUP(canfd1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) SH_PFC_PIN_GROUP(du_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) SH_PFC_PIN_GROUP(du_clk_in_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) SH_PFC_PIN_GROUP(du_clk_out_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) SH_PFC_PIN_GROUP(du_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) SH_PFC_PIN_GROUP(du_disp_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) SH_PFC_PIN_GROUP(du_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) SH_PFC_PIN_GROUP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) SH_PFC_PIN_GROUP(i2c2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) SH_PFC_PIN_GROUP(i2c3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) SH_PFC_PIN_GROUP(i2c3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) SH_PFC_PIN_GROUP(msiof0_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) SH_PFC_PIN_GROUP(msiof0_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) SH_PFC_PIN_GROUP(msiof1_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) SH_PFC_PIN_GROUP(msiof1_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) SH_PFC_PIN_GROUP(msiof2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) SH_PFC_PIN_GROUP(msiof2_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) SH_PFC_PIN_GROUP(msiof2_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) SH_PFC_PIN_GROUP(msiof2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) SH_PFC_PIN_GROUP(msiof2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) SH_PFC_PIN_GROUP(msiof2_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) SH_PFC_PIN_GROUP(msiof2_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) SH_PFC_PIN_GROUP(msiof3_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) SH_PFC_PIN_GROUP(msiof3_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) SH_PFC_PIN_GROUP(msiof3_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) SH_PFC_PIN_GROUP(msiof3_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) SH_PFC_PIN_GROUP(msiof3_txd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) SH_PFC_PIN_GROUP(msiof3_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) SH_PFC_PIN_GROUP(msiof3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) SH_PFC_PIN_GROUP(msiof3_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) SH_PFC_PIN_GROUP(msiof3_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) SH_PFC_PIN_GROUP(msiof3_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) SH_PFC_PIN_GROUP(msiof3_txd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) SH_PFC_PIN_GROUP(msiof3_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) SH_PFC_PIN_GROUP(pwm0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) SH_PFC_PIN_GROUP(pwm0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) SH_PFC_PIN_GROUP(pwm1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) SH_PFC_PIN_GROUP(pwm1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) SH_PFC_PIN_GROUP(pwm2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) SH_PFC_PIN_GROUP(pwm2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) SH_PFC_PIN_GROUP(pwm3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) SH_PFC_PIN_GROUP(pwm3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) SH_PFC_PIN_GROUP(pwm3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) SH_PFC_PIN_GROUP(scif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) SH_PFC_PIN_GROUP(scif0_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) SH_PFC_PIN_GROUP(scif0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) SH_PFC_PIN_GROUP(scif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) SH_PFC_PIN_GROUP(scif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) SH_PFC_PIN_GROUP(scif1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) SH_PFC_PIN_GROUP(scif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) SH_PFC_PIN_GROUP(scif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) SH_PFC_PIN_GROUP(scif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) SH_PFC_PIN_GROUP(scif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) SH_PFC_PIN_GROUP(scif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) SH_PFC_PIN_GROUP(scif3_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) SH_PFC_PIN_GROUP(scif3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) SH_PFC_PIN_GROUP(scif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) SH_PFC_PIN_GROUP(scif4_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) SH_PFC_PIN_GROUP(scif4_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) SH_PFC_PIN_GROUP(scif5_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) SH_PFC_PIN_GROUP(scif5_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) SH_PFC_PIN_GROUP(scif5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) SH_PFC_PIN_GROUP(scif5_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) SH_PFC_PIN_GROUP(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) SH_PFC_PIN_GROUP(ssi34_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) SH_PFC_PIN_GROUP(ssi4_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) SH_PFC_PIN_GROUP(ssi4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) SH_PFC_PIN_GROUP(ssi4_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) SH_PFC_PIN_GROUP(ssi4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) VIN_DATA_PIN_GROUP(vin4_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) VIN_DATA_PIN_GROUP(vin4_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) VIN_DATA_PIN_GROUP(vin4_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) VIN_DATA_PIN_GROUP(vin4_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) SH_PFC_PIN_GROUP(vin4_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) VIN_DATA_PIN_GROUP(vin4_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) VIN_DATA_PIN_GROUP(vin4_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) SH_PFC_PIN_GROUP(vin4_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) SH_PFC_PIN_GROUP(vin4_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) SH_PFC_PIN_GROUP(vin4_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) SH_PFC_PIN_GROUP(vin4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) "audio_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) "audio_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) "audio_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) "audio_clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static const char * const avb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) "avb0_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) "avb0_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) "avb0_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) "avb0_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) "avb0_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) "avb0_avtp_pps_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) "avb0_avtp_match_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) "avb0_avtp_capture_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) "avb0_avtp_pps_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) "avb0_avtp_match_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) "avb0_avtp_capture_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) "can0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) "can0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) "can1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) "can1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static const char * const can_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static const char * const canfd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) "canfd0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static const char * const canfd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) "canfd1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) "du_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) "du_clk_in_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) "du_clk_out_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) "du_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) "du_disp_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) "du_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) "i2c2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) "i2c3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) "i2c3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) "pwm0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) "pwm0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) "pwm1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) "pwm1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) "pwm2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) "pwm2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) "pwm3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) "pwm3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) "pwm3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) "scif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) "scif0_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) "scif0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) "scif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) "scif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) "scif1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) "scif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) "scif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) "scif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) "scif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) "scif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) "scif3_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) "scif3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) "scif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) "scif4_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) "scif4_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) "scif5_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) "scif5_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) "scif5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) "scif5_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) "scif_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) "ssi34_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) "ssi4_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) "ssi4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) "ssi4_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) "ssi4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) static const char * const vin4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) "vin4_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) "vin4_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) "vin4_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) "vin4_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) "vin4_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) "vin4_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) "vin4_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) "vin4_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) "vin4_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) "vin4_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) "vin4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) "msiof0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) "msiof0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) "msiof1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "msiof1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) "msiof2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) "msiof2_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) "msiof2_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) "msiof2_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) "msiof2_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) "msiof2_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) "msiof2_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) "msiof3_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) "msiof3_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) "msiof3_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) "msiof3_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) "msiof3_txd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) "msiof3_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) "msiof3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) "msiof3_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) "msiof3_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) "msiof3_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) "msiof3_txd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) "msiof3_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) SH_PFC_FUNCTION(avb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) SH_PFC_FUNCTION(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) SH_PFC_FUNCTION(canfd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) SH_PFC_FUNCTION(canfd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) SH_PFC_FUNCTION(vin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define F_(x, y) FN_##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) #define FM(x) FN_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) GP_0_8_FN, GPSR0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) GP_0_7_FN, GPSR0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) GP_0_6_FN, GPSR0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) GP_0_5_FN, GPSR0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) GP_0_4_FN, GPSR0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) GP_0_3_FN, GPSR0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) GP_0_2_FN, GPSR0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) GP_0_1_FN, GPSR0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) GP_0_0_FN, GPSR0_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) GP_1_31_FN, GPSR1_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) GP_1_30_FN, GPSR1_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) GP_1_29_FN, GPSR1_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) GP_1_28_FN, GPSR1_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) GP_1_27_FN, GPSR1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) GP_1_26_FN, GPSR1_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) GP_1_25_FN, GPSR1_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) GP_1_24_FN, GPSR1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) GP_1_23_FN, GPSR1_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) GP_1_22_FN, GPSR1_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) GP_1_21_FN, GPSR1_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) GP_1_20_FN, GPSR1_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) GP_1_19_FN, GPSR1_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) GP_1_18_FN, GPSR1_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) GP_1_17_FN, GPSR1_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) GP_1_16_FN, GPSR1_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) GP_1_15_FN, GPSR1_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) GP_1_14_FN, GPSR1_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) GP_1_13_FN, GPSR1_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) GP_1_12_FN, GPSR1_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) GP_1_11_FN, GPSR1_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) GP_1_10_FN, GPSR1_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) GP_1_9_FN, GPSR1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) GP_1_8_FN, GPSR1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) GP_1_7_FN, GPSR1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) GP_1_6_FN, GPSR1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) GP_1_5_FN, GPSR1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) GP_1_4_FN, GPSR1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) GP_1_3_FN, GPSR1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) GP_1_2_FN, GPSR1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) GP_1_1_FN, GPSR1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) GP_1_0_FN, GPSR1_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) GP_2_31_FN, GPSR2_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) GP_2_30_FN, GPSR2_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) GP_2_29_FN, GPSR2_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) GP_2_28_FN, GPSR2_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) GP_2_27_FN, GPSR2_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) GP_2_26_FN, GPSR2_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) GP_2_25_FN, GPSR2_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) GP_2_24_FN, GPSR2_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) GP_2_23_FN, GPSR2_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) GP_2_22_FN, GPSR2_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) GP_2_21_FN, GPSR2_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) GP_2_20_FN, GPSR2_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) GP_2_19_FN, GPSR2_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) GP_2_18_FN, GPSR2_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) GP_2_17_FN, GPSR2_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) GP_2_16_FN, GPSR2_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) GP_2_15_FN, GPSR2_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) GP_2_14_FN, GPSR2_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) GP_2_13_FN, GPSR2_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) GP_2_12_FN, GPSR2_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) GP_2_11_FN, GPSR2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) GP_2_10_FN, GPSR2_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) GP_2_9_FN, GPSR2_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) GP_2_8_FN, GPSR2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) GP_2_7_FN, GPSR2_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) GP_2_6_FN, GPSR2_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) GP_2_5_FN, GPSR2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) GP_2_4_FN, GPSR2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) GP_2_3_FN, GPSR2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) GP_2_2_FN, GPSR2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) GP_2_1_FN, GPSR2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) GP_2_0_FN, GPSR2_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) GP_3_9_FN, GPSR3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) GP_3_8_FN, GPSR3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) GP_3_7_FN, GPSR3_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) GP_3_6_FN, GPSR3_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) GP_3_5_FN, GPSR3_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) GP_3_4_FN, GPSR3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) GP_3_3_FN, GPSR3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) GP_3_2_FN, GPSR3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) GP_3_1_FN, GPSR3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) GP_3_0_FN, GPSR3_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) GP_4_31_FN, GPSR4_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) GP_4_30_FN, GPSR4_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) GP_4_29_FN, GPSR4_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) GP_4_28_FN, GPSR4_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) GP_4_27_FN, GPSR4_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) GP_4_26_FN, GPSR4_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) GP_4_25_FN, GPSR4_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) GP_4_24_FN, GPSR4_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) GP_4_23_FN, GPSR4_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) GP_4_22_FN, GPSR4_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) GP_4_21_FN, GPSR4_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) GP_4_20_FN, GPSR4_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) GP_4_19_FN, GPSR4_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) GP_4_18_FN, GPSR4_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) GP_4_17_FN, GPSR4_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) GP_4_16_FN, GPSR4_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) GP_4_15_FN, GPSR4_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) GP_4_14_FN, GPSR4_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) GP_4_13_FN, GPSR4_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) GP_4_12_FN, GPSR4_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) GP_4_11_FN, GPSR4_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) GP_4_10_FN, GPSR4_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) GP_4_9_FN, GPSR4_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) GP_4_8_FN, GPSR4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) GP_4_7_FN, GPSR4_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) GP_4_6_FN, GPSR4_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) GP_4_5_FN, GPSR4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) GP_4_4_FN, GPSR4_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) GP_4_3_FN, GPSR4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) GP_4_2_FN, GPSR4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) GP_4_1_FN, GPSR4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) GP_4_0_FN, GPSR4_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) GP_5_20_FN, GPSR5_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) GP_5_19_FN, GPSR5_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) GP_5_18_FN, GPSR5_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) GP_5_17_FN, GPSR5_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) GP_5_16_FN, GPSR5_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) GP_5_15_FN, GPSR5_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) GP_5_14_FN, GPSR5_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) GP_5_13_FN, GPSR5_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) GP_5_12_FN, GPSR5_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) GP_5_11_FN, GPSR5_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) GP_5_10_FN, GPSR5_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) GP_5_9_FN, GPSR5_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) GP_5_8_FN, GPSR5_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) GP_5_7_FN, GPSR5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) GP_5_6_FN, GPSR5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) GP_5_5_FN, GPSR5_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) GP_5_4_FN, GPSR5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) GP_5_3_FN, GPSR5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) GP_5_2_FN, GPSR5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) GP_5_1_FN, GPSR5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) GP_5_0_FN, GPSR5_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) GP_6_13_FN, GPSR6_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) GP_6_12_FN, GPSR6_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) GP_6_11_FN, GPSR6_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) GP_6_10_FN, GPSR6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) GP_6_9_FN, GPSR6_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) GP_6_8_FN, GPSR6_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) GP_6_7_FN, GPSR6_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) GP_6_6_FN, GPSR6_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) GP_6_5_FN, GPSR6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) GP_6_4_FN, GPSR6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) GP_6_3_FN, GPSR6_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) GP_6_2_FN, GPSR6_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) GP_6_1_FN, GPSR6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) GP_6_0_FN, GPSR6_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) IP0_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) IP0_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) IP0_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) IP0_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) IP0_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) IP0_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) IP0_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) IP0_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) IP1_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) IP1_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) IP1_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) IP1_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) IP1_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) IP1_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) IP1_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) IP1_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) IP2_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) IP2_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) IP2_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) IP2_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) IP2_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) IP2_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) IP2_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) IP2_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) IP3_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) IP3_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) IP3_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) IP3_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) IP3_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) IP3_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) IP3_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) IP3_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) IP4_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) IP4_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) IP4_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) IP4_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) IP4_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) IP4_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) IP4_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) IP4_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) IP5_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) IP5_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) IP5_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) IP5_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) IP5_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) IP5_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) IP5_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) IP5_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) IP6_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) IP6_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) IP6_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) IP6_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) IP6_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) IP6_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) IP6_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) IP6_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) IP7_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) IP7_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) IP7_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) IP7_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) IP7_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) IP7_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) IP7_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) IP7_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) IP8_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) IP8_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) IP8_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) IP8_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) IP8_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) IP8_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) IP8_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) IP8_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) IP9_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) IP9_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) IP9_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) IP9_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) IP9_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) IP9_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) IP9_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) IP9_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) IP10_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) IP10_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) IP10_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) IP10_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) IP10_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) IP10_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) IP10_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) IP10_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) IP11_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) IP11_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) IP11_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) IP11_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) IP11_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) IP11_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) IP11_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) IP11_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) IP12_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) IP12_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) IP12_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) IP12_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) IP12_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) IP12_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) IP12_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) IP12_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) /* IP13_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) /* IP13_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* IP13_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* IP13_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /* IP13_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* IP13_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) IP13_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) IP13_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) GROUP(1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) 1, 1, 1, 1, 1, 1, 4, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) /* RESERVED 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) MOD_SEL0_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) MOD_SEL0_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) MOD_SEL0_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) MOD_SEL0_27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) MOD_SEL0_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) MOD_SEL0_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) MOD_SEL0_24_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) MOD_SEL0_22_21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) MOD_SEL0_20_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) MOD_SEL0_18_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) /* RESERVED 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) MOD_SEL0_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) MOD_SEL0_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) MOD_SEL0_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) MOD_SEL0_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) MOD_SEL0_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) MOD_SEL0_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) /* RESERVED 9, 8, 7, 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) MOD_SEL0_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) MOD_SEL0_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) MOD_SEL0_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) MOD_SEL0_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) MOD_SEL0_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) MOD_SEL0_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) GROUP(1, 1, 1, 1, 1, 1, 2, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) MOD_SEL1_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) MOD_SEL1_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) MOD_SEL1_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) MOD_SEL1_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) MOD_SEL1_27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) MOD_SEL1_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) /* RESERVED 25, 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /* RESERVED 23, 22, 21, 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) /* RESERVED 19, 18, 17, 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) /* RESERVED 15, 14, 13, 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* RESERVED 11, 10, 9, 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* RESERVED 7, 6, 5, 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) /* RESERVED 3, 2, 1, 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static int r8a77995_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) int bit = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) *pocctrl = 0xe6060380;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) bit = 29 - (pin - RCAR_GP_PIN(3, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) enum ioctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) TDSELCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) [TDSELCTRL] = { 0xe60603c0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) static const struct sh_pfc_soc_operations r8a77995_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .pin_to_pocctrl = r8a77995_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) const struct sh_pfc_soc_info r8a77995_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .name = "r8a77995_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .ops = &r8a77995_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .ioctrl_regs = pinmux_ioctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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