^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A77990 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018-2019 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * R8A7796 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2016-2017 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CFG_FLAGS (SH_PFC_PIN_CFG_PULL_UP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_CFG_18(0, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_CFG_23(1, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_CFG_26(2, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PORT_GP_CFG_11(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PORT_GP_CFG_20(5, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PORT_GP_CFG_9(6, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PORT_GP_CFG_1(6, 9, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PORT_GP_CFG_1(6, 10, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PORT_GP_CFG_1(6, 11, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PORT_GP_CFG_1(6, 12, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PORT_GP_CFG_1(6, 13, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PORT_GP_CFG_1(6, 14, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PORT_GP_CFG_1(6, 15, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PORT_GP_CFG_1(6, 16, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PORT_GP_CFG_1(6, 17, fn, sfx, CFG_FLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPU_ALL_NOGP(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PIN_NOGP_CFG(AVB_MDC, "AVB_MDC", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PIN_NOGP_CFG(FSCLKST_N, "FSCLKST_N", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT_N", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PIN_NOGP_CFG(TRST_N, "TRST_N", fn, SH_PFC_PIN_CFG_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * F_() : just information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * FM() : macro for FN_xxx / xxx_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPSR0_17 F_(SDA4, IP7_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPSR0_16 F_(SCL4, IP7_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPSR0_15 F_(D15, IP7_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPSR0_14 F_(D14, IP7_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPSR0_13 F_(D13, IP7_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GPSR0_12 F_(D12, IP7_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPSR0_11 F_(D11, IP7_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPSR0_10 F_(D10, IP6_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPSR0_9 F_(D9, IP6_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPSR0_8 F_(D8, IP6_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPSR0_7 F_(D7, IP6_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPSR0_6 F_(D6, IP6_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPSR0_5 F_(D5, IP6_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPSR0_4 F_(D4, IP6_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPSR0_3 F_(D3, IP6_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPSR0_2 F_(D2, IP5_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPSR0_1 F_(D1, IP5_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPSR0_0 F_(D0, IP5_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GPSR1_22 F_(WE0_N, IP5_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GPSR1_21 F_(CS0_N, IP5_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPSR1_20 FM(CLKOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPSR1_19 F_(A19, IP5_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GPSR1_18 F_(A18, IP5_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GPSR1_17 F_(A17, IP5_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPSR1_16 F_(A16, IP4_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GPSR1_15 F_(A15, IP4_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPSR1_14 F_(A14, IP4_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPSR1_13 F_(A13, IP4_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPSR1_12 F_(A12, IP4_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPSR1_11 F_(A11, IP4_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPSR1_10 F_(A10, IP4_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPSR1_9 F_(A9, IP4_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPSR1_8 F_(A8, IP3_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPSR1_7 F_(A7, IP3_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPSR1_6 F_(A6, IP3_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPSR1_5 F_(A5, IP3_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPSR1_4 F_(A4, IP3_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GPSR1_3 F_(A3, IP3_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPSR1_2 F_(A2, IP3_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GPSR1_1 F_(A1, IP3_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPSR1_0 F_(A0, IP2_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPSR2_25 F_(EX_WAIT0, IP2_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPSR2_24 F_(RD_WR_N, IP2_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPSR2_23 F_(RD_N, IP2_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPSR2_22 F_(BS_N, IP2_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPSR2_21 FM(AVB_PHY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GPSR2_20 F_(AVB_TXCREFCLK, IP2_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPSR2_19 FM(AVB_RD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GPSR2_18 F_(AVB_RD2, IP1_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPSR2_17 F_(AVB_RD1, IP1_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPSR2_16 F_(AVB_RD0, IP1_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPSR2_15 FM(AVB_RXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPSR2_14 FM(AVB_RX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPSR2_13 F_(RPC_RESET_N, IP1_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPSR2_12 F_(RPC_INT_N, IP1_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPSR2_11 F_(QSPI1_SSL, IP1_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GPSR2_9 F_(QSPI1_IO2, IP1_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPSR2_8 F_(QSPI1_MISO_IO1, IP0_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPSR2_7 F_(QSPI1_MOSI_IO0, IP0_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPSR2_6 F_(QSPI1_SPCLK, IP0_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPSR2_5 FM(QSPI0_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPSR2_4 F_(QSPI0_IO3, IP0_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPSR2_3 F_(QSPI0_IO2, IP0_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPSR2_2 F_(QSPI0_MISO_IO1, IP0_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPSR2_1 F_(QSPI0_MOSI_IO0, IP0_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPSR2_0 F_(QSPI0_SPCLK, IP0_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPSR3_15 F_(SD1_WP, IP11_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPSR3_14 F_(SD1_CD, IP11_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPSR3_13 F_(SD0_WP, IP10_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPSR3_12 F_(SD0_CD, IP10_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPSR3_11 F_(SD1_DAT3, IP9_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPSR3_10 F_(SD1_DAT2, IP9_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPSR3_9 F_(SD1_DAT1, IP9_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPSR3_8 F_(SD1_DAT0, IP8_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPSR3_7 F_(SD1_CMD, IP8_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPSR3_6 F_(SD1_CLK, IP8_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GPSR3_5 F_(SD0_DAT3, IP8_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GPSR3_4 F_(SD0_DAT2, IP8_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GPSR3_3 F_(SD0_DAT1, IP8_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GPSR3_2 F_(SD0_DAT0, IP8_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GPSR3_1 F_(SD0_CMD, IP8_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GPSR3_0 F_(SD0_CLK, IP7_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GPSR4_10 F_(SD3_DS, IP10_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPSR4_9 F_(SD3_DAT7, IP10_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPSR4_8 F_(SD3_DAT6, IP10_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPSR4_7 F_(SD3_DAT5, IP10_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GPSR4_6 F_(SD3_DAT4, IP10_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GPSR4_5 F_(SD3_DAT3, IP10_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GPSR4_4 F_(SD3_DAT2, IP9_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GPSR4_3 F_(SD3_DAT1, IP9_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GPSR4_2 F_(SD3_DAT0, IP9_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GPSR4_1 F_(SD3_CMD, IP9_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GPSR4_0 F_(SD3_CLK, IP9_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GPSR5_19 F_(MLB_DAT, IP13_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GPSR5_18 F_(MLB_SIG, IP13_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GPSR5_17 F_(MLB_CLK, IP13_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GPSR5_16 F_(SSI_SDATA9, IP13_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GPSR5_15 F_(MSIOF0_SS2, IP13_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GPSR5_14 F_(MSIOF0_SS1, IP13_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GPSR5_13 F_(MSIOF0_SYNC, IP12_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GPSR5_12 F_(MSIOF0_TXD, IP12_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GPSR5_11 F_(MSIOF0_RXD, IP12_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GPSR5_10 F_(MSIOF0_SCK, IP12_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GPSR5_9 F_(RX2_A, IP12_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define GPSR5_8 F_(TX2_A, IP12_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define GPSR5_7 F_(SCK2_A, IP12_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GPSR5_6 F_(TX1, IP12_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GPSR5_5 F_(RX1, IP11_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GPSR5_4 F_(RTS0_N_A, IP11_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GPSR5_3 F_(CTS0_N_A, IP11_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GPSR5_2 F_(TX0_A, IP11_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPSR5_1 F_(RX0_A, IP11_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GPSR5_0 F_(SCK0_A, IP11_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* GPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GPSR6_17 F_(USB30_PWEN, IP15_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GPSR6_16 F_(SSI_SDATA6, IP15_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GPSR6_15 F_(SSI_WS6, IP15_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GPSR6_14 F_(SSI_SCK6, IP15_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GPSR6_13 F_(SSI_SDATA5, IP15_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GPSR6_12 F_(SSI_WS5, IP15_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GPSR6_11 F_(SSI_SCK5, IP14_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GPSR6_10 F_(SSI_SDATA4, IP14_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GPSR6_9 F_(USB30_OVC, IP15_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GPSR6_8 F_(AUDIO_CLKA, IP15_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GPSR6_7 F_(SSI_SDATA3, IP14_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GPSR6_6 F_(SSI_WS349, IP14_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GPSR6_5 F_(SSI_SCK349, IP14_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GPSR6_4 F_(SSI_SDATA2, IP14_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GPSR6_3 F_(SSI_SDATA1, IP14_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GPSR6_2 F_(SSI_SDATA0, IP14_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GPSR6_1 F_(SSI_WS01239, IP13_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define GPSR6_0 F_(SSI_SCK01239, IP13_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IP0_3_0 FM(QSPI0_SPCLK) FM(HSCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IP0_7_4 FM(QSPI0_MOSI_IO0) FM(HCTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IP0_11_8 FM(QSPI0_MISO_IO1) FM(HRTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IP0_15_12 FM(QSPI0_IO2) FM(HTX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IP0_19_16 FM(QSPI0_IO3) FM(HRX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IP0_23_20 FM(QSPI1_SPCLK) FM(RIF2_CLK_A) FM(HSCK4_B) FM(VI4_DATA0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IP0_27_24 FM(QSPI1_MOSI_IO0) FM(RIF2_SYNC_A) FM(HTX4_B) FM(VI4_DATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IP0_31_28 FM(QSPI1_MISO_IO1) FM(RIF2_D0_A) FM(HRX4_B) FM(VI4_DATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IP1_3_0 FM(QSPI1_IO2) FM(RIF2_D1_A) FM(HTX3_C) FM(VI4_DATA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IP1_11_8 FM(QSPI1_SSL) FM(RIF3_SYNC_A) FM(HSCK3_C) FM(VI4_DATA5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IP1_15_12 FM(RPC_INT_N) FM(RIF3_D0_A) FM(HCTS3_N_C) FM(VI4_DATA6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IP1_19_16 FM(RPC_RESET_N) FM(RIF3_D1_A) FM(HRTS3_N_C) FM(VI4_DATA7_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IP1_23_20 FM(AVB_RD0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IP1_27_24 FM(AVB_RD1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IP1_31_28 FM(AVB_RD2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IP2_3_0 FM(AVB_TXCREFCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IP2_7_4 FM(AVB_MDIO) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IP2_11_8 FM(AVB_MDC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IP2_15_12 FM(BS_N) FM(PWM0_A) FM(AVB_MAGIC) FM(VI4_CLK) F_(0, 0) FM(TX3_C) F_(0, 0) FM(VI5_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IP2_19_16 FM(RD_N) FM(PWM1_A) FM(AVB_LINK) FM(VI4_FIELD) F_(0, 0) FM(RX3_C) FM(FSCLKST2_N_A) FM(VI5_DATA0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IP2_23_20 FM(RD_WR_N) FM(SCL7_A) FM(AVB_AVTP_MATCH) FM(VI4_VSYNC_N) FM(TX5_B) FM(SCK3_C) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IP2_27_24 FM(EX_WAIT0) FM(SDA7_A) FM(AVB_AVTP_CAPTURE) FM(VI4_HSYNC_N) FM(RX5_B) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IP2_31_28 FM(A0) FM(IRQ0) FM(PWM2_A) FM(MSIOF3_SS1_B) FM(VI5_CLK_A) FM(DU_CDE) FM(HRX3_D) FM(IERX) FM(QSTB_QHE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IP3_3_0 FM(A1) FM(IRQ1) FM(PWM3_A) FM(DU_DOTCLKIN1) FM(VI5_DATA0_A) FM(DU_DISP_CDE) FM(SDA6_B) FM(IETX) FM(QCPV_QDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) FM(SCL6_B) F_(0, 0) FM(QSTVB_QVE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IP3_11_8 FM(A3) FM(CTS4_N_A) FM(PWM4_A) FM(VI4_DATA12) F_(0, 0) FM(DU_DOTCLKOUT0) FM(HTX3_D) FM(IECLK) FM(LCDOUT12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IP3_15_12 FM(A4) FM(RTS4_N_A) FM(MSIOF3_SYNC_B) FM(VI4_DATA8) FM(PWM2_B) FM(DU_DG4) FM(RIF2_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IP3_19_16 FM(A5) FM(SCK4_A) FM(MSIOF3_SCK_B) FM(VI4_DATA9) FM(PWM3_B) F_(0, 0) FM(RIF2_SYNC_B) F_(0, 0) FM(QPOLA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IP3_23_20 FM(A6) FM(RX4_A) FM(MSIOF3_RXD_B) FM(VI4_DATA10) F_(0, 0) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IP3_27_24 FM(A7) FM(TX4_A) FM(MSIOF3_TXD_B) FM(VI4_DATA11) F_(0, 0) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IP3_31_28 FM(A8) FM(SDA6_A) FM(RX3_B) FM(HRX4_C) FM(VI5_HSYNC_N_A) FM(DU_HSYNC) FM(VI4_DATA0_B) F_(0, 0) FM(QSTH_QHS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IP4_3_0 FM(A9) FM(TX5_A) FM(IRQ3) FM(VI4_DATA16) FM(VI5_VSYNC_N_A) FM(DU_DG7) F_(0, 0) F_(0, 0) FM(LCDOUT15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IP4_7_4 FM(A10) FM(IRQ4) FM(MSIOF2_SYNC_B) FM(VI4_DATA13) FM(VI5_FIELD_A) FM(DU_DG5) FM(FSCLKST2_N_B) F_(0, 0) FM(LCDOUT13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IP4_11_8 FM(A11) FM(SCL6_A) FM(TX3_B) FM(HTX4_C) F_(0, 0) FM(DU_VSYNC) FM(VI4_DATA1_B) F_(0, 0) FM(QSTVA_QVS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IP4_15_12 FM(A12) FM(RX5_A) FM(MSIOF2_SS2_B) FM(VI4_DATA17) FM(VI5_DATA3_A) FM(DU_DG6) F_(0, 0) F_(0, 0) FM(LCDOUT14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IP4_19_16 FM(A13) FM(SCK5_A) FM(MSIOF2_SCK_B) FM(VI4_DATA14) FM(HRX4_D) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(LCDOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IP4_23_20 FM(A14) FM(MSIOF1_SS1) FM(MSIOF2_RXD_B) FM(VI4_DATA15) FM(HTX4_D) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(LCDOUT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IP4_27_24 FM(A15) FM(MSIOF1_SS2) FM(MSIOF2_TXD_B) FM(VI4_DATA18) FM(VI5_DATA4_A) FM(DU_DB4) F_(0, 0) F_(0, 0) FM(LCDOUT4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IP4_31_28 FM(A16) FM(MSIOF1_SYNC) FM(MSIOF2_SS1_B) FM(VI4_DATA19) FM(VI5_DATA5_A) FM(DU_DB5) F_(0, 0) F_(0, 0) FM(LCDOUT5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IP5_3_0 FM(A17) FM(MSIOF1_RXD) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA6_A) FM(DU_DB6) F_(0, 0) F_(0, 0) FM(LCDOUT6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IP5_7_4 FM(A18) FM(MSIOF1_TXD) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA7_A) FM(DU_DB0) F_(0, 0) FM(HRX4_E) FM(LCDOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IP5_11_8 FM(A19) FM(MSIOF1_SCK) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA2_A) FM(DU_DB1) F_(0, 0) FM(HTX4_E) FM(LCDOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IP5_15_12 FM(CS0_N) FM(SCL5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR0) FM(VI4_DATA2_B) F_(0, 0) FM(LCDOUT16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IP5_19_16 FM(WE0_N) FM(SDA5) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR1) FM(VI4_DATA3_B) F_(0, 0) FM(LCDOUT17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IP5_23_20 FM(D0) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DR2) FM(CTS4_N_C) F_(0, 0) FM(LCDOUT18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IP5_27_24 FM(D1) FM(MSIOF3_SYNC_A) FM(SCK3_A) FM(VI4_DATA23) FM(VI5_CLKENB_A) FM(DU_DB7) FM(RTS4_N_C) F_(0, 0) FM(LCDOUT7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IP5_31_28 FM(D2) FM(MSIOF3_RXD_A) FM(RX5_C) F_(0, 0) FM(VI5_DATA14_A) FM(DU_DR3) FM(RX4_C) F_(0, 0) FM(LCDOUT19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IP6_3_0 FM(D3) FM(MSIOF3_TXD_A) FM(TX5_C) F_(0, 0) FM(VI5_DATA15_A) FM(DU_DR4) FM(TX4_C) F_(0, 0) FM(LCDOUT20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IP6_7_4 FM(D4) FM(CANFD1_TX) FM(HSCK3_B) FM(CAN1_TX) FM(RTS3_N_A) FM(MSIOF3_SS2_A) F_(0, 0) FM(VI5_DATA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IP6_11_8 FM(D5) FM(RX3_A) FM(HRX3_B) F_(0, 0) F_(0, 0) FM(DU_DR5) FM(VI4_DATA4_B) F_(0, 0) FM(LCDOUT21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IP6_15_12 FM(D6) FM(TX3_A) FM(HTX3_B) F_(0, 0) F_(0, 0) FM(DU_DR6) FM(VI4_DATA5_B) F_(0, 0) FM(LCDOUT22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IP6_19_16 FM(D7) FM(CANFD1_RX) FM(IRQ5) FM(CAN1_RX) FM(CTS3_N_A) F_(0, 0) F_(0, 0) FM(VI5_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IP6_23_20 FM(D8) FM(MSIOF2_SCK_A) FM(SCK4_B) F_(0, 0) FM(VI5_DATA12_A) FM(DU_DR7) FM(RIF3_CLK_B) FM(HCTS3_N_E) FM(LCDOUT23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IP6_27_24 FM(D9) FM(MSIOF2_SYNC_A) F_(0, 0) F_(0, 0) FM(VI5_DATA10_A) FM(DU_DG0) FM(RIF3_SYNC_B) FM(HRX3_E) FM(LCDOUT8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IP6_31_28 FM(D10) FM(MSIOF2_RXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA13_A) FM(DU_DG1) FM(RIF3_D0_B) FM(HTX3_E) FM(LCDOUT9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IP7_3_0 FM(D11) FM(MSIOF2_TXD_A) F_(0, 0) F_(0, 0) FM(VI5_DATA11_A) FM(DU_DG2) FM(RIF3_D1_B) FM(HRTS3_N_E) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IP7_7_4 FM(D12) FM(CANFD0_TX) FM(TX4_B) FM(CAN0_TX) FM(VI5_DATA8_A) F_(0, 0) F_(0, 0) FM(VI5_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IP7_11_8 FM(D13) FM(CANFD0_RX) FM(RX4_B) FM(CAN0_RX) FM(VI5_DATA9_A) FM(SCL7_B) F_(0, 0) FM(VI5_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IP7_15_12 FM(D14) FM(CAN_CLK) FM(HRX3_A) FM(MSIOF2_SS2_A) F_(0, 0) FM(SDA7_B) F_(0, 0) FM(VI5_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IP7_19_16 FM(D15) FM(MSIOF2_SS1_A) FM(HTX3_A) FM(MSIOF3_SS1_A) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) FM(LCDOUT11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IP7_23_20 FM(SCL4) FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) FM(DU_DOTCLKIN0) FM(VI4_DATA6_B) FM(VI5_DATA6_B) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IP7_27_24 FM(SDA4) FM(WE1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI4_DATA7_B) FM(VI5_DATA7_B) FM(QPOLB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IP7_31_28 FM(SD0_CLK) FM(NFDATA8) FM(SCL1_C) FM(HSCK1_B) FM(SDA2_E) FM(FMCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IP8_3_0 FM(SD0_CMD) FM(NFDATA9) F_(0, 0) FM(HRX1_B) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IP8_7_4 FM(SD0_DAT0) FM(NFDATA10) F_(0, 0) FM(HTX1_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IP8_11_8 FM(SD0_DAT1) FM(NFDATA11) FM(SDA2_C) FM(HCTS1_N_B) F_(0, 0) FM(FMIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IP8_15_12 FM(SD0_DAT2) FM(NFDATA12) FM(SCL2_C) FM(HRTS1_N_B) F_(0, 0) FM(BPFCLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IP8_19_16 FM(SD0_DAT3) FM(NFDATA13) FM(SDA1_C) FM(SCL2_E) FM(SPEEDIN_C) FM(REMOCON_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IP8_23_20 FM(SD1_CLK) FM(NFDATA14_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IP8_27_24 FM(SD1_CMD) FM(NFDATA15_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IP8_31_28 FM(SD1_DAT0) FM(NFWP_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IP9_3_0 FM(SD1_DAT1) FM(NFCE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IP9_7_4 FM(SD1_DAT2) FM(NFALE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IP9_11_8 FM(SD1_DAT3) FM(NFRB_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IP9_15_12 FM(SD3_CLK) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IP9_19_16 FM(SD3_CMD) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IP9_23_20 FM(SD3_DAT0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IP9_27_24 FM(SD3_DAT1) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IP9_31_28 FM(SD3_DAT2) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IP10_3_0 FM(SD3_DAT3) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IP10_7_4 FM(SD3_DAT4) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IP10_11_8 FM(SD3_DAT5) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IP10_15_12 FM(SD3_DAT6) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IP10_19_16 FM(SD3_DAT7) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IP10_23_20 FM(SD3_DS) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IP10_27_24 FM(SD0_CD) FM(NFALE_A) FM(SD3_CD) FM(RIF0_CLK_B) FM(SCL2_B) FM(TCLK1_A) FM(SSI_SCK2_B) FM(TS_SCK0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IP10_31_28 FM(SD0_WP) FM(NFRB_N_A) FM(SD3_WP) FM(RIF0_D0_B) FM(SDA2_B) FM(TCLK2_A) FM(SSI_WS2_B) FM(TS_SDAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IP11_3_0 FM(SD1_CD) FM(NFCE_N_A) FM(SSI_SCK1) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IP11_7_4 FM(SD1_WP) FM(NFWP_N_A) FM(SSI_WS1) FM(RIF0_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IP11_11_8 FM(RX0_A) FM(HRX1_A) FM(SSI_SCK2_A) FM(RIF1_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IP11_19_16 FM(CTS0_N_A) FM(NFDATA14_A) FM(AUDIO_CLKOUT_A) FM(RIF1_D1) FM(SCIF_CLK_A) FM(FMCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IP11_23_20 FM(RTS0_N_A) FM(NFDATA15_A) FM(AUDIO_CLKOUT1_A) FM(RIF1_CLK) FM(SCL2_A) FM(FMIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IP11_27_24 FM(SCK0_A) FM(HSCK1_A) FM(USB3HS0_ID) FM(RTS1_N) FM(SDA2_A) FM(FMCLK_C) F_(0, 0) F_(0, 0) FM(USB0_ID) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IP11_31_28 FM(RX1) FM(HRX2_B) FM(SSI_SCK9_B) FM(AUDIO_CLKOUT1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IP12_3_0 FM(TX1) FM(HTX2_B) FM(SSI_WS9_B) FM(AUDIO_CLKOUT3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IP12_7_4 FM(SCK2_A) FM(HSCK0_A) FM(AUDIO_CLKB_A) FM(CTS1_N) FM(RIF0_CLK_A) FM(REMOCON_A) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IP12_11_8 FM(TX2_A) FM(HRX0_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) FM(SCL1_A) F_(0, 0) FM(FSO_CFE_0_N_A) FM(TS_SDEN1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IP12_15_12 FM(RX2_A) FM(HTX0_A) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(SDA1_A) F_(0, 0) FM(FSO_CFE_1_N_A) FM(TS_SPSYNC1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IP12_19_16 FM(MSIOF0_SCK) F_(0, 0) FM(SSI_SCK78) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IP12_23_20 FM(MSIOF0_RXD) F_(0, 0) FM(SSI_WS78) F_(0, 0) F_(0, 0) FM(TX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IP12_27_24 FM(MSIOF0_TXD) F_(0, 0) FM(SSI_SDATA7) F_(0, 0) F_(0, 0) FM(RX2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IP12_31_28 FM(MSIOF0_SYNC) FM(AUDIO_CLKOUT_B) FM(SSI_SDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IP13_3_0 FM(MSIOF0_SS1) FM(HRX2_A) FM(SSI_SCK4) FM(HCTS0_N_A) FM(BPFCLK_C) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IP13_7_4 FM(MSIOF0_SS2) FM(HTX2_A) FM(SSI_WS4) FM(HRTS0_N_A) FM(FMIN_C) FM(BPFCLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IP13_11_8 FM(SSI_SDATA9) F_(0, 0) FM(AUDIO_CLKC_A) FM(SCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IP13_15_12 FM(MLB_CLK) FM(RX0_B) F_(0, 0) FM(RIF0_D0_A) FM(SCL1_B) FM(TCLK1_B) F_(0, 0) F_(0, 0) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IP13_19_16 FM(MLB_SIG) FM(SCK0_B) F_(0, 0) FM(RIF0_D1_A) FM(SDA1_B) FM(TCLK2_B) F_(0, 0) F_(0, 0) FM(SIM0_D_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IP13_23_20 FM(MLB_DAT) FM(TX0_B) F_(0, 0) FM(RIF0_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IP13_27_24 FM(SSI_SCK01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IP13_31_28 FM(SSI_WS01239) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IP14_3_0 FM(SSI_SDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IP14_7_4 FM(SSI_SDATA1) FM(AUDIO_CLKC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IP14_11_8 FM(SSI_SDATA2) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IP14_15_12 FM(SSI_SCK349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IP14_19_16 FM(SSI_WS349) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IP14_23_20 FM(SSI_SDATA3) FM(AUDIO_CLKOUT1_C) FM(AUDIO_CLKB_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IP14_27_24 FM(SSI_SDATA4) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IP14_31_28 FM(SSI_SCK5) FM(HRX0_B) F_(0, 0) FM(USB0_PWEN_B) FM(SCL2_D) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IP15_3_0 FM(SSI_WS5) FM(HTX0_B) F_(0, 0) FM(USB0_OVC_B) FM(SDA2_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IP15_7_4 FM(SSI_SDATA5) FM(HSCK0_B) FM(AUDIO_CLKB_C) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IP15_11_8 FM(SSI_SCK6) FM(HSCK2_A) FM(AUDIO_CLKC_C) FM(TPU0TO1) F_(0, 0) F_(0, 0) FM(FSO_CFE_0_N_B) F_(0, 0) FM(SIM0_RST_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IP15_15_12 FM(SSI_WS6) FM(HCTS2_N_A) FM(AUDIO_CLKOUT2_C) FM(TPU0TO2) FM(SDA1_D) F_(0, 0) FM(FSO_CFE_1_N_B) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IP15_19_16 FM(SSI_SDATA6) FM(HRTS2_N_A) FM(AUDIO_CLKOUT3_C) FM(TPU0TO3) FM(SCL1_D) F_(0, 0) FM(FSO_TOE_N_B) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IP15_23_20 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IP15_27_24 FM(USB30_PWEN) FM(USB0_PWEN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IP15_31_28 FM(USB30_OVC) FM(USB0_OVC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PINMUX_GPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GPSR2_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) GPSR2_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) GPSR2_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) GPSR1_22 GPSR2_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) GPSR1_21 GPSR2_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) GPSR1_20 GPSR2_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) GPSR1_19 GPSR2_19 GPSR5_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) GPSR1_18 GPSR2_18 GPSR5_18 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) GPSR0_17 GPSR1_17 GPSR2_17 GPSR5_17 GPSR6_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) GPSR0_16 GPSR1_16 GPSR2_16 GPSR5_16 GPSR6_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR5_15 GPSR6_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 GPSR6_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 GPSR6_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 GPSR6_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 GPSR6_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define PINMUX_IPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* The bit numbering in MOD_SEL fields is reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define REV4(f0, f1, f2, f3) f0 f2 f1 f3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define REV8(f0, f1, f2, f3, f4, f5, f6, f7) f0 f4 f2 f6 f1 f5 f3 f7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MOD_SEL0_30_29 REV4(FM(SEL_ADGB_0), FM(SEL_ADGB_1), FM(SEL_ADGB_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MOD_SEL0_28 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MOD_SEL0_27_26 REV4(FM(SEL_FM_0), FM(SEL_FM_1), FM(SEL_FM_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MOD_SEL0_25 FM(SEL_FSO_0) FM(SEL_FSO_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MOD_SEL0_24 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MOD_SEL0_23 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MOD_SEL0_22 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MOD_SEL0_21_20 REV4(FM(SEL_I2C1_0), FM(SEL_I2C1_1), FM(SEL_I2C1_2), FM(SEL_I2C1_3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MOD_SEL0_19_18_17 REV8(FM(SEL_I2C2_0), FM(SEL_I2C2_1), FM(SEL_I2C2_2), FM(SEL_I2C2_3), FM(SEL_I2C2_4), F_(0, 0), F_(0, 0), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MOD_SEL0_16 FM(SEL_NDF_0) FM(SEL_NDF_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MOD_SEL0_15 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MOD_SEL0_14 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MOD_SEL0_13_12 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MOD_SEL0_11_10 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MOD_SEL0_9 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MOD_SEL0_8 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MOD_SEL0_7 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MOD_SEL0_6_5 REV4(FM(SEL_REMOCON_0), FM(SEL_REMOCON_1), FM(SEL_REMOCON_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MOD_SEL0_4 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MOD_SEL0_3 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MOD_SEL0_2 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MOD_SEL0_1_0 REV4(FM(SEL_SPEED_PULSE_IF_0), FM(SEL_SPEED_PULSE_IF_1), FM(SEL_SPEED_PULSE_IF_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MOD_SEL1_31 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MOD_SEL1_30 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MOD_SEL1_29 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MOD_SEL1_28 FM(SEL_USB_20_CH0_0) FM(SEL_USB_20_CH0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MOD_SEL1_26 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MOD_SEL1_25 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MOD_SEL1_24_23_22 REV8(FM(SEL_HSCIF3_0), FM(SEL_HSCIF3_1), FM(SEL_HSCIF3_2), FM(SEL_HSCIF3_3), FM(SEL_HSCIF3_4), F_(0, 0), F_(0, 0), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MOD_SEL1_21_20_19 REV8(FM(SEL_HSCIF4_0), FM(SEL_HSCIF4_1), FM(SEL_HSCIF4_2), FM(SEL_HSCIF4_3), FM(SEL_HSCIF4_4), F_(0, 0), F_(0, 0), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MOD_SEL1_18 FM(SEL_I2C6_0) FM(SEL_I2C6_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MOD_SEL1_17 FM(SEL_I2C7_0) FM(SEL_I2C7_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MOD_SEL1_16 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MOD_SEL1_15 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MOD_SEL1_14_13 REV4(FM(SEL_SCIF3_0), FM(SEL_SCIF3_1), FM(SEL_SCIF3_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MOD_SEL1_12_11 REV4(FM(SEL_SCIF4_0), FM(SEL_SCIF4_1), FM(SEL_SCIF4_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define MOD_SEL1_10_9 REV4(FM(SEL_SCIF5_0), FM(SEL_SCIF5_1), FM(SEL_SCIF5_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MOD_SEL1_8 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MOD_SEL1_7 FM(SEL_VIN5_0) FM(SEL_VIN5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MOD_SEL1_6_5 REV4(FM(SEL_ADGC_0), FM(SEL_ADGC_1), FM(SEL_ADGC_2), F_(0, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MOD_SEL1_4 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define PINMUX_MOD_SELS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MOD_SEL1_31 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MOD_SEL0_30_29 MOD_SEL1_30 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MOD_SEL1_29 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MOD_SEL0_28 MOD_SEL1_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MOD_SEL0_27_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MOD_SEL1_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MOD_SEL0_25 MOD_SEL1_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MOD_SEL0_24 MOD_SEL1_24_23_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MOD_SEL0_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MOD_SEL0_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MOD_SEL0_21_20 MOD_SEL1_21_20_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MOD_SEL0_19_18_17 MOD_SEL1_18 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MOD_SEL1_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MOD_SEL0_16 MOD_SEL1_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MOD_SEL0_15 MOD_SEL1_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MOD_SEL0_14 MOD_SEL1_14_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MOD_SEL0_13_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MOD_SEL1_12_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MOD_SEL0_11_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MOD_SEL1_10_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MOD_SEL0_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MOD_SEL0_8 MOD_SEL1_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MOD_SEL0_7 MOD_SEL1_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MOD_SEL0_6_5 MOD_SEL1_6_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MOD_SEL0_4 MOD_SEL1_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MOD_SEL0_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MOD_SEL0_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MOD_SEL0_1_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * These pins are not able to be muxed but have other properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * that can be set, such as pull-up/pull-down enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define PINMUX_STATIC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) FM(AVB_TD3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) FM(PRESETOUT_N) FM(FSCLKST_N) FM(TRST_N) FM(TCK) FM(TMS) FM(TDI) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) FM(ASEBRK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) FM(MLB_REF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define FM(x) x##_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_DATA_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_SINGLE(CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_SINGLE(AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINMUX_SINGLE(AVB_RD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_SINGLE(AVB_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_SINGLE(AVB_RX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_SINGLE(QSPI0_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_GPSR(IP0_3_0, QSPI0_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_IPSR_MSEL(IP0_3_0, HSCK4_A, SEL_HSCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINMUX_IPSR_GPSR(IP0_7_4, QSPI0_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_IPSR_MSEL(IP0_7_4, HCTS4_N_A, SEL_HSCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_GPSR(IP0_11_8, QSPI0_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINMUX_IPSR_MSEL(IP0_11_8, HRTS4_N_A, SEL_HSCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_IPSR_GPSR(IP0_15_12, QSPI0_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_IPSR_GPSR(IP0_15_12, HTX4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_IPSR_GPSR(IP0_19_16, QSPI0_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINMUX_IPSR_MSEL(IP0_19_16, HRX4_A, SEL_HSCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINMUX_IPSR_GPSR(IP0_23_20, QSPI1_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_IPSR_MSEL(IP0_23_20, RIF2_CLK_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_MSEL(IP0_23_20, HSCK4_B, SEL_HSCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_MSEL(IP0_23_20, VI4_DATA0_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_GPSR(IP0_27_24, QSPI1_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_IPSR_MSEL(IP0_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_IPSR_GPSR(IP0_27_24, HTX4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA1_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_IPSR_GPSR(IP0_31_28, QSPI1_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_IPSR_MSEL(IP0_31_28, RIF2_D0_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_IPSR_MSEL(IP0_31_28, HRX4_B, SEL_HSCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA2_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_IPSR_GPSR(IP1_3_0, QSPI1_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_IPSR_MSEL(IP1_3_0, RIF2_D1_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_IPSR_GPSR(IP1_3_0, HTX3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA3_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_IPSR_GPSR(IP1_11_8, QSPI1_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_IPSR_MSEL(IP1_11_8, RIF3_SYNC_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_IPSR_MSEL(IP1_11_8, HSCK3_C, SEL_HSCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA5_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_IPSR_GPSR(IP1_15_12, RPC_INT_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_IPSR_MSEL(IP1_15_12, RIF3_D0_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_MSEL(IP1_15_12, HCTS3_N_C, SEL_HSCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA6_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_IPSR_GPSR(IP1_19_16, RPC_RESET_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_MSEL(IP1_19_16, RIF3_D1_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_MSEL(IP1_19_16, HRTS3_N_C, SEL_HSCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA7_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_IPSR_GPSR(IP1_23_20, AVB_RD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_GPSR(IP1_27_24, AVB_RD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_GPSR(IP1_31_28, AVB_RD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_IPSR_GPSR(IP2_3_0, AVB_TXCREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_GPSR(IP2_7_4, AVB_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_GPSR(IP2_11_8, AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_GPSR(IP2_15_12, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_IPSR_MSEL(IP2_15_12, PWM0_A, SEL_PWM0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_IPSR_GPSR(IP2_15_12, AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_IPSR_GPSR(IP2_15_12, VI4_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_GPSR(IP2_15_12, TX3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_IPSR_MSEL(IP2_15_12, VI5_CLK_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_IPSR_GPSR(IP2_19_16, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_MSEL(IP2_19_16, PWM1_A, SEL_PWM1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_IPSR_GPSR(IP2_19_16, AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_IPSR_GPSR(IP2_19_16, VI4_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_IPSR_MSEL(IP2_19_16, RX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_IPSR_GPSR(IP2_19_16, FSCLKST2_N_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_IPSR_MSEL(IP2_19_16, VI5_DATA0_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_IPSR_GPSR(IP2_23_20, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_MSEL(IP2_23_20, SCL7_A, SEL_I2C7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_IPSR_GPSR(IP2_23_20, AVB_AVTP_MATCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_GPSR(IP2_23_20, VI4_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINMUX_IPSR_GPSR(IP2_23_20, TX5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_MSEL(IP2_23_20, SCK3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_MSEL(IP2_23_20, PWM5_A, SEL_PWM5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_IPSR_GPSR(IP2_27_24, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_MSEL(IP2_27_24, SDA7_A, SEL_I2C7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_GPSR(IP2_27_24, AVB_AVTP_CAPTURE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_GPSR(IP2_27_24, VI4_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_IPSR_MSEL(IP2_27_24, RX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_MSEL(IP2_27_24, PWM6_A, SEL_PWM6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_IPSR_GPSR(IP2_31_28, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_IPSR_GPSR(IP2_31_28, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_IPSR_MSEL(IP2_31_28, PWM2_A, SEL_PWM2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_MSEL(IP2_31_28, MSIOF3_SS1_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_MSEL(IP2_31_28, VI5_CLK_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_IPSR_GPSR(IP2_31_28, DU_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_MSEL(IP2_31_28, HRX3_D, SEL_HSCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_IPSR_GPSR(IP2_31_28, IERX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_GPSR(IP2_31_28, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_GPSR(IP3_3_0, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_IPSR_GPSR(IP3_3_0, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_MSEL(IP3_3_0, PWM3_A, SEL_PWM3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_IPSR_GPSR(IP3_3_0, DU_DOTCLKIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_MSEL(IP3_3_0, VI5_DATA0_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP3_3_0, DU_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_MSEL(IP3_3_0, SDA6_B, SEL_I2C6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_IPSR_GPSR(IP3_3_0, IETX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_GPSR(IP3_3_0, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINMUX_IPSR_GPSR(IP3_7_4, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_IPSR_GPSR(IP3_7_4, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_GPSR(IP3_11_8, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINMUX_IPSR_MSEL(IP3_11_8, CTS4_N_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_MSEL(IP3_11_8, PWM4_A, SEL_PWM4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_GPSR(IP3_11_8, VI4_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_IPSR_GPSR(IP3_11_8, DU_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_IPSR_GPSR(IP3_11_8, HTX3_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_GPSR(IP3_11_8, IECLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_GPSR(IP3_15_12, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_IPSR_MSEL(IP3_15_12, RTS4_N_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SYNC_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_GPSR(IP3_15_12, VI4_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_IPSR_MSEL(IP3_15_12, PWM2_B, SEL_PWM2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_MSEL(IP3_15_12, RIF2_CLK_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_GPSR(IP3_19_16, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_MSEL(IP3_19_16, SCK4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SCK_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_GPSR(IP3_19_16, VI4_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_MSEL(IP3_19_16, PWM3_B, SEL_PWM3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_MSEL(IP3_19_16, RIF2_SYNC_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_GPSR(IP3_19_16, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_GPSR(IP3_23_20, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_IPSR_MSEL(IP3_23_20, RX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_GPSR(IP3_23_20, VI4_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_MSEL(IP3_23_20, RIF2_D0_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_GPSR(IP3_27_24, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_GPSR(IP3_27_24, TX4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_GPSR(IP3_27_24, MSIOF3_TXD_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_GPSR(IP3_27_24, VI4_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_MSEL(IP3_27_24, RIF2_D1_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_GPSR(IP3_31_28, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_MSEL(IP3_31_28, SDA6_A, SEL_I2C6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_MSEL(IP3_31_28, RX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_MSEL(IP3_31_28, HRX4_C, SEL_HSCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_MSEL(IP3_31_28, VI5_HSYNC_N_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_IPSR_GPSR(IP3_31_28, DU_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_IPSR_MSEL(IP3_31_28, VI4_DATA0_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_GPSR(IP3_31_28, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_GPSR(IP4_3_0, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_GPSR(IP4_3_0, TX5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_IPSR_GPSR(IP4_3_0, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_IPSR_GPSR(IP4_3_0, VI4_DATA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_MSEL(IP4_3_0, VI5_VSYNC_N_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_GPSR(IP4_3_0, DU_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_IPSR_GPSR(IP4_7_4, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_GPSR(IP4_7_4, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_MSEL(IP4_7_4, MSIOF2_SYNC_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_GPSR(IP4_7_4, VI4_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_MSEL(IP4_7_4, VI5_FIELD_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_IPSR_GPSR(IP4_7_4, DU_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_IPSR_GPSR(IP4_7_4, FSCLKST2_N_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_IPSR_GPSR(IP4_11_8, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_MSEL(IP4_11_8, SCL6_A, SEL_I2C6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_GPSR(IP4_11_8, TX3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_IPSR_GPSR(IP4_11_8, HTX4_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_GPSR(IP4_11_8, DU_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_MSEL(IP4_11_8, VI4_DATA1_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_GPSR(IP4_11_8, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_IPSR_GPSR(IP4_15_12, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_MSEL(IP4_15_12, RX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_IPSR_GPSR(IP4_15_12, MSIOF2_SS2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_GPSR(IP4_15_12, VI4_DATA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_MSEL(IP4_15_12, VI5_DATA3_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_GPSR(IP4_15_12, DU_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_IPSR_GPSR(IP4_15_12, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_GPSR(IP4_19_16, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_MSEL(IP4_19_16, SCK5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_MSEL(IP4_19_16, MSIOF2_SCK_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_IPSR_GPSR(IP4_19_16, VI4_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_MSEL(IP4_19_16, HRX4_D, SEL_HSCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_GPSR(IP4_19_16, DU_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_GPSR(IP4_19_16, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_GPSR(IP4_23_20, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_IPSR_GPSR(IP4_23_20, MSIOF1_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_MSEL(IP4_23_20, MSIOF2_RXD_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_GPSR(IP4_23_20, VI4_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PINMUX_IPSR_GPSR(IP4_23_20, HTX4_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_GPSR(IP4_23_20, DU_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_GPSR(IP4_23_20, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_GPSR(IP4_27_24, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_GPSR(IP4_27_24, MSIOF1_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_IPSR_GPSR(IP4_27_24, MSIOF2_TXD_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_IPSR_GPSR(IP4_27_24, VI4_DATA18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_MSEL(IP4_27_24, VI5_DATA4_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_GPSR(IP4_27_24, DU_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_GPSR(IP4_27_24, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP4_31_28, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_IPSR_GPSR(IP4_31_28, MSIOF1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_GPSR(IP4_31_28, MSIOF2_SS1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_IPSR_MSEL(IP4_31_28, VI5_DATA5_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_GPSR(IP4_31_28, DU_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_GPSR(IP4_31_28, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_GPSR(IP5_3_0, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_IPSR_MSEL(IP5_3_0, VI5_DATA6_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_IPSR_GPSR(IP5_3_0, DU_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_IPSR_GPSR(IP5_3_0, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_GPSR(IP5_7_4, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_MSEL(IP5_7_4, VI5_DATA7_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_IPSR_GPSR(IP5_7_4, DU_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_MSEL(IP5_7_4, HRX4_E, SEL_HSCIF4_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_GPSR(IP5_7_4, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_GPSR(IP5_11_8, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_MSEL(IP5_11_8, VI5_DATA2_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_GPSR(IP5_11_8, DU_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP5_11_8, HTX4_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_GPSR(IP5_11_8, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP5_15_12, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_GPSR(IP5_15_12, SCL5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_GPSR(IP5_15_12, DU_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_MSEL(IP5_15_12, VI4_DATA2_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_GPSR(IP5_15_12, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP5_19_16, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP5_19_16, SDA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_GPSR(IP5_19_16, DU_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_MSEL(IP5_19_16, VI4_DATA3_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_GPSR(IP5_19_16, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_GPSR(IP5_23_20, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_GPSR(IP5_23_20, DU_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_MSEL(IP5_23_20, CTS4_N_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_GPSR(IP5_23_20, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_GPSR(IP5_27_24, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_SYNC_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_MSEL(IP5_27_24, SCK3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_MSEL(IP5_27_24, VI5_CLKENB_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_GPSR(IP5_27_24, DU_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_MSEL(IP5_27_24, RTS4_N_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_GPSR(IP5_27_24, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_GPSR(IP5_31_28, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_RXD_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_MSEL(IP5_31_28, RX5_C, SEL_SCIF5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP5_31_28, VI5_DATA14_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_IPSR_GPSR(IP5_31_28, DU_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_MSEL(IP5_31_28, RX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_GPSR(IP5_31_28, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_GPSR(IP6_3_0, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_GPSR(IP6_3_0, MSIOF3_TXD_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP6_3_0, TX5_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_MSEL(IP6_3_0, VI5_DATA15_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_IPSR_GPSR(IP6_3_0, DU_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_GPSR(IP6_3_0, TX4_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_GPSR(IP6_3_0, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_GPSR(IP6_7_4, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_GPSR(IP6_7_4, CANFD1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_MSEL(IP6_7_4, HSCK3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_GPSR(IP6_7_4, CAN1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_MSEL(IP6_7_4, RTS3_N_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_GPSR(IP6_7_4, MSIOF3_SS2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_MSEL(IP6_7_4, VI5_DATA1_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_GPSR(IP6_11_8, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_MSEL(IP6_11_8, RX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_MSEL(IP6_11_8, HRX3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_GPSR(IP6_11_8, DU_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_MSEL(IP6_11_8, VI4_DATA4_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_GPSR(IP6_11_8, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_GPSR(IP6_15_12, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_GPSR(IP6_15_12, TX3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_GPSR(IP6_15_12, HTX3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_GPSR(IP6_15_12, DU_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA5_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_GPSR(IP6_19_16, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_GPSR(IP6_19_16, CANFD1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_GPSR(IP6_19_16, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_GPSR(IP6_19_16, CAN1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_IPSR_MSEL(IP6_19_16, CTS3_N_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_MSEL(IP6_19_16, VI5_DATA2_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_GPSR(IP6_23_20, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_SCK_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_MSEL(IP6_23_20, SCK4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_MSEL(IP6_23_20, VI5_DATA12_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_GPSR(IP6_23_20, DU_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_MSEL(IP6_23_20, RIF3_CLK_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_MSEL(IP6_23_20, HCTS3_N_E, SEL_HSCIF3_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_GPSR(IP6_27_24, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_SYNC_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_MSEL(IP6_27_24, VI5_DATA10_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_GPSR(IP6_27_24, DU_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_MSEL(IP6_27_24, RIF3_SYNC_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_MSEL(IP6_27_24, HRX3_E, SEL_HSCIF3_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP6_31_28, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_RXD_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_MSEL(IP6_31_28, VI5_DATA13_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_GPSR(IP6_31_28, DU_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_MSEL(IP6_31_28, RIF3_D0_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_GPSR(IP6_31_28, HTX3_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_GPSR(IP7_3_0, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_IPSR_GPSR(IP7_3_0, MSIOF2_TXD_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_MSEL(IP7_3_0, VI5_DATA11_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_GPSR(IP7_3_0, DU_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_MSEL(IP7_3_0, RIF3_D1_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_MSEL(IP7_3_0, HRTS3_N_E, SEL_HSCIF3_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP7_7_4, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_GPSR(IP7_7_4, CANFD0_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_GPSR(IP7_7_4, TX4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_GPSR(IP7_7_4, CAN0_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA8_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_MSEL(IP7_7_4, VI5_DATA3_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_GPSR(IP7_11_8, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_GPSR(IP7_11_8, CANFD0_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_MSEL(IP7_11_8, RX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_IPSR_GPSR(IP7_11_8, CAN0_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA9_A, SEL_VIN5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_MSEL(IP7_11_8, SCL7_B, SEL_I2C7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_MSEL(IP7_11_8, VI5_DATA4_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_GPSR(IP7_15_12, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP7_15_12, CAN_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_MSEL(IP7_15_12, HRX3_A, SEL_HSCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_GPSR(IP7_15_12, MSIOF2_SS2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_MSEL(IP7_15_12, SDA7_B, SEL_I2C7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_IPSR_MSEL(IP7_15_12, VI5_DATA5_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_GPSR(IP7_19_16, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_GPSR(IP7_19_16, MSIOF2_SS1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_GPSR(IP7_19_16, HTX3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_GPSR(IP7_19_16, MSIOF3_SS1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_IPSR_GPSR(IP7_19_16, DU_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_GPSR(IP7_19_16, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP7_23_20, SCL4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_GPSR(IP7_23_20, CS1_N_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_IPSR_GPSR(IP7_23_20, DU_DOTCLKIN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_MSEL(IP7_23_20, VI4_DATA6_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_MSEL(IP7_23_20, VI5_DATA6_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_GPSR(IP7_23_20, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_IPSR_GPSR(IP7_27_24, SDA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_GPSR(IP7_27_24, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_MSEL(IP7_27_24, VI4_DATA7_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_MSEL(IP7_27_24, VI5_DATA7_B, SEL_VIN5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_GPSR(IP7_27_24, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP7_31_28, SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_GPSR(IP7_31_28, NFDATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_MSEL(IP7_31_28, SCL1_C, SEL_I2C1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_MSEL(IP7_31_28, HSCK1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_MSEL(IP7_31_28, SDA2_E, SEL_I2C2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_MSEL(IP7_31_28, FMCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_GPSR(IP8_3_0, SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_GPSR(IP8_3_0, NFDATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_MSEL(IP8_3_0, HRX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_MSEL(IP8_3_0, SPEEDIN_B, SEL_SPEED_PULSE_IF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_GPSR(IP8_7_4, NFDATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_IPSR_GPSR(IP8_7_4, HTX1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_MSEL(IP8_7_4, REMOCON_B, SEL_REMOCON_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_IPSR_GPSR(IP8_11_8, SD0_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_GPSR(IP8_11_8, NFDATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_MSEL(IP8_11_8, SDA2_C, SEL_I2C2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_MSEL(IP8_11_8, HCTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_MSEL(IP8_11_8, FMIN_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_GPSR(IP8_15_12, SD0_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_GPSR(IP8_15_12, NFDATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_IPSR_MSEL(IP8_15_12, SCL2_C, SEL_I2C2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_IPSR_MSEL(IP8_15_12, HRTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_GPSR(IP8_15_12, BPFCLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINMUX_IPSR_GPSR(IP8_19_16, SD0_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_IPSR_GPSR(IP8_19_16, NFDATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_MSEL(IP8_19_16, SDA1_C, SEL_I2C1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_MSEL(IP8_19_16, SCL2_E, SEL_I2C2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_C, SEL_SPEED_PULSE_IF_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_MSEL(IP8_19_16, REMOCON_C, SEL_REMOCON_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_GPSR(IP8_23_20, SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_MSEL(IP8_23_20, NFDATA14_B, SEL_NDF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_IPSR_GPSR(IP8_27_24, SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_MSEL(IP8_27_24, NFDATA15_B, SEL_NDF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_MSEL(IP8_31_28, NFWP_N_B, SEL_NDF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_GPSR(IP9_3_0, SD1_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_MSEL(IP9_3_0, NFCE_N_B, SEL_NDF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_IPSR_GPSR(IP9_7_4, SD1_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_MSEL(IP9_7_4, NFALE_B, SEL_NDF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_GPSR(IP9_11_8, SD1_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_IPSR_MSEL(IP9_11_8, NFRB_N_B, SEL_NDF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_IPSR_GPSR(IP9_15_12, SD3_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_GPSR(IP9_15_12, NFWE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_GPSR(IP9_19_16, SD3_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_GPSR(IP9_19_16, NFRE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_GPSR(IP9_23_20, SD3_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_GPSR(IP9_23_20, NFDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_GPSR(IP9_27_24, NFDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_IPSR_GPSR(IP9_31_28, NFDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_GPSR(IP10_3_0, NFDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_IPSR_GPSR(IP10_7_4, NFDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_GPSR(IP10_11_8, NFDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_IPSR_GPSR(IP10_15_12, NFDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_IPSR_GPSR(IP10_19_16, NFDATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_GPSR(IP10_23_20, SD3_DS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_IPSR_GPSR(IP10_23_20, NFCLE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_GPSR(IP10_27_24, SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_MSEL(IP10_27_24, NFALE_A, SEL_NDF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_GPSR(IP10_27_24, SD3_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_IPSR_MSEL(IP10_27_24, SCL2_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_MSEL(IP10_27_24, TCLK1_A, SEL_TIMER_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_MSEL(IP10_27_24, SSI_SCK2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_GPSR(IP10_27_24, TS_SCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_GPSR(IP10_31_28, SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_IPSR_MSEL(IP10_31_28, NFRB_N_A, SEL_NDF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_GPSR(IP10_31_28, SD3_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_MSEL(IP10_31_28, SDA2_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP10_31_28, TCLK2_A, SEL_TIMER_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_MSEL(IP10_31_28, SSI_WS2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_IPSR_GPSR(IP10_31_28, TS_SDAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_GPSR(IP11_3_0, SD1_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_MSEL(IP11_3_0, NFCE_N_A, SEL_NDF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_GPSR(IP11_3_0, SSI_SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_GPSR(IP11_3_0, TS_SDEN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_GPSR(IP11_7_4, SD1_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_MSEL(IP11_7_4, NFWP_N_A, SEL_NDF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_IPSR_GPSR(IP11_7_4, SSI_WS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_MSEL(IP11_7_4, RIF0_SYNC_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_GPSR(IP11_7_4, TS_SPSYNC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_MSEL(IP11_11_8, RX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_IPSR_MSEL(IP11_11_8, HRX1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_MSEL(IP11_11_8, SSI_SCK2_A, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_GPSR(IP11_11_8, RIF1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_IPSR_GPSR(IP11_11_8, TS_SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_IPSR_GPSR(IP11_15_12, HTX1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_IPSR_MSEL(IP11_15_12, SSI_WS2_A, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_GPSR(IP11_15_12, RIF1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_GPSR(IP11_15_12, TS_SDAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_MSEL(IP11_19_16, CTS0_N_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_MSEL(IP11_19_16, NFDATA14_A, SEL_NDF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_IPSR_GPSR(IP11_19_16, AUDIO_CLKOUT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_GPSR(IP11_19_16, RIF1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_MSEL(IP11_19_16, SCIF_CLK_A, SEL_SCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_MSEL(IP11_19_16, FMCLK_A, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_MSEL(IP11_23_20, RTS0_N_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_MSEL(IP11_23_20, NFDATA15_A, SEL_NDF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_GPSR(IP11_23_20, AUDIO_CLKOUT1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_GPSR(IP11_23_20, RIF1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_MSEL(IP11_23_20, SCL2_A, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_MSEL(IP11_23_20, FMIN_A, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_MSEL(IP11_27_24, SCK0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_GPSR(IP11_27_24, USB3HS0_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PINMUX_IPSR_MSEL(IP11_27_24, FMCLK_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_GPSR(IP11_27_24, USB0_ID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_GPSR(IP11_31_28, RX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_IPSR_MSEL(IP11_31_28, HRX2_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_IPSR_MSEL(IP11_31_28, SSI_SCK9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_GPSR(IP12_3_0, TX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_IPSR_GPSR(IP12_3_0, HTX2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_MSEL(IP12_3_0, SSI_WS9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_GPSR(IP12_3_0, AUDIO_CLKOUT3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_IPSR_MSEL(IP12_7_4, SCK2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINMUX_IPSR_MSEL(IP12_7_4, HSCK0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_IPSR_MSEL(IP12_7_4, AUDIO_CLKB_A, SEL_ADGB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_GPSR(IP12_7_4, CTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_IPSR_MSEL(IP12_7_4, RIF0_CLK_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_A, SEL_REMOCON_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINMUX_IPSR_MSEL(IP12_7_4, SCIF_CLK_B, SEL_SCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_IPSR_MSEL(IP12_11_8, TX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_MSEL(IP12_11_8, HRX0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_IPSR_GPSR(IP12_11_8, AUDIO_CLKOUT2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_IPSR_MSEL(IP12_11_8, SCL1_A, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_MSEL(IP12_11_8, FSO_CFE_0_N_A, SEL_FSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_GPSR(IP12_11_8, TS_SDEN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_IPSR_MSEL(IP12_15_12, RX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_IPSR_GPSR(IP12_15_12, HTX0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINMUX_IPSR_GPSR(IP12_15_12, AUDIO_CLKOUT3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_MSEL(IP12_15_12, SDA1_A, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_MSEL(IP12_15_12, FSO_CFE_1_N_A, SEL_FSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_GPSR(IP12_15_12, TS_SPSYNC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_IPSR_GPSR(IP12_19_16, MSIOF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_GPSR(IP12_19_16, SSI_SCK78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_GPSR(IP12_23_20, MSIOF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINMUX_IPSR_GPSR(IP12_23_20, SSI_WS78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_IPSR_MSEL(IP12_23_20, TX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_GPSR(IP12_27_24, MSIOF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_IPSR_GPSR(IP12_27_24, SSI_SDATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_MSEL(IP12_27_24, RX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_IPSR_GPSR(IP12_31_28, AUDIO_CLKOUT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_IPSR_GPSR(IP12_31_28, SSI_SDATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_IPSR_MSEL(IP13_3_0, HRX2_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_GPSR(IP13_3_0, SSI_SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_IPSR_MSEL(IP13_3_0, HCTS0_N_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_IPSR_GPSR(IP13_3_0, BPFCLK_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_MSEL(IP13_3_0, SPEEDIN_A, SEL_SPEED_PULSE_IF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINMUX_IPSR_GPSR(IP13_7_4, HTX2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_IPSR_GPSR(IP13_7_4, SSI_WS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_IPSR_MSEL(IP13_7_4, HRTS0_N_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_MSEL(IP13_7_4, FMIN_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_IPSR_GPSR(IP13_7_4, BPFCLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_GPSR(IP13_11_8, SSI_SDATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKC_A, SEL_ADGC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_IPSR_GPSR(IP13_11_8, SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_GPSR(IP13_15_12, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_MSEL(IP13_15_12, RX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_MSEL(IP13_15_12, SCL1_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_IPSR_MSEL(IP13_15_12, TCLK1_B, SEL_TIMER_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_GPSR(IP13_15_12, SIM0_RST_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_IPSR_GPSR(IP13_19_16, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_MSEL(IP13_19_16, SCK0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_IPSR_MSEL(IP13_19_16, SDA1_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_MSEL(IP13_19_16, TCLK2_B, SEL_TIMER_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_MSEL(IP13_19_16, SIM0_D_A, SEL_SIMCARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_GPSR(IP13_23_20, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINMUX_IPSR_MSEL(IP13_23_20, TX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_IPSR_GPSR(IP13_23_20, SIM0_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_GPSR(IP13_27_24, SSI_SCK01239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_GPSR(IP13_31_28, SSI_WS01239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_IPSR_GPSR(IP14_3_0, SSI_SDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_GPSR(IP14_7_4, SSI_SDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_B, SEL_ADGC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_IPSR_MSEL(IP14_7_4, PWM0_B, SEL_PWM0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_IPSR_GPSR(IP14_11_8, SSI_SDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_GPSR(IP14_11_8, AUDIO_CLKOUT2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK9_A, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_MSEL(IP14_11_8, PWM1_B, SEL_PWM1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_IPSR_GPSR(IP14_15_12, SSI_SCK349),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_IPSR_MSEL(IP14_15_12, PWM2_C, SEL_PWM2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINMUX_IPSR_GPSR(IP14_19_16, SSI_WS349),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_IPSR_MSEL(IP14_19_16, PWM3_C, SEL_PWM3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_GPSR(IP14_23_20, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_IPSR_GPSR(IP14_23_20, AUDIO_CLKOUT1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_MSEL(IP14_23_20, AUDIO_CLKB_B, SEL_ADGB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_MSEL(IP14_23_20, PWM4_B, SEL_PWM4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINMUX_IPSR_GPSR(IP14_27_24, SSI_SDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS9_A, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_IPSR_MSEL(IP14_27_24, PWM5_B, SEL_PWM5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_GPSR(IP14_31_28, SSI_SCK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_MSEL(IP14_31_28, HRX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_IPSR_GPSR(IP14_31_28, USB0_PWEN_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_IPSR_MSEL(IP14_31_28, SCL2_D, SEL_I2C2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_IPSR_MSEL(IP14_31_28, PWM6_B, SEL_PWM6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_IPSR_GPSR(IP15_3_0, SSI_WS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_IPSR_GPSR(IP15_3_0, HTX0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_IPSR_MSEL(IP15_3_0, USB0_OVC_B, SEL_USB_20_CH0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_IPSR_MSEL(IP15_3_0, SDA2_D, SEL_I2C2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_IPSR_GPSR(IP15_7_4, SSI_SDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINMUX_IPSR_MSEL(IP15_7_4, HSCK0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_IPSR_MSEL(IP15_7_4, AUDIO_CLKB_C, SEL_ADGB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_IPSR_GPSR(IP15_7_4, TPU0TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_IPSR_MSEL(IP15_11_8, HSCK2_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINMUX_IPSR_MSEL(IP15_11_8, AUDIO_CLKC_C, SEL_ADGC_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_IPSR_GPSR(IP15_11_8, TPU0TO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_IPSR_MSEL(IP15_11_8, FSO_CFE_0_N_B, SEL_FSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINMUX_IPSR_GPSR(IP15_11_8, SIM0_RST_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_IPSR_GPSR(IP15_15_12, AUDIO_CLKOUT2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_IPSR_GPSR(IP15_15_12, TPU0TO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINMUX_IPSR_MSEL(IP15_15_12, SDA1_D, SEL_I2C1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_IPSR_MSEL(IP15_15_12, FSO_CFE_1_N_B, SEL_FSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_IPSR_MSEL(IP15_15_12, SIM0_D_B, SEL_SIMCARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINMUX_IPSR_GPSR(IP15_19_16, AUDIO_CLKOUT3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINMUX_IPSR_GPSR(IP15_19_16, TPU0TO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_IPSR_MSEL(IP15_19_16, SCL1_D, SEL_I2C1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINMUX_IPSR_MSEL(IP15_19_16, FSO_TOE_N_B, SEL_FSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINMUX_IPSR_GPSR(IP15_19_16, SIM0_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINMUX_IPSR_GPSR(IP15_23_20, AUDIO_CLKA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_IPSR_GPSR(IP15_27_24, USB30_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINMUX_IPSR_GPSR(IP15_27_24, USB0_PWEN_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_IPSR_GPSR(IP15_31_28, USB30_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINMUX_IPSR_MSEL(IP15_31_28, USB0_OVC_A, SEL_USB_20_CH0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * Static pins can not be muxed between different functions but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) * still need mark entries in the pinmux list. Add each static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) * pin to the list without an associated function. The sh-pfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) * core will do the right thing and skip trying to mux the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) * while still applying configuration to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define FM(x) PINMUX_DATA(x##_MARK, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINMUX_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * Pins not associated with a GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GP_ASSIGN_LAST(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* - AUDIO CLOCK ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const unsigned int audio_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* CLK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) RCAR_GP_PIN(6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static const unsigned int audio_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const unsigned int audio_clk_b_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* CLK B_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static const unsigned int audio_clk_b_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) AUDIO_CLKB_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static const unsigned int audio_clk_b_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* CLK B_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const unsigned int audio_clk_b_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) AUDIO_CLKB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static const unsigned int audio_clk_b_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* CLK B_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) RCAR_GP_PIN(6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static const unsigned int audio_clk_b_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) AUDIO_CLKB_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static const unsigned int audio_clk_c_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /* CLK C_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static const unsigned int audio_clk_c_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) AUDIO_CLKC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static const unsigned int audio_clk_c_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) /* CLK C_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const unsigned int audio_clk_c_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) AUDIO_CLKC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) static const unsigned int audio_clk_c_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* CLK C_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) static const unsigned int audio_clk_c_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) AUDIO_CLKC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static const unsigned int audio_clkout_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* CLKOUT_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const unsigned int audio_clkout_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) AUDIO_CLKOUT_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static const unsigned int audio_clkout_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* CLKOUT_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static const unsigned int audio_clkout_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) AUDIO_CLKOUT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const unsigned int audio_clkout1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* CLKOUT1_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static const unsigned int audio_clkout1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) AUDIO_CLKOUT1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static const unsigned int audio_clkout1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* CLKOUT1_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static const unsigned int audio_clkout1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) AUDIO_CLKOUT1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const unsigned int audio_clkout1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* CLKOUT1_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static const unsigned int audio_clkout1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) AUDIO_CLKOUT1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const unsigned int audio_clkout2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* CLKOUT2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const unsigned int audio_clkout2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) AUDIO_CLKOUT2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const unsigned int audio_clkout2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* CLKOUT2_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) RCAR_GP_PIN(6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static const unsigned int audio_clkout2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) AUDIO_CLKOUT2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const unsigned int audio_clkout2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* CLKOUT2_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static const unsigned int audio_clkout2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) AUDIO_CLKOUT2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const unsigned int audio_clkout3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* CLKOUT3_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static const unsigned int audio_clkout3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) AUDIO_CLKOUT3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const unsigned int audio_clkout3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* CLKOUT3_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const unsigned int audio_clkout3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) AUDIO_CLKOUT3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static const unsigned int audio_clkout3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* CLKOUT3_C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) RCAR_GP_PIN(6, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const unsigned int audio_clkout3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) AUDIO_CLKOUT3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* - EtherAVB --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* AVB_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* AVB_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* AVB_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned int avb_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * AVB_RX_CTL, AVB_RXC, AVB_RD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) * AVB_RD1, AVB_RD2, AVB_RD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * AVB_TXCREFCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const unsigned int avb_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) AVB_TXCREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const unsigned int avb_avtp_pps_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* AVB_AVTP_PPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const unsigned int avb_avtp_pps_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) AVB_AVTP_PPS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const unsigned int avb_avtp_match_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* AVB_AVTP_MATCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const unsigned int avb_avtp_match_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) AVB_AVTP_MATCH_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static const unsigned int avb_avtp_capture_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) /* AVB_AVTP_CAPTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static const unsigned int avb_avtp_capture_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) AVB_AVTP_CAPTURE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* - CAN ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static const unsigned int can0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int can0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) CAN0_TX_MARK, CAN0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static const unsigned int can1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static const unsigned int can1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) CAN1_TX_MARK, CAN1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) /* - CAN Clock -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const unsigned int can_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static const unsigned int can_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* - CAN FD --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const unsigned int canfd0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static const unsigned int canfd0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) CANFD0_TX_MARK, CANFD0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static const unsigned int canfd1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static const unsigned int canfd1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) CANFD1_TX_MARK, CANFD1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* - DRIF0 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static const unsigned int drif0_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static const unsigned int drif0_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const unsigned int drif0_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static const unsigned int drif0_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) RIF0_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static const unsigned int drif0_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static const unsigned int drif0_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) RIF0_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) static const unsigned int drif0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static const unsigned int drif0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static const unsigned int drif0_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static const unsigned int drif0_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) RIF0_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static const unsigned int drif0_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static const unsigned int drif0_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) RIF0_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* - DRIF1 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static const unsigned int drif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static const unsigned int drif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) RIF1_CLK_MARK, RIF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static const unsigned int drif1_data0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static const unsigned int drif1_data0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) RIF1_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static const unsigned int drif1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned int drif1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) RIF1_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* - DRIF2 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static const unsigned int drif2_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static const unsigned int drif2_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const unsigned int drif2_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static const unsigned int drif2_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) RIF2_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static const unsigned int drif2_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const unsigned int drif2_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) RIF2_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int drif2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static const unsigned int drif2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const unsigned int drif2_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const unsigned int drif2_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) RIF2_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static const unsigned int drif2_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static const unsigned int drif2_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) RIF2_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /* - DRIF3 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static const unsigned int drif3_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static const unsigned int drif3_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const unsigned int drif3_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static const unsigned int drif3_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) RIF3_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static const unsigned int drif3_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static const unsigned int drif3_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) RIF3_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const unsigned int drif3_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static const unsigned int drif3_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static const unsigned int drif3_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static const unsigned int drif3_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) RIF3_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static const unsigned int drif3_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const unsigned int drif3_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) RIF3_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) DU_DR3_MARK, DU_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) DU_DG3_MARK, DU_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) DU_DB3_MARK, DU_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static const unsigned int du_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) RCAR_GP_PIN(0, 1), RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static const unsigned int du_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static const unsigned int du_clk_in_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* CLKIN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static const unsigned int du_clk_in_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) DU_DOTCLKIN0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static const unsigned int du_clk_in_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) /* CLKIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static const unsigned int du_clk_in_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) DU_DOTCLKIN1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) static const unsigned int du_clk_out_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static const unsigned int du_clk_out_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) DU_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static const unsigned int du_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* VSYNC, HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static const unsigned int du_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) DU_VSYNC_MARK, DU_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static const unsigned int du_disp_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* DISP_CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const unsigned int du_disp_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) DU_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) DU_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static const unsigned int du_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static const unsigned int du_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) DU_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) /* - HSCIF0 --------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static const unsigned int hscif0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static const unsigned int hscif0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) HRX0_A_MARK, HTX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const unsigned int hscif0_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) static const unsigned int hscif0_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) HSCK0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static const unsigned int hscif0_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const unsigned int hscif0_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) HRTS0_N_A_MARK, HCTS0_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static const unsigned int hscif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static const unsigned int hscif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) HRX0_B_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static const unsigned int hscif0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) RCAR_GP_PIN(6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static const unsigned int hscif0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) HSCK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* - HSCIF1 ------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const unsigned int hscif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static const unsigned int hscif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) HRX1_A_MARK, HTX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static const unsigned int hscif1_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static const unsigned int hscif1_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) HSCK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const unsigned int hscif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static const unsigned int hscif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) HRX1_B_MARK, HTX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static const unsigned int hscif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static const unsigned int hscif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) HSCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static const unsigned int hscif1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const unsigned int hscif1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) HRTS1_N_B_MARK, HCTS1_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* - HSCIF2 ------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static const unsigned int hscif2_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static const unsigned int hscif2_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) HRX2_A_MARK, HTX2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static const unsigned int hscif2_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static const unsigned int hscif2_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) HSCK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static const unsigned int hscif2_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static const unsigned int hscif2_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) HRTS2_N_A_MARK, HCTS2_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static const unsigned int hscif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static const unsigned int hscif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) HRX2_B_MARK, HTX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* - HSCIF3 ------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static const unsigned int hscif3_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static const unsigned int hscif3_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) HRX3_A_MARK, HTX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static const unsigned int hscif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) static const unsigned int hscif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) HRX3_B_MARK, HTX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static const unsigned int hscif3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static const unsigned int hscif3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) HSCK3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static const unsigned int hscif3_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) static const unsigned int hscif3_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) HRX3_C_MARK, HTX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const unsigned int hscif3_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const unsigned int hscif3_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) HSCK3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static const unsigned int hscif3_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static const unsigned int hscif3_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) HRTS3_N_C_MARK, HCTS3_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static const unsigned int hscif3_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) static const unsigned int hscif3_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) HRX3_D_MARK, HTX3_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static const unsigned int hscif3_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static const unsigned int hscif3_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) HRX3_E_MARK, HTX3_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static const unsigned int hscif3_ctrl_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static const unsigned int hscif3_ctrl_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) HRTS3_N_E_MARK, HCTS3_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* - HSCIF4 -------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static const unsigned int hscif4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static const unsigned int hscif4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) HRX4_A_MARK, HTX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static const unsigned int hscif4_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static const unsigned int hscif4_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) HSCK4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) static const unsigned int hscif4_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static const unsigned int hscif4_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) HRTS4_N_A_MARK, HCTS4_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) static const unsigned int hscif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static const unsigned int hscif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) HRX4_B_MARK, HTX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) static const unsigned int hscif4_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static const unsigned int hscif4_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) HSCK4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static const unsigned int hscif4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static const unsigned int hscif4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) HRX4_C_MARK, HTX4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static const unsigned int hscif4_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static const unsigned int hscif4_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) HRX4_D_MARK, HTX4_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static const unsigned int hscif4_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) static const unsigned int hscif4_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) HRX4_E_MARK, HTX4_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) /* - I2C -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static const unsigned int i2c1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static const unsigned int i2c1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) SCL1_A_MARK, SDA1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static const unsigned int i2c1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static const unsigned int i2c1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) SCL1_B_MARK, SDA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) static const unsigned int i2c1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static const unsigned int i2c1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) SCL1_C_MARK, SDA1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static const unsigned int i2c1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static const unsigned int i2c1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) SCL1_D_MARK, SDA1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static const unsigned int i2c2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static const unsigned int i2c2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) SCL2_A_MARK, SDA2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) SCL2_B_MARK, SDA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static const unsigned int i2c2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) static const unsigned int i2c2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) SCL2_C_MARK, SDA2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) static const unsigned int i2c2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static const unsigned int i2c2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) SCL2_D_MARK, SDA2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) static const unsigned int i2c2_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static const unsigned int i2c2_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) SCL2_E_MARK, SDA2_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static const unsigned int i2c4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) static const unsigned int i2c4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) SCL4_MARK, SDA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static const unsigned int i2c5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static const unsigned int i2c5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) SCL5_MARK, SDA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) static const unsigned int i2c6_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static const unsigned int i2c6_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) SCL6_A_MARK, SDA6_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) static const unsigned int i2c6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static const unsigned int i2c6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) SCL6_B_MARK, SDA6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static const unsigned int i2c7_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) static const unsigned int i2c7_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) SCL7_A_MARK, SDA7_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static const unsigned int i2c7_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static const unsigned int i2c7_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) SCL7_B_MARK, SDA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* - INTC-EX ---------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static const unsigned int intc_ex_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static const unsigned int intc_ex_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) static const unsigned int intc_ex_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static const unsigned int intc_ex_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static const unsigned int intc_ex_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) static const unsigned int intc_ex_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) static const unsigned int intc_ex_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static const unsigned int intc_ex_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static const unsigned int intc_ex_irq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static const unsigned int intc_ex_irq4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) IRQ4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) static const unsigned int intc_ex_irq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static const unsigned int intc_ex_irq5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) IRQ5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static const unsigned int msiof0_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) static const unsigned int msiof0_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) static const unsigned int msiof0_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static const unsigned int msiof0_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static const unsigned int msiof1_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static const unsigned int msiof1_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static const unsigned int msiof1_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const unsigned int msiof1_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static const unsigned int msiof2_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static const unsigned int msiof2_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) MSIOF2_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) static const unsigned int msiof2_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static const unsigned int msiof2_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) MSIOF2_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static const unsigned int msiof2_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static const unsigned int msiof2_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) MSIOF2_SS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) static const unsigned int msiof2_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const unsigned int msiof2_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) MSIOF2_SS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static const unsigned int msiof2_txd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static const unsigned int msiof2_txd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) MSIOF2_TXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static const unsigned int msiof2_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static const unsigned int msiof2_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) MSIOF2_RXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) static const unsigned int msiof2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static const unsigned int msiof2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) MSIOF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static const unsigned int msiof2_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) static const unsigned int msiof2_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) MSIOF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) static const unsigned int msiof2_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static const unsigned int msiof2_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) MSIOF2_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static const unsigned int msiof2_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) static const unsigned int msiof2_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) MSIOF2_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) static const unsigned int msiof2_txd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static const unsigned int msiof2_txd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) MSIOF2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) static const unsigned int msiof2_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) static const unsigned int msiof2_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) MSIOF2_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* - MSIOF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static const unsigned int msiof3_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) static const unsigned int msiof3_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) MSIOF3_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static const unsigned int msiof3_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static const unsigned int msiof3_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) MSIOF3_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) static const unsigned int msiof3_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static const unsigned int msiof3_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) MSIOF3_SS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) static const unsigned int msiof3_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static const unsigned int msiof3_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) MSIOF3_SS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static const unsigned int msiof3_txd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) static const unsigned int msiof3_txd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) MSIOF3_TXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) static const unsigned int msiof3_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) static const unsigned int msiof3_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) MSIOF3_RXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static const unsigned int msiof3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static const unsigned int msiof3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) MSIOF3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) static const unsigned int msiof3_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static const unsigned int msiof3_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) MSIOF3_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static const unsigned int msiof3_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static const unsigned int msiof3_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) MSIOF3_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) static const unsigned int msiof3_txd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static const unsigned int msiof3_txd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) MSIOF3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static const unsigned int msiof3_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static const unsigned int msiof3_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) MSIOF3_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* - PWM0 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) static const unsigned int pwm0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static const unsigned int pwm0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) PWM0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) /* - PWM1 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const unsigned int pwm1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static const unsigned int pwm1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) PWM1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) RCAR_GP_PIN(6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /* - PWM2 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static const unsigned int pwm2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static const unsigned int pwm2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) PWM2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) static const unsigned int pwm2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) RCAR_GP_PIN(6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) static const unsigned int pwm2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) PWM2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* - PWM3 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static const unsigned int pwm3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) static const unsigned int pwm3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) PWM3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) static const unsigned int pwm3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static const unsigned int pwm3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) static const unsigned int pwm3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static const unsigned int pwm3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) PWM3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* - PWM4 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) static const unsigned int pwm4_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static const unsigned int pwm4_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) PWM4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) static const unsigned int pwm4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) static const unsigned int pwm4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) /* - PWM5 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) static const unsigned int pwm5_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) static const unsigned int pwm5_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) PWM5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static const unsigned int pwm5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) static const unsigned int pwm5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) PWM5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) /* - PWM6 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static const unsigned int pwm6_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) static const unsigned int pwm6_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) PWM6_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) static const unsigned int pwm6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) RCAR_GP_PIN(6, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) static const unsigned int pwm6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) PWM6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) static const unsigned int scif0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) static const unsigned int scif0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) RX0_A_MARK, TX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static const unsigned int scif0_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static const unsigned int scif0_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) SCK0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static const unsigned int scif0_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) static const unsigned int scif0_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) RTS0_N_A_MARK, CTS0_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) static const unsigned int scif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) static const unsigned int scif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) RX0_B_MARK, TX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) static const unsigned int scif0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static const unsigned int scif0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) SCK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) static const unsigned int scif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static const unsigned int scif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) RX1_MARK, TX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) static const unsigned int scif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) static const unsigned int scif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) SCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) static const unsigned int scif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) static const unsigned int scif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) RTS1_N_MARK, CTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) static const unsigned int scif2_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) static const unsigned int scif2_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) RX2_A_MARK, TX2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) static const unsigned int scif2_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static const unsigned int scif2_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) SCK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) static const unsigned int scif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) static const unsigned int scif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) RX2_B_MARK, TX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static const unsigned int scif3_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) static const unsigned int scif3_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) RX3_A_MARK, TX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) static const unsigned int scif3_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) static const unsigned int scif3_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) SCK3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static const unsigned int scif3_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) static const unsigned int scif3_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) RTS3_N_A_MARK, CTS3_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) static const unsigned int scif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static const unsigned int scif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) RX3_B_MARK, TX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) static const unsigned int scif3_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) static const unsigned int scif3_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) RX3_C_MARK, TX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) static const unsigned int scif3_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) static const unsigned int scif3_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) SCK3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static const unsigned int scif4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static const unsigned int scif4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) RX4_A_MARK, TX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) static const unsigned int scif4_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static const unsigned int scif4_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) SCK4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) static const unsigned int scif4_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static const unsigned int scif4_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) RTS4_N_A_MARK, CTS4_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) static const unsigned int scif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) static const unsigned int scif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) RX4_B_MARK, TX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) static const unsigned int scif4_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) static const unsigned int scif4_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) SCK4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static const unsigned int scif4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) static const unsigned int scif4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) RX4_C_MARK, TX4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) static const unsigned int scif4_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) static const unsigned int scif4_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) RTS4_N_C_MARK, CTS4_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) static const unsigned int scif5_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) static const unsigned int scif5_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) RX5_A_MARK, TX5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) static const unsigned int scif5_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) static const unsigned int scif5_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) SCK5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) static const unsigned int scif5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) static const unsigned int scif5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) RX5_B_MARK, TX5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) static const unsigned int scif5_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) static const unsigned int scif5_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) RX5_C_MARK, TX5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) static const unsigned int scif_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) static const unsigned int scif_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) SCIF_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) SD0_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) SD0_DAT0_MARK, SD0_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) SD0_DAT2_MARK, SD0_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) SD0_CLK_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) SD0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) SD1_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) SD1_DAT0_MARK, SD1_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) SD1_DAT2_MARK, SD1_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) SD1_CLK_MARK, SD1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) /* - SDHI3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) static const unsigned int sdhi3_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) static const unsigned int sdhi3_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) SD3_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) static const unsigned int sdhi3_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) static const unsigned int sdhi3_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) SD3_DAT0_MARK, SD3_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) SD3_DAT2_MARK, SD3_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static const unsigned int sdhi3_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) static const unsigned int sdhi3_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) SD3_DAT0_MARK, SD3_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) SD3_DAT2_MARK, SD3_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) SD3_DAT4_MARK, SD3_DAT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) SD3_DAT6_MARK, SD3_DAT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) static const unsigned int sdhi3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) static const unsigned int sdhi3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) SD3_CLK_MARK, SD3_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) static const unsigned int sdhi3_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) static const unsigned int sdhi3_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) SD3_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) static const unsigned int sdhi3_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) static const unsigned int sdhi3_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) SD3_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) static const unsigned int sdhi3_ds_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /* DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) static const unsigned int sdhi3_ds_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) SD3_DS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) /* - SSI -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) static const unsigned int ssi0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) RCAR_GP_PIN(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) static const unsigned int ssi0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) SSI_SDATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) static const unsigned int ssi01239_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static const unsigned int ssi01239_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) SSI_SCK01239_MARK, SSI_WS01239_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) static const unsigned int ssi1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) static const unsigned int ssi1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) SSI_SDATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) static const unsigned int ssi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) static const unsigned int ssi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) SSI_SCK1_MARK, SSI_WS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) static const unsigned int ssi2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) RCAR_GP_PIN(6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) static const unsigned int ssi2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) SSI_SDATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static const unsigned int ssi2_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) static const unsigned int ssi2_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) static const unsigned int ssi2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static const unsigned int ssi2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static const unsigned int ssi3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) static const unsigned int ssi3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) SSI_SDATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) static const unsigned int ssi349_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) static const unsigned int ssi349_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) SSI_SCK349_MARK, SSI_WS349_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) static const unsigned int ssi4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) static const unsigned int ssi4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) SSI_SDATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) static const unsigned int ssi4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) static const unsigned int ssi4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) SSI_SCK4_MARK, SSI_WS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) static const unsigned int ssi5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) RCAR_GP_PIN(6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) static const unsigned int ssi5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) SSI_SDATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) static const unsigned int ssi5_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static const unsigned int ssi5_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) SSI_SCK5_MARK, SSI_WS5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) static const unsigned int ssi6_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) RCAR_GP_PIN(6, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static const unsigned int ssi6_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) SSI_SDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) static const unsigned int ssi6_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) static const unsigned int ssi6_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) SSI_SCK6_MARK, SSI_WS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) static const unsigned int ssi7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) static const unsigned int ssi7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) static const unsigned int ssi78_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) static const unsigned int ssi78_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) SSI_SCK78_MARK, SSI_WS78_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) static const unsigned int ssi8_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) static const unsigned int ssi8_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) static const unsigned int ssi9_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) static const unsigned int ssi9_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) SSI_SDATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) static const unsigned int ssi9_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) static const unsigned int ssi9_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) static const unsigned int ssi9_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) static const unsigned int ssi9_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) /* - TMU -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) static const unsigned int tmu_tclk1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) static const unsigned int tmu_tclk1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) TCLK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) static const unsigned int tmu_tclk1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) static const unsigned int tmu_tclk1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) static const unsigned int tmu_tclk2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) static const unsigned int tmu_tclk2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) TCLK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) static const unsigned int tmu_tclk2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) static const unsigned int tmu_tclk2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) TCLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) static const unsigned int usb0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) static const unsigned int usb0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) USB0_PWEN_A_MARK, USB0_OVC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) static const unsigned int usb0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) static const unsigned int usb0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) USB0_PWEN_B_MARK, USB0_OVC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) static const unsigned int usb0_id_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) /* ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) RCAR_GP_PIN(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) static const unsigned int usb0_id_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) USB0_ID_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) /* - USB30 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) static const unsigned int usb30_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) static const unsigned int usb30_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) USB30_PWEN_MARK, USB30_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) static const unsigned int usb30_id_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) /* ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) static const unsigned int usb30_id_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) USB3HS0_ID_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) /* - VIN4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) static const unsigned int vin4_data18_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) static const unsigned int vin4_data18_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) VI4_DATA10_MARK, VI4_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) VI4_DATA12_MARK, VI4_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) VI4_DATA14_MARK, VI4_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) VI4_DATA18_MARK, VI4_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) VI4_DATA20_MARK, VI4_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) VI4_DATA22_MARK, VI4_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) static const union vin_data vin4_data_a_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) static const union vin_data vin4_data_a_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) VI4_DATA8_MARK, VI4_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) VI4_DATA10_MARK, VI4_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) VI4_DATA12_MARK, VI4_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) VI4_DATA14_MARK, VI4_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) VI4_DATA16_MARK, VI4_DATA17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) VI4_DATA18_MARK, VI4_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) VI4_DATA20_MARK, VI4_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) VI4_DATA22_MARK, VI4_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) static const unsigned int vin4_data18_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) static const unsigned int vin4_data18_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) VI4_DATA10_MARK, VI4_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) VI4_DATA12_MARK, VI4_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) VI4_DATA14_MARK, VI4_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) VI4_DATA18_MARK, VI4_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) VI4_DATA20_MARK, VI4_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) VI4_DATA22_MARK, VI4_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) static const union vin_data vin4_data_b_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) RCAR_GP_PIN(1, 19), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) static const union vin_data vin4_data_b_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) VI4_DATA8_MARK, VI4_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) VI4_DATA10_MARK, VI4_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) VI4_DATA12_MARK, VI4_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) VI4_DATA14_MARK, VI4_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) VI4_DATA16_MARK, VI4_DATA17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) VI4_DATA18_MARK, VI4_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) VI4_DATA20_MARK, VI4_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) VI4_DATA22_MARK, VI4_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static const unsigned int vin4_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) /* HSYNC, VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) static const unsigned int vin4_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) static const unsigned int vin4_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) static const unsigned int vin4_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) VI4_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) static const unsigned int vin4_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) static const unsigned int vin4_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) VI4_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) static const unsigned int vin4_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) static const unsigned int vin4_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) VI4_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) /* - VIN5 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) static const union vin_data16 vin5_data_a_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) .data16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) static const union vin_data16 vin5_data_a_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) .data16 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) VI5_DATA0_A_MARK, VI5_DATA1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) VI5_DATA2_A_MARK, VI5_DATA3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) VI5_DATA4_A_MARK, VI5_DATA5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) VI5_DATA6_A_MARK, VI5_DATA7_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) VI5_DATA8_A_MARK, VI5_DATA9_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) VI5_DATA10_A_MARK, VI5_DATA11_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) VI5_DATA12_A_MARK, VI5_DATA13_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) VI5_DATA14_A_MARK, VI5_DATA15_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) static const unsigned int vin5_data8_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) static const unsigned int vin5_data8_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) VI5_DATA0_B_MARK, VI5_DATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) VI5_DATA2_B_MARK, VI5_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) VI5_DATA4_B_MARK, VI5_DATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) VI5_DATA6_B_MARK, VI5_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static const unsigned int vin5_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /* HSYNC_N, VSYNC_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) static const unsigned int vin5_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) VI5_HSYNC_N_A_MARK, VI5_VSYNC_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) static const unsigned int vin5_field_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) static const unsigned int vin5_field_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) VI5_FIELD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) static const unsigned int vin5_clkenb_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) static const unsigned int vin5_clkenb_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) VI5_CLKENB_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) static const unsigned int vin5_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) static const unsigned int vin5_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) VI5_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) static const unsigned int vin5_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) static const unsigned int vin5_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) VI5_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) struct sh_pfc_pin_group common[247];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) struct sh_pfc_pin_group automotive[21];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) } pinmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) SH_PFC_PIN_GROUP(audio_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) SH_PFC_PIN_GROUP(audio_clk_b_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) SH_PFC_PIN_GROUP(audio_clk_b_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) SH_PFC_PIN_GROUP(audio_clk_b_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) SH_PFC_PIN_GROUP(audio_clk_c_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) SH_PFC_PIN_GROUP(audio_clk_c_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) SH_PFC_PIN_GROUP(audio_clk_c_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) SH_PFC_PIN_GROUP(audio_clkout_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) SH_PFC_PIN_GROUP(audio_clkout_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) SH_PFC_PIN_GROUP(audio_clkout1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) SH_PFC_PIN_GROUP(audio_clkout1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) SH_PFC_PIN_GROUP(audio_clkout1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) SH_PFC_PIN_GROUP(audio_clkout2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) SH_PFC_PIN_GROUP(audio_clkout2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) SH_PFC_PIN_GROUP(audio_clkout2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) SH_PFC_PIN_GROUP(audio_clkout3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) SH_PFC_PIN_GROUP(audio_clkout3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) SH_PFC_PIN_GROUP(audio_clkout3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) SH_PFC_PIN_GROUP(avb_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) SH_PFC_PIN_GROUP(avb_avtp_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) SH_PFC_PIN_GROUP(avb_avtp_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) SH_PFC_PIN_GROUP(avb_avtp_capture),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) SH_PFC_PIN_GROUP(can0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) SH_PFC_PIN_GROUP(can1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) SH_PFC_PIN_GROUP(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) SH_PFC_PIN_GROUP(canfd0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) SH_PFC_PIN_GROUP(canfd1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) SH_PFC_PIN_GROUP(du_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) SH_PFC_PIN_GROUP(du_clk_in_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) SH_PFC_PIN_GROUP(du_clk_in_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) SH_PFC_PIN_GROUP(du_clk_out_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) SH_PFC_PIN_GROUP(du_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) SH_PFC_PIN_GROUP(du_disp_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) SH_PFC_PIN_GROUP(du_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) SH_PFC_PIN_GROUP(hscif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) SH_PFC_PIN_GROUP(hscif0_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) SH_PFC_PIN_GROUP(hscif0_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) SH_PFC_PIN_GROUP(hscif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) SH_PFC_PIN_GROUP(hscif0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) SH_PFC_PIN_GROUP(hscif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) SH_PFC_PIN_GROUP(hscif1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) SH_PFC_PIN_GROUP(hscif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) SH_PFC_PIN_GROUP(hscif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) SH_PFC_PIN_GROUP(hscif1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) SH_PFC_PIN_GROUP(hscif2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) SH_PFC_PIN_GROUP(hscif2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) SH_PFC_PIN_GROUP(hscif2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) SH_PFC_PIN_GROUP(hscif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) SH_PFC_PIN_GROUP(hscif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) SH_PFC_PIN_GROUP(hscif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) SH_PFC_PIN_GROUP(hscif3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) SH_PFC_PIN_GROUP(hscif3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) SH_PFC_PIN_GROUP(hscif3_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) SH_PFC_PIN_GROUP(hscif3_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) SH_PFC_PIN_GROUP(hscif3_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) SH_PFC_PIN_GROUP(hscif3_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) SH_PFC_PIN_GROUP(hscif3_ctrl_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) SH_PFC_PIN_GROUP(hscif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) SH_PFC_PIN_GROUP(hscif4_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) SH_PFC_PIN_GROUP(hscif4_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) SH_PFC_PIN_GROUP(hscif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) SH_PFC_PIN_GROUP(hscif4_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) SH_PFC_PIN_GROUP(hscif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) SH_PFC_PIN_GROUP(hscif4_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) SH_PFC_PIN_GROUP(hscif4_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) SH_PFC_PIN_GROUP(i2c1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) SH_PFC_PIN_GROUP(i2c1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) SH_PFC_PIN_GROUP(i2c1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) SH_PFC_PIN_GROUP(i2c2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) SH_PFC_PIN_GROUP(i2c2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) SH_PFC_PIN_GROUP(i2c2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) SH_PFC_PIN_GROUP(i2c2_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) SH_PFC_PIN_GROUP(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) SH_PFC_PIN_GROUP(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) SH_PFC_PIN_GROUP(i2c6_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) SH_PFC_PIN_GROUP(i2c6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) SH_PFC_PIN_GROUP(i2c7_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) SH_PFC_PIN_GROUP(i2c7_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) SH_PFC_PIN_GROUP(intc_ex_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) SH_PFC_PIN_GROUP(intc_ex_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) SH_PFC_PIN_GROUP(intc_ex_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) SH_PFC_PIN_GROUP(intc_ex_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) SH_PFC_PIN_GROUP(intc_ex_irq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) SH_PFC_PIN_GROUP(intc_ex_irq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) SH_PFC_PIN_GROUP(msiof0_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) SH_PFC_PIN_GROUP(msiof0_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) SH_PFC_PIN_GROUP(msiof1_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) SH_PFC_PIN_GROUP(msiof1_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) SH_PFC_PIN_GROUP(msiof2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) SH_PFC_PIN_GROUP(msiof2_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) SH_PFC_PIN_GROUP(msiof2_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) SH_PFC_PIN_GROUP(msiof2_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) SH_PFC_PIN_GROUP(msiof2_txd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) SH_PFC_PIN_GROUP(msiof2_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) SH_PFC_PIN_GROUP(msiof2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) SH_PFC_PIN_GROUP(msiof2_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) SH_PFC_PIN_GROUP(msiof2_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) SH_PFC_PIN_GROUP(msiof2_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) SH_PFC_PIN_GROUP(msiof2_txd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) SH_PFC_PIN_GROUP(msiof2_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) SH_PFC_PIN_GROUP(msiof3_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) SH_PFC_PIN_GROUP(msiof3_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) SH_PFC_PIN_GROUP(msiof3_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) SH_PFC_PIN_GROUP(msiof3_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) SH_PFC_PIN_GROUP(msiof3_txd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) SH_PFC_PIN_GROUP(msiof3_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) SH_PFC_PIN_GROUP(msiof3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) SH_PFC_PIN_GROUP(msiof3_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) SH_PFC_PIN_GROUP(msiof3_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) SH_PFC_PIN_GROUP(msiof3_txd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) SH_PFC_PIN_GROUP(msiof3_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) SH_PFC_PIN_GROUP(pwm0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) SH_PFC_PIN_GROUP(pwm1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) SH_PFC_PIN_GROUP(pwm2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) SH_PFC_PIN_GROUP(pwm2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) SH_PFC_PIN_GROUP(pwm3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) SH_PFC_PIN_GROUP(pwm3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) SH_PFC_PIN_GROUP(pwm3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) SH_PFC_PIN_GROUP(pwm4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) SH_PFC_PIN_GROUP(pwm4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) SH_PFC_PIN_GROUP(pwm5_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) SH_PFC_PIN_GROUP(pwm5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) SH_PFC_PIN_GROUP(pwm6_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) SH_PFC_PIN_GROUP(pwm6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) SH_PFC_PIN_GROUP(scif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) SH_PFC_PIN_GROUP(scif0_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) SH_PFC_PIN_GROUP(scif0_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) SH_PFC_PIN_GROUP(scif0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) SH_PFC_PIN_GROUP(scif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) SH_PFC_PIN_GROUP(scif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) SH_PFC_PIN_GROUP(scif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) SH_PFC_PIN_GROUP(scif2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) SH_PFC_PIN_GROUP(scif2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) SH_PFC_PIN_GROUP(scif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) SH_PFC_PIN_GROUP(scif3_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) SH_PFC_PIN_GROUP(scif3_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) SH_PFC_PIN_GROUP(scif3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) SH_PFC_PIN_GROUP(scif3_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) SH_PFC_PIN_GROUP(scif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) SH_PFC_PIN_GROUP(scif4_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) SH_PFC_PIN_GROUP(scif4_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) SH_PFC_PIN_GROUP(scif4_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) SH_PFC_PIN_GROUP(scif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) SH_PFC_PIN_GROUP(scif4_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) SH_PFC_PIN_GROUP(scif5_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) SH_PFC_PIN_GROUP(scif5_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) SH_PFC_PIN_GROUP(scif5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) SH_PFC_PIN_GROUP(scif5_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) SH_PFC_PIN_GROUP(scif_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) SH_PFC_PIN_GROUP(sdhi3_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) SH_PFC_PIN_GROUP(sdhi3_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) SH_PFC_PIN_GROUP(sdhi3_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) SH_PFC_PIN_GROUP(sdhi3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) SH_PFC_PIN_GROUP(sdhi3_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) SH_PFC_PIN_GROUP(sdhi3_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) SH_PFC_PIN_GROUP(sdhi3_ds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) SH_PFC_PIN_GROUP(ssi0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) SH_PFC_PIN_GROUP(ssi01239_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) SH_PFC_PIN_GROUP(ssi1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) SH_PFC_PIN_GROUP(ssi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) SH_PFC_PIN_GROUP(ssi2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) SH_PFC_PIN_GROUP(ssi2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) SH_PFC_PIN_GROUP(ssi2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) SH_PFC_PIN_GROUP(ssi349_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) SH_PFC_PIN_GROUP(ssi4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) SH_PFC_PIN_GROUP(ssi4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) SH_PFC_PIN_GROUP(ssi5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) SH_PFC_PIN_GROUP(ssi5_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) SH_PFC_PIN_GROUP(ssi6_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) SH_PFC_PIN_GROUP(ssi6_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) SH_PFC_PIN_GROUP(ssi7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) SH_PFC_PIN_GROUP(ssi78_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) SH_PFC_PIN_GROUP(ssi8_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) SH_PFC_PIN_GROUP(ssi9_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) SH_PFC_PIN_GROUP(ssi9_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) SH_PFC_PIN_GROUP(ssi9_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) SH_PFC_PIN_GROUP(tmu_tclk1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) SH_PFC_PIN_GROUP(tmu_tclk1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) SH_PFC_PIN_GROUP(tmu_tclk2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) SH_PFC_PIN_GROUP(tmu_tclk2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) SH_PFC_PIN_GROUP(usb0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) SH_PFC_PIN_GROUP(usb0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) SH_PFC_PIN_GROUP(usb0_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) SH_PFC_PIN_GROUP(usb30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) SH_PFC_PIN_GROUP(usb30_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) VIN_DATA_PIN_GROUP(vin4_data, 8, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) VIN_DATA_PIN_GROUP(vin4_data, 10, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) VIN_DATA_PIN_GROUP(vin4_data, 12, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) VIN_DATA_PIN_GROUP(vin4_data, 16, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) SH_PFC_PIN_GROUP(vin4_data18_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) VIN_DATA_PIN_GROUP(vin4_data, 20, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) VIN_DATA_PIN_GROUP(vin4_data, 24, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) VIN_DATA_PIN_GROUP(vin4_data, 8, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) VIN_DATA_PIN_GROUP(vin4_data, 10, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) VIN_DATA_PIN_GROUP(vin4_data, 12, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) VIN_DATA_PIN_GROUP(vin4_data, 16, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) SH_PFC_PIN_GROUP(vin4_data18_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) VIN_DATA_PIN_GROUP(vin4_data, 20, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) VIN_DATA_PIN_GROUP(vin4_data, 24, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) SH_PFC_PIN_GROUP(vin4_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) SH_PFC_PIN_GROUP(vin4_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) SH_PFC_PIN_GROUP(vin4_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) SH_PFC_PIN_GROUP(vin4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) VIN_DATA_PIN_GROUP(vin5_data, 8, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) VIN_DATA_PIN_GROUP(vin5_data, 10, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) VIN_DATA_PIN_GROUP(vin5_data, 12, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) VIN_DATA_PIN_GROUP(vin5_data, 16, _a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) SH_PFC_PIN_GROUP(vin5_data8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) SH_PFC_PIN_GROUP(vin5_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) SH_PFC_PIN_GROUP(vin5_field_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) SH_PFC_PIN_GROUP(vin5_clkenb_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) SH_PFC_PIN_GROUP(vin5_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) SH_PFC_PIN_GROUP(vin5_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) .automotive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) SH_PFC_PIN_GROUP(drif0_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) SH_PFC_PIN_GROUP(drif0_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) SH_PFC_PIN_GROUP(drif0_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) SH_PFC_PIN_GROUP(drif0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) SH_PFC_PIN_GROUP(drif0_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) SH_PFC_PIN_GROUP(drif0_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) SH_PFC_PIN_GROUP(drif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) SH_PFC_PIN_GROUP(drif1_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) SH_PFC_PIN_GROUP(drif1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) SH_PFC_PIN_GROUP(drif2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) SH_PFC_PIN_GROUP(drif2_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) SH_PFC_PIN_GROUP(drif2_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) SH_PFC_PIN_GROUP(drif2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) SH_PFC_PIN_GROUP(drif2_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) SH_PFC_PIN_GROUP(drif2_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) SH_PFC_PIN_GROUP(drif3_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) SH_PFC_PIN_GROUP(drif3_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) SH_PFC_PIN_GROUP(drif3_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) SH_PFC_PIN_GROUP(drif3_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) SH_PFC_PIN_GROUP(drif3_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) SH_PFC_PIN_GROUP(drif3_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) "audio_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) "audio_clk_b_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) "audio_clk_b_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) "audio_clk_b_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) "audio_clk_c_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) "audio_clk_c_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) "audio_clk_c_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) "audio_clkout_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) "audio_clkout_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) "audio_clkout1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) "audio_clkout1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) "audio_clkout1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) "audio_clkout2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) "audio_clkout2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) "audio_clkout2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) "audio_clkout3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) "audio_clkout3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) "audio_clkout3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) "avb_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) "avb_avtp_pps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) "avb_avtp_match",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) "avb_avtp_capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) "can0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) "can1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) static const char * const can_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) static const char * const canfd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) "canfd0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) static const char * const canfd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) "canfd1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) static const char * const drif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) "drif0_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) "drif0_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) "drif0_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) "drif0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) "drif0_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) "drif0_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) static const char * const drif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) "drif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) "drif1_data0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) "drif1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) static const char * const drif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) "drif2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) "drif2_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) "drif2_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) "drif2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) "drif2_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) "drif2_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) static const char * const drif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) "drif3_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) "drif3_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) "drif3_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) "drif3_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) "drif3_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) "drif3_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) "du_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) "du_clk_in_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) "du_clk_in_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) "du_clk_out_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) "du_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) "du_disp_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) "du_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) "hscif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) "hscif0_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) "hscif0_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) "hscif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) "hscif0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) "hscif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) "hscif1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) "hscif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) "hscif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) "hscif1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) static const char * const hscif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) "hscif2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) "hscif2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) "hscif2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) "hscif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) static const char * const hscif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) "hscif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) "hscif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) "hscif3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) "hscif3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) "hscif3_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) "hscif3_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) "hscif3_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) "hscif3_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) "hscif3_ctrl_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) static const char * const hscif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) "hscif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) "hscif4_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) "hscif4_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) "hscif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) "hscif4_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) "hscif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) "hscif4_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) "hscif4_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) "i2c1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) "i2c1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) "i2c1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) "i2c2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) "i2c2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) "i2c2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) "i2c2_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) static const char * const i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) "i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) static const char * const i2c6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) "i2c6_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) "i2c6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) static const char * const i2c7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) "i2c7_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) "i2c7_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) static const char * const intc_ex_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) "intc_ex_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) "intc_ex_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) "intc_ex_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) "intc_ex_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) "intc_ex_irq4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) "intc_ex_irq5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) "msiof0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) "msiof0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) "msiof1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) "msiof1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) "msiof2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) "msiof2_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) "msiof2_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) "msiof2_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) "msiof2_txd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) "msiof2_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) "msiof2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) "msiof2_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) "msiof2_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) "msiof2_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) "msiof2_txd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) "msiof2_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) "msiof3_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) "msiof3_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) "msiof3_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) "msiof3_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) "msiof3_txd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) "msiof3_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) "msiof3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) "msiof3_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) "msiof3_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) "msiof3_txd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) "msiof3_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) "pwm0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) "pwm1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) "pwm2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) "pwm2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) "pwm3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) "pwm3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) "pwm3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) "pwm4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) "pwm4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) "pwm5_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) "pwm5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) static const char * const pwm6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) "pwm6_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) "pwm6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) "scif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) "scif0_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) "scif0_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) "scif0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) "scif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) "scif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) "scif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) "scif2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) "scif2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) "scif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) "scif3_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) "scif3_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) "scif3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) "scif3_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) "scif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) "scif4_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) "scif4_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) "scif4_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) "scif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) "scif4_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) "scif5_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) "scif5_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) "scif5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) "scif5_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) "scif_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) static const char * const sdhi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) "sdhi3_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) "sdhi3_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) "sdhi3_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) "sdhi3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) "sdhi3_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) "sdhi3_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) "sdhi3_ds",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) "ssi0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) "ssi01239_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) "ssi1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) "ssi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) "ssi2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) "ssi2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) "ssi2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) "ssi349_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) "ssi4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) "ssi4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) "ssi5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) "ssi5_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) "ssi6_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) "ssi6_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) "ssi7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) "ssi78_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) "ssi8_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) "ssi9_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) "ssi9_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) "ssi9_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) static const char * const tmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) "tmu_tclk1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) "tmu_tclk1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) "tmu_tclk2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) "tmu_tclk2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) "usb0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) "usb0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) "usb0_id",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) static const char * const usb30_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) "usb30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) "usb30_id",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) static const char * const vin4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) "vin4_data8_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) "vin4_data10_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) "vin4_data12_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) "vin4_data16_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) "vin4_data18_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) "vin4_data20_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) "vin4_data24_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) "vin4_data8_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) "vin4_data10_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) "vin4_data12_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) "vin4_data16_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) "vin4_data18_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) "vin4_data20_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) "vin4_data24_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) "vin4_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) "vin4_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) "vin4_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) "vin4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) static const char * const vin5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) "vin5_data8_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) "vin5_data10_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) "vin5_data12_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) "vin5_data16_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) "vin5_data8_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) "vin5_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) "vin5_field_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) "vin5_clkenb_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) "vin5_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) "vin5_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) struct sh_pfc_function common[47];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) struct sh_pfc_function automotive[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) } pinmux_functions = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) SH_PFC_FUNCTION(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) SH_PFC_FUNCTION(canfd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) SH_PFC_FUNCTION(canfd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) SH_PFC_FUNCTION(hscif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) SH_PFC_FUNCTION(hscif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) SH_PFC_FUNCTION(hscif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) SH_PFC_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) SH_PFC_FUNCTION(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) SH_PFC_FUNCTION(i2c6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) SH_PFC_FUNCTION(i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) SH_PFC_FUNCTION(intc_ex),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) SH_PFC_FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) SH_PFC_FUNCTION(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) SH_PFC_FUNCTION(sdhi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) SH_PFC_FUNCTION(tmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) SH_PFC_FUNCTION(usb30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) SH_PFC_FUNCTION(vin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) SH_PFC_FUNCTION(vin5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) .automotive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) SH_PFC_FUNCTION(drif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) SH_PFC_FUNCTION(drif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) SH_PFC_FUNCTION(drif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) SH_PFC_FUNCTION(drif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) #define F_(x, y) FN_##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) #define FM(x) FN_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) GP_0_17_FN, GPSR0_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) GP_0_16_FN, GPSR0_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) GP_0_15_FN, GPSR0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) GP_0_14_FN, GPSR0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) GP_0_13_FN, GPSR0_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) GP_0_12_FN, GPSR0_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) GP_0_11_FN, GPSR0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) GP_0_10_FN, GPSR0_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) GP_0_9_FN, GPSR0_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) GP_0_8_FN, GPSR0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) GP_0_7_FN, GPSR0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) GP_0_6_FN, GPSR0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) GP_0_5_FN, GPSR0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) GP_0_4_FN, GPSR0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) GP_0_3_FN, GPSR0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) GP_0_2_FN, GPSR0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) GP_0_1_FN, GPSR0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) GP_0_0_FN, GPSR0_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) GP_1_22_FN, GPSR1_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) GP_1_21_FN, GPSR1_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) GP_1_20_FN, GPSR1_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) GP_1_19_FN, GPSR1_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) GP_1_18_FN, GPSR1_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) GP_1_17_FN, GPSR1_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) GP_1_16_FN, GPSR1_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) GP_1_15_FN, GPSR1_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) GP_1_14_FN, GPSR1_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) GP_1_13_FN, GPSR1_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) GP_1_12_FN, GPSR1_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) GP_1_11_FN, GPSR1_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) GP_1_10_FN, GPSR1_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) GP_1_9_FN, GPSR1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) GP_1_8_FN, GPSR1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) GP_1_7_FN, GPSR1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) GP_1_6_FN, GPSR1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) GP_1_5_FN, GPSR1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) GP_1_4_FN, GPSR1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) GP_1_3_FN, GPSR1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) GP_1_2_FN, GPSR1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) GP_1_1_FN, GPSR1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) GP_1_0_FN, GPSR1_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) GP_2_25_FN, GPSR2_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) GP_2_24_FN, GPSR2_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) GP_2_23_FN, GPSR2_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) GP_2_22_FN, GPSR2_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) GP_2_21_FN, GPSR2_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) GP_2_20_FN, GPSR2_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) GP_2_19_FN, GPSR2_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) GP_2_18_FN, GPSR2_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) GP_2_17_FN, GPSR2_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) GP_2_16_FN, GPSR2_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) GP_2_15_FN, GPSR2_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) GP_2_14_FN, GPSR2_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) GP_2_13_FN, GPSR2_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) GP_2_12_FN, GPSR2_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) GP_2_11_FN, GPSR2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) GP_2_10_FN, GPSR2_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) GP_2_9_FN, GPSR2_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) GP_2_8_FN, GPSR2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) GP_2_7_FN, GPSR2_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) GP_2_6_FN, GPSR2_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) GP_2_5_FN, GPSR2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) GP_2_4_FN, GPSR2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) GP_2_3_FN, GPSR2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) GP_2_2_FN, GPSR2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) GP_2_1_FN, GPSR2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) GP_2_0_FN, GPSR2_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) GP_3_15_FN, GPSR3_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) GP_3_14_FN, GPSR3_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) GP_3_13_FN, GPSR3_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) GP_3_12_FN, GPSR3_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) GP_3_11_FN, GPSR3_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) GP_3_10_FN, GPSR3_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) GP_3_9_FN, GPSR3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) GP_3_8_FN, GPSR3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) GP_3_7_FN, GPSR3_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) GP_3_6_FN, GPSR3_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) GP_3_5_FN, GPSR3_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) GP_3_4_FN, GPSR3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) GP_3_3_FN, GPSR3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) GP_3_2_FN, GPSR3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) GP_3_1_FN, GPSR3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) GP_3_0_FN, GPSR3_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) GP_4_10_FN, GPSR4_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) GP_4_9_FN, GPSR4_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) GP_4_8_FN, GPSR4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) GP_4_7_FN, GPSR4_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) GP_4_6_FN, GPSR4_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) GP_4_5_FN, GPSR4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) GP_4_4_FN, GPSR4_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) GP_4_3_FN, GPSR4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) GP_4_2_FN, GPSR4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) GP_4_1_FN, GPSR4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) GP_4_0_FN, GPSR4_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) GP_5_19_FN, GPSR5_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) GP_5_18_FN, GPSR5_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) GP_5_17_FN, GPSR5_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) GP_5_16_FN, GPSR5_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) GP_5_15_FN, GPSR5_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) GP_5_14_FN, GPSR5_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) GP_5_13_FN, GPSR5_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) GP_5_12_FN, GPSR5_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) GP_5_11_FN, GPSR5_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) GP_5_10_FN, GPSR5_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) GP_5_9_FN, GPSR5_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) GP_5_8_FN, GPSR5_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) GP_5_7_FN, GPSR5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) GP_5_6_FN, GPSR5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) GP_5_5_FN, GPSR5_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) GP_5_4_FN, GPSR5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) GP_5_3_FN, GPSR5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) GP_5_2_FN, GPSR5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) GP_5_1_FN, GPSR5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) GP_5_0_FN, GPSR5_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) GP_6_17_FN, GPSR6_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) GP_6_16_FN, GPSR6_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) GP_6_15_FN, GPSR6_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) GP_6_14_FN, GPSR6_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) GP_6_13_FN, GPSR6_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) GP_6_12_FN, GPSR6_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) GP_6_11_FN, GPSR6_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) GP_6_10_FN, GPSR6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) GP_6_9_FN, GPSR6_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) GP_6_8_FN, GPSR6_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) GP_6_7_FN, GPSR6_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) GP_6_6_FN, GPSR6_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) GP_6_5_FN, GPSR6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) GP_6_4_FN, GPSR6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) GP_6_3_FN, GPSR6_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) GP_6_2_FN, GPSR6_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) GP_6_1_FN, GPSR6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) GP_6_0_FN, GPSR6_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) IP0_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) IP0_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) IP0_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) IP0_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) IP0_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) IP0_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) IP0_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) IP0_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) IP1_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) IP1_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) IP1_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) IP1_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) IP1_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) IP1_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) IP1_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) IP1_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) IP2_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) IP2_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) IP2_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) IP2_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) IP2_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) IP2_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) IP2_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) IP2_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) IP3_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) IP3_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) IP3_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) IP3_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) IP3_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) IP3_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) IP3_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) IP3_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) IP4_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) IP4_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) IP4_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) IP4_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) IP4_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) IP4_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) IP4_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) IP4_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) IP5_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) IP5_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) IP5_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) IP5_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) IP5_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) IP5_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) IP5_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) IP5_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) IP6_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) IP6_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) IP6_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) IP6_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) IP6_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) IP6_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) IP6_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) IP6_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) IP7_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) IP7_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) IP7_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) IP7_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) IP7_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) IP7_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) IP7_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) IP7_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) IP8_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) IP8_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) IP8_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) IP8_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) IP8_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) IP8_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) IP8_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) IP8_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) IP9_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) IP9_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) IP9_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) IP9_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) IP9_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) IP9_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) IP9_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) IP9_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) IP10_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) IP10_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) IP10_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) IP10_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) IP10_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) IP10_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) IP10_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) IP10_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) IP11_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) IP11_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) IP11_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) IP11_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) IP11_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) IP11_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) IP11_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) IP11_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) IP12_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) IP12_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) IP12_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) IP12_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) IP12_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) IP12_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) IP12_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) IP12_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) IP13_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) IP13_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) IP13_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) IP13_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) IP13_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) IP13_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) IP13_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) IP13_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) IP14_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) IP14_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) IP14_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) IP14_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) IP14_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) IP14_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) IP14_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) IP14_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) IP15_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) IP15_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) IP15_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) IP15_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) IP15_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) IP15_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) IP15_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) IP15_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) GROUP(1, 2, 1, 2, 1, 1, 1, 1, 2, 3, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) 1, 2, 2, 1, 1, 1, 2, 1, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) /* RESERVED 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) MOD_SEL0_30_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) MOD_SEL0_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) MOD_SEL0_27_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) MOD_SEL0_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) MOD_SEL0_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) MOD_SEL0_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) MOD_SEL0_22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) MOD_SEL0_21_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) MOD_SEL0_19_18_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) MOD_SEL0_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) MOD_SEL0_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) MOD_SEL0_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) MOD_SEL0_13_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) MOD_SEL0_11_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) MOD_SEL0_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) MOD_SEL0_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) MOD_SEL0_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) MOD_SEL0_6_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) MOD_SEL0_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) MOD_SEL0_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) MOD_SEL0_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) MOD_SEL0_1_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) 1, 2, 2, 2, 1, 1, 2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) MOD_SEL1_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) MOD_SEL1_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) MOD_SEL1_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) MOD_SEL1_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) /* RESERVED 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) MOD_SEL1_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) MOD_SEL1_25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) MOD_SEL1_24_23_22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) MOD_SEL1_21_20_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) MOD_SEL1_18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) MOD_SEL1_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) MOD_SEL1_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) MOD_SEL1_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) MOD_SEL1_14_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) MOD_SEL1_12_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) MOD_SEL1_10_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) MOD_SEL1_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) MOD_SEL1_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) MOD_SEL1_6_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) MOD_SEL1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) /* RESERVED 3, 2, 1, 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) enum ioctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) POCCTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) TDSELCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) [POCCTRL0] = { 0xe6060380, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) [TDSELCTRL] = { 0xe60603c0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) static int r8a77990_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) int bit = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) bit = pin & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) bit = (pin & 0x1f) + 19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) static const struct pinmux_bias_reg pinmux_bias_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) [0] = RCAR_GP_PIN(2, 23), /* RD# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) [1] = RCAR_GP_PIN(2, 22), /* BS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) [2] = RCAR_GP_PIN(2, 21), /* AVB_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) [3] = PIN_AVB_MDC, /* AVB_MDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) [4] = PIN_AVB_MDIO, /* AVB_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) [5] = RCAR_GP_PIN(2, 20), /* AVB_TXCREFCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) [6] = PIN_AVB_TD3, /* AVB_TD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) [7] = PIN_AVB_TD2, /* AVB_TD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) [8] = PIN_AVB_TD1, /* AVB_TD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) [9] = PIN_AVB_TD0, /* AVB_TD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) [10] = PIN_AVB_TXC, /* AVB_TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) [11] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) [12] = RCAR_GP_PIN(2, 19), /* AVB_RD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) [13] = RCAR_GP_PIN(2, 18), /* AVB_RD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) [14] = RCAR_GP_PIN(2, 17), /* AVB_RD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) [15] = RCAR_GP_PIN(2, 16), /* AVB_RD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) [16] = RCAR_GP_PIN(2, 15), /* AVB_RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) [17] = RCAR_GP_PIN(2, 14), /* AVB_RX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) [18] = RCAR_GP_PIN(2, 13), /* RPC_RESET# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) [19] = RCAR_GP_PIN(2, 12), /* RPC_INT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) [20] = RCAR_GP_PIN(2, 11), /* QSPI1_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) [21] = RCAR_GP_PIN(2, 10), /* QSPI1_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) [22] = RCAR_GP_PIN(2, 9), /* QSPI1_IO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) [23] = RCAR_GP_PIN(2, 8), /* QSPI1_MISO/IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) [24] = RCAR_GP_PIN(2, 7), /* QSPI1_MOSI/IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) [25] = RCAR_GP_PIN(2, 6), /* QSPI1_SPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) [26] = RCAR_GP_PIN(2, 5), /* QSPI0_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) [27] = RCAR_GP_PIN(2, 4), /* QSPI0_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) [28] = RCAR_GP_PIN(2, 3), /* QSPI0_IO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) [29] = RCAR_GP_PIN(2, 2), /* QSPI0_MISO/IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) [30] = RCAR_GP_PIN(2, 1), /* QSPI0_MOSI/IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) [31] = RCAR_GP_PIN(2, 0), /* QSPI0_SPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) [0] = RCAR_GP_PIN(0, 4), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) [1] = RCAR_GP_PIN(0, 3), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) [2] = RCAR_GP_PIN(0, 2), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) [3] = RCAR_GP_PIN(0, 1), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) [4] = RCAR_GP_PIN(0, 0), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) [5] = RCAR_GP_PIN(1, 22), /* WE0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) [6] = RCAR_GP_PIN(1, 21), /* CS0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) [7] = RCAR_GP_PIN(1, 20), /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) [8] = RCAR_GP_PIN(1, 19), /* A19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) [9] = RCAR_GP_PIN(1, 18), /* A18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) [10] = RCAR_GP_PIN(1, 17), /* A17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) [11] = RCAR_GP_PIN(1, 16), /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) [12] = RCAR_GP_PIN(1, 15), /* A15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) [13] = RCAR_GP_PIN(1, 14), /* A14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) [14] = RCAR_GP_PIN(1, 13), /* A13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) [15] = RCAR_GP_PIN(1, 12), /* A12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) [16] = RCAR_GP_PIN(1, 11), /* A11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) [17] = RCAR_GP_PIN(1, 10), /* A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) [18] = RCAR_GP_PIN(1, 9), /* A9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) [19] = RCAR_GP_PIN(1, 8), /* A8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) [20] = RCAR_GP_PIN(1, 7), /* A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) [21] = RCAR_GP_PIN(1, 6), /* A6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) [22] = RCAR_GP_PIN(1, 5), /* A5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) [23] = RCAR_GP_PIN(1, 4), /* A4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) [24] = RCAR_GP_PIN(1, 3), /* A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) [25] = RCAR_GP_PIN(1, 2), /* A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) [26] = RCAR_GP_PIN(1, 1), /* A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) [27] = RCAR_GP_PIN(1, 0), /* A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) [28] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) [29] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) [30] = RCAR_GP_PIN(2, 25), /* PUEN_EX_WAIT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) [31] = RCAR_GP_PIN(2, 24), /* PUEN_RD/WR# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) [0] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) [1] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) [2] = PIN_ASEBRK, /* ASEBRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) [3] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) [4] = PIN_TDI, /* TDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) [5] = PIN_TMS, /* TMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) [6] = PIN_TCK, /* TCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) [7] = PIN_TRST_N, /* TRST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) [8] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) [9] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) [10] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) [11] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) [12] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) [13] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) [14] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) [15] = PIN_FSCLKST_N, /* FSCLKST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) [16] = RCAR_GP_PIN(0, 17), /* SDA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) [17] = RCAR_GP_PIN(0, 16), /* SCL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) [18] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) [19] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) [20] = PIN_PRESETOUT_N, /* PRESETOUT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) [21] = RCAR_GP_PIN(0, 15), /* D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) [22] = RCAR_GP_PIN(0, 14), /* D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) [23] = RCAR_GP_PIN(0, 13), /* D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) [24] = RCAR_GP_PIN(0, 12), /* D12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) [25] = RCAR_GP_PIN(0, 11), /* D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) [26] = RCAR_GP_PIN(0, 10), /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) [27] = RCAR_GP_PIN(0, 9), /* D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) [28] = RCAR_GP_PIN(0, 8), /* D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) [29] = RCAR_GP_PIN(0, 7), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) [30] = RCAR_GP_PIN(0, 6), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) [31] = RCAR_GP_PIN(0, 5), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) [0] = RCAR_GP_PIN(5, 0), /* SCK0_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) [1] = RCAR_GP_PIN(5, 4), /* RTS0#_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) [2] = RCAR_GP_PIN(5, 3), /* CTS0#_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) [3] = RCAR_GP_PIN(5, 2), /* TX0_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) [4] = RCAR_GP_PIN(5, 1), /* RX0_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) [5] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) [6] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) [7] = RCAR_GP_PIN(3, 15), /* SD1_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) [8] = RCAR_GP_PIN(3, 14), /* SD1_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) [9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) [10] = RCAR_GP_PIN(3, 12), /* SD0_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) [11] = RCAR_GP_PIN(4, 10), /* SD3_DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) [12] = RCAR_GP_PIN(4, 9), /* SD3_DAT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) [13] = RCAR_GP_PIN(4, 8), /* SD3_DAT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) [14] = RCAR_GP_PIN(4, 7), /* SD3_DAT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) [15] = RCAR_GP_PIN(4, 6), /* SD3_DAT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) [16] = RCAR_GP_PIN(4, 5), /* SD3_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) [17] = RCAR_GP_PIN(4, 4), /* SD3_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) [18] = RCAR_GP_PIN(4, 3), /* SD3_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) [19] = RCAR_GP_PIN(4, 2), /* SD3_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) [20] = RCAR_GP_PIN(4, 1), /* SD3_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) [21] = RCAR_GP_PIN(4, 0), /* SD3_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) [22] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) [23] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) [24] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) [25] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) [26] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) [27] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) [28] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) [29] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) [30] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) [31] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) [0] = RCAR_GP_PIN(6, 8), /* AUDIO_CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) [1] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) [2] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) [3] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) [4] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) [5] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) [6] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) [7] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) [8] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) [9] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) [10] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) [12] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) [13] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) [14] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) [15] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) [16] = PIN_MLB_REF, /* MLB_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) [17] = RCAR_GP_PIN(5, 19), /* MLB_DAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) [18] = RCAR_GP_PIN(5, 18), /* MLB_SIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) [19] = RCAR_GP_PIN(5, 17), /* MLB_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) [20] = RCAR_GP_PIN(5, 16), /* SSI_SDATA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) [21] = RCAR_GP_PIN(5, 15), /* MSIOF0_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) [22] = RCAR_GP_PIN(5, 14), /* MSIOF0_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) [23] = RCAR_GP_PIN(5, 13), /* MSIOF0_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) [24] = RCAR_GP_PIN(5, 12), /* MSIOF0_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) [25] = RCAR_GP_PIN(5, 11), /* MSIOF0_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) [26] = RCAR_GP_PIN(5, 10), /* MSIOF0_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) [27] = RCAR_GP_PIN(5, 9), /* RX2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) [28] = RCAR_GP_PIN(5, 8), /* TX2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) [29] = RCAR_GP_PIN(5, 7), /* SCK2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) [30] = RCAR_GP_PIN(5, 6), /* TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) [31] = RCAR_GP_PIN(5, 5), /* RX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) [0] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) [1] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) [2] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) [3] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) [4] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) [5] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) [6] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) [7] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) [8] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) [9] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) [10] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) [11] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) [12] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) [13] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) [14] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) [15] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) [16] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) [17] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) [18] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) [19] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) [20] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) [21] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) [22] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) [23] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) [24] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) [25] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) [26] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) [27] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) [28] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) [29] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) [30] = RCAR_GP_PIN(6, 9), /* PUEN_USB30_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) [31] = RCAR_GP_PIN(6, 17), /* PUEN_USB30_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) static unsigned int r8a77990_pinmux_get_bias(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) const struct pinmux_bias_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) return PIN_CONFIG_BIAS_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) return PIN_CONFIG_BIAS_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) static void r8a77990_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) unsigned int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) const struct pinmux_bias_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) u32 enable, updown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) if (bias != PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) enable |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) if (bias == PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) updown |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) sh_pfc_write(pfc, reg->pud, updown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) sh_pfc_write(pfc, reg->puen, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) static const struct sh_pfc_soc_operations r8a77990_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) .pin_to_pocctrl = r8a77990_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) .get_bias = r8a77990_pinmux_get_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) .set_bias = r8a77990_pinmux_set_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) #ifdef CONFIG_PINCTRL_PFC_R8A774C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) const struct sh_pfc_soc_info r8a774c0_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) .name = "r8a774c0_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) .ops = &r8a77990_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) .nr_groups = ARRAY_SIZE(pinmux_groups.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) .nr_functions = ARRAY_SIZE(pinmux_functions.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) .bias_regs = pinmux_bias_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) .ioctrl_regs = pinmux_ioctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) #ifdef CONFIG_PINCTRL_PFC_R8A77990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) const struct sh_pfc_soc_info r8a77990_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) .name = "r8a77990_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) .ops = &r8a77990_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) ARRAY_SIZE(pinmux_groups.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) ARRAY_SIZE(pinmux_functions.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) .bias_regs = pinmux_bias_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) .ioctrl_regs = pinmux_ioctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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