^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A77980 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2018 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * R-Car Gen3 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_28(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_CFG_30(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_25(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_15(5, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * F_() : just information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * FM() : macro for FN_xxx / xxx_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPSR0_17 F_(DU_DB7, IP2_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPSR0_16 F_(DU_DB6, IP2_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPSR0_15 F_(DU_DB5, IP1_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPSR0_14 F_(DU_DB4, IP1_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPSR0_13 F_(DU_DB3, IP1_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPSR0_12 F_(DU_DB2, IP1_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPSR0_11 F_(DU_DG7, IP1_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPSR0_10 F_(DU_DG6, IP1_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPSR0_9 F_(DU_DG5, IP1_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPSR0_8 F_(DU_DG4, IP1_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPSR0_7 F_(DU_DG3, IP0_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPSR0_6 F_(DU_DG2, IP0_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPSR0_5 F_(DU_DR7, IP0_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPSR0_4 F_(DU_DR6, IP0_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPSR0_3 F_(DU_DR5, IP0_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPSR0_2 F_(DU_DR4, IP0_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPSR0_1 F_(DU_DR3, IP0_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GPSR0_0 F_(DU_DR2, IP0_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPSR1_26 F_(DIGRF_CLKIN, IP8_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPSR1_25 F_(CANFD_CLK_A, IP8_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPSR1_24 F_(CANFD1_RX, IP8_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPSR1_23 F_(CANFD1_TX, IP8_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPSR1_22 F_(CANFD0_RX_A, IP8_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPSR1_21 F_(CANFD0_TX_A, IP8_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPSR1_20 F_(AVB_AVTP_CAPTURE, IP8_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPSR1_19 F_(AVB_AVTP_MATCH, IP7_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPSR1_18 FM(AVB_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPSR1_17 FM(AVB_PHY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPSR1_16 FM(AVB_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPSR1_15 FM(AVB_MDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GPSR1_14 FM(AVB_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPSR1_13 FM(AVB_TXCREFCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPSR1_12 FM(AVB_TD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPSR1_11 FM(AVB_TD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPSR1_10 FM(AVB_TD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPSR1_9 FM(AVB_TD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPSR1_8 FM(AVB_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPSR1_7 FM(AVB_TX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPSR1_6 FM(AVB_RD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPSR1_5 FM(AVB_RD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPSR1_4 FM(AVB_RD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPSR1_3 FM(AVB_RD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPSR1_2 FM(AVB_RXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPSR1_1 FM(AVB_RX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GPSR1_0 F_(IRQ0, IP2_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPSR2_29 F_(FSO_TOE_N, IP10_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPSR2_28 F_(FSO_CFE_1_N, IP10_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GPSR2_27 F_(FSO_CFE_0_N, IP10_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GPSR2_26 F_(SDA3, IP10_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPSR2_25 F_(SCL3, IP10_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GPSR2_24 F_(MSIOF0_SS2, IP9_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPSR2_23 F_(MSIOF0_SS1, IP9_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPSR2_22 F_(MSIOF0_SYNC, IP9_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPSR2_21 F_(MSIOF0_SCK, IP9_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPSR2_20 F_(MSIOF0_TXD, IP9_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPSR2_19 F_(MSIOF0_RXD, IP9_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPSR2_18 F_(IRQ5, IP9_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPSR2_17 F_(IRQ4, IP9_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPSR4_24 FM(GETHER_LINK_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPSR4_23 FM(GETHER_PHY_INT_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPSR4_22 FM(GETHER_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPSR4_21 FM(GETHER_MDC_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPSR4_20 FM(GETHER_MDIO_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPSR4_19 FM(GETHER_TXCREFCLK_MEGA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPSR4_18 FM(GETHER_TXCREFCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPSR4_17 FM(GETHER_TD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPSR4_16 FM(GETHER_TD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPSR4_15 FM(GETHER_TD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GPSR4_14 FM(GETHER_TD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GPSR4_13 FM(GETHER_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GPSR4_12 FM(GETHER_TX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GPSR4_11 FM(GETHER_RD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GPSR4_10 FM(GETHER_RD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GPSR4_9 FM(GETHER_RD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GPSR4_8 FM(GETHER_RD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GPSR4_7 FM(GETHER_RXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GPSR4_6 FM(GETHER_RX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPSR4_5 F_(SDA2, IP7_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPSR4_4 F_(SCL2, IP7_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPSR4_3 F_(SDA1, IP7_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GPSR4_2 F_(SCL1, IP7_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GPSR4_1 F_(SDA0, IP7_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GPSR4_0 F_(SCL0, IP7_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GPSR5_14 FM(RPC_INT_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GPSR5_13 FM(RPC_WP_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GPSR5_12 FM(RPC_RESET_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GPSR5_11 FM(QSPI1_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GPSR5_10 FM(QSPI1_IO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GPSR5_9 FM(QSPI1_IO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GPSR5_8 FM(QSPI1_MISO_IO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GPSR5_7 FM(QSPI1_MOSI_IO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GPSR5_6 FM(QSPI1_SPCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GPSR5_5 FM(QSPI0_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GPSR5_4 FM(QSPI0_IO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GPSR5_3 FM(QSPI0_IO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GPSR5_2 FM(QSPI0_MISO_IO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GPSR5_1 FM(QSPI0_MOSI_IO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GPSR5_0 FM(QSPI0_SPCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IP0_3_0 FM(DU_DR2) FM(SCK4) FM(GETHER_RMII_CRS_DV) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IP0_7_4 FM(DU_DR3) FM(RX4) FM(GETHER_RMII_RX_ER) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IP0_11_8 FM(DU_DR4) FM(TX4) FM(GETHER_RMII_RXD0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IP0_15_12 FM(DU_DR5) FM(CTS4_N) FM(GETHER_RMII_RXD1) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IP0_19_16 FM(DU_DR6) FM(RTS4_N) FM(GETHER_RMII_TXD_EN) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IP0_23_20 FM(DU_DR7) F_(0, 0) FM(GETHER_RMII_TXD0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IP0_27_24 FM(DU_DG2) F_(0, 0) FM(GETHER_RMII_TXD1) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IP0_31_28 FM(DU_DG3) FM(CPG_CPCKOUT) FM(GETHER_RMII_REFCLK) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IP1_3_0 FM(DU_DG4) FM(SCL5) F_(0, 0) FM(A8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IP1_11_8 FM(DU_DG6) FM(SCIF_CLK_A) FM(GETHER_MDIO_B) FM(A10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IP1_15_12 FM(DU_DG7) FM(HRX0_A) F_(0, 0) FM(A11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IP1_19_16 FM(DU_DB2) FM(HSCK0_A) F_(0, 0) FM(A12) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IP1_23_20 FM(DU_DB3) FM(HRTS0_N_A) F_(0, 0) FM(A13) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IP1_27_24 FM(DU_DB4) FM(HCTS0_N_A) F_(0, 0) FM(A14) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IP1_31_28 FM(DU_DB5) FM(HTX0_A) FM(PWM0_A) FM(A15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IP2_3_0 FM(DU_DB6) FM(MSIOF3_RXD) F_(0, 0) FM(A16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IP2_7_4 FM(DU_DB7) FM(MSIOF3_TXD) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IP2_11_8 FM(DU_DOTCLKOUT) FM(MSIOF3_SS1) FM(GETHER_LINK_B) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(MSIOF3_SS2) FM(GETHER_PHY_INT_B) FM(A19) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IP3_23_20 FM(VI0_DATA2) FM(AVB_AVTP_PPS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) FM(MMC_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) F_(0, 0) FM(D8) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) F_(0, 0) FM(D9) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) F_(0, 0) FM(D10) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) F_(0, 0) FM(D11) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IP6_23_20 FM(VI1_DATA9) FM(TCLK1_A) F_(0, 0) FM(D12) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IP6_27_24 FM(VI1_DATA10) FM(TCLK2_A) F_(0, 0) FM(D13) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) F_(0, 0) FM(D14) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) F_(0, 0) FM(D15) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IP7_7_4 FM(SCL0) F_(0, 0) F_(0, 0) FM(CLKOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IP7_11_8 FM(SDA0) F_(0, 0) F_(0, 0) FM(BS_N) FM(SCK0) FM(HSCK0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IP7_15_12 FM(SCL1) F_(0, 0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(HCTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IP7_19_16 FM(SDA1) F_(0, 0) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(HRTS0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IP7_23_20 FM(SCL2) F_(0, 0) F_(0, 0) FM(WE1_N) FM(RX0) FM(HRX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IP7_27_24 FM(SDA2) F_(0, 0) F_(0, 0) FM(EX_WAIT0) FM(TX0) FM(HTX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IP7_31_28 FM(AVB_AVTP_MATCH) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IP8_3_0 FM(AVB_AVTP_CAPTURE) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IP8_7_4 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IP8_11_8 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IP8_15_12 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IP8_19_16 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IP8_23_20 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IP8_27_24 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IP8_31_28 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IP9_3_0 FM(IRQ4) F_(0, 0) F_(0, 0) FM(VI0_DATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IP9_7_4 FM(IRQ5) F_(0, 0) F_(0, 0) FM(VI0_DATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IP9_11_8 FM(MSIOF0_RXD) FM(DU_DR0) F_(0, 0) FM(VI0_DATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IP9_15_12 FM(MSIOF0_TXD) FM(DU_DR1) F_(0, 0) FM(VI0_DATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IP9_19_16 FM(MSIOF0_SCK) FM(DU_DG0) F_(0, 0) FM(VI0_DATA16) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IP9_23_20 FM(MSIOF0_SYNC) FM(DU_DG1) F_(0, 0) FM(VI0_DATA17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IP9_27_24 FM(MSIOF0_SS1) FM(DU_DB0) FM(TCLK3) FM(VI0_DATA18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IP9_31_28 FM(MSIOF0_SS2) FM(DU_DB1) FM(TCLK4) FM(VI0_DATA19) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IP10_3_0 FM(SCL3) F_(0, 0) F_(0, 0) FM(VI0_DATA20) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IP10_7_4 FM(SDA3) F_(0, 0) F_(0, 0) FM(VI0_DATA21) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IP10_11_8 FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) FM(VI0_DATA22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IP10_15_12 FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) FM(VI0_DATA23) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IP10_19_16 FM(FSO_TOE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IP10_23_20 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IP10_27_24 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IP10_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PINMUX_GPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GPSR2_29 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GPSR2_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) GPSR1_27 GPSR2_27 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) GPSR1_26 GPSR2_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GPSR1_25 GPSR2_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GPSR1_24 GPSR2_24 GPSR4_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GPSR1_23 GPSR2_23 GPSR4_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GPSR1_22 GPSR2_22 GPSR4_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GPSR0_21 GPSR1_21 GPSR2_21 GPSR4_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GPSR0_20 GPSR1_20 GPSR2_20 GPSR4_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) GPSR0_19 GPSR1_19 GPSR2_19 GPSR4_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GPSR0_18 GPSR1_18 GPSR2_18 GPSR4_18 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) GPSR0_17 GPSR1_17 GPSR2_17 GPSR4_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 GPSR4_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 GPSR4_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PINMUX_IPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* MOD_SEL0 */ /* 0 */ /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MOD_SEL0_11 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MOD_SEL0_10 FM(SEL_GETHER_0) FM(SEL_GETHER_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MOD_SEL0_9 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MOD_SEL0_8 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MOD_SEL0_7 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MOD_SEL0_6 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MOD_SEL0_5 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MOD_SEL0_4 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MOD_SEL0_2 FM(SEL_RSP_0) FM(SEL_RSP_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MOD_SEL0_1 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PINMUX_MOD_SELS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MOD_SEL0_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MOD_SEL0_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MOD_SEL0_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MOD_SEL0_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MOD_SEL0_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MOD_SEL0_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MOD_SEL0_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MOD_SEL0_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MOD_SEL0_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MOD_SEL0_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MOD_SEL0_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define FM(x) x##_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINMUX_DATA_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINMUX_SINGLE(AVB_RX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINMUX_SINGLE(AVB_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINMUX_SINGLE(AVB_RD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINMUX_SINGLE(AVB_RD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINMUX_SINGLE(AVB_RD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINMUX_SINGLE(AVB_RD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINMUX_SINGLE(AVB_TX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINMUX_SINGLE(AVB_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINMUX_SINGLE(AVB_TD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINMUX_SINGLE(AVB_TD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINMUX_SINGLE(AVB_TD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINMUX_SINGLE(AVB_TD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINMUX_SINGLE(AVB_TXCREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINMUX_SINGLE(AVB_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINMUX_SINGLE(AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PINMUX_SINGLE(AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINMUX_SINGLE(AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINMUX_SINGLE(AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINMUX_SINGLE(GETHER_RX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINMUX_SINGLE(GETHER_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINMUX_SINGLE(GETHER_RD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINMUX_SINGLE(GETHER_RD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINMUX_SINGLE(GETHER_RD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINMUX_SINGLE(GETHER_RD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINMUX_SINGLE(GETHER_TX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINMUX_SINGLE(GETHER_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINMUX_SINGLE(GETHER_TD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINMUX_SINGLE(GETHER_TD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINMUX_SINGLE(GETHER_TD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINMUX_SINGLE(GETHER_TD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINMUX_SINGLE(GETHER_TXCREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINMUX_SINGLE(GETHER_TXCREFCLK_MEGA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINMUX_SINGLE(GETHER_MDIO_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINMUX_SINGLE(GETHER_MDC_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINMUX_SINGLE(GETHER_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINMUX_SINGLE(GETHER_PHY_INT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINMUX_SINGLE(GETHER_LINK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINMUX_SINGLE(QSPI0_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINMUX_SINGLE(QSPI0_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINMUX_SINGLE(QSPI0_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINMUX_SINGLE(QSPI0_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINMUX_SINGLE(QSPI0_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINMUX_SINGLE(QSPI0_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINMUX_SINGLE(QSPI1_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINMUX_SINGLE(QSPI1_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINMUX_SINGLE(QSPI1_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINMUX_SINGLE(QSPI1_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINMUX_SINGLE(QSPI1_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINMUX_SINGLE(QSPI1_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINMUX_SINGLE(RPC_RESET_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINMUX_SINGLE(RPC_WP_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINMUX_SINGLE(RPC_INT_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINMUX_IPSR_GPSR(IP0_3_0, SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINMUX_IPSR_GPSR(IP0_3_0, GETHER_RMII_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINMUX_IPSR_GPSR(IP0_3_0, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINMUX_IPSR_GPSR(IP0_7_4, RX4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINMUX_IPSR_GPSR(IP0_7_4, GETHER_RMII_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINMUX_IPSR_GPSR(IP0_7_4, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINMUX_IPSR_GPSR(IP0_11_8, TX4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_IPSR_GPSR(IP0_11_8, GETHER_RMII_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINMUX_IPSR_GPSR(IP0_11_8, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINMUX_IPSR_GPSR(IP0_15_12, CTS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINMUX_IPSR_GPSR(IP0_15_12, GETHER_RMII_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_IPSR_GPSR(IP0_15_12, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINMUX_IPSR_GPSR(IP0_19_16, RTS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINMUX_IPSR_GPSR(IP0_19_16, GETHER_RMII_TXD_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINMUX_IPSR_GPSR(IP0_19_16, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINMUX_IPSR_GPSR(IP0_23_20, GETHER_RMII_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINMUX_IPSR_GPSR(IP0_23_20, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_IPSR_GPSR(IP0_27_24, GETHER_RMII_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINMUX_IPSR_GPSR(IP0_27_24, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINMUX_IPSR_GPSR(IP0_31_28, CPG_CPCKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINMUX_IPSR_GPSR(IP0_31_28, GETHER_RMII_REFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINMUX_IPSR_GPSR(IP0_31_28, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINMUX_IPSR_GPSR(IP1_3_0, SCL5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINMUX_IPSR_GPSR(IP1_3_0, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINMUX_IPSR_GPSR(IP1_7_4, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINMUX_IPSR_MSEL(IP1_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINMUX_IPSR_MSEL(IP1_11_8, GETHER_MDIO_B, SEL_GETHER_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINMUX_IPSR_GPSR(IP1_11_8, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINMUX_IPSR_MSEL(IP1_15_12, HRX0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINMUX_IPSR_GPSR(IP1_15_12, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINMUX_IPSR_MSEL(IP1_19_16, HSCK0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINMUX_IPSR_GPSR(IP1_19_16, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINMUX_IPSR_GPSR(IP1_19_16, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINMUX_IPSR_GPSR(IP1_23_20, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINMUX_IPSR_GPSR(IP1_23_20, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINMUX_IPSR_MSEL(IP1_27_24, HCTS0_N_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINMUX_IPSR_GPSR(IP1_27_24, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINMUX_IPSR_MSEL(IP1_31_28, HTX0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINMUX_IPSR_MSEL(IP1_31_28, PWM0_A, SEL_PWM0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINMUX_IPSR_GPSR(IP1_31_28, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINMUX_IPSR_GPSR(IP2_3_0, MSIOF3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_IPSR_GPSR(IP2_3_0, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_IPSR_GPSR(IP2_7_4, MSIOF3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_IPSR_GPSR(IP2_7_4, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_IPSR_GPSR(IP2_11_8, MSIOF3_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINMUX_IPSR_MSEL(IP2_11_8, GETHER_LINK_B, SEL_GETHER_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINMUX_IPSR_GPSR(IP2_11_8, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINMUX_IPSR_GPSR(IP2_15_12, MSIOF3_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_IPSR_MSEL(IP2_15_12, GETHER_PHY_INT_B, SEL_GETHER_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_IPSR_GPSR(IP2_15_12, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINMUX_IPSR_GPSR(IP2_15_12, FXR_TXENA_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINMUX_IPSR_GPSR(IP2_19_16, FXR_TXENB_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINMUX_IPSR_GPSR(IP3_3_0, RX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINMUX_IPSR_GPSR(IP3_7_4, TX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_IPSR_GPSR(IP3_23_20, AVB_AVTP_PPS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_GPSR(IP5_7_4, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_IPSR_GPSR(IP5_11_8, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_GPSR(IP5_15_12, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_IPSR_GPSR(IP5_19_16, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_IPSR_GPSR(IP5_19_16, MMC_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_IPSR_GPSR(IP5_23_20, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_GPSR(IP5_23_20, MMC_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_GPSR(IP5_27_24, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_GPSR(IP5_27_24, MMC_DS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_GPSR(IP5_31_28, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP5_31_28, MMC_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINMUX_IPSR_GPSR(IP6_3_0, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP6_3_0, MMC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_GPSR(IP6_7_4, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_GPSR(IP6_7_4, MMC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_IPSR_GPSR(IP6_11_8, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_GPSR(IP6_11_8, MMC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_GPSR(IP6_15_12, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_IPSR_GPSR(IP6_15_12, MMC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_GPSR(IP6_19_16, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_IPSR_GPSR(IP6_19_16, MMC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_MSEL(IP6_23_20, TCLK1_A, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_GPSR(IP6_23_20, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_IPSR_GPSR(IP6_23_20, MMC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_MSEL(IP6_27_24, TCLK2_A, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_GPSR(IP6_27_24, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_GPSR(IP6_27_24, MMC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_GPSR(IP6_31_28, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_GPSR(IP6_31_28, MMC_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_GPSR(IP7_3_0, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_GPSR(IP7_3_0, MMC_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_MSEL(IP7_11_8, HSCK0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_IPSR_GPSR(IP7_15_12, HCTS0_N_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_IPSR_MSEL(IP1_23_20, HRTS0_N_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_IPSR_GPSR(IP7_23_20, RX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_IPSR_MSEL(IP7_23_20, HRX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_GPSR(IP7_27_24, TX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_MSEL(IP7_27_24, HTX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_IPSR_GPSR(IP7_31_28, AVB_AVTP_MATCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_IPSR_GPSR(IP7_31_28, TPU0TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_GPSR(IP8_3_0, AVB_AVTP_CAPTURE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_GPSR(IP8_3_0, TPU0TO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_TX_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_GPSR(IP8_7_4, FXR_TXDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_MSEL(IP8_7_4, PWM0_B, SEL_PWM0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_IPSR_GPSR(IP8_7_4, DU_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_MSEL(IP8_11_8, CANFD0_RX_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_IPSR_GPSR(IP8_11_8, RXDA_EXTFXR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_MSEL(IP8_11_8, PWM1_B, SEL_PWM1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_GPSR(IP8_11_8, DU_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_GPSR(IP8_15_12, FXR_TXDB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_MSEL(IP8_15_12, PWM2_B, SEL_PWM2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_MSEL(IP8_15_12, TCLK1_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_MSEL(IP8_15_12, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_GPSR(IP8_19_16, CANFD1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_GPSR(IP8_19_16, RXDB_EXTFXR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_MSEL(IP8_19_16, PWM3_B, SEL_PWM3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_MSEL(IP8_19_16, TCLK2_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_MSEL(IP8_19_16, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_MSEL(IP8_23_20, CANFD_CLK_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_GPSR(IP8_23_20, CLK_EXTFXR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PINMUX_IPSR_MSEL(IP8_23_20, PWM4_B, SEL_PWM4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_MSEL(IP8_23_20, SPEEDIN_B, SEL_RSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_MSEL(IP8_23_20, SCIF_CLK_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_GPSR(IP8_31_28, DIGRF_CLKEN_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_IPSR_GPSR(IP9_3_0, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP9_3_0, VI0_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_GPSR(IP9_7_4, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_IPSR_GPSR(IP9_7_4, VI0_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_GPSR(IP9_11_8, MSIOF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_GPSR(IP9_11_8, DU_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_GPSR(IP9_11_8, VI0_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_GPSR(IP9_15_12, MSIOF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_GPSR(IP9_15_12, DU_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_IPSR_GPSR(IP9_15_12, VI0_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_IPSR_GPSR(IP9_19_16, MSIOF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_IPSR_GPSR(IP9_19_16, DU_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_IPSR_GPSR(IP9_19_16, VI0_DATA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_GPSR(IP9_23_20, MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_GPSR(IP9_23_20, DU_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_GPSR(IP9_23_20, VI0_DATA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_GPSR(IP9_27_24, MSIOF0_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_GPSR(IP9_27_24, DU_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_GPSR(IP9_27_24, TCLK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_GPSR(IP9_27_24, VI0_DATA18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP9_31_28, MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_GPSR(IP9_31_28, DU_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_GPSR(IP9_31_28, TCLK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP9_31_28, VI0_DATA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP10_3_0, SCL3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_GPSR(IP10_3_0, VI0_DATA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP10_7_4, SDA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_GPSR(IP10_7_4, VI0_DATA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP10_11_8, FSO_CFE_0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP10_11_8, VI0_DATA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_GPSR(IP10_15_12, FSO_CFE_1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_GPSR(IP10_15_12, VI0_DATA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_GPSR(IP10_19_16, FSO_TOE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* - AVB -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* AVB_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* AVB_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* AVB_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const unsigned int avb_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) /* AVB_MDC, AVB_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const unsigned int avb_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) AVB_MDC_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const unsigned int avb_rgmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * AVB_TX_CTL, AVB_TXC, AVB_TD0, AVB_TD1, AVB_TD2, AVB_TD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * AVB_RX_CTL, AVB_RXC, AVB_RD0, AVB_RD1, AVB_RD2, AVB_RD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const unsigned int avb_rgmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) AVB_TX_CTL_MARK, AVB_TXC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) AVB_TD0_MARK, AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) AVB_RX_CTL_MARK, AVB_RXC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) AVB_RD0_MARK, AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const unsigned int avb_txcrefclk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* AVB_TXCREFCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const unsigned int avb_txcrefclk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) AVB_TXCREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const unsigned int avb_avtp_pps_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* AVB_AVTP_PPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const unsigned int avb_avtp_pps_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) AVB_AVTP_PPS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const unsigned int avb_avtp_capture_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* AVB_AVTP_CAPTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const unsigned int avb_avtp_capture_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) AVB_AVTP_CAPTURE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const unsigned int avb_avtp_match_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* AVB_AVTP_MATCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static const unsigned int avb_avtp_match_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) AVB_AVTP_MATCH_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /* - CANFD0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const unsigned int canfd0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* CANFD0_TX, CANFD0_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const unsigned int canfd0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const unsigned int canfd0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* CANFD0_TX, CANFD0_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const unsigned int canfd0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* - CANFD1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const unsigned int canfd1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* CANFD1_TX, CANFD1_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const unsigned int canfd1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) CANFD1_TX_MARK, CANFD1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* - CANFD Clock ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const unsigned int canfd_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* CANFD_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const unsigned int canfd_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) CANFD_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const unsigned int canfd_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* CANFD_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const unsigned int canfd_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) CANFD_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) /* DU_DR[7:2], DU_DG[7:2], DU_DB[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const unsigned int du_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* DU_DR[7:0], DU_DG[7:0], DU_DB[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const unsigned int du_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) DU_DR1_MARK, DU_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) DU_DG1_MARK, DU_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) DU_DB1_MARK, DU_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const unsigned int du_clk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) /* DU_DOTCLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const unsigned int du_clk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) DU_DOTCLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const unsigned int du_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* DU_EXVSYNC/DU_VSYNC, DU_EXHSYNC/DU_HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const unsigned int du_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const unsigned int du_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* DU_EXODDF/DU_ODDF/DISP/CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) static const unsigned int du_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* DU_CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) DU_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const unsigned int du_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* DU_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const unsigned int du_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) DU_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* - GETHER ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const unsigned int gether_link_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* GETHER_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const unsigned int gether_link_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GETHER_LINK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const unsigned int gether_phy_int_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* GETHER_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const unsigned int gether_phy_int_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GETHER_PHY_INT_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static const unsigned int gether_mdio_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* GETHER_MDC, GETHER_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static const unsigned int gether_mdio_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) GETHER_MDC_A_MARK, GETHER_MDIO_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static const unsigned int gether_link_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* GETHER_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const unsigned int gether_link_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GETHER_LINK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static const unsigned int gether_phy_int_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) /* GETHER_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const unsigned int gether_phy_int_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GETHER_PHY_INT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const unsigned int gether_mdio_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) GETHER_MDC_B_MARK, GETHER_MDIO_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const unsigned int gether_mdio_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* GETHER_MDC, GETHER_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static const unsigned int gether_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* GETHER_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static const unsigned int gether_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) GETHER_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const unsigned int gether_rgmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * GETHER_TX_CTL, GETHER_TXC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * GETHER_TD0, GETHER_TD1, GETHER_TD2, GETHER_TD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * GETHER_RX_CTL, GETHER_RXC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * GETHER_RD0, GETHER_RD1, GETHER_RD2, GETHER_RD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const unsigned int gether_rgmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) GETHER_TX_CTL_MARK, GETHER_TXC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) GETHER_TD0_MARK, GETHER_TD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) GETHER_TD2_MARK, GETHER_TD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) GETHER_RX_CTL_MARK, GETHER_RXC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) GETHER_RD0_MARK, AVB_RD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) GETHER_RD2_MARK, AVB_RD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const unsigned int gether_txcrefclk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* GETHER_TXCREFCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const unsigned int gether_txcrefclk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) GETHER_TXCREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static const unsigned int gether_txcrefclk_mega_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* GETHER_TXCREFCLK_MEGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const unsigned int gether_txcrefclk_mega_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) GETHER_TXCREFCLK_MEGA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static const unsigned int gether_rmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * GETHER_RMII_CRS_DV, GETHER_RMII_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * GETHER_RMII_RXD0, GETHER_RMII_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * GETHER_RMII_TXD_EN, GETHER_RMII_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * GETHER_RMII_TXD1, GETHER_RMII_REFCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const unsigned int gether_rmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) GETHER_RMII_CRS_DV_MARK, GETHER_RMII_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) GETHER_RMII_RXD0_MARK, GETHER_RMII_RXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) GETHER_RMII_TXD_EN_MARK, GETHER_RMII_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) GETHER_RMII_TXD1_MARK, GETHER_RMII_REFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const unsigned int hscif0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* HRX0, HTX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const unsigned int hscif0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) HRX0_A_MARK, HTX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const unsigned int hscif0_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* HSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const unsigned int hscif0_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) HSCK0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static const unsigned int hscif0_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* HRTS0#, HCTS0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const unsigned int hscif0_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) HRTS0_N_A_MARK, HCTS0_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const unsigned int hscif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* HRX0, HTX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const unsigned int hscif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) HRX0_B_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const unsigned int hscif0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* HSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const unsigned int hscif0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) HSCK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static const unsigned int hscif0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* HRTS0#, HCTS0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static const unsigned int hscif0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) HRTS0_N_B_MARK, HCTS0_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const unsigned int hscif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* HRX1, HTX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const unsigned int hscif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) HRX1_MARK, HTX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static const unsigned int hscif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* HSCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const unsigned int hscif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) HSCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const unsigned int hscif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* HRTS1#, HCTS1# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const unsigned int hscif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) HRTS1_N_MARK, HCTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* - HSCIF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const unsigned int hscif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* HRX2, HTX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const unsigned int hscif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) HRX2_MARK, HTX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static const unsigned int hscif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* HSCK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const unsigned int hscif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) HSCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const unsigned int hscif2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* HRTS2#, HCTS2# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static const unsigned int hscif2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) HRTS2_N_MARK, HCTS2_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* - HSCIF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const unsigned int hscif3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* HRX3, HTX3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static const unsigned int hscif3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) HRX3_MARK, HTX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) static const unsigned int hscif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* HSCK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static const unsigned int hscif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) HSCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const unsigned int hscif3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* HRTS3#, HCTS3# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const unsigned int hscif3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) HRTS3_N_MARK, HCTS3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) /* - I2C0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* SDA0, SCL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) SDA0_MARK, SCL0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /* - I2C1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const unsigned int i2c1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* SDA1, SCL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const unsigned int i2c1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) SDA1_MARK, SCL1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const unsigned int i2c2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /* SDA2, SCL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const unsigned int i2c2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) SDA2_MARK, SCL2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static const unsigned int i2c3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* SDA3, SCL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static const unsigned int i2c3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) SDA3_MARK, SCL3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* - I2C4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static const unsigned int i2c4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) /* SDA4, SCL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const unsigned int i2c4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) SDA4_MARK, SCL4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /* - I2C5 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static const unsigned int i2c5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* SDA5, SCL5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static const unsigned int i2c5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) SDA5_MARK, SCL5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* - INTC-EX ---------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const unsigned int intc_ex_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const unsigned int intc_ex_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const unsigned int intc_ex_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const unsigned int intc_ex_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static const unsigned int intc_ex_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const unsigned int intc_ex_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static const unsigned int intc_ex_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static const unsigned int intc_ex_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static const unsigned int intc_ex_irq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const unsigned int intc_ex_irq4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) IRQ4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static const unsigned int intc_ex_irq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const unsigned int intc_ex_irq5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) IRQ5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* - MMC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static const unsigned int mmc_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* MMC_D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static const unsigned int mmc_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) MMC_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static const unsigned int mmc_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* MMC_D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static const unsigned int mmc_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) MMC_D0_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static const unsigned int mmc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* MMC_D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static const unsigned int mmc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) MMC_D0_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) MMC_D4_MARK, MMC_D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) MMC_D6_MARK, MMC_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static const unsigned int mmc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* MMC_CLK, MMC_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const unsigned int mmc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) MMC_CLK_MARK, MMC_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) static const unsigned int mmc_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* MMC_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const unsigned int mmc_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) MMC_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static const unsigned int mmc_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* MMC_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static const unsigned int mmc_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) MMC_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const unsigned int mmc_ds_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) /* MMC_DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static const unsigned int mmc_ds_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) MMC_DS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* MSIOF0_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* MSIOF0_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* MSIOF0_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) /* MSIOF0_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static const unsigned int msiof0_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* MSIOF0_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static const unsigned int msiof0_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static const unsigned int msiof0_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* MSIOF0_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static const unsigned int msiof0_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* MSIOF1_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* MSIOF1_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* MSIOF1_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) /* MSIOF1_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) static const unsigned int msiof1_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* MSIOF1_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static const unsigned int msiof1_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static const unsigned int msiof1_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* MSIOF1_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static const unsigned int msiof1_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static const unsigned int msiof2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* MSIOF2_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const unsigned int msiof2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static const unsigned int msiof2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* MSIOF2_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const unsigned int msiof2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) MSIOF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static const unsigned int msiof2_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* MSIOF2_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const unsigned int msiof2_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static const unsigned int msiof2_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* MSIOF2_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const unsigned int msiof2_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const unsigned int msiof2_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* MSIOF2_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static const unsigned int msiof2_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static const unsigned int msiof2_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* MSIOF2_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const unsigned int msiof2_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* - MSIOF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static const unsigned int msiof3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* MSIOF3_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static const unsigned int msiof3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MSIOF3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static const unsigned int msiof3_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* MSIOF3_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static const unsigned int msiof3_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) MSIOF3_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int msiof3_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* MSIOF3_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static const unsigned int msiof3_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) MSIOF3_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static const unsigned int msiof3_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* MSIOF3_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const unsigned int msiof3_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MSIOF3_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const unsigned int msiof3_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* MSIOF3_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) static const unsigned int msiof3_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) MSIOF3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const unsigned int msiof3_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* MSIOF3_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static const unsigned int msiof3_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) MSIOF3_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* - PWM0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static const unsigned int pwm0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static const unsigned int pwm0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) PWM0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* - PWM1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const unsigned int pwm1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static const unsigned int pwm1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) PWM1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* - PWM2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static const unsigned int pwm2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* PWM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static const unsigned int pwm2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) PWM2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* PWM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* - PWM3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static const unsigned int pwm3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* PWM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static const unsigned int pwm3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) PWM3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const unsigned int pwm3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* PWM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static const unsigned int pwm3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* - PWM4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const unsigned int pwm4_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* PWM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static const unsigned int pwm4_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) PWM4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static const unsigned int pwm4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* PWM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static const unsigned int pwm4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* - QSPI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static const unsigned int qspi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static const unsigned int qspi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static const unsigned int qspi0_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned int qspi0_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static const unsigned int qspi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static const unsigned int qspi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) QSPI0_IO2_MARK, QSPI0_IO3_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* - QSPI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const unsigned int qspi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static const unsigned int qspi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static const unsigned int qspi1_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const unsigned int qspi1_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const unsigned int qspi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static const unsigned int qspi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) QSPI1_IO2_MARK, QSPI1_IO3_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* - RPC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const unsigned int rpc_clk1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Octal-SPI flash: C/SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static const unsigned int rpc_clk1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) QSPI0_SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const unsigned int rpc_clk2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* HyperFlash: CK, CK# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static const unsigned int rpc_clk2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static const unsigned int rpc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* Octal-SPI flash: S#/CS, DQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) /* HyperFlash: CS#, RDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const unsigned int rpc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) QSPI0_SSL_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static const unsigned int rpc_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* DQ[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const unsigned int rpc_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) QSPI0_IO2_MARK, QSPI0_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) QSPI1_IO2_MARK, QSPI1_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static const unsigned int rpc_reset_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* RPC_RESET# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static const unsigned int rpc_reset_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) RPC_RESET_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static const unsigned int rpc_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* RPC_INT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static const unsigned int rpc_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) RPC_INT_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static const unsigned int rpc_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* RPC_WP# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static const unsigned int rpc_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) RPC_WP_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static const unsigned int scif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* RX0, TX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static const unsigned int scif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) RX0_MARK, TX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static const unsigned int scif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* SCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const unsigned int scif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) SCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static const unsigned int scif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* RTS0#, CTS0# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static const unsigned int scif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) RTS0_N_MARK, CTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static const unsigned int scif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* RX1, TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const unsigned int scif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) RX1_A_MARK, TX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const unsigned int scif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* SCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned int scif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) SCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static const unsigned int scif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* RTS1#, CTS1# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static const unsigned int scif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) RTS1_N_MARK, CTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) /* RX1, TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static const unsigned int scif3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) /* RX3, TX3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) static const unsigned int scif3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) RX3_MARK, TX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static const unsigned int scif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* SCK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static const unsigned int scif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) SCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const unsigned int scif3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* RTS3#, CTS3# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static const unsigned int scif3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) RTS3_N_MARK, CTS3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static const unsigned int scif4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* RX4, TX4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static const unsigned int scif4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) RX4_MARK, TX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static const unsigned int scif4_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* SCK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const unsigned int scif4_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) SCK4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const unsigned int scif4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /* RTS4#, CTS4# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static const unsigned int scif4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) RTS4_N_MARK, CTS4_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static const unsigned int scif_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const unsigned int scif_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) SCIF_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* - TMU -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) static const unsigned int tmu_tclk1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* TCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static const unsigned int tmu_tclk1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) TCLK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const unsigned int tmu_tclk1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* TCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const unsigned int tmu_tclk1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const unsigned int tmu_tclk2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* TCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static const unsigned int tmu_tclk2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) TCLK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static const unsigned int tmu_tclk2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* TCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static const unsigned int tmu_tclk2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) TCLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* - TPU ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const unsigned int tpu_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* TPU0TO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static const unsigned int tpu_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) TPU0TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const unsigned int tpu_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* TPU0TO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) static const unsigned int tpu_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static const unsigned int tpu_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /* TPU0TO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) static const unsigned int tpu_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) TPU0TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static const unsigned int tpu_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* TPU0TO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const unsigned int tpu_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static const union vin_data vin0_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const union vin_data vin0_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) VI0_DATA0_MARK, VI0_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) VI0_DATA2_MARK, VI0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) VI0_DATA4_MARK, VI0_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) VI0_DATA6_MARK, VI0_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) VI0_DATA8_MARK, VI0_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) VI0_DATA10_MARK, VI0_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) VI0_DATA12_MARK, VI0_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) VI0_DATA14_MARK, VI0_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) VI0_DATA16_MARK, VI0_DATA17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) VI0_DATA18_MARK, VI0_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) VI0_DATA20_MARK, VI0_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) VI0_DATA22_MARK, VI0_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static const unsigned int vin0_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static const unsigned int vin0_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) VI0_DATA2_MARK, VI0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) VI0_DATA4_MARK, VI0_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) VI0_DATA6_MARK, VI0_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) VI0_DATA10_MARK, VI0_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) VI0_DATA12_MARK, VI0_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) VI0_DATA14_MARK, VI0_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) VI0_DATA18_MARK, VI0_DATA19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) VI0_DATA20_MARK, VI0_DATA21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) VI0_DATA22_MARK, VI0_DATA23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static const unsigned int vin0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* VI0_VSYNC#, VI0_HSYNC# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const unsigned int vin0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) VI0_VSYNC_N_MARK, VI0_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) static const unsigned int vin0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /* VI0_FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static const unsigned int vin0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static const unsigned int vin0_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) /* VI0_CLKENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) static const unsigned int vin0_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static const unsigned int vin0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* VI0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static const unsigned int vin0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* - VIN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static const union vin_data12 vin1_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static const union vin_data12 vin1_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) VI1_DATA0_MARK, VI1_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) VI1_DATA2_MARK, VI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) VI1_DATA4_MARK, VI1_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) VI1_DATA6_MARK, VI1_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) VI1_DATA8_MARK, VI1_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) VI1_DATA10_MARK, VI1_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static const unsigned int vin1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* VI1_VSYNC#, VI1_HSYNC# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static const unsigned int vin1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) VI1_VSYNC_N_MARK, VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static const unsigned int vin1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* VI1_FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static const unsigned int vin1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static const unsigned int vin1_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* VI1_CLKENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static const unsigned int vin1_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static const unsigned int vin1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* VI1_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static const unsigned int vin1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) SH_PFC_PIN_GROUP(avb_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) SH_PFC_PIN_GROUP(avb_rgmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) SH_PFC_PIN_GROUP(avb_txcrefclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) SH_PFC_PIN_GROUP(avb_avtp_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) SH_PFC_PIN_GROUP(avb_avtp_capture),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) SH_PFC_PIN_GROUP(avb_avtp_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) SH_PFC_PIN_GROUP(canfd0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) SH_PFC_PIN_GROUP(canfd0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) SH_PFC_PIN_GROUP(canfd1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) SH_PFC_PIN_GROUP(canfd_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) SH_PFC_PIN_GROUP(canfd_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) SH_PFC_PIN_GROUP(du_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) SH_PFC_PIN_GROUP(du_clk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) SH_PFC_PIN_GROUP(du_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) SH_PFC_PIN_GROUP(du_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) SH_PFC_PIN_GROUP(du_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) SH_PFC_PIN_GROUP(gether_link_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) SH_PFC_PIN_GROUP(gether_phy_int_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) SH_PFC_PIN_GROUP(gether_mdio_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) SH_PFC_PIN_GROUP(gether_link_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) SH_PFC_PIN_GROUP(gether_phy_int_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) SH_PFC_PIN_GROUP(gether_mdio_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) SH_PFC_PIN_GROUP(gether_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) SH_PFC_PIN_GROUP(gether_rgmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) SH_PFC_PIN_GROUP(gether_txcrefclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) SH_PFC_PIN_GROUP(gether_txcrefclk_mega),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) SH_PFC_PIN_GROUP(gether_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) SH_PFC_PIN_GROUP(hscif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) SH_PFC_PIN_GROUP(hscif0_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) SH_PFC_PIN_GROUP(hscif0_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) SH_PFC_PIN_GROUP(hscif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) SH_PFC_PIN_GROUP(hscif0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) SH_PFC_PIN_GROUP(hscif0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) SH_PFC_PIN_GROUP(hscif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) SH_PFC_PIN_GROUP(hscif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) SH_PFC_PIN_GROUP(hscif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) SH_PFC_PIN_GROUP(hscif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) SH_PFC_PIN_GROUP(hscif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) SH_PFC_PIN_GROUP(hscif2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) SH_PFC_PIN_GROUP(hscif3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) SH_PFC_PIN_GROUP(hscif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) SH_PFC_PIN_GROUP(hscif3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) SH_PFC_PIN_GROUP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) SH_PFC_PIN_GROUP(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) SH_PFC_PIN_GROUP(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) SH_PFC_PIN_GROUP(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) SH_PFC_PIN_GROUP(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) SH_PFC_PIN_GROUP(intc_ex_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) SH_PFC_PIN_GROUP(intc_ex_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) SH_PFC_PIN_GROUP(intc_ex_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) SH_PFC_PIN_GROUP(intc_ex_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) SH_PFC_PIN_GROUP(intc_ex_irq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) SH_PFC_PIN_GROUP(intc_ex_irq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) SH_PFC_PIN_GROUP(mmc_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) SH_PFC_PIN_GROUP(mmc_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) SH_PFC_PIN_GROUP(mmc_ds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) SH_PFC_PIN_GROUP(msiof0_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) SH_PFC_PIN_GROUP(msiof0_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) SH_PFC_PIN_GROUP(msiof1_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) SH_PFC_PIN_GROUP(msiof1_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) SH_PFC_PIN_GROUP(msiof2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) SH_PFC_PIN_GROUP(msiof2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) SH_PFC_PIN_GROUP(msiof2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) SH_PFC_PIN_GROUP(msiof2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) SH_PFC_PIN_GROUP(msiof2_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) SH_PFC_PIN_GROUP(msiof2_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) SH_PFC_PIN_GROUP(msiof3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) SH_PFC_PIN_GROUP(msiof3_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) SH_PFC_PIN_GROUP(msiof3_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) SH_PFC_PIN_GROUP(msiof3_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) SH_PFC_PIN_GROUP(msiof3_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) SH_PFC_PIN_GROUP(msiof3_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) SH_PFC_PIN_GROUP(pwm0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) SH_PFC_PIN_GROUP(pwm1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) SH_PFC_PIN_GROUP(pwm2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) SH_PFC_PIN_GROUP(pwm3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) SH_PFC_PIN_GROUP(pwm3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) SH_PFC_PIN_GROUP(pwm4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) SH_PFC_PIN_GROUP(pwm4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) SH_PFC_PIN_GROUP(qspi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) SH_PFC_PIN_GROUP(qspi0_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) SH_PFC_PIN_GROUP(qspi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) SH_PFC_PIN_GROUP(qspi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) SH_PFC_PIN_GROUP(qspi1_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) SH_PFC_PIN_GROUP(qspi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) SH_PFC_PIN_GROUP(rpc_clk1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) SH_PFC_PIN_GROUP(rpc_clk2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) SH_PFC_PIN_GROUP(rpc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) SH_PFC_PIN_GROUP(rpc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) SH_PFC_PIN_GROUP(rpc_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) SH_PFC_PIN_GROUP(rpc_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) SH_PFC_PIN_GROUP(rpc_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) SH_PFC_PIN_GROUP(scif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) SH_PFC_PIN_GROUP(scif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) SH_PFC_PIN_GROUP(scif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) SH_PFC_PIN_GROUP(scif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) SH_PFC_PIN_GROUP(scif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) SH_PFC_PIN_GROUP(scif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) SH_PFC_PIN_GROUP(scif3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) SH_PFC_PIN_GROUP(scif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) SH_PFC_PIN_GROUP(scif3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) SH_PFC_PIN_GROUP(scif4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) SH_PFC_PIN_GROUP(scif4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) SH_PFC_PIN_GROUP(scif4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) SH_PFC_PIN_GROUP(scif_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) SH_PFC_PIN_GROUP(tmu_tclk1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) SH_PFC_PIN_GROUP(tmu_tclk1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) SH_PFC_PIN_GROUP(tmu_tclk2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) SH_PFC_PIN_GROUP(tmu_tclk2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) SH_PFC_PIN_GROUP(tpu_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) SH_PFC_PIN_GROUP(tpu_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) SH_PFC_PIN_GROUP(tpu_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) SH_PFC_PIN_GROUP(tpu_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) VIN_DATA_PIN_GROUP(vin0_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) VIN_DATA_PIN_GROUP(vin0_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) VIN_DATA_PIN_GROUP(vin0_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) VIN_DATA_PIN_GROUP(vin0_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) SH_PFC_PIN_GROUP(vin0_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) VIN_DATA_PIN_GROUP(vin0_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) VIN_DATA_PIN_GROUP(vin0_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) SH_PFC_PIN_GROUP(vin0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) SH_PFC_PIN_GROUP(vin0_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) VIN_DATA_PIN_GROUP(vin1_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) VIN_DATA_PIN_GROUP(vin1_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) VIN_DATA_PIN_GROUP(vin1_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) SH_PFC_PIN_GROUP(vin1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) SH_PFC_PIN_GROUP(vin1_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) "avb_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) "avb_rgmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) "avb_txcrefclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) "avb_avtp_pps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) "avb_avtp_capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) "avb_avtp_match",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static const char * const canfd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) "canfd0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) "canfd0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static const char * const canfd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) "canfd1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static const char * const canfd_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) "canfd_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) "canfd_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) "du_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) "du_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) "du_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) "du_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) "du_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) static const char * const gether_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) "gether_link_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) "gether_phy_int_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) "gether_mdio_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) "gether_link_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) "gether_phy_int_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) "gether_mdio_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) "gether_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) "gether_rgmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) "gether_txcrefclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) "gether_txcrefclk_mega",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) "gether_rmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) "hscif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) "hscif0_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) "hscif0_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) "hscif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) "hscif0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) "hscif0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) "hscif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) "hscif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) "hscif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static const char * const hscif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) "hscif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) "hscif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) "hscif2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) static const char * const hscif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) "hscif3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) "hscif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) "hscif3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) static const char * const i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) "i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static const char * const intc_ex_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) "intc_ex_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) "intc_ex_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) "intc_ex_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) "intc_ex_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) "intc_ex_irq4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) "intc_ex_irq5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) "mmc_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) "mmc_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) "mmc_ds",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) "msiof0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) "msiof0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) "msiof1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) "msiof1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) "msiof2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) "msiof2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) "msiof2_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) "msiof2_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) "msiof2_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) "msiof2_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) "msiof3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) "msiof3_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) "msiof3_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) "msiof3_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) "msiof3_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) "msiof3_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) "pwm0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) "pwm1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) "pwm2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) "pwm3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) "pwm3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) "pwm4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) "pwm4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) static const char * const qspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) "qspi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) "qspi0_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) "qspi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static const char * const qspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) "qspi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "qspi1_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) "qspi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) static const char * const rpc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) "rpc_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) "rpc_clk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) "rpc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) "rpc_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) "rpc_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) "rpc_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) "rpc_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) "scif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) "scif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) "scif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) "scif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) "scif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) "scif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) "scif3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) "scif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) "scif3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) "scif4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) "scif4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) "scif4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) "scif_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static const char * const tmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) "tmu_tclk1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) "tmu_tclk1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) "tmu_tclk2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) "tmu_tclk2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static const char * const tpu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) "tpu_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) "tpu_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) "tpu_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) "tpu_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) "vin0_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) "vin0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) "vin0_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) "vin0_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) "vin0_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) "vin0_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) "vin0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) "vin0_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) "vin1_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) "vin1_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) "vin1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) "vin1_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) SH_PFC_FUNCTION(canfd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) SH_PFC_FUNCTION(canfd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) SH_PFC_FUNCTION(canfd_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) SH_PFC_FUNCTION(gether),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) SH_PFC_FUNCTION(hscif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) SH_PFC_FUNCTION(hscif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) SH_PFC_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) SH_PFC_FUNCTION(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) SH_PFC_FUNCTION(intc_ex),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) SH_PFC_FUNCTION(qspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) SH_PFC_FUNCTION(qspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) SH_PFC_FUNCTION(rpc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) SH_PFC_FUNCTION(tmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) SH_PFC_FUNCTION(tpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #define F_(x, y) FN_##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define FM(x) FN_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) GP_0_21_FN, GPSR0_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) GP_0_20_FN, GPSR0_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) GP_0_19_FN, GPSR0_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) GP_0_18_FN, GPSR0_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) GP_0_17_FN, GPSR0_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) GP_0_16_FN, GPSR0_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) GP_0_15_FN, GPSR0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) GP_0_14_FN, GPSR0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) GP_0_13_FN, GPSR0_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) GP_0_12_FN, GPSR0_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) GP_0_11_FN, GPSR0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) GP_0_10_FN, GPSR0_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) GP_0_9_FN, GPSR0_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) GP_0_8_FN, GPSR0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) GP_0_7_FN, GPSR0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) GP_0_6_FN, GPSR0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) GP_0_5_FN, GPSR0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) GP_0_4_FN, GPSR0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) GP_0_3_FN, GPSR0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) GP_0_2_FN, GPSR0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) GP_0_1_FN, GPSR0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) GP_0_0_FN, GPSR0_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) GP_1_27_FN, GPSR1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) GP_1_26_FN, GPSR1_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) GP_1_25_FN, GPSR1_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) GP_1_24_FN, GPSR1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) GP_1_23_FN, GPSR1_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) GP_1_22_FN, GPSR1_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) GP_1_21_FN, GPSR1_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) GP_1_20_FN, GPSR1_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) GP_1_19_FN, GPSR1_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) GP_1_18_FN, GPSR1_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) GP_1_17_FN, GPSR1_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) GP_1_16_FN, GPSR1_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) GP_1_15_FN, GPSR1_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) GP_1_14_FN, GPSR1_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) GP_1_13_FN, GPSR1_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) GP_1_12_FN, GPSR1_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) GP_1_11_FN, GPSR1_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) GP_1_10_FN, GPSR1_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) GP_1_9_FN, GPSR1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) GP_1_8_FN, GPSR1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) GP_1_7_FN, GPSR1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) GP_1_6_FN, GPSR1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) GP_1_5_FN, GPSR1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) GP_1_4_FN, GPSR1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) GP_1_3_FN, GPSR1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) GP_1_2_FN, GPSR1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) GP_1_1_FN, GPSR1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) GP_1_0_FN, GPSR1_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) GP_2_29_FN, GPSR2_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) GP_2_28_FN, GPSR2_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) GP_2_27_FN, GPSR2_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) GP_2_26_FN, GPSR2_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) GP_2_25_FN, GPSR2_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) GP_2_24_FN, GPSR2_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) GP_2_23_FN, GPSR2_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) GP_2_22_FN, GPSR2_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) GP_2_21_FN, GPSR2_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) GP_2_20_FN, GPSR2_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) GP_2_19_FN, GPSR2_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) GP_2_18_FN, GPSR2_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) GP_2_17_FN, GPSR2_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) GP_2_16_FN, GPSR2_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) GP_2_15_FN, GPSR2_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) GP_2_14_FN, GPSR2_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) GP_2_13_FN, GPSR2_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) GP_2_12_FN, GPSR2_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) GP_2_11_FN, GPSR2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) GP_2_10_FN, GPSR2_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) GP_2_9_FN, GPSR2_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) GP_2_8_FN, GPSR2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) GP_2_7_FN, GPSR2_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) GP_2_6_FN, GPSR2_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) GP_2_5_FN, GPSR2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) GP_2_4_FN, GPSR2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) GP_2_3_FN, GPSR2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) GP_2_2_FN, GPSR2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) GP_2_1_FN, GPSR2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) GP_2_0_FN, GPSR2_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) GP_3_16_FN, GPSR3_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) GP_3_15_FN, GPSR3_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) GP_3_14_FN, GPSR3_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) GP_3_13_FN, GPSR3_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) GP_3_12_FN, GPSR3_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) GP_3_11_FN, GPSR3_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) GP_3_10_FN, GPSR3_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) GP_3_9_FN, GPSR3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) GP_3_8_FN, GPSR3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) GP_3_7_FN, GPSR3_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) GP_3_6_FN, GPSR3_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) GP_3_5_FN, GPSR3_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) GP_3_4_FN, GPSR3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) GP_3_3_FN, GPSR3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) GP_3_2_FN, GPSR3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) GP_3_1_FN, GPSR3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) GP_3_0_FN, GPSR3_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) GP_4_24_FN, GPSR4_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) GP_4_23_FN, GPSR4_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) GP_4_22_FN, GPSR4_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) GP_4_21_FN, GPSR4_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) GP_4_20_FN, GPSR4_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) GP_4_19_FN, GPSR4_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) GP_4_18_FN, GPSR4_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) GP_4_17_FN, GPSR4_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) GP_4_16_FN, GPSR4_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) GP_4_15_FN, GPSR4_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) GP_4_14_FN, GPSR4_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) GP_4_13_FN, GPSR4_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) GP_4_12_FN, GPSR4_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) GP_4_11_FN, GPSR4_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) GP_4_10_FN, GPSR4_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) GP_4_9_FN, GPSR4_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) GP_4_8_FN, GPSR4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) GP_4_7_FN, GPSR4_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) GP_4_6_FN, GPSR4_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) GP_4_5_FN, GPSR4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) GP_4_4_FN, GPSR4_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) GP_4_3_FN, GPSR4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) GP_4_2_FN, GPSR4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) GP_4_1_FN, GPSR4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) GP_4_0_FN, GPSR4_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) GP_5_14_FN, GPSR5_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) GP_5_13_FN, GPSR5_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) GP_5_12_FN, GPSR5_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) GP_5_11_FN, GPSR5_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) GP_5_10_FN, GPSR5_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) GP_5_9_FN, GPSR5_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) GP_5_8_FN, GPSR5_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) GP_5_7_FN, GPSR5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) GP_5_6_FN, GPSR5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) GP_5_5_FN, GPSR5_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) GP_5_4_FN, GPSR5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) GP_5_3_FN, GPSR5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) GP_5_2_FN, GPSR5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) GP_5_1_FN, GPSR5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) GP_5_0_FN, GPSR5_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) IP0_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) IP0_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) IP0_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) IP0_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) IP0_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) IP0_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) IP0_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) IP0_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) IP1_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) IP1_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) IP1_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) IP1_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) IP1_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) IP1_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) IP1_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) IP1_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) IP2_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) IP2_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) IP2_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) IP2_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) IP2_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) IP2_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) IP2_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) IP2_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) IP3_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) IP3_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) IP3_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) IP3_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) IP3_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) IP3_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) IP3_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) IP3_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) IP4_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) IP4_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) IP4_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) IP4_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) IP4_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) IP4_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) IP4_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) IP4_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) IP5_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) IP5_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) IP5_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) IP5_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) IP5_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) IP5_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) IP5_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) IP5_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) IP6_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) IP6_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) IP6_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) IP6_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) IP6_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) IP6_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) IP6_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) IP6_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) IP7_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) IP7_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) IP7_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) IP7_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) IP7_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) IP7_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) IP7_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) IP7_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) IP8_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) IP8_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) IP8_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) IP8_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) IP8_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) IP8_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) IP8_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) IP8_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) IP9_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) IP9_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) IP9_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) IP9_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) IP9_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) IP9_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) IP9_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) IP9_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) IP10_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) IP10_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) IP10_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) IP10_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) IP10_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) IP10_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) IP10_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) IP10_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) /* RESERVED 31, 30, 29, 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) /* RESERVED 27, 26, 25, 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /* RESERVED 23, 22, 21, 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) /* RESERVED 19, 18, 17, 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /* RESERVED 15, 14, 13, 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) MOD_SEL0_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) MOD_SEL0_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) MOD_SEL0_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) MOD_SEL0_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) MOD_SEL0_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) MOD_SEL0_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) MOD_SEL0_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) MOD_SEL0_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) MOD_SEL0_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) MOD_SEL0_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) MOD_SEL0_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) enum ioctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) POCCTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) POCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) POCCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) POCCTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) TDSELCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [POCCTRL0] = { 0xe6060380, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [POCCTRL1] = { 0xe6060384, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [POCCTRL2] = { 0xe6060388, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) [POCCTRL3] = { 0xe606038c, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) [TDSELCTRL] = { 0xe60603c0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static int r8a77980_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) int bit = pin & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) else if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) return bit + 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) return bit - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) if ((pin >= RCAR_GP_PIN(2, 17) && pin <= RCAR_GP_PIN(2, 24)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) return bit + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) if (pin >= RCAR_GP_PIN(2, 25) && pin <= RCAR_GP_PIN(2, 29))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) return pin - 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static const struct sh_pfc_soc_operations pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .pin_to_pocctrl = r8a77980_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) const struct sh_pfc_soc_info r8a77980_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .name = "r8a77980_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) .ops = &pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) .ioctrl_regs = pinmux_ioctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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