^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A77970 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2017 Cogent Embedded, Inc. <source@cogentembedded.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * R-Car Gen3 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_CFG_22(0, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_28(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_CFG_17(2, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_CFG_17(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_6(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_15(5, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * F_() : just information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * FM() : macro for FN_xxx / xxx_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GPSR0_21 F_(DU_EXODDF_DU_ODDF_DISP_CDE, IP2_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPSR0_20 F_(DU_EXVSYNC_DU_VSYNC, IP2_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPSR0_19 F_(DU_EXHSYNC_DU_HSYNC, IP2_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPSR0_18 F_(DU_DOTCLKOUT, IP2_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define GPSR0_17 F_(DU_DB7, IP2_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GPSR0_16 F_(DU_DB6, IP2_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GPSR0_15 F_(DU_DB5, IP1_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPSR0_14 F_(DU_DB4, IP1_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPSR0_13 F_(DU_DB3, IP1_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPSR0_12 F_(DU_DB2, IP1_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPSR0_11 F_(DU_DG7, IP1_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPSR0_10 F_(DU_DG6, IP1_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPSR0_9 F_(DU_DG5, IP1_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPSR0_8 F_(DU_DG4, IP1_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPSR0_7 F_(DU_DG3, IP0_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPSR0_6 F_(DU_DG2, IP0_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GPSR0_5 F_(DU_DR7, IP0_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GPSR0_4 F_(DU_DR6, IP0_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPSR0_3 F_(DU_DR5, IP0_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPSR0_2 F_(DU_DR4, IP0_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPSR0_1 F_(DU_DR3, IP0_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPSR0_0 F_(DU_DR2, IP0_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GPSR1_27 F_(DIGRF_CLKOUT, IP8_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GPSR1_26 F_(DIGRF_CLKIN, IP8_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GPSR1_25 F_(CANFD_CLK_A, IP8_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GPSR1_24 F_(CANFD1_RX, IP8_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GPSR1_23 F_(CANFD1_TX, IP8_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GPSR1_22 F_(CANFD0_RX_A, IP8_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GPSR1_21 F_(CANFD0_TX_A, IP8_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GPSR1_20 F_(AVB0_AVTP_CAPTURE, IP7_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GPSR1_19 FM(AVB0_AVTP_MATCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GPSR1_18 FM(AVB0_LINK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GPSR1_17 FM(AVB0_PHY_INT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GPSR1_16 FM(AVB0_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GPSR1_15 FM(AVB0_MDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GPSR1_14 FM(AVB0_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GPSR1_13 FM(AVB0_TXCREFCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GPSR1_12 FM(AVB0_TD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GPSR1_11 FM(AVB0_TD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GPSR1_10 FM(AVB0_TD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GPSR1_9 FM(AVB0_TD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GPSR1_8 FM(AVB0_TXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPSR1_7 FM(AVB0_TX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPSR1_6 FM(AVB0_RD3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPSR1_5 FM(AVB0_RD2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPSR1_4 FM(AVB0_RD1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPSR1_3 FM(AVB0_RD0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPSR1_2 FM(AVB0_RXC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPSR1_1 FM(AVB0_RX_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPSR1_0 F_(IRQ0, IP2_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GPSR2_16 F_(VI0_FIELD, IP4_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPSR2_15 F_(VI0_DATA11, IP4_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPSR2_14 F_(VI0_DATA10, IP4_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GPSR2_13 F_(VI0_DATA9, IP4_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GPSR2_12 F_(VI0_DATA8, IP4_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPSR2_11 F_(VI0_DATA7, IP4_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GPSR2_10 F_(VI0_DATA6, IP4_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPSR2_9 F_(VI0_DATA5, IP4_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPSR2_8 F_(VI0_DATA4, IP3_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GPSR2_7 F_(VI0_DATA3, IP3_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GPSR2_6 F_(VI0_DATA2, IP3_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPSR2_5 F_(VI0_DATA1, IP3_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPSR2_4 F_(VI0_DATA0, IP3_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPSR2_3 F_(VI0_VSYNC_N, IP3_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPSR2_1 F_(VI0_CLKENB, IP3_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPSR2_0 F_(VI0_CLK, IP2_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPSR3_16 F_(VI1_FIELD, IP7_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GPSR3_15 F_(VI1_DATA11, IP6_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPSR3_14 F_(VI1_DATA10, IP6_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPSR3_13 F_(VI1_DATA9, IP6_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPSR3_12 F_(VI1_DATA8, IP6_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPSR3_11 F_(VI1_DATA7, IP6_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPSR3_10 F_(VI1_DATA6, IP6_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPSR3_9 F_(VI1_DATA5, IP6_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPSR3_8 F_(VI1_DATA4, IP6_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPSR3_7 F_(VI1_DATA3, IP5_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GPSR3_6 F_(VI1_DATA2, IP5_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPSR3_5 F_(VI1_DATA1, IP5_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GPSR3_4 F_(VI1_DATA0, IP5_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPSR3_3 F_(VI1_VSYNC_N, IP5_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPSR3_2 F_(VI1_HSYNC_N, IP5_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPSR3_1 F_(VI1_CLKENB, IP5_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPSR3_0 F_(VI1_CLK, IP5_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPSR4_5 F_(SDA2, IP7_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GPSR4_4 F_(SCL2, IP7_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GPSR4_3 F_(SDA1, IP7_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPSR4_2 F_(SCL1, IP7_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPSR4_1 F_(SDA0, IP7_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPSR4_0 F_(SCL0, IP7_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPSR5_14 FM(RPC_INT_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPSR5_13 FM(RPC_WP_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPSR5_12 FM(RPC_RESET_N)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPSR5_11 FM(QSPI1_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GPSR5_10 FM(QSPI1_IO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GPSR5_9 FM(QSPI1_IO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPSR5_8 FM(QSPI1_MISO_IO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPSR5_7 FM(QSPI1_MOSI_IO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPSR5_6 FM(QSPI1_SPCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPSR5_5 FM(QSPI0_SSL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GPSR5_4 FM(QSPI0_IO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPSR5_3 FM(QSPI0_IO2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPSR5_2 FM(QSPI0_MISO_IO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPSR5_1 FM(QSPI0_MOSI_IO0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPSR5_0 FM(QSPI0_SPCLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IP0_3_0 FM(DU_DR2) FM(HSCK0) F_(0, 0) FM(A0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IP0_7_4 FM(DU_DR3) FM(HRTS0_N) F_(0, 0) FM(A1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IP0_11_8 FM(DU_DR4) FM(HCTS0_N) F_(0, 0) FM(A2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IP0_15_12 FM(DU_DR5) FM(HTX0) F_(0, 0) FM(A3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IP0_19_16 FM(DU_DR6) FM(MSIOF3_RXD) F_(0, 0) FM(A4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IP0_23_20 FM(DU_DR7) FM(MSIOF3_TXD) F_(0, 0) FM(A5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IP0_27_24 FM(DU_DG2) FM(MSIOF3_SS1) F_(0, 0) FM(A6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IP0_31_28 FM(DU_DG3) FM(MSIOF3_SS2) F_(0, 0) FM(A7) FM(PWMFSW0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IP1_3_0 FM(DU_DG4) F_(0, 0) F_(0, 0) FM(A8) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IP1_11_8 FM(DU_DG6) F_(0, 0) F_(0, 0) FM(A10) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IP1_15_12 FM(DU_DG7) F_(0, 0) F_(0, 0) FM(A11) FM(IRQ1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IP1_19_16 FM(DU_DB2) F_(0, 0) F_(0, 0) FM(A12) FM(IRQ2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IP1_23_20 FM(DU_DB3) F_(0, 0) F_(0, 0) FM(A13) FM(FXR_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IP1_27_24 FM(DU_DB4) F_(0, 0) F_(0, 0) FM(A14) FM(FXR_CLKOUT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IP1_31_28 FM(DU_DB5) F_(0, 0) F_(0, 0) FM(A15) FM(FXR_TXENA_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IP2_3_0 FM(DU_DB6) F_(0, 0) F_(0, 0) FM(A16) FM(FXR_TXENB_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IP2_7_4 FM(DU_DB7) F_(0, 0) F_(0, 0) FM(A17) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IP2_11_8 FM(DU_DOTCLKOUT) FM(SCIF_CLK_A) F_(0, 0) FM(A18) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IP2_15_12 FM(DU_EXHSYNC_DU_HSYNC) FM(HRX0) F_(0, 0) FM(A19) FM(IRQ3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IP2_19_16 FM(DU_EXVSYNC_DU_VSYNC) FM(MSIOF3_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IP2_23_20 FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(MSIOF3_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IP2_27_24 FM(IRQ0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IP2_31_28 FM(VI0_CLK) FM(MSIOF2_SCK) FM(SCK3) F_(0, 0) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IP3_3_0 FM(VI0_CLKENB) FM(MSIOF2_RXD) FM(RX3) FM(RD_WR_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IP3_11_8 FM(VI0_VSYNC_N) FM(MSIOF2_SYNC) FM(CTS3_N) F_(0, 0) FM(HTX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IP3_15_12 FM(VI0_DATA0) FM(MSIOF2_SS1) FM(RTS3_N) F_(0, 0) FM(HRX3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IP3_19_16 FM(VI0_DATA1) FM(MSIOF2_SS2) FM(SCK1) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IP3_23_20 FM(VI0_DATA2) FM(AVB0_AVTP_PPS) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IP3_27_24 FM(VI0_DATA3) FM(HSCK1) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IP3_31_28 FM(VI0_DATA4) FM(HRTS1_N) FM(RX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IP4_3_0 FM(VI0_DATA5) FM(HCTS1_N) FM(TX1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IP4_7_4 FM(VI0_DATA6) FM(HTX1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IP4_11_8 FM(VI0_DATA7) FM(HRX1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IP4_15_12 FM(VI0_DATA8) FM(HSCK2) FM(PWM0_A) FM(A22) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IP4_19_16 FM(VI0_DATA9) FM(HCTS2_N) FM(PWM1_A) FM(A23) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IP4_23_20 FM(VI0_DATA10) FM(HRTS2_N) FM(PWM2_A) FM(A24) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IP4_27_24 FM(VI0_DATA11) FM(HTX2) FM(PWM3_A) FM(A25) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IP4_31_28 FM(VI0_FIELD) FM(HRX2) FM(PWM4_A) FM(CS1_N) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IP5_3_0 FM(VI1_CLK) FM(MSIOF1_RXD) F_(0, 0) FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IP5_7_4 FM(VI1_CLKENB) FM(MSIOF1_TXD) F_(0, 0) FM(D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IP5_11_8 FM(VI1_HSYNC_N) FM(MSIOF1_SCK) F_(0, 0) FM(D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IP5_15_12 FM(VI1_VSYNC_N) FM(MSIOF1_SYNC) F_(0, 0) FM(D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IP5_19_16 FM(VI1_DATA0) FM(MSIOF1_SS1) F_(0, 0) FM(D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IP5_23_20 FM(VI1_DATA1) FM(MSIOF1_SS2) F_(0, 0) FM(D4) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IP5_27_24 FM(VI1_DATA2) FM(CANFD0_TX_B) F_(0, 0) FM(D5) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IP5_31_28 FM(VI1_DATA3) FM(CANFD0_RX_B) F_(0, 0) FM(D6) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IP6_3_0 FM(VI1_DATA4) FM(CANFD_CLK_B) F_(0, 0) FM(D7) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IP6_7_4 FM(VI1_DATA5) F_(0, 0) FM(SCK4) FM(D8) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IP6_11_8 FM(VI1_DATA6) F_(0, 0) FM(RX4) FM(D9) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IP6_15_12 FM(VI1_DATA7) F_(0, 0) FM(TX4) FM(D10) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IP6_19_16 FM(VI1_DATA8) F_(0, 0) FM(CTS4_N) FM(D11) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IP6_23_20 FM(VI1_DATA9) F_(0, 0) FM(RTS4_N) FM(D12) FM(MMC_D6) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IP6_27_24 FM(VI1_DATA10) F_(0, 0) F_(0, 0) FM(D13) FM(MMC_D7) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IP6_31_28 FM(VI1_DATA11) FM(SCL4) FM(IRQ4) FM(D14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IP7_3_0 FM(VI1_FIELD) FM(SDA4) FM(IRQ5) FM(D15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IP7_7_4 FM(SCL0) FM(DU_DR0) FM(TPU0TO0) FM(CLKOUT) F_(0, 0) FM(MSIOF0_RXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IP7_11_8 FM(SDA0) FM(DU_DR1) FM(TPU0TO1) FM(BS_N) FM(SCK0) FM(MSIOF0_TXD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IP7_15_12 FM(SCL1) FM(DU_DG0) FM(TPU0TO2) FM(RD_N) FM(CTS0_N) FM(MSIOF0_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IP7_19_16 FM(SDA1) FM(DU_DG1) FM(TPU0TO3) FM(WE0_N) FM(RTS0_N) FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IP7_23_20 FM(SCL2) FM(DU_DB0) FM(TCLK1_A) FM(WE1_N) FM(RX0) FM(MSIOF0_SS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IP7_27_24 FM(SDA2) FM(DU_DB1) FM(TCLK2_A) FM(EX_WAIT0) FM(TX0) FM(MSIOF0_SS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IP7_31_28 FM(AVB0_AVTP_CAPTURE) F_(0, 0) F_(0, 0) F_(0, 0) FM(FSCLKST2_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IP8_3_0 FM(CANFD0_TX_A) FM(FXR_TXDA) FM(PWM0_B) FM(DU_DISP) FM(FSCLKST2_N_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IP8_7_4 FM(CANFD0_RX_A) FM(RXDA_EXTFXR) FM(PWM1_B) FM(DU_CDE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IP8_11_8 FM(CANFD1_TX) FM(FXR_TXDB) FM(PWM2_B) FM(TCLK1_B) FM(TX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IP8_15_12 FM(CANFD1_RX) FM(RXDB_EXTFXR) FM(PWM3_B) FM(TCLK2_B) FM(RX1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IP8_19_16 FM(CANFD_CLK_A) FM(CLK_EXTFXR) FM(PWM4_B) FM(SPEEDIN_B) FM(SCIF_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IP8_23_20 FM(DIGRF_CLKIN) FM(DIGRF_CLKEN_IN) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IP8_27_24 FM(DIGRF_CLKOUT) FM(DIGRF_CLKEN_OUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IP8_31_28 F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define PINMUX_GPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) GPSR1_27 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) GPSR1_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) GPSR1_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) GPSR1_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) GPSR1_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) GPSR1_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) GPSR0_21 GPSR1_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) GPSR0_20 GPSR1_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) GPSR0_19 GPSR1_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) GPSR0_18 GPSR1_18 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) GPSR0_17 GPSR1_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GPSR0_16 GPSR1_16 GPSR2_16 GPSR3_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GPSR0_15 GPSR1_15 GPSR2_15 GPSR3_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR5_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR5_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR5_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR5_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR5_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR5_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR5_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR5_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR5_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define PINMUX_IPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FM(IP8_3_0) IP8_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FM(IP8_7_4) IP8_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FM(IP8_11_8) IP8_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FM(IP8_15_12) IP8_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FM(IP8_19_16) IP8_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FM(IP8_23_20) IP8_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FM(IP8_27_24) IP8_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FM(IP8_31_28) IP8_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* MOD_SEL0 */ /* 0 */ /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MOD_SEL0_11 FM(SEL_I2C3_0) FM(SEL_I2C3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MOD_SEL0_10 FM(SEL_HSCIF0_0) FM(SEL_HSCIF0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MOD_SEL0_9 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MOD_SEL0_8 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MOD_SEL0_7 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MOD_SEL0_6 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MOD_SEL0_5 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MOD_SEL0_4 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MOD_SEL0_3 FM(SEL_PWM0_0) FM(SEL_PWM0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MOD_SEL0_2 FM(SEL_RFSO_0) FM(SEL_RFSO_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define MOD_SEL0_1 FM(SEL_RSP_0) FM(SEL_RSP_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MOD_SEL0_0 FM(SEL_TMU_0) FM(SEL_TMU_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PINMUX_MOD_SELS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) MOD_SEL0_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) MOD_SEL0_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MOD_SEL0_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MOD_SEL0_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MOD_SEL0_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MOD_SEL0_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) MOD_SEL0_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) MOD_SEL0_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MOD_SEL0_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MOD_SEL0_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MOD_SEL0_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MOD_SEL0_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define FM(x) x##_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINMUX_DATA_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINMUX_SINGLE(AVB0_RX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINMUX_SINGLE(AVB0_RXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINMUX_SINGLE(AVB0_RD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINMUX_SINGLE(AVB0_RD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINMUX_SINGLE(AVB0_RD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINMUX_SINGLE(AVB0_RD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINMUX_SINGLE(AVB0_TX_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINMUX_SINGLE(AVB0_TXC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINMUX_SINGLE(AVB0_TD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINMUX_SINGLE(AVB0_TD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINMUX_SINGLE(AVB0_TD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINMUX_SINGLE(AVB0_TD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINMUX_SINGLE(AVB0_TXCREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINMUX_SINGLE(AVB0_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINMUX_SINGLE(AVB0_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINMUX_SINGLE(AVB0_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINMUX_SINGLE(AVB0_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINMUX_SINGLE(AVB0_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINMUX_SINGLE(AVB0_AVTP_MATCH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINMUX_SINGLE(QSPI0_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINMUX_SINGLE(QSPI0_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINMUX_SINGLE(QSPI0_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINMUX_SINGLE(QSPI0_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINMUX_SINGLE(QSPI0_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINMUX_SINGLE(QSPI0_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINMUX_SINGLE(QSPI1_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINMUX_SINGLE(QSPI1_MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINMUX_SINGLE(QSPI1_MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINMUX_SINGLE(QSPI1_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINMUX_SINGLE(QSPI1_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINMUX_SINGLE(QSPI1_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINMUX_SINGLE(RPC_RESET_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINMUX_SINGLE(RPC_WP_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINMUX_SINGLE(RPC_INT_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINMUX_IPSR_GPSR(IP0_3_0, DU_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINMUX_IPSR_GPSR(IP0_3_0, HSCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINMUX_IPSR_GPSR(IP0_3_0, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINMUX_IPSR_GPSR(IP0_7_4, DU_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINMUX_IPSR_GPSR(IP0_7_4, HRTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINMUX_IPSR_GPSR(IP0_7_4, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINMUX_IPSR_GPSR(IP0_11_8, DU_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINMUX_IPSR_GPSR(IP0_11_8, HCTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINMUX_IPSR_GPSR(IP0_11_8, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINMUX_IPSR_GPSR(IP0_15_12, DU_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINMUX_IPSR_GPSR(IP0_15_12, HTX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINMUX_IPSR_GPSR(IP0_15_12, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINMUX_IPSR_GPSR(IP0_19_16, DU_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINMUX_IPSR_GPSR(IP0_19_16, MSIOF3_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINMUX_IPSR_GPSR(IP0_19_16, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINMUX_IPSR_GPSR(IP0_23_20, DU_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINMUX_IPSR_GPSR(IP0_23_20, MSIOF3_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINMUX_IPSR_GPSR(IP0_23_20, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINMUX_IPSR_GPSR(IP0_27_24, DU_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINMUX_IPSR_GPSR(IP0_27_24, MSIOF3_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINMUX_IPSR_GPSR(IP0_27_24, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINMUX_IPSR_GPSR(IP0_31_28, DU_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINMUX_IPSR_GPSR(IP0_31_28, MSIOF3_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINMUX_IPSR_GPSR(IP0_31_28, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINMUX_IPSR_GPSR(IP0_31_28, PWMFSW0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINMUX_IPSR_GPSR(IP1_3_0, DU_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINMUX_IPSR_GPSR(IP1_3_0, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINMUX_IPSR_MSEL(IP1_3_0, FSO_CFE_0_N_A, SEL_RFSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINMUX_IPSR_GPSR(IP1_7_4, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINMUX_IPSR_GPSR(IP1_11_8, DU_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINMUX_IPSR_GPSR(IP1_11_8, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINMUX_IPSR_MSEL(IP1_11_8, FSO_TOE_N_A, SEL_RFSO_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINMUX_IPSR_GPSR(IP1_15_12, DU_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINMUX_IPSR_GPSR(IP1_15_12, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINMUX_IPSR_GPSR(IP1_15_12, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINMUX_IPSR_GPSR(IP1_19_16, DU_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINMUX_IPSR_GPSR(IP1_19_16, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINMUX_IPSR_GPSR(IP1_19_16, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINMUX_IPSR_GPSR(IP1_23_20, DU_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINMUX_IPSR_GPSR(IP1_23_20, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINMUX_IPSR_GPSR(IP1_23_20, FXR_CLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINMUX_IPSR_GPSR(IP1_27_24, DU_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINMUX_IPSR_GPSR(IP1_27_24, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINMUX_IPSR_GPSR(IP1_27_24, FXR_CLKOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINMUX_IPSR_GPSR(IP1_31_28, DU_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINMUX_IPSR_GPSR(IP1_31_28, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINMUX_IPSR_GPSR(IP1_31_28, FXR_TXENA_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINMUX_IPSR_GPSR(IP2_3_0, DU_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINMUX_IPSR_GPSR(IP2_3_0, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINMUX_IPSR_GPSR(IP2_3_0, FXR_TXENB_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINMUX_IPSR_GPSR(IP2_7_4, DU_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINMUX_IPSR_GPSR(IP2_7_4, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINMUX_IPSR_GPSR(IP2_11_8, DU_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINMUX_IPSR_MSEL(IP2_11_8, SCIF_CLK_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINMUX_IPSR_GPSR(IP2_11_8, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINMUX_IPSR_GPSR(IP2_15_12, DU_EXHSYNC_DU_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINMUX_IPSR_GPSR(IP2_15_12, HRX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_IPSR_GPSR(IP2_15_12, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINMUX_IPSR_GPSR(IP2_15_12, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINMUX_IPSR_GPSR(IP2_19_16, DU_EXVSYNC_DU_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINMUX_IPSR_GPSR(IP2_19_16, MSIOF3_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_IPSR_GPSR(IP2_23_20, DU_EXODDF_DU_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINMUX_IPSR_GPSR(IP2_23_20, MSIOF3_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINMUX_IPSR_GPSR(IP2_27_24, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINMUX_IPSR_GPSR(IP2_31_28, VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINMUX_IPSR_GPSR(IP2_31_28, MSIOF2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINMUX_IPSR_GPSR(IP2_31_28, SCK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINMUX_IPSR_GPSR(IP2_31_28, HSCK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_IPSR_GPSR(IP3_3_0, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINMUX_IPSR_GPSR(IP3_3_0, RX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINMUX_IPSR_GPSR(IP3_3_0, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINMUX_IPSR_GPSR(IP3_3_0, HCTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINMUX_IPSR_GPSR(IP3_7_4, TX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINMUX_IPSR_GPSR(IP3_11_8, VI0_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINMUX_IPSR_GPSR(IP3_11_8, CTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINMUX_IPSR_GPSR(IP3_11_8, HTX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINMUX_IPSR_GPSR(IP3_15_12, VI0_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINMUX_IPSR_GPSR(IP3_15_12, MSIOF2_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINMUX_IPSR_GPSR(IP3_15_12, RTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINMUX_IPSR_GPSR(IP3_15_12, HRX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINMUX_IPSR_GPSR(IP3_19_16, VI0_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINMUX_IPSR_GPSR(IP3_19_16, MSIOF2_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINMUX_IPSR_GPSR(IP3_19_16, SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINMUX_IPSR_MSEL(IP3_19_16, SPEEDIN_A, SEL_RSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINMUX_IPSR_GPSR(IP3_23_20, VI0_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINMUX_IPSR_GPSR(IP3_23_20, AVB0_AVTP_PPS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINMUX_IPSR_MSEL(IP3_23_20, SDA3_A, SEL_I2C3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINMUX_IPSR_GPSR(IP3_27_24, VI0_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINMUX_IPSR_GPSR(IP3_27_24, HSCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINMUX_IPSR_MSEL(IP3_27_24, SCL3_A, SEL_I2C3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINMUX_IPSR_GPSR(IP3_31_28, VI0_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINMUX_IPSR_GPSR(IP3_31_28, HRTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINMUX_IPSR_MSEL(IP3_31_28, RX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINMUX_IPSR_GPSR(IP4_3_0, VI0_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINMUX_IPSR_GPSR(IP4_3_0, HCTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINMUX_IPSR_MSEL(IP4_3_0, TX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINMUX_IPSR_GPSR(IP4_7_4, VI0_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_IPSR_GPSR(IP4_7_4, HTX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINMUX_IPSR_GPSR(IP4_7_4, CTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINMUX_IPSR_GPSR(IP4_11_8, VI0_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINMUX_IPSR_GPSR(IP4_11_8, HRX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINMUX_IPSR_GPSR(IP4_11_8, RTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINMUX_IPSR_GPSR(IP4_15_12, VI0_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_IPSR_GPSR(IP4_15_12, HSCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_IPSR_MSEL(IP4_15_12, PWM0_A, SEL_PWM0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_IPSR_GPSR(IP4_19_16, VI0_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_IPSR_GPSR(IP4_19_16, HCTS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINMUX_IPSR_MSEL(IP4_19_16, PWM1_A, SEL_PWM1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_IPSR_MSEL(IP4_19_16, FSO_CFE_0_N_B, SEL_RFSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINMUX_IPSR_GPSR(IP4_23_20, VI0_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINMUX_IPSR_GPSR(IP4_23_20, HRTS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINMUX_IPSR_MSEL(IP4_23_20, PWM2_A, SEL_PWM2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_IPSR_MSEL(IP4_23_20, FSO_CFE_1_N_B, SEL_RFSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_IPSR_GPSR(IP4_27_24, VI0_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_IPSR_GPSR(IP4_27_24, HTX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINMUX_IPSR_MSEL(IP4_27_24, PWM3_A, SEL_PWM3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_IPSR_MSEL(IP4_27_24, FSO_TOE_N_B, SEL_RFSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_IPSR_GPSR(IP4_31_28, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINMUX_IPSR_GPSR(IP4_31_28, HRX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINMUX_IPSR_MSEL(IP4_31_28, PWM4_A, SEL_PWM4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_GPSR(IP4_31_28, CS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_IPSR_GPSR(IP4_31_28, FSCLKST2_N_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_IPSR_GPSR(IP5_3_0, VI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_IPSR_GPSR(IP5_3_0, MSIOF1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_GPSR(IP5_3_0, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINMUX_IPSR_GPSR(IP5_7_4, VI1_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_IPSR_GPSR(IP5_7_4, MSIOF1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_IPSR_GPSR(IP5_7_4, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_IPSR_GPSR(IP5_11_8, VI1_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINMUX_IPSR_GPSR(IP5_11_8, MSIOF1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_IPSR_GPSR(IP5_11_8, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_IPSR_GPSR(IP5_15_12, VI1_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_GPSR(IP5_15_12, MSIOF1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_GPSR(IP5_15_12, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_GPSR(IP5_19_16, VI1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_IPSR_GPSR(IP5_19_16, MSIOF1_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_IPSR_GPSR(IP5_19_16, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_IPSR_GPSR(IP5_23_20, VI1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_IPSR_GPSR(IP5_23_20, MSIOF1_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_IPSR_GPSR(IP5_23_20, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_IPSR_GPSR(IP5_23_20, MMC_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_IPSR_GPSR(IP5_27_24, VI1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_IPSR_MSEL(IP5_27_24, CANFD0_TX_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_IPSR_GPSR(IP5_27_24, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_IPSR_GPSR(IP5_27_24, MMC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_GPSR(IP5_31_28, VI1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_IPSR_MSEL(IP5_31_28, CANFD0_RX_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINMUX_IPSR_GPSR(IP5_31_28, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_GPSR(IP5_31_28, MMC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_IPSR_GPSR(IP6_3_0, VI1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_IPSR_MSEL(IP6_3_0, CANFD_CLK_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_IPSR_GPSR(IP6_3_0, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_IPSR_GPSR(IP6_3_0, MMC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_IPSR_GPSR(IP6_7_4, VI1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_IPSR_GPSR(IP6_7_4, SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_IPSR_GPSR(IP6_7_4, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_GPSR(IP6_7_4, MMC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINMUX_IPSR_GPSR(IP6_11_8, VI1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_IPSR_GPSR(IP6_11_8, RX4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_GPSR(IP6_11_8, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_GPSR(IP6_11_8, MMC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_IPSR_GPSR(IP6_15_12, VI1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_IPSR_GPSR(IP6_15_12, TX4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR_GPSR(IP6_15_12, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_GPSR(IP6_15_12, MMC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_GPSR(IP6_19_16, VI1_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_IPSR_GPSR(IP6_19_16, CTS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_IPSR_GPSR(IP6_19_16, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_IPSR_GPSR(IP6_19_16, MMC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_GPSR(IP6_23_20, VI1_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_IPSR_GPSR(IP6_23_20, RTS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_GPSR(IP6_23_20, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINMUX_IPSR_GPSR(IP6_23_20, MMC_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_MSEL(IP6_23_20, SCL3_B, SEL_I2C3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_IPSR_GPSR(IP6_27_24, VI1_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_IPSR_GPSR(IP6_27_24, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_GPSR(IP6_27_24, MMC_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_IPSR_MSEL(IP6_27_24, SDA3_B, SEL_I2C3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_IPSR_GPSR(IP6_31_28, VI1_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_GPSR(IP6_31_28, SCL4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_IPSR_GPSR(IP6_31_28, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_IPSR_GPSR(IP6_31_28, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_IPSR_GPSR(IP7_3_0, VI1_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_IPSR_GPSR(IP7_3_0, SDA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_IPSR_GPSR(IP7_3_0, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_GPSR(IP7_3_0, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_GPSR(IP7_7_4, SCL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINMUX_IPSR_GPSR(IP7_7_4, DU_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_GPSR(IP7_7_4, TPU0TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_GPSR(IP7_7_4, CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_IPSR_GPSR(IP7_7_4, MSIOF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_GPSR(IP7_11_8, SDA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_GPSR(IP7_11_8, DU_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_GPSR(IP7_11_8, TPU0TO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_IPSR_GPSR(IP7_11_8, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_GPSR(IP7_11_8, SCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_GPSR(IP7_11_8, MSIOF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_IPSR_GPSR(IP7_15_12, SCL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_IPSR_GPSR(IP7_15_12, DU_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_GPSR(IP7_15_12, TPU0TO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_GPSR(IP7_15_12, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_IPSR_GPSR(IP7_15_12, CTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_GPSR(IP7_15_12, MSIOF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_GPSR(IP7_19_16, SDA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINMUX_IPSR_GPSR(IP7_19_16, DU_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_GPSR(IP7_19_16, TPU0TO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_GPSR(IP7_19_16, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_IPSR_GPSR(IP7_19_16, RTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_GPSR(IP7_19_16, MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_GPSR(IP7_23_20, SCL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP7_23_20, DU_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_MSEL(IP7_23_20, TCLK1_A, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_IPSR_GPSR(IP7_23_20, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_GPSR(IP7_23_20, RX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_GPSR(IP7_23_20, MSIOF0_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP7_27_24, SDA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_GPSR(IP7_27_24, DU_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_IPSR_MSEL(IP7_27_24, TCLK2_A, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_GPSR(IP7_27_24, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_GPSR(IP7_27_24, TX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_IPSR_GPSR(IP7_27_24, MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_IPSR_GPSR(IP7_31_28, AVB0_AVTP_CAPTURE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_GPSR(IP7_31_28, FSCLKST2_N_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_MSEL(IP8_3_0, CANFD0_TX_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_IPSR_GPSR(IP8_3_0, FXR_TXDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_IPSR_MSEL(IP8_3_0, PWM0_B, SEL_PWM0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_GPSR(IP8_3_0, DU_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_GPSR(IP8_3_0, FSCLKST2_N_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_MSEL(IP8_7_4, CANFD0_RX_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_IPSR_GPSR(IP8_7_4, RXDA_EXTFXR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_MSEL(IP8_7_4, PWM1_B, SEL_PWM1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_GPSR(IP8_7_4, DU_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_IPSR_GPSR(IP8_11_8, CANFD1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_GPSR(IP8_11_8, FXR_TXDB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_MSEL(IP8_11_8, PWM2_B, SEL_PWM2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_MSEL(IP8_11_8, TCLK1_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_MSEL(IP8_11_8, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_GPSR(IP8_15_12, CANFD1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_GPSR(IP8_15_12, RXDB_EXTFXR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_MSEL(IP8_15_12, PWM3_B, SEL_PWM3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_MSEL(IP8_15_12, TCLK2_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_IPSR_MSEL(IP8_15_12, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_IPSR_MSEL(IP8_19_16, CANFD_CLK_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP8_19_16, CLK_EXTFXR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_MSEL(IP8_19_16, PWM4_B, SEL_PWM4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_MSEL(IP8_19_16, SPEEDIN_B, SEL_RSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_IPSR_MSEL(IP8_19_16, SCIF_CLK_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_GPSR(IP8_23_20, DIGRF_CLKEN_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_IPSR_GPSR(IP8_27_24, DIGRF_CLKEN_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* - AVB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const unsigned int avb0_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* AVB0_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const unsigned int avb0_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) AVB0_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const unsigned int avb0_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* AVB0_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const unsigned int avb0_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) AVB0_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const unsigned int avb0_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* AVB0_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const unsigned int avb0_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) AVB0_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const unsigned int avb0_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* AVB0_MDC, AVB0_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const unsigned int avb0_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) AVB0_MDC_MARK, AVB0_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const unsigned int avb0_rgmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, AVB0_TD1, AVB0_TD2, AVB0_TD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, AVB0_RD1, AVB0_RD2, AVB0_RD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const unsigned int avb0_rgmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) AVB0_TX_CTL_MARK, AVB0_TXC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) AVB0_TD0_MARK, AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) AVB0_RX_CTL_MARK, AVB0_RXC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) AVB0_RD0_MARK, AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const unsigned int avb0_txcrefclk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* AVB0_TXCREFCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const unsigned int avb0_txcrefclk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) AVB0_TXCREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const unsigned int avb0_avtp_pps_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* AVB0_AVTP_PPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const unsigned int avb0_avtp_pps_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) AVB0_AVTP_PPS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const unsigned int avb0_avtp_capture_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* AVB0_AVTP_CAPTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const unsigned int avb0_avtp_capture_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) AVB0_AVTP_CAPTURE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const unsigned int avb0_avtp_match_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* AVB0_AVTP_MATCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const unsigned int avb0_avtp_match_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) AVB0_AVTP_MATCH_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* - CANFD Clock ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const unsigned int canfd_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* CANFD_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const unsigned int canfd_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) CANFD_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const unsigned int canfd_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* CANFD_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const unsigned int canfd_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) CANFD_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* - CANFD0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const unsigned int canfd0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const unsigned int canfd0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const unsigned int canfd0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const unsigned int canfd0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* - CANFD1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const unsigned int canfd1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const unsigned int canfd1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) CANFD1_TX_MARK, CANFD1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 16), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) DU_DR4_MARK, DU_DR3_MARK, DU_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) DU_DG4_MARK, DU_DG3_MARK, DU_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DU_DB4_MARK, DU_DB3_MARK, DU_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const unsigned int du_clk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* DOTCLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const unsigned int du_clk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) DU_DOTCLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const unsigned int du_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const unsigned int du_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const unsigned int du_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* EXODDF/ODDF/DISP/CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const unsigned int du_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) DU_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const unsigned int du_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const unsigned int du_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) DU_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const unsigned int hscif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* HRX, HTX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const unsigned int hscif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) HRX0_MARK, HTX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const unsigned int hscif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* HSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const unsigned int hscif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) HSCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const unsigned int hscif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* HRTS#, HCTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const unsigned int hscif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) HRTS0_N_MARK, HCTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const unsigned int hscif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* HRX, HTX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const unsigned int hscif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) HRX1_MARK, HTX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const unsigned int hscif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* HSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const unsigned int hscif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) HSCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const unsigned int hscif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* HRTS#, HCTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const unsigned int hscif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) HRTS1_N_MARK, HCTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* - HSCIF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const unsigned int hscif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* HRX, HTX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const unsigned int hscif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) HRX2_MARK, HTX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const unsigned int hscif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* HSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const unsigned int hscif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) HSCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const unsigned int hscif2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* HRTS#, HCTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned int hscif2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) HRTS2_N_MARK, HCTS2_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) /* - HSCIF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const unsigned int hscif3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* HRX, HTX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const unsigned int hscif3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) HRX3_MARK, HTX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const unsigned int hscif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* HSCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const unsigned int hscif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) HSCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const unsigned int hscif3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* HRTS#, HCTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const unsigned int hscif3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) HRTS3_N_MARK, HCTS3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* - I2C0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) SDA0_MARK, SCL0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* - I2C1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static const unsigned int i2c1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static const unsigned int i2c1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) SDA1_MARK, SCL1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static const unsigned int i2c2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static const unsigned int i2c2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) SDA2_MARK, SCL2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const unsigned int i2c3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static const unsigned int i2c3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) SDA3_A_MARK, SCL3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static const unsigned int i2c3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const unsigned int i2c3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) SDA3_B_MARK, SCL3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* - I2C4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const unsigned int i2c4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const unsigned int i2c4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) SDA4_MARK, SCL4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* - INTC-EX ---------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static const unsigned int intc_ex_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const unsigned int intc_ex_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const unsigned int intc_ex_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const unsigned int intc_ex_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const unsigned int intc_ex_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const unsigned int intc_ex_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static const unsigned int intc_ex_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static const unsigned int intc_ex_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const unsigned int intc_ex_irq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static const unsigned int intc_ex_irq4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) IRQ4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const unsigned int intc_ex_irq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const unsigned int intc_ex_irq5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) IRQ5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) /* - MMC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static const unsigned int mmc_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static const unsigned int mmc_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) MMC_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const unsigned int mmc_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const unsigned int mmc_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MMC_D0_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static const unsigned int mmc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const unsigned int mmc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) MMC_D0_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) MMC_D4_MARK, MMC_D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) MMC_D6_MARK, MMC_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const unsigned int mmc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static const unsigned int mmc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) MMC_CLK_MARK, MMC_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static const unsigned int msiof0_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const unsigned int msiof0_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const unsigned int msiof0_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const unsigned int msiof0_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const unsigned int msiof1_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const unsigned int msiof1_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static const unsigned int msiof1_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static const unsigned int msiof1_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static const unsigned int msiof2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const unsigned int msiof2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const unsigned int msiof2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static const unsigned int msiof2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) MSIOF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static const unsigned int msiof2_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static const unsigned int msiof2_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const unsigned int msiof2_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const unsigned int msiof2_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static const unsigned int msiof2_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static const unsigned int msiof2_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static const unsigned int msiof2_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static const unsigned int msiof2_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* - MSIOF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static const unsigned int msiof3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const unsigned int msiof3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) MSIOF3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const unsigned int msiof3_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static const unsigned int msiof3_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) MSIOF3_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const unsigned int msiof3_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const unsigned int msiof3_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) MSIOF3_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const unsigned int msiof3_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const unsigned int msiof3_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) MSIOF3_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static const unsigned int msiof3_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static const unsigned int msiof3_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) MSIOF3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const unsigned int msiof3_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const unsigned int msiof3_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MSIOF3_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* - PWM0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static const unsigned int pwm0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const unsigned int pwm0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PWM0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* - PWM1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const unsigned int pwm1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static const unsigned int pwm1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PWM1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* - PWM2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static const unsigned int pwm2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const unsigned int pwm2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) PWM2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* - PWM3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static const unsigned int pwm3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const unsigned int pwm3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PWM3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static const unsigned int pwm3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const unsigned int pwm3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) /* - PWM4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static const unsigned int pwm4_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static const unsigned int pwm4_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PWM4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static const unsigned int pwm4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static const unsigned int pwm4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* - QSPI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static const unsigned int qspi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const unsigned int qspi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static const unsigned int qspi0_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const unsigned int qspi0_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static const unsigned int qspi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const unsigned int qspi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) QSPI0_IO2_MARK, QSPI0_IO3_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* - QSPI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const unsigned int qspi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static const unsigned int qspi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static const unsigned int qspi1_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const unsigned int qspi1_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static const unsigned int qspi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static const unsigned int qspi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) QSPI1_IO2_MARK, QSPI1_IO3_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) /* - RPC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const unsigned int rpc_clk1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Octal-SPI flash: C/SCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static const unsigned int rpc_clk1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) QSPI0_SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const unsigned int rpc_clk2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* HyperFlash: CK, CK# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const unsigned int rpc_clk2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static const unsigned int rpc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* Octal-SPI flash: S#/CS, DQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* HyperFlash: CS#, RDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static const unsigned int rpc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) QSPI0_SSL_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static const unsigned int rpc_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* DQ[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const unsigned int rpc_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) QSPI0_IO2_MARK, QSPI0_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) QSPI1_IO2_MARK, QSPI1_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static const unsigned int rpc_reset_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) /* RPC_RESET# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const unsigned int rpc_reset_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) RPC_RESET_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static const unsigned int rpc_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) /* RPC_INT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const unsigned int rpc_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) RPC_INT_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const unsigned int rpc_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) /* RPC_WP# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static const unsigned int rpc_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) RPC_WP_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const unsigned int scif_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const unsigned int scif_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) SCIF_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static const unsigned int scif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const unsigned int scif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) RX0_MARK, TX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static const unsigned int scif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static const unsigned int scif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) SCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const unsigned int scif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* RTS#, CTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const unsigned int scif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) RTS0_N_MARK, CTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static const unsigned int scif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const unsigned int scif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) RX1_A_MARK, TX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const unsigned int scif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static const unsigned int scif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) SCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static const unsigned int scif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* RTS#, CTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const unsigned int scif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) RTS1_N_MARK, CTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static const unsigned int scif3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static const unsigned int scif3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) RX3_MARK, TX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int scif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static const unsigned int scif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) SCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static const unsigned int scif3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* RTS#, CTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const unsigned int scif3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) RTS3_N_MARK, CTS3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static const unsigned int scif4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static const unsigned int scif4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) RX4_MARK, TX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static const unsigned int scif4_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static const unsigned int scif4_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) SCK4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) static const unsigned int scif4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) /* RTS#, CTS# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) static const unsigned int scif4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) RTS4_N_MARK, CTS4_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) /* - TMU -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) static const unsigned int tmu_tclk1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* TCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static const unsigned int tmu_tclk1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) TCLK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) static const unsigned int tmu_tclk1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* TCLK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static const unsigned int tmu_tclk1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static const unsigned int tmu_tclk2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* TCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static const unsigned int tmu_tclk2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) TCLK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const unsigned int tmu_tclk2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* TCLK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static const unsigned int tmu_tclk2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) TCLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static const union vin_data12 vin0_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) static const union vin_data12 vin0_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) VI0_DATA0_MARK, VI0_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) VI0_DATA2_MARK, VI0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) VI0_DATA4_MARK, VI0_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) VI0_DATA6_MARK, VI0_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) VI0_DATA8_MARK, VI0_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) VI0_DATA10_MARK, VI0_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static const unsigned int vin0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) /* HSYNC#, VSYNC# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) static const unsigned int vin0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) VI0_HSYNC_N_MARK, VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static const unsigned int vin0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) /* FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static const unsigned int vin0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static const unsigned int vin0_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* CLKENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) static const unsigned int vin0_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static const unsigned int vin0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static const unsigned int vin0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* - VIN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static const union vin_data12 vin1_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static const union vin_data12 vin1_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) VI1_DATA0_MARK, VI1_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) VI1_DATA2_MARK, VI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) VI1_DATA4_MARK, VI1_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) VI1_DATA6_MARK, VI1_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) VI1_DATA8_MARK, VI1_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) VI1_DATA10_MARK, VI1_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static const unsigned int vin1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* HSYNC#, VSYNC# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static const unsigned int vin1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) VI1_HSYNC_N_MARK, VI1_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const unsigned int vin1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const unsigned int vin1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int vin1_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static const unsigned int vin1_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* CLKENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const unsigned int vin1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static const unsigned int vin1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) SH_PFC_PIN_GROUP(avb0_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) SH_PFC_PIN_GROUP(avb0_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) SH_PFC_PIN_GROUP(avb0_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) SH_PFC_PIN_GROUP(avb0_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) SH_PFC_PIN_GROUP(avb0_rgmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) SH_PFC_PIN_GROUP(avb0_txcrefclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) SH_PFC_PIN_GROUP(avb0_avtp_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) SH_PFC_PIN_GROUP(avb0_avtp_capture),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) SH_PFC_PIN_GROUP(avb0_avtp_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) SH_PFC_PIN_GROUP(canfd_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) SH_PFC_PIN_GROUP(canfd_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) SH_PFC_PIN_GROUP(canfd0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) SH_PFC_PIN_GROUP(canfd0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) SH_PFC_PIN_GROUP(canfd1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) SH_PFC_PIN_GROUP(du_clk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) SH_PFC_PIN_GROUP(du_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) SH_PFC_PIN_GROUP(du_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) SH_PFC_PIN_GROUP(du_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) SH_PFC_PIN_GROUP(hscif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) SH_PFC_PIN_GROUP(hscif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) SH_PFC_PIN_GROUP(hscif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) SH_PFC_PIN_GROUP(hscif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) SH_PFC_PIN_GROUP(hscif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) SH_PFC_PIN_GROUP(hscif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) SH_PFC_PIN_GROUP(hscif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) SH_PFC_PIN_GROUP(hscif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) SH_PFC_PIN_GROUP(hscif2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) SH_PFC_PIN_GROUP(hscif3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SH_PFC_PIN_GROUP(hscif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) SH_PFC_PIN_GROUP(hscif3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) SH_PFC_PIN_GROUP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) SH_PFC_PIN_GROUP(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) SH_PFC_PIN_GROUP(i2c3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) SH_PFC_PIN_GROUP(i2c3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SH_PFC_PIN_GROUP(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) SH_PFC_PIN_GROUP(intc_ex_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SH_PFC_PIN_GROUP(intc_ex_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SH_PFC_PIN_GROUP(intc_ex_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SH_PFC_PIN_GROUP(intc_ex_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) SH_PFC_PIN_GROUP(intc_ex_irq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) SH_PFC_PIN_GROUP(intc_ex_irq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) SH_PFC_PIN_GROUP(msiof0_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) SH_PFC_PIN_GROUP(msiof0_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) SH_PFC_PIN_GROUP(msiof1_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) SH_PFC_PIN_GROUP(msiof1_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) SH_PFC_PIN_GROUP(msiof2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) SH_PFC_PIN_GROUP(msiof2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) SH_PFC_PIN_GROUP(msiof2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) SH_PFC_PIN_GROUP(msiof2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) SH_PFC_PIN_GROUP(msiof2_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SH_PFC_PIN_GROUP(msiof2_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SH_PFC_PIN_GROUP(msiof3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) SH_PFC_PIN_GROUP(msiof3_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) SH_PFC_PIN_GROUP(msiof3_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) SH_PFC_PIN_GROUP(msiof3_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) SH_PFC_PIN_GROUP(msiof3_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SH_PFC_PIN_GROUP(msiof3_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) SH_PFC_PIN_GROUP(pwm0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SH_PFC_PIN_GROUP(pwm1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) SH_PFC_PIN_GROUP(pwm2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) SH_PFC_PIN_GROUP(pwm3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) SH_PFC_PIN_GROUP(pwm3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) SH_PFC_PIN_GROUP(pwm4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) SH_PFC_PIN_GROUP(pwm4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) SH_PFC_PIN_GROUP(qspi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) SH_PFC_PIN_GROUP(qspi0_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) SH_PFC_PIN_GROUP(qspi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) SH_PFC_PIN_GROUP(qspi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) SH_PFC_PIN_GROUP(qspi1_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) SH_PFC_PIN_GROUP(qspi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) SH_PFC_PIN_GROUP(rpc_clk1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) SH_PFC_PIN_GROUP(rpc_clk2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) SH_PFC_PIN_GROUP(rpc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) SH_PFC_PIN_GROUP(rpc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) SH_PFC_PIN_GROUP(rpc_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SH_PFC_PIN_GROUP(rpc_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) SH_PFC_PIN_GROUP(rpc_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SH_PFC_PIN_GROUP(scif_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) SH_PFC_PIN_GROUP(scif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) SH_PFC_PIN_GROUP(scif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) SH_PFC_PIN_GROUP(scif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SH_PFC_PIN_GROUP(scif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SH_PFC_PIN_GROUP(scif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) SH_PFC_PIN_GROUP(scif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) SH_PFC_PIN_GROUP(scif3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) SH_PFC_PIN_GROUP(scif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) SH_PFC_PIN_GROUP(scif3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) SH_PFC_PIN_GROUP(scif4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) SH_PFC_PIN_GROUP(scif4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) SH_PFC_PIN_GROUP(scif4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) SH_PFC_PIN_GROUP(tmu_tclk1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SH_PFC_PIN_GROUP(tmu_tclk1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SH_PFC_PIN_GROUP(tmu_tclk2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SH_PFC_PIN_GROUP(tmu_tclk2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) VIN_DATA_PIN_GROUP(vin0_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) VIN_DATA_PIN_GROUP(vin0_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) VIN_DATA_PIN_GROUP(vin0_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) SH_PFC_PIN_GROUP(vin0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) SH_PFC_PIN_GROUP(vin0_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) VIN_DATA_PIN_GROUP(vin1_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) VIN_DATA_PIN_GROUP(vin1_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) VIN_DATA_PIN_GROUP(vin1_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SH_PFC_PIN_GROUP(vin1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) SH_PFC_PIN_GROUP(vin1_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static const char * const avb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "avb0_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "avb0_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "avb0_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) "avb0_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) "avb0_rgmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) "avb0_txcrefclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) "avb0_avtp_pps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) "avb0_avtp_capture",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) "avb0_avtp_match",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) static const char * const canfd_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) "canfd_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) "canfd_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static const char * const canfd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "canfd0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) "canfd0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const char * const canfd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "canfd1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) "du_clk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) "du_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "du_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "du_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) "hscif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) "hscif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) "hscif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) "hscif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) "hscif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) "hscif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static const char * const hscif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) "hscif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "hscif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) "hscif2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static const char * const hscif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) "hscif3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) "hscif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) "hscif3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "i2c3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) "i2c3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static const char * const intc_ex_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "intc_ex_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "intc_ex_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) "intc_ex_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) "intc_ex_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) "intc_ex_irq4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) "intc_ex_irq5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) "msiof0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) "msiof0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) "msiof1_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) "msiof1_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) "msiof2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) "msiof2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) "msiof2_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) "msiof2_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "msiof2_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "msiof2_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) "msiof3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) "msiof3_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) "msiof3_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) "msiof3_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) "msiof3_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) "msiof3_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) "pwm0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) "pwm1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) "pwm2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) "pwm3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) "pwm3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "pwm4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) "pwm4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static const char * const qspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) "qspi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) "qspi0_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) "qspi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static const char * const qspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) "qspi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) "qspi1_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) "qspi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static const char * const rpc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) "rpc_clk1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) "rpc_clk2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) "rpc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) "rpc_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) "rpc_reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) "rpc_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) "rpc_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "scif_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) "scif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) "scif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) "scif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) "scif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) "scif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) "scif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) "scif3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) "scif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) "scif3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) "scif4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "scif4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) "scif4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static const char * const tmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) "tmu_tclk1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) "tmu_tclk1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) "tmu_tclk2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) "tmu_tclk2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) "vin0_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) "vin0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) "vin0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) "vin0_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) "vin1_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) "vin1_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) "vin1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) "vin1_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) SH_PFC_FUNCTION(avb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) SH_PFC_FUNCTION(canfd_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) SH_PFC_FUNCTION(canfd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) SH_PFC_FUNCTION(canfd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) SH_PFC_FUNCTION(hscif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) SH_PFC_FUNCTION(hscif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) SH_PFC_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) SH_PFC_FUNCTION(intc_ex),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) SH_PFC_FUNCTION(qspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) SH_PFC_FUNCTION(qspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) SH_PFC_FUNCTION(rpc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) SH_PFC_FUNCTION(tmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #define F_(x, y) FN_##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define FM(x) FN_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) GP_0_21_FN, GPSR0_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) GP_0_20_FN, GPSR0_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) GP_0_19_FN, GPSR0_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) GP_0_18_FN, GPSR0_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) GP_0_17_FN, GPSR0_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) GP_0_16_FN, GPSR0_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) GP_0_15_FN, GPSR0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) GP_0_14_FN, GPSR0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) GP_0_13_FN, GPSR0_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) GP_0_12_FN, GPSR0_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) GP_0_11_FN, GPSR0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) GP_0_10_FN, GPSR0_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) GP_0_9_FN, GPSR0_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) GP_0_8_FN, GPSR0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) GP_0_7_FN, GPSR0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) GP_0_6_FN, GPSR0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) GP_0_5_FN, GPSR0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) GP_0_4_FN, GPSR0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) GP_0_3_FN, GPSR0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) GP_0_2_FN, GPSR0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) GP_0_1_FN, GPSR0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) GP_0_0_FN, GPSR0_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) GP_1_27_FN, GPSR1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) GP_1_26_FN, GPSR1_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) GP_1_25_FN, GPSR1_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) GP_1_24_FN, GPSR1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) GP_1_23_FN, GPSR1_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) GP_1_22_FN, GPSR1_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) GP_1_21_FN, GPSR1_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) GP_1_20_FN, GPSR1_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) GP_1_19_FN, GPSR1_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) GP_1_18_FN, GPSR1_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) GP_1_17_FN, GPSR1_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) GP_1_16_FN, GPSR1_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) GP_1_15_FN, GPSR1_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) GP_1_14_FN, GPSR1_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) GP_1_13_FN, GPSR1_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) GP_1_12_FN, GPSR1_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) GP_1_11_FN, GPSR1_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) GP_1_10_FN, GPSR1_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) GP_1_9_FN, GPSR1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) GP_1_8_FN, GPSR1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) GP_1_7_FN, GPSR1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) GP_1_6_FN, GPSR1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) GP_1_5_FN, GPSR1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) GP_1_4_FN, GPSR1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) GP_1_3_FN, GPSR1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) GP_1_2_FN, GPSR1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) GP_1_1_FN, GPSR1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) GP_1_0_FN, GPSR1_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) GP_2_16_FN, GPSR2_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) GP_2_15_FN, GPSR2_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) GP_2_14_FN, GPSR2_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) GP_2_13_FN, GPSR2_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) GP_2_12_FN, GPSR2_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) GP_2_11_FN, GPSR2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) GP_2_10_FN, GPSR2_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) GP_2_9_FN, GPSR2_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) GP_2_8_FN, GPSR2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) GP_2_7_FN, GPSR2_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) GP_2_6_FN, GPSR2_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) GP_2_5_FN, GPSR2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) GP_2_4_FN, GPSR2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) GP_2_3_FN, GPSR2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) GP_2_2_FN, GPSR2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) GP_2_1_FN, GPSR2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) GP_2_0_FN, GPSR2_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) GP_3_16_FN, GPSR3_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) GP_3_15_FN, GPSR3_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) GP_3_14_FN, GPSR3_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) GP_3_13_FN, GPSR3_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) GP_3_12_FN, GPSR3_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) GP_3_11_FN, GPSR3_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) GP_3_10_FN, GPSR3_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) GP_3_9_FN, GPSR3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) GP_3_8_FN, GPSR3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) GP_3_7_FN, GPSR3_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) GP_3_6_FN, GPSR3_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) GP_3_5_FN, GPSR3_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) GP_3_4_FN, GPSR3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) GP_3_3_FN, GPSR3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) GP_3_2_FN, GPSR3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) GP_3_1_FN, GPSR3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) GP_3_0_FN, GPSR3_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) GP_4_5_FN, GPSR4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) GP_4_4_FN, GPSR4_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) GP_4_3_FN, GPSR4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) GP_4_2_FN, GPSR4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) GP_4_1_FN, GPSR4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) GP_4_0_FN, GPSR4_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) GP_5_14_FN, GPSR5_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) GP_5_13_FN, GPSR5_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) GP_5_12_FN, GPSR5_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) GP_5_11_FN, GPSR5_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) GP_5_10_FN, GPSR5_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) GP_5_9_FN, GPSR5_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) GP_5_8_FN, GPSR5_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) GP_5_7_FN, GPSR5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) GP_5_6_FN, GPSR5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) GP_5_5_FN, GPSR5_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) GP_5_4_FN, GPSR5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) GP_5_3_FN, GPSR5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) GP_5_2_FN, GPSR5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) GP_5_1_FN, GPSR5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) GP_5_0_FN, GPSR5_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) IP0_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) IP0_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) IP0_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) IP0_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) IP0_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) IP0_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) IP0_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) IP0_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) IP1_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) IP1_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) IP1_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) IP1_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) IP1_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) IP1_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) IP1_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) IP1_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) IP2_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) IP2_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) IP2_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) IP2_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) IP2_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) IP2_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) IP2_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) IP2_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) IP3_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) IP3_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) IP3_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) IP3_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) IP3_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) IP3_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) IP3_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) IP3_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) IP4_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) IP4_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) IP4_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) IP4_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) IP4_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) IP4_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) IP4_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) IP4_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) IP5_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) IP5_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) IP5_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) IP5_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) IP5_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) IP5_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) IP5_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) IP5_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) IP6_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) IP6_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) IP6_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) IP6_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) IP6_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) IP6_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) IP6_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) IP6_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) IP7_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) IP7_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) IP7_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) IP7_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) IP7_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) IP7_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) IP7_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) IP7_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) IP8_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) IP8_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) IP8_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) IP8_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) IP8_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) IP8_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) IP8_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) IP8_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) GROUP(4, 4, 4, 4, 4, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) /* RESERVED 31, 30, 29, 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* RESERVED 27, 26, 25, 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) /* RESERVED 23, 22, 21, 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /* RESERVED 19, 18, 17, 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) /* RESERVED 15, 14, 13, 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) MOD_SEL0_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) MOD_SEL0_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) MOD_SEL0_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) MOD_SEL0_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) MOD_SEL0_7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) MOD_SEL0_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) MOD_SEL0_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) MOD_SEL0_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) MOD_SEL0_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) MOD_SEL0_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) MOD_SEL0_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) MOD_SEL0_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) enum ioctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) POCCTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) POCCTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) POCCTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) TDSELCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) [POCCTRL0] = { 0xe6060380 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) [POCCTRL1] = { 0xe6060384 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) [POCCTRL2] = { 0xe6060388 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) [TDSELCTRL] = { 0xe60603c0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static int r8a77970_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) int bit = pin & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) if (pin >= RCAR_GP_PIN(0, 0) && pin <= RCAR_GP_PIN(0, 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) if (pin >= RCAR_GP_PIN(2, 0) && pin <= RCAR_GP_PIN(2, 9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) return bit + 22;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) *pocctrl = pinmux_ioctrl_regs[POCCTRL1].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (pin >= RCAR_GP_PIN(2, 10) && pin <= RCAR_GP_PIN(2, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) return bit - 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) return bit + 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) static const struct sh_pfc_soc_operations pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .pin_to_pocctrl = r8a77970_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) const struct sh_pfc_soc_info r8a77970_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .name = "r8a77970_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .ops = &pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .ioctrl_regs = pinmux_ioctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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