^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A77950 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015-2017 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | SH_PFC_PIN_CFG_PULL_UP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_GP_CFG_28(1, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CPU_ALL_NOGP(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PIN_NOGP_CFG(ASEBRK, "ASEBRK", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PIN_NOGP_CFG(AVB_MDIO, "AVB_MDIO", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PIN_NOGP_CFG(AVB_RD0, "AVB_RD0", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PIN_NOGP_CFG(AVB_RD1, "AVB_RD1", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PIN_NOGP_CFG(AVB_RD2, "AVB_RD2", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PIN_NOGP_CFG(AVB_RD3, "AVB_RD3", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PIN_NOGP_CFG(AVB_RXC, "AVB_RXC", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PIN_NOGP_CFG(AVB_RX_CTL, "AVB_RX_CTL", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PIN_NOGP_CFG(AVB_TD0, "AVB_TD0", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PIN_NOGP_CFG(AVB_TD1, "AVB_TD1", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PIN_NOGP_CFG(AVB_TD2, "AVB_TD2", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PIN_NOGP_CFG(AVB_TD3, "AVB_TD3", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PIN_NOGP_CFG(AVB_TXC, "AVB_TXC", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PIN_NOGP_CFG(AVB_TXCREFCLK, "AVB_TXCREFCLK", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PIN_NOGP_CFG(AVB_TX_CTL, "AVB_TX_CTL", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PIN_NOGP_CFG(CLKOUT, "CLKOUT", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PIN_NOGP_CFG(DU_DOTCLKIN1, "DU_DOTCLKIN1", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PIN_NOGP_CFG(DU_DOTCLKIN2, "DU_DOTCLKIN2", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PIN_NOGP_CFG(DU_DOTCLKIN3, "DU_DOTCLKIN3", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PIN_NOGP_CFG(EXTALR, "EXTALR", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PIN_NOGP_CFG(QSPI0_IO2, "QSPI0_IO2", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PIN_NOGP_CFG(QSPI0_IO3, "QSPI0_IO3", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PIN_NOGP_CFG(QSPI0_MISO_IO1, "QSPI0_MISO_IO1", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PIN_NOGP_CFG(QSPI0_MOSI_IO0, "QSPI0_MOSI_IO0", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PIN_NOGP_CFG(QSPI0_SPCLK, "QSPI0_SPCLK", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PIN_NOGP_CFG(QSPI0_SSL, "QSPI0_SSL", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PIN_NOGP_CFG(QSPI1_IO2, "QSPI1_IO2", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PIN_NOGP_CFG(QSPI1_IO3, "QSPI1_IO3", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PIN_NOGP_CFG(QSPI1_MISO_IO1, "QSPI1_MISO_IO1", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PIN_NOGP_CFG(QSPI1_MOSI_IO0, "QSPI1_MOSI_IO0", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PIN_NOGP_CFG(QSPI1_SPCLK, "QSPI1_SPCLK", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PIN_NOGP_CFG(QSPI1_SSL, "QSPI1_SSL", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PIN_NOGP_CFG(RPC_INT_N, "RPC_INT#", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PIN_NOGP_CFG(RPC_RESET_N, "RPC_RESET#", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PIN_NOGP_CFG(RPC_WP_N, "RPC_WP#", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PIN_NOGP_CFG(TDO, "TDO", fn, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PIN_NOGP_CFG(TMS, "TMS", fn, CFG_FLAGS), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * F_() : just information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * FM() : macro for FN_xxx / xxx_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPSR0_15 F_(D15, IP7_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPSR0_14 F_(D14, IP7_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPSR0_13 F_(D13, IP7_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPSR0_12 F_(D12, IP6_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPSR0_11 F_(D11, IP6_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GPSR0_10 F_(D10, IP6_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GPSR0_9 F_(D9, IP6_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GPSR0_8 F_(D8, IP6_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GPSR0_7 F_(D7, IP6_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GPSR0_6 F_(D6, IP6_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GPSR0_5 F_(D5, IP6_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GPSR0_4 F_(D4, IP5_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GPSR0_3 F_(D3, IP5_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GPSR0_2 F_(D2, IP5_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GPSR0_1 F_(D1, IP5_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GPSR0_0 F_(D0, IP5_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPSR1_26 F_(WE1_N, IP5_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPSR1_25 F_(WE0_N, IP5_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPSR1_23 F_(RD_N, IP4_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPSR1_22 F_(BS_N, IP4_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GPSR1_20 F_(CS0_N, IP4_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPSR1_19 F_(A19, IP4_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GPSR1_18 F_(A18, IP4_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GPSR1_17 F_(A17, IP4_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GPSR1_16 F_(A16, IP3_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GPSR1_15 F_(A15, IP3_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GPSR1_14 F_(A14, IP3_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPSR1_13 F_(A13, IP3_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GPSR1_12 F_(A12, IP3_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GPSR1_11 F_(A11, IP3_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GPSR1_10 F_(A10, IP3_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GPSR1_9 F_(A9, IP3_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GPSR1_8 F_(A8, IP2_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GPSR1_7 F_(A7, IP2_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GPSR1_6 F_(A6, IP2_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GPSR1_5 F_(A5, IP2_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GPSR1_4 F_(A4, IP2_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GPSR1_3 F_(A3, IP2_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GPSR1_2 F_(A2, IP2_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GPSR1_1 F_(A1, IP2_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GPSR1_0 F_(A0, IP1_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GPSR2_8 F_(PWM2_A, IP1_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPSR2_7 F_(PWM1_A, IP1_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GPSR2_6 F_(PWM0, IP1_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GPSR2_5 F_(IRQ5, IP1_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GPSR2_4 F_(IRQ4, IP1_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GPSR2_3 F_(IRQ3, IP1_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GPSR2_2 F_(IRQ2, IP1_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GPSR2_1 F_(IRQ1, IP0_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GPSR2_0 F_(IRQ0, IP0_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GPSR3_15 F_(SD1_WP, IP10_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GPSR3_14 F_(SD1_CD, IP10_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GPSR3_13 F_(SD0_WP, IP10_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GPSR3_12 F_(SD0_CD, IP10_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GPSR4_17 FM(SD3_DS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GPSR4_12 FM(SD3_DAT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GPSR4_11 FM(SD3_DAT2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GPSR4_10 FM(SD3_DAT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GPSR4_9 FM(SD3_DAT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GPSR4_8 FM(SD3_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GPSR4_7 FM(SD3_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GPSR4_6 F_(SD2_DS, IP9_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GPSR4_1 FM(SD2_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GPSR5_22 FM(MSIOF0_RXD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define GPSR5_20 FM(MSIOF0_TXD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define GPSR5_17 FM(MSIOF0_SCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GPSR5_14 F_(HTX0, IP12_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GPSR5_13 F_(HRX0, IP12_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GPSR5_12 F_(HSCK0, IP12_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GPSR5_11 F_(RX2_A, IP12_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GPSR5_10 F_(TX2_A, IP12_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GPSR5_9 F_(SCK2, IP11_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GPSR5_8 F_(RTS1_N, IP11_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define GPSR5_7 F_(CTS1_N, IP11_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define GPSR5_6 F_(TX1_A, IP11_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define GPSR5_5 F_(RX1_A, IP11_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define GPSR5_4 F_(RTS0_N, IP11_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define GPSR5_3 F_(CTS0_N, IP11_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define GPSR5_2 F_(TX0, IP11_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define GPSR5_1 F_(RX0, IP10_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define GPSR5_0 F_(SCK0, IP10_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* GPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define GPSR6_13 FM(SSI_SDATA5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define GPSR6_12 FM(SSI_WS5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define GPSR6_11 FM(SSI_SCK5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define GPSR6_6 F_(SSI_WS349, IP14_15_12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define GPSR6_5 F_(SSI_SCK349, IP14_11_8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* GPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define GPSR7_3 FM(GP7_03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define GPSR7_2 FM(GP7_02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define GPSR7_1 FM(AVS2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define GPSR7_0 FM(AVS1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IP11_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IP11_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IP14_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IP14_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define PINMUX_GPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) GPSR6_31 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) GPSR6_30 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) GPSR6_29 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) GPSR6_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) GPSR1_27 GPSR6_27 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GPSR1_26 GPSR6_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) GPSR1_25 GPSR5_25 GPSR6_25 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) GPSR1_24 GPSR5_24 GPSR6_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) GPSR1_23 GPSR5_23 GPSR6_23 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GPSR1_22 GPSR5_22 GPSR6_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) GPSR1_21 GPSR5_21 GPSR6_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) GPSR1_20 GPSR5_20 GPSR6_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) GPSR1_19 GPSR5_19 GPSR6_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) GPSR1_18 GPSR5_18 GPSR6_18 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define PINMUX_IPSR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) FM(IP16_11_8) IP16_11_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) FM(IP16_15_12) IP16_15_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) FM(IP16_19_16) IP16_19_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) FM(IP16_23_20) IP16_23_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) FM(IP16_27_24) IP16_27_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) FM(IP16_31_28) IP16_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define PINMUX_MOD_SELS\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MOD_SEL1_31_30 MOD_SEL2_31 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MOD_SEL0_30_29 MOD_SEL2_30 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MOD_SEL1_29_28_27 MOD_SEL2_29 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MOD_SEL0_28_27 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) MOD_SEL0_26_25_24 MOD_SEL1_26 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MOD_SEL1_25_24 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MOD_SEL0_23 MOD_SEL1_23_22_21 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) MOD_SEL0_22 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) MOD_SEL0_21_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MOD_SEL1_20 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MOD_SEL0_19 MOD_SEL1_19 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MOD_SEL0_18 MOD_SEL1_18_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MOD_SEL0_17 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MOD_SEL0_16_15 MOD_SEL1_16 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MOD_SEL1_15_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) MOD_SEL0_14 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) MOD_SEL0_13 MOD_SEL1_13 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MOD_SEL0_12 MOD_SEL1_12 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MOD_SEL0_11 MOD_SEL1_11 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) MOD_SEL0_10 MOD_SEL1_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) MOD_SEL0_9 MOD_SEL1_9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) MOD_SEL0_8 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MOD_SEL0_7_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) MOD_SEL1_6 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MOD_SEL0_5_4 MOD_SEL1_5 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) MOD_SEL1_4 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MOD_SEL0_3 MOD_SEL1_3 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MOD_SEL0_2_1 MOD_SEL1_2 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MOD_SEL1_1 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MOD_SEL1_0 MOD_SEL2_0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * These pins are not able to be muxed but have other properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * that can be set, such as drive-strength or pull-up/pull-down enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define PINMUX_STATIC \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) FM(QSPI0_IO2) FM(QSPI0_IO3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) FM(QSPI1_IO2) FM(QSPI1_IO3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) FM(CLKOUT) FM(PRESETOUT) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define PINMUX_PHYS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) FM(SCL0) FM(SDA0) FM(SCL3) FM(SDA3) FM(SCL5) FM(SDA5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define F_(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define FM(x) x##_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_GPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_MOD_SELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_PHYS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_DATA_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_SINGLE(AVS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_SINGLE(AVS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_SINGLE(GP7_02),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_SINGLE(GP7_03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_SINGLE(MSIOF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_SINGLE(MSIOF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_SINGLE(MSIOF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_SINGLE(SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_SINGLE(SD3_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_SINGLE(SD3_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_SINGLE(SD3_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_SINGLE(SD3_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_SINGLE(SD3_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_SINGLE(SD3_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_SINGLE(SD3_DS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_SINGLE(SSI_SCK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_SINGLE(SSI_SDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_SINGLE(SSI_WS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_IPSR_PHYS_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_PHYS_MSEL(IP0_19_16, MSIOF2_RXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_IPSR_PHYS_MSEL(IP0_19_16, CTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_PHYS(IP0_19_16, SCL5, I2C_SEL_5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_PHYS_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, I2C_SEL_5_0, SEL_ETHERAVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_PHYS_MSEL(IP0_23_20, MSIOF2_TXD_C, I2C_SEL_5_0, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_IPSR_PHYS_MSEL(IP0_23_20, RTS4_N_A, I2C_SEL_5_0, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_PHYS(IP0_23_20, SDA5, I2C_SEL_5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_IPSR_GPSR(IP1_7_4, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_GPSR(IP1_11_8, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_GPSR(IP1_15_12, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_GPSR(IP1_19_16, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_PHYS_MSEL(IP1_23_20, PWM1_A, I2C_SEL_3_0, SEL_PWM1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_MSEL(IP1_23_20, A21, I2C_SEL_3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_PHYS_MSEL(IP1_23_20, HRX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_IPSR_PHYS_MSEL(IP1_23_20, VI4_DATA7_B, I2C_SEL_3_0, SEL_VIN4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_PHYS_MSEL(IP1_23_20, IERX_B, I2C_SEL_3_0, SEL_IEBUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_PHYS(IP1_23_20, SCL3, I2C_SEL_3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_PHYS_MSEL(IP1_27_24, PWM2_A, I2C_SEL_3_0, SEL_PWM2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_MSEL(IP1_27_24, A20, I2C_SEL_3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_IPSR_PHYS_MSEL(IP1_27_24, HTX3_D, I2C_SEL_3_0, SEL_HSCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_IPSR_PHYS_MSEL(IP1_27_24, IETX_B, I2C_SEL_3_0, SEL_IEBUS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_PHYS(IP1_27_24, SDA3, I2C_SEL_3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_IPSR_GPSR(IP1_31_28, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_IPSR_GPSR(IP2_3_0, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_IPSR_GPSR(IP2_7_4, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_GPSR(IP2_11_8, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_GPSR(IP2_15_12, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_GPSR(IP2_19_16, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_GPSR(IP2_23_20, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_IPSR_GPSR(IP2_27_24, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_GPSR(IP2_31_28, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_IPSR_GPSR(IP3_3_0, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_GPSR(IP3_7_4, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_GPSR(IP3_11_8, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_GPSR(IP3_15_12, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP3_19_16, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_GPSR(IP3_23_20, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_GPSR(IP3_27_24, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_GPSR(IP3_31_28, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_GPSR(IP4_3_0, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP4_7_4, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_GPSR(IP4_11_8, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_GPSR(IP5_15_12, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP5_19_16, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_IPSR_GPSR(IP5_23_20, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_IPSR_GPSR(IP5_27_24, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP5_31_28, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_GPSR(IP6_3_0, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_GPSR(IP6_7_4, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_GPSR(IP6_11_8, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_GPSR(IP6_15_12, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_GPSR(IP6_19_16, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_GPSR(IP6_23_20, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_GPSR(IP6_27_24, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_GPSR(IP6_31_28, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_GPSR(IP7_3_0, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_GPSR(IP7_7_4, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_GPSR(IP7_11_8, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_MSEL(IP10_19_16, SD1_CD, I2C_SEL_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_IPSR_PHYS_MSEL(IP10_19_16, SIM0_CLK_B, I2C_SEL_0_0, SEL_SIMCARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_PHYS(IP10_19_16, SCL0, I2C_SEL_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_IPSR_MSEL(IP10_23_20, SD1_WP, I2C_SEL_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_PHYS_MSEL(IP10_23_20, SIM0_D_B, I2C_SEL_0_0, SEL_SIMCARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_IPSR_PHYS(IP10_23_20, SDA0, I2C_SEL_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_GPSR(IP10_31_28, RX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_GPSR(IP11_3_0, TX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINMUX_IPSR_GPSR(IP13_3_0, RX5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINMUX_IPSR_GPSR(IP13_7_4, TX5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK349),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS349),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* IPSR17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * Static pins can not be muxed between different functions but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) * still need mark entries in the pinmux list. Add each static
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) * pin to the list without an associated function. The sh-pfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) * core will do the right thing and skip trying to mux the pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) * while still applying configuration to it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define FM(x) PINMUX_DATA(x##_MARK, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PINMUX_STATIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) * Pins not associated with a GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) GP_ASSIGN_LAST(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) PINMUX_NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* - AUDIO CLOCK ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const unsigned int audio_clk_a_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* CLK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) RCAR_GP_PIN(6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const unsigned int audio_clk_a_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) AUDIO_CLKA_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const unsigned int audio_clk_a_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* CLK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static const unsigned int audio_clk_a_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) AUDIO_CLKA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static const unsigned int audio_clk_a_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /* CLK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const unsigned int audio_clk_a_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) AUDIO_CLKA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static const unsigned int audio_clk_b_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* CLK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static const unsigned int audio_clk_b_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) AUDIO_CLKB_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static const unsigned int audio_clk_b_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* CLK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static const unsigned int audio_clk_b_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) AUDIO_CLKB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const unsigned int audio_clk_c_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* CLK C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static const unsigned int audio_clk_c_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) AUDIO_CLKC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static const unsigned int audio_clk_c_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* CLK C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int audio_clk_c_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) AUDIO_CLKC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const unsigned int audio_clkout_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static const unsigned int audio_clkout_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) AUDIO_CLKOUT_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static const unsigned int audio_clkout_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const unsigned int audio_clkout_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) AUDIO_CLKOUT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const unsigned int audio_clkout_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const unsigned int audio_clkout_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) AUDIO_CLKOUT_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const unsigned int audio_clkout_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const unsigned int audio_clkout_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) AUDIO_CLKOUT_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static const unsigned int audio_clkout1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* CLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const unsigned int audio_clkout1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) AUDIO_CLKOUT1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static const unsigned int audio_clkout1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* CLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static const unsigned int audio_clkout1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) AUDIO_CLKOUT1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static const unsigned int audio_clkout2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* CLKOUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static const unsigned int audio_clkout2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) AUDIO_CLKOUT2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const unsigned int audio_clkout2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* CLKOUT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) RCAR_GP_PIN(6, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static const unsigned int audio_clkout2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) AUDIO_CLKOUT2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const unsigned int audio_clkout3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* CLKOUT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static const unsigned int audio_clkout3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) AUDIO_CLKOUT3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const unsigned int audio_clkout3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* CLKOUT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) RCAR_GP_PIN(6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static const unsigned int audio_clkout3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) AUDIO_CLKOUT3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* - EtherAVB --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* AVB_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* AVB_MAGIC_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* AVB_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static const unsigned int avb_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) /* AVB_MDC, AVB_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) RCAR_GP_PIN(2, 9), PIN_AVB_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) static const unsigned int avb_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) AVB_MDC_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static const unsigned int avb_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) * AVB_TX_CTL, AVB_TXC, AVB_TD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) * AVB_TD1, AVB_TD2, AVB_TD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) * AVB_RX_CTL, AVB_RXC, AVB_RD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) * AVB_RD1, AVB_RD2, AVB_RD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) * AVB_TXCREFCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) PIN_AVB_TX_CTL, PIN_AVB_TXC, PIN_AVB_TD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) PIN_AVB_TD1, PIN_AVB_TD2, PIN_AVB_TD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) PIN_AVB_RX_CTL, PIN_AVB_RXC, PIN_AVB_RD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) PIN_AVB_RD1, PIN_AVB_RD2, PIN_AVB_RD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) PIN_AVB_TXCREFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) static const unsigned int avb_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) AVB_TXCREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) static const unsigned int avb_avtp_pps_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* AVB_AVTP_PPS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static const unsigned int avb_avtp_pps_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) AVB_AVTP_PPS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static const unsigned int avb_avtp_match_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* AVB_AVTP_MATCH_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static const unsigned int avb_avtp_match_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) AVB_AVTP_MATCH_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static const unsigned int avb_avtp_capture_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* AVB_AVTP_CAPTURE_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static const unsigned int avb_avtp_capture_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) AVB_AVTP_CAPTURE_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const unsigned int avb_avtp_match_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* AVB_AVTP_MATCH_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static const unsigned int avb_avtp_match_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) AVB_AVTP_MATCH_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int avb_avtp_capture_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* AVB_AVTP_CAPTURE_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const unsigned int avb_avtp_capture_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) AVB_AVTP_CAPTURE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* - CAN ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const unsigned int can0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static const unsigned int can0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) CAN0_TX_A_MARK, CAN0_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static const unsigned int can0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static const unsigned int can0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) CAN0_TX_B_MARK, CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static const unsigned int can1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static const unsigned int can1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) CAN1_TX_MARK, CAN1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) /* - CAN Clock -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static const unsigned int can_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const unsigned int can_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) /* - CAN FD --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static const unsigned int canfd0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static const unsigned int canfd0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) static const unsigned int canfd0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) static const unsigned int canfd0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const unsigned int canfd1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static const unsigned int canfd1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) CANFD1_TX_MARK, CANFD1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) /* - DRIF0 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static const unsigned int drif0_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static const unsigned int drif0_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static const unsigned int drif0_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static const unsigned int drif0_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) RIF0_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const unsigned int drif0_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static const unsigned int drif0_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) RIF0_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const unsigned int drif0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const unsigned int drif0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const unsigned int drif0_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static const unsigned int drif0_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) RIF0_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned int drif0_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) static const unsigned int drif0_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) RIF0_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static const unsigned int drif0_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) static const unsigned int drif0_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static const unsigned int drif0_data0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static const unsigned int drif0_data0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) RIF0_D0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static const unsigned int drif0_data1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static const unsigned int drif0_data1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) RIF0_D1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) /* - DRIF1 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static const unsigned int drif1_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const unsigned int drif1_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static const unsigned int drif1_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const unsigned int drif1_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) RIF1_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static const unsigned int drif1_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) RCAR_GP_PIN(6, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static const unsigned int drif1_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) RIF1_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static const unsigned int drif1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static const unsigned int drif1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static const unsigned int drif1_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static const unsigned int drif1_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) RIF1_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) static const unsigned int drif1_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) static const unsigned int drif1_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) RIF1_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) static const unsigned int drif1_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static const unsigned int drif1_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) static const unsigned int drif1_data0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) static const unsigned int drif1_data0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) RIF1_D0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static const unsigned int drif1_data1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static const unsigned int drif1_data1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) RIF1_D1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /* - DRIF2 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) static const unsigned int drif2_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static const unsigned int drif2_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static const unsigned int drif2_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static const unsigned int drif2_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) RIF2_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static const unsigned int drif2_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const unsigned int drif2_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RIF2_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static const unsigned int drif2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const unsigned int drif2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static const unsigned int drif2_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) RCAR_GP_PIN(6, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) static const unsigned int drif2_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) RIF2_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const unsigned int drif2_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) RCAR_GP_PIN(6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static const unsigned int drif2_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) RIF2_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* - DRIF3 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const unsigned int drif3_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static const unsigned int drif3_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static const unsigned int drif3_data0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static const unsigned int drif3_data0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) RIF3_D0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static const unsigned int drif3_data1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) RCAR_GP_PIN(6, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) static const unsigned int drif3_data1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) RIF3_D1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) static const unsigned int drif3_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) /* CLK, SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static const unsigned int drif3_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static const unsigned int drif3_data0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static const unsigned int drif3_data0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) RIF3_D0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) static const unsigned int drif3_data1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static const unsigned int drif3_data1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) RIF3_D1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) DU_DR3_MARK, DU_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) DU_DG3_MARK, DU_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) DU_DB3_MARK, DU_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) static const unsigned int du_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static const unsigned int du_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static const unsigned int du_clk_out_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) RCAR_GP_PIN(1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static const unsigned int du_clk_out_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) DU_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static const unsigned int du_clk_out_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static const unsigned int du_clk_out_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) DU_DOTCLKOUT1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static const unsigned int du_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static const unsigned int du_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static const unsigned int du_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) /* EXDISP/EXODDF/EXCDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) static const unsigned int du_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) DU_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static const unsigned int du_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static const unsigned int du_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) DU_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) static const unsigned int hscif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) static const unsigned int hscif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) HRX0_MARK, HTX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) static const unsigned int hscif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) static const unsigned int hscif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) HSCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static const unsigned int hscif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static const unsigned int hscif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) HRTS0_N_MARK, HCTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) static const unsigned int hscif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static const unsigned int hscif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) HRX1_A_MARK, HTX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) static const unsigned int hscif1_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static const unsigned int hscif1_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) HSCK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) static const unsigned int hscif1_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static const unsigned int hscif1_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) HRTS1_N_A_MARK, HCTS1_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static const unsigned int hscif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static const unsigned int hscif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) HRX1_B_MARK, HTX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static const unsigned int hscif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) static const unsigned int hscif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) HSCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static const unsigned int hscif1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static const unsigned int hscif1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) HRTS1_N_B_MARK, HCTS1_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) /* - HSCIF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static const unsigned int hscif2_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) static const unsigned int hscif2_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) HRX2_A_MARK, HTX2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static const unsigned int hscif2_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) static const unsigned int hscif2_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) HSCK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static const unsigned int hscif2_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) static const unsigned int hscif2_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) HRTS2_N_A_MARK, HCTS2_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) static const unsigned int hscif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static const unsigned int hscif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) HRX2_B_MARK, HTX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static const unsigned int hscif2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static const unsigned int hscif2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) HSCK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) static const unsigned int hscif2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static const unsigned int hscif2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) HRTS2_N_B_MARK, HCTS2_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* - HSCIF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static const unsigned int hscif3_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) static const unsigned int hscif3_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) HRX3_A_MARK, HTX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) static const unsigned int hscif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) static const unsigned int hscif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) HSCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) static const unsigned int hscif3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static const unsigned int hscif3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) HRTS3_N_MARK, HCTS3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static const unsigned int hscif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static const unsigned int hscif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) HRX3_B_MARK, HTX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static const unsigned int hscif3_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static const unsigned int hscif3_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) HRX3_C_MARK, HTX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const unsigned int hscif3_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static const unsigned int hscif3_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) HRX3_D_MARK, HTX3_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /* - HSCIF4 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static const unsigned int hscif4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static const unsigned int hscif4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) HRX4_A_MARK, HTX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static const unsigned int hscif4_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static const unsigned int hscif4_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) HSCK4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) static const unsigned int hscif4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static const unsigned int hscif4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) HRTS4_N_MARK, HCTS4_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) static const unsigned int hscif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static const unsigned int hscif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) HRX4_B_MARK, HTX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) /* - I2C -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) SCL0_MARK, SDA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static const unsigned int i2c1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static const unsigned int i2c1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) SDA1_A_MARK, SCL1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static const unsigned int i2c1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static const unsigned int i2c1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) SDA1_B_MARK, SCL1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static const unsigned int i2c2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static const unsigned int i2c2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) SDA2_A_MARK, SCL2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) SDA2_B_MARK, SCL2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static const unsigned int i2c3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static const unsigned int i2c3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) SCL3_MARK, SDA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static const unsigned int i2c5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static const unsigned int i2c5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) SCL5_MARK, SDA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static const unsigned int i2c6_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static const unsigned int i2c6_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) SDA6_A_MARK, SCL6_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) static const unsigned int i2c6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static const unsigned int i2c6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) SDA6_B_MARK, SCL6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static const unsigned int i2c6_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) /* SDA, SCL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) static const unsigned int i2c6_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) SDA6_C_MARK, SCL6_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) /* - INTC-EX ---------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) static const unsigned int intc_ex_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) static const unsigned int intc_ex_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) static const unsigned int intc_ex_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) static const unsigned int intc_ex_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static const unsigned int intc_ex_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) static const unsigned int intc_ex_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static const unsigned int intc_ex_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static const unsigned int intc_ex_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static const unsigned int intc_ex_irq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static const unsigned int intc_ex_irq4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) IRQ4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static const unsigned int intc_ex_irq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static const unsigned int intc_ex_irq5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) IRQ5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static const unsigned int msiof0_txd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) static const unsigned int msiof0_txd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static const unsigned int msiof0_rxd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) RCAR_GP_PIN(5, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static const unsigned int msiof0_rxd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static const unsigned int msiof1_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) RCAR_GP_PIN(6, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) static const unsigned int msiof1_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) MSIOF1_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static const unsigned int msiof1_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) static const unsigned int msiof1_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) MSIOF1_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static const unsigned int msiof1_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) RCAR_GP_PIN(6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) static const unsigned int msiof1_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) MSIOF1_SS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static const unsigned int msiof1_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static const unsigned int msiof1_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) MSIOF1_SS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static const unsigned int msiof1_txd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) static const unsigned int msiof1_txd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) MSIOF1_TXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static const unsigned int msiof1_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static const unsigned int msiof1_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) MSIOF1_RXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static const unsigned int msiof1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static const unsigned int msiof1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) MSIOF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static const unsigned int msiof1_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static const unsigned int msiof1_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) MSIOF1_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static const unsigned int msiof1_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static const unsigned int msiof1_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) MSIOF1_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static const unsigned int msiof1_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const unsigned int msiof1_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) MSIOF1_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static const unsigned int msiof1_txd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static const unsigned int msiof1_txd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) MSIOF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) static const unsigned int msiof1_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static const unsigned int msiof1_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) MSIOF1_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) static const unsigned int msiof1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) RCAR_GP_PIN(6, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) static const unsigned int msiof1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) MSIOF1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static const unsigned int msiof1_sync_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) static const unsigned int msiof1_sync_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) MSIOF1_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static const unsigned int msiof1_ss1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) static const unsigned int msiof1_ss1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) MSIOF1_SS1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static const unsigned int msiof1_ss2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static const unsigned int msiof1_ss2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) MSIOF1_SS2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static const unsigned int msiof1_txd_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) RCAR_GP_PIN(6, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static const unsigned int msiof1_txd_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) MSIOF1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) static const unsigned int msiof1_rxd_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) static const unsigned int msiof1_rxd_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) MSIOF1_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static const unsigned int msiof1_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static const unsigned int msiof1_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) MSIOF1_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) static const unsigned int msiof1_sync_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) static const unsigned int msiof1_sync_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) MSIOF1_SYNC_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) static const unsigned int msiof1_ss1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) static const unsigned int msiof1_ss1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) MSIOF1_SS1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static const unsigned int msiof1_ss2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) static const unsigned int msiof1_ss2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) MSIOF1_SS2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static const unsigned int msiof1_txd_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) static const unsigned int msiof1_txd_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) MSIOF1_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static const unsigned int msiof1_rxd_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) static const unsigned int msiof1_rxd_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) MSIOF1_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) static const unsigned int msiof1_clk_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static const unsigned int msiof1_clk_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) MSIOF1_SCK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) static const unsigned int msiof1_sync_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static const unsigned int msiof1_sync_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) MSIOF1_SYNC_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static const unsigned int msiof1_ss1_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) static const unsigned int msiof1_ss1_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) MSIOF1_SS1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) static const unsigned int msiof1_ss2_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) static const unsigned int msiof1_ss2_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) MSIOF1_SS2_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static const unsigned int msiof1_txd_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) static const unsigned int msiof1_txd_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) MSIOF1_TXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static const unsigned int msiof1_rxd_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) static const unsigned int msiof1_rxd_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) MSIOF1_RXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static const unsigned int msiof1_clk_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) static const unsigned int msiof1_clk_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) MSIOF1_SCK_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static const unsigned int msiof1_sync_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) RCAR_GP_PIN(5, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static const unsigned int msiof1_sync_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) MSIOF1_SYNC_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const unsigned int msiof1_ss1_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) RCAR_GP_PIN(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) static const unsigned int msiof1_ss1_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) MSIOF1_SS1_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static const unsigned int msiof1_ss2_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) RCAR_GP_PIN(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static const unsigned int msiof1_ss2_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) MSIOF1_SS2_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static const unsigned int msiof1_txd_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) RCAR_GP_PIN(6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static const unsigned int msiof1_txd_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) MSIOF1_TXD_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static const unsigned int msiof1_rxd_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static const unsigned int msiof1_rxd_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) MSIOF1_RXD_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static const unsigned int msiof1_clk_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static const unsigned int msiof1_clk_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) MSIOF1_SCK_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) static const unsigned int msiof1_sync_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const unsigned int msiof1_sync_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) MSIOF1_SYNC_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static const unsigned int msiof1_ss1_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static const unsigned int msiof1_ss1_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) MSIOF1_SS1_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) static const unsigned int msiof1_ss2_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static const unsigned int msiof1_ss2_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) MSIOF1_SS2_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static const unsigned int msiof1_txd_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static const unsigned int msiof1_txd_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) MSIOF1_TXD_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static const unsigned int msiof1_rxd_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static const unsigned int msiof1_rxd_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) MSIOF1_RXD_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static const unsigned int msiof2_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static const unsigned int msiof2_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) MSIOF2_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) static const unsigned int msiof2_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static const unsigned int msiof2_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) MSIOF2_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) static const unsigned int msiof2_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static const unsigned int msiof2_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) MSIOF2_SS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) static const unsigned int msiof2_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static const unsigned int msiof2_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) MSIOF2_SS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) static const unsigned int msiof2_txd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) static const unsigned int msiof2_txd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) MSIOF2_TXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) static const unsigned int msiof2_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) static const unsigned int msiof2_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) MSIOF2_RXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static const unsigned int msiof2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static const unsigned int msiof2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) MSIOF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) static const unsigned int msiof2_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) static const unsigned int msiof2_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) MSIOF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static const unsigned int msiof2_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) static const unsigned int msiof2_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) MSIOF2_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) static const unsigned int msiof2_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) static const unsigned int msiof2_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) MSIOF2_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) static const unsigned int msiof2_txd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) static const unsigned int msiof2_txd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) MSIOF2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) static const unsigned int msiof2_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static const unsigned int msiof2_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) MSIOF2_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static const unsigned int msiof2_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) static const unsigned int msiof2_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) MSIOF2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) static const unsigned int msiof2_sync_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) static const unsigned int msiof2_sync_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) MSIOF2_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) static const unsigned int msiof2_ss1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) static const unsigned int msiof2_ss1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) MSIOF2_SS1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) static const unsigned int msiof2_ss2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) static const unsigned int msiof2_ss2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) MSIOF2_SS2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) static const unsigned int msiof2_txd_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) static const unsigned int msiof2_txd_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) MSIOF2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) static const unsigned int msiof2_rxd_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) static const unsigned int msiof2_rxd_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) MSIOF2_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) static const unsigned int msiof2_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) static const unsigned int msiof2_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) MSIOF2_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) static const unsigned int msiof2_sync_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) static const unsigned int msiof2_sync_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) MSIOF2_SYNC_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static const unsigned int msiof2_ss1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) static const unsigned int msiof2_ss1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) MSIOF2_SS1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static const unsigned int msiof2_ss2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static const unsigned int msiof2_ss2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) MSIOF2_SS2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static const unsigned int msiof2_txd_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static const unsigned int msiof2_txd_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) MSIOF2_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) static const unsigned int msiof2_rxd_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) static const unsigned int msiof2_rxd_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) MSIOF2_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) /* - MSIOF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) static const unsigned int msiof3_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static const unsigned int msiof3_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) MSIOF3_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) static const unsigned int msiof3_sync_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) static const unsigned int msiof3_sync_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) MSIOF3_SYNC_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) static const unsigned int msiof3_ss1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) static const unsigned int msiof3_ss1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) MSIOF3_SS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) static const unsigned int msiof3_ss2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) static const unsigned int msiof3_ss2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) MSIOF3_SS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) static const unsigned int msiof3_txd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) static const unsigned int msiof3_txd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) MSIOF3_TXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) static const unsigned int msiof3_rxd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) static const unsigned int msiof3_rxd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) MSIOF3_RXD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) static const unsigned int msiof3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static const unsigned int msiof3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) MSIOF3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) static const unsigned int msiof3_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static const unsigned int msiof3_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) MSIOF3_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) static const unsigned int msiof3_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) static const unsigned int msiof3_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) MSIOF3_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) static const unsigned int msiof3_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) static const unsigned int msiof3_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) MSIOF3_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) static const unsigned int msiof3_txd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) static const unsigned int msiof3_txd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) MSIOF3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) static const unsigned int msiof3_rxd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static const unsigned int msiof3_rxd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) MSIOF3_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static const unsigned int msiof3_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) static const unsigned int msiof3_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) MSIOF3_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) static const unsigned int msiof3_sync_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) static const unsigned int msiof3_sync_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) MSIOF3_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) static const unsigned int msiof3_txd_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) static const unsigned int msiof3_txd_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) MSIOF3_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) static const unsigned int msiof3_rxd_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) static const unsigned int msiof3_rxd_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) MSIOF3_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static const unsigned int msiof3_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) static const unsigned int msiof3_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) MSIOF3_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) static const unsigned int msiof3_sync_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static const unsigned int msiof3_sync_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) MSIOF3_SYNC_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static const unsigned int msiof3_ss1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) RCAR_GP_PIN(1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) static const unsigned int msiof3_ss1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) MSIOF3_SS1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static const unsigned int msiof3_txd_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static const unsigned int msiof3_txd_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) MSIOF3_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) static const unsigned int msiof3_rxd_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static const unsigned int msiof3_rxd_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) MSIOF3_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) /* - PWM0 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) static const unsigned int pwm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) static const unsigned int pwm0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) PWM0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) /* - PWM1 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) static const unsigned int pwm1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) static const unsigned int pwm1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) PWM1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) /* - PWM2 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) static const unsigned int pwm2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) static const unsigned int pwm2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) PWM2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) /* - PWM3 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static const unsigned int pwm3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static const unsigned int pwm3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) PWM3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) static const unsigned int pwm3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static const unsigned int pwm3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /* - PWM4 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static const unsigned int pwm4_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) static const unsigned int pwm4_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) PWM4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static const unsigned int pwm4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) static const unsigned int pwm4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) /* - PWM5 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) static const unsigned int pwm5_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) static const unsigned int pwm5_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) PWM5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) static const unsigned int pwm5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static const unsigned int pwm5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) PWM5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) /* - PWM6 --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) static const unsigned int pwm6_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) static const unsigned int pwm6_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) PWM6_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) static const unsigned int pwm6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) /* PWM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) static const unsigned int pwm6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) PWM6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) /* - QSPI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) static const unsigned int qspi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) /* QSPI0_SPCLK, QSPI0_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) PIN_QSPI0_SPCLK, PIN_QSPI0_SSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) static const unsigned int qspi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) static const unsigned int qspi0_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) static const unsigned int qspi0_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) static const unsigned int qspi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) /* QSPI0_MOSI_IO0, QSPI0_MISO_IO1, QSPI0_IO2, QSPI0_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) PIN_QSPI0_MOSI_IO0, PIN_QSPI0_MISO_IO1, PIN_QSPI0_IO2, PIN_QSPI0_IO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) static const unsigned int qspi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) QSPI0_IO2_MARK, QSPI0_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) /* - QSPI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) static const unsigned int qspi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) /* QSPI1_SPCLK, QSPI1_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) PIN_QSPI1_SPCLK, PIN_QSPI1_SSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static const unsigned int qspi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) static const unsigned int qspi1_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) static const unsigned int qspi1_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) static const unsigned int qspi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) /* QSPI1_MOSI_IO0, QSPI1_MISO_IO1, QSPI1_IO2, QSPI1_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) PIN_QSPI1_MOSI_IO0, PIN_QSPI1_MISO_IO1, PIN_QSPI1_IO2, PIN_QSPI1_IO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) static const unsigned int qspi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) QSPI1_IO2_MARK, QSPI1_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) /* - SATA --------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) static const unsigned int sata0_devslp_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* DEVSLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) RCAR_GP_PIN(6, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) static const unsigned int sata0_devslp_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) SATA_DEVSLP_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) static const unsigned int sata0_devslp_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) /* DEVSLP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static const unsigned int sata0_devslp_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) SATA_DEVSLP_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) static const unsigned int scif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) static const unsigned int scif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) RX0_MARK, TX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) static const unsigned int scif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) static const unsigned int scif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) SCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) static const unsigned int scif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) static const unsigned int scif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) RTS0_N_MARK, CTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) static const unsigned int scif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) static const unsigned int scif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) RX1_A_MARK, TX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) static const unsigned int scif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) static const unsigned int scif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) SCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) static const unsigned int scif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) static const unsigned int scif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) RTS1_N_MARK, CTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) static const unsigned int scif2_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) static const unsigned int scif2_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) RX2_A_MARK, TX2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) static const unsigned int scif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) static const unsigned int scif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) SCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) static const unsigned int scif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) static const unsigned int scif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) RX2_B_MARK, TX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) static const unsigned int scif3_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) static const unsigned int scif3_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) RX3_A_MARK, TX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) static const unsigned int scif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) static const unsigned int scif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) SCK3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) static const unsigned int scif3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) static const unsigned int scif3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) RTS3_N_MARK, CTS3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) static const unsigned int scif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) static const unsigned int scif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) RX3_B_MARK, TX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) static const unsigned int scif4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) static const unsigned int scif4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) RX4_A_MARK, TX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static const unsigned int scif4_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) static const unsigned int scif4_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) SCK4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) static const unsigned int scif4_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) static const unsigned int scif4_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) RTS4_N_A_MARK, CTS4_N_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static const unsigned int scif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static const unsigned int scif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) RX4_B_MARK, TX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) static const unsigned int scif4_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) static const unsigned int scif4_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) SCK4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static const unsigned int scif4_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) static const unsigned int scif4_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) RTS4_N_B_MARK, CTS4_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) static const unsigned int scif4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) static const unsigned int scif4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) RX4_C_MARK, TX4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) static const unsigned int scif4_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) static const unsigned int scif4_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) SCK4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) static const unsigned int scif4_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) static const unsigned int scif4_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) RTS4_N_C_MARK, CTS4_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) static const unsigned int scif5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) static const unsigned int scif5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) RX5_MARK, TX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) static const unsigned int scif5_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static const unsigned int scif5_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) SCK5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) static const unsigned int scif_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static const unsigned int scif_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) SCIF_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) SD0_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) SD0_DAT0_MARK, SD0_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) SD0_DAT2_MARK, SD0_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) SD0_CLK_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) SD0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) SD1_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) SD1_DAT0_MARK, SD1_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) SD1_DAT2_MARK, SD1_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) SD1_CLK_MARK, SD1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) SD2_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) SD2_DAT0_MARK, SD2_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) SD2_DAT2_MARK, SD2_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) static const unsigned int sdhi2_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) static const unsigned int sdhi2_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) SD2_DAT0_MARK, SD2_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) SD2_DAT2_MARK, SD2_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) SD2_DAT4_MARK, SD2_DAT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) SD2_DAT6_MARK, SD2_DAT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) SD2_CLK_MARK, SD2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) static const unsigned int sdhi2_cd_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) static const unsigned int sdhi2_cd_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) SD2_CD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) static const unsigned int sdhi2_cd_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) static const unsigned int sdhi2_cd_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) SD2_CD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) static const unsigned int sdhi2_wp_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) static const unsigned int sdhi2_wp_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) SD2_WP_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) static const unsigned int sdhi2_wp_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) static const unsigned int sdhi2_wp_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) SD2_WP_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) static const unsigned int sdhi2_ds_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) /* DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) static const unsigned int sdhi2_ds_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) SD2_DS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /* - SDHI3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) static const unsigned int sdhi3_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) static const unsigned int sdhi3_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) SD3_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) static const unsigned int sdhi3_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) static const unsigned int sdhi3_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) SD3_DAT0_MARK, SD3_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) SD3_DAT2_MARK, SD3_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) static const unsigned int sdhi3_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) static const unsigned int sdhi3_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) SD3_DAT0_MARK, SD3_DAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) SD3_DAT2_MARK, SD3_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) SD3_DAT4_MARK, SD3_DAT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) SD3_DAT6_MARK, SD3_DAT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) static const unsigned int sdhi3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) static const unsigned int sdhi3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) SD3_CLK_MARK, SD3_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) static const unsigned int sdhi3_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) static const unsigned int sdhi3_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) SD3_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) static const unsigned int sdhi3_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) static const unsigned int sdhi3_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) SD3_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) static const unsigned int sdhi3_ds_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) /* DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) static const unsigned int sdhi3_ds_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) SD3_DS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) /* - SSI -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) static const unsigned int ssi0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) RCAR_GP_PIN(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static const unsigned int ssi0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) SSI_SDATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) static const unsigned int ssi01239_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) static const unsigned int ssi01239_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) SSI_SCK01239_MARK, SSI_WS01239_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) static const unsigned int ssi1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) static const unsigned int ssi1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) SSI_SDATA1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) static const unsigned int ssi1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) static const unsigned int ssi1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) static const unsigned int ssi1_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) static const unsigned int ssi1_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) static const unsigned int ssi1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) static const unsigned int ssi1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) static const unsigned int ssi2_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) RCAR_GP_PIN(6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) static const unsigned int ssi2_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) SSI_SDATA2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static const unsigned int ssi2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) static const unsigned int ssi2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) SSI_SDATA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) static const unsigned int ssi2_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) static const unsigned int ssi2_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) static const unsigned int ssi2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) static const unsigned int ssi2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) static const unsigned int ssi3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) static const unsigned int ssi3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) SSI_SDATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) static const unsigned int ssi349_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) static const unsigned int ssi349_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) SSI_SCK349_MARK, SSI_WS349_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) static const unsigned int ssi4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) static const unsigned int ssi4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) SSI_SDATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) static const unsigned int ssi4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) static const unsigned int ssi4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) SSI_SCK4_MARK, SSI_WS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) static const unsigned int ssi5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) RCAR_GP_PIN(6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) static const unsigned int ssi5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) SSI_SDATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) static const unsigned int ssi5_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) static const unsigned int ssi5_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) SSI_SCK5_MARK, SSI_WS5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) static const unsigned int ssi6_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) RCAR_GP_PIN(6, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) static const unsigned int ssi6_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) SSI_SDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) static const unsigned int ssi6_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static const unsigned int ssi6_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) SSI_SCK6_MARK, SSI_WS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) static const unsigned int ssi7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) static const unsigned int ssi7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) static const unsigned int ssi78_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) static const unsigned int ssi78_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) SSI_SCK78_MARK, SSI_WS78_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) static const unsigned int ssi8_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) RCAR_GP_PIN(6, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) static const unsigned int ssi8_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) static const unsigned int ssi9_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) static const unsigned int ssi9_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) SSI_SDATA9_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) static const unsigned int ssi9_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) static const unsigned int ssi9_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) SSI_SDATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) static const unsigned int ssi9_ctrl_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) static const unsigned int ssi9_ctrl_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) static const unsigned int ssi9_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) static const unsigned int ssi9_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) /* - TMU -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) static const unsigned int tmu_tclk1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) static const unsigned int tmu_tclk1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) TCLK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) static const unsigned int tmu_tclk1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) static const unsigned int tmu_tclk1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) static const unsigned int tmu_tclk2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) static const unsigned int tmu_tclk2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) TCLK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) static const unsigned int tmu_tclk2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /* TCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) static const unsigned int tmu_tclk2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) TCLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) /* - TPU ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) static const unsigned int tpu_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) /* TPU0TO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) static const unsigned int tpu_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) TPU0TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) static const unsigned int tpu_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) /* TPU0TO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) static const unsigned int tpu_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) static const unsigned int tpu_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) /* TPU0TO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) RCAR_GP_PIN(6, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) static const unsigned int tpu_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) TPU0TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) static const unsigned int tpu_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) /* TPU0TO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) RCAR_GP_PIN(6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) static const unsigned int tpu_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) static const unsigned int usb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) static const unsigned int usb0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) USB0_PWEN_MARK, USB0_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) /* - USB1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) static const unsigned int usb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) static const unsigned int usb1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) USB1_PWEN_MARK, USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) /* - USB2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) static const unsigned int usb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) static const unsigned int usb2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) USB2_PWEN_MARK, USB2_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) /* - USB30 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) static const unsigned int usb30_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) static const unsigned int usb30_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) USB30_PWEN_MARK, USB30_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) /* - USB31 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) static const unsigned int usb31_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) static const unsigned int usb31_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) USB31_PWEN_MARK, USB31_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) SH_PFC_PIN_GROUP(audio_clk_a_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) SH_PFC_PIN_GROUP(audio_clk_a_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) SH_PFC_PIN_GROUP(audio_clk_a_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) SH_PFC_PIN_GROUP(audio_clk_b_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) SH_PFC_PIN_GROUP(audio_clk_b_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) SH_PFC_PIN_GROUP(audio_clk_c_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) SH_PFC_PIN_GROUP(audio_clk_c_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) SH_PFC_PIN_GROUP(audio_clkout_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) SH_PFC_PIN_GROUP(audio_clkout_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) SH_PFC_PIN_GROUP(audio_clkout_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) SH_PFC_PIN_GROUP(audio_clkout_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) SH_PFC_PIN_GROUP(audio_clkout1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) SH_PFC_PIN_GROUP(audio_clkout1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) SH_PFC_PIN_GROUP(audio_clkout2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) SH_PFC_PIN_GROUP(audio_clkout2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) SH_PFC_PIN_GROUP(audio_clkout3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) SH_PFC_PIN_GROUP(audio_clkout3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) SH_PFC_PIN_GROUP(avb_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) SH_PFC_PIN_GROUP(avb_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) SH_PFC_PIN_GROUP(avb_avtp_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) SH_PFC_PIN_GROUP(avb_avtp_match_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) SH_PFC_PIN_GROUP(avb_avtp_capture_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) SH_PFC_PIN_GROUP(avb_avtp_match_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) SH_PFC_PIN_GROUP(avb_avtp_capture_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) SH_PFC_PIN_GROUP(can0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) SH_PFC_PIN_GROUP(can0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) SH_PFC_PIN_GROUP(can1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) SH_PFC_PIN_GROUP(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) SH_PFC_PIN_GROUP(canfd0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) SH_PFC_PIN_GROUP(canfd0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) SH_PFC_PIN_GROUP(canfd1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) SH_PFC_PIN_GROUP(drif0_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) SH_PFC_PIN_GROUP(drif0_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) SH_PFC_PIN_GROUP(drif0_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) SH_PFC_PIN_GROUP(drif0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) SH_PFC_PIN_GROUP(drif0_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) SH_PFC_PIN_GROUP(drif0_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) SH_PFC_PIN_GROUP(drif0_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) SH_PFC_PIN_GROUP(drif0_data0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) SH_PFC_PIN_GROUP(drif0_data1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) SH_PFC_PIN_GROUP(drif1_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) SH_PFC_PIN_GROUP(drif1_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) SH_PFC_PIN_GROUP(drif1_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) SH_PFC_PIN_GROUP(drif1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) SH_PFC_PIN_GROUP(drif1_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) SH_PFC_PIN_GROUP(drif1_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) SH_PFC_PIN_GROUP(drif1_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) SH_PFC_PIN_GROUP(drif1_data0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) SH_PFC_PIN_GROUP(drif1_data1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) SH_PFC_PIN_GROUP(drif2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) SH_PFC_PIN_GROUP(drif2_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) SH_PFC_PIN_GROUP(drif2_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) SH_PFC_PIN_GROUP(drif2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) SH_PFC_PIN_GROUP(drif2_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) SH_PFC_PIN_GROUP(drif2_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) SH_PFC_PIN_GROUP(drif3_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) SH_PFC_PIN_GROUP(drif3_data0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) SH_PFC_PIN_GROUP(drif3_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) SH_PFC_PIN_GROUP(drif3_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) SH_PFC_PIN_GROUP(drif3_data0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) SH_PFC_PIN_GROUP(drif3_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) SH_PFC_PIN_GROUP(du_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) SH_PFC_PIN_GROUP(du_clk_out_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) SH_PFC_PIN_GROUP(du_clk_out_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) SH_PFC_PIN_GROUP(du_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) SH_PFC_PIN_GROUP(du_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) SH_PFC_PIN_GROUP(du_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) SH_PFC_PIN_GROUP(hscif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) SH_PFC_PIN_GROUP(hscif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) SH_PFC_PIN_GROUP(hscif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) SH_PFC_PIN_GROUP(hscif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) SH_PFC_PIN_GROUP(hscif1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) SH_PFC_PIN_GROUP(hscif1_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) SH_PFC_PIN_GROUP(hscif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) SH_PFC_PIN_GROUP(hscif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) SH_PFC_PIN_GROUP(hscif1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) SH_PFC_PIN_GROUP(hscif2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) SH_PFC_PIN_GROUP(hscif2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) SH_PFC_PIN_GROUP(hscif2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) SH_PFC_PIN_GROUP(hscif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) SH_PFC_PIN_GROUP(hscif2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) SH_PFC_PIN_GROUP(hscif2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) SH_PFC_PIN_GROUP(hscif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) SH_PFC_PIN_GROUP(hscif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) SH_PFC_PIN_GROUP(hscif3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) SH_PFC_PIN_GROUP(hscif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) SH_PFC_PIN_GROUP(hscif3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) SH_PFC_PIN_GROUP(hscif3_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) SH_PFC_PIN_GROUP(hscif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) SH_PFC_PIN_GROUP(hscif4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) SH_PFC_PIN_GROUP(hscif4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) SH_PFC_PIN_GROUP(hscif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) SH_PFC_PIN_GROUP(i2c1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) SH_PFC_PIN_GROUP(i2c2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) SH_PFC_PIN_GROUP(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) SH_PFC_PIN_GROUP(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) SH_PFC_PIN_GROUP(i2c6_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) SH_PFC_PIN_GROUP(i2c6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) SH_PFC_PIN_GROUP(i2c6_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) SH_PFC_PIN_GROUP(intc_ex_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) SH_PFC_PIN_GROUP(intc_ex_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) SH_PFC_PIN_GROUP(intc_ex_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) SH_PFC_PIN_GROUP(intc_ex_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) SH_PFC_PIN_GROUP(intc_ex_irq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) SH_PFC_PIN_GROUP(intc_ex_irq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) SH_PFC_PIN_GROUP(msiof0_txd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) SH_PFC_PIN_GROUP(msiof0_rxd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) SH_PFC_PIN_GROUP(msiof1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) SH_PFC_PIN_GROUP(msiof1_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) SH_PFC_PIN_GROUP(msiof1_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) SH_PFC_PIN_GROUP(msiof1_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) SH_PFC_PIN_GROUP(msiof1_txd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) SH_PFC_PIN_GROUP(msiof1_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) SH_PFC_PIN_GROUP(msiof1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) SH_PFC_PIN_GROUP(msiof1_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) SH_PFC_PIN_GROUP(msiof1_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) SH_PFC_PIN_GROUP(msiof1_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) SH_PFC_PIN_GROUP(msiof1_txd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) SH_PFC_PIN_GROUP(msiof1_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) SH_PFC_PIN_GROUP(msiof1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) SH_PFC_PIN_GROUP(msiof1_sync_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) SH_PFC_PIN_GROUP(msiof1_ss1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) SH_PFC_PIN_GROUP(msiof1_ss2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) SH_PFC_PIN_GROUP(msiof1_txd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) SH_PFC_PIN_GROUP(msiof1_rxd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) SH_PFC_PIN_GROUP(msiof1_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) SH_PFC_PIN_GROUP(msiof1_sync_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) SH_PFC_PIN_GROUP(msiof1_ss1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) SH_PFC_PIN_GROUP(msiof1_ss2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) SH_PFC_PIN_GROUP(msiof1_txd_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) SH_PFC_PIN_GROUP(msiof1_rxd_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) SH_PFC_PIN_GROUP(msiof1_clk_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) SH_PFC_PIN_GROUP(msiof1_sync_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) SH_PFC_PIN_GROUP(msiof1_ss1_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) SH_PFC_PIN_GROUP(msiof1_ss2_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) SH_PFC_PIN_GROUP(msiof1_txd_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) SH_PFC_PIN_GROUP(msiof1_rxd_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) SH_PFC_PIN_GROUP(msiof1_clk_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) SH_PFC_PIN_GROUP(msiof1_sync_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) SH_PFC_PIN_GROUP(msiof1_ss1_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) SH_PFC_PIN_GROUP(msiof1_ss2_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) SH_PFC_PIN_GROUP(msiof1_txd_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) SH_PFC_PIN_GROUP(msiof1_rxd_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) SH_PFC_PIN_GROUP(msiof1_clk_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) SH_PFC_PIN_GROUP(msiof1_sync_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) SH_PFC_PIN_GROUP(msiof1_ss1_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) SH_PFC_PIN_GROUP(msiof1_ss2_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) SH_PFC_PIN_GROUP(msiof1_txd_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) SH_PFC_PIN_GROUP(msiof1_rxd_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) SH_PFC_PIN_GROUP(msiof2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) SH_PFC_PIN_GROUP(msiof2_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) SH_PFC_PIN_GROUP(msiof2_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) SH_PFC_PIN_GROUP(msiof2_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) SH_PFC_PIN_GROUP(msiof2_txd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) SH_PFC_PIN_GROUP(msiof2_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) SH_PFC_PIN_GROUP(msiof2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) SH_PFC_PIN_GROUP(msiof2_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) SH_PFC_PIN_GROUP(msiof2_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) SH_PFC_PIN_GROUP(msiof2_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) SH_PFC_PIN_GROUP(msiof2_txd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) SH_PFC_PIN_GROUP(msiof2_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) SH_PFC_PIN_GROUP(msiof2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) SH_PFC_PIN_GROUP(msiof2_sync_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) SH_PFC_PIN_GROUP(msiof2_ss1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) SH_PFC_PIN_GROUP(msiof2_ss2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) SH_PFC_PIN_GROUP(msiof2_txd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) SH_PFC_PIN_GROUP(msiof2_rxd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) SH_PFC_PIN_GROUP(msiof2_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) SH_PFC_PIN_GROUP(msiof2_sync_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) SH_PFC_PIN_GROUP(msiof2_ss1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) SH_PFC_PIN_GROUP(msiof2_ss2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) SH_PFC_PIN_GROUP(msiof2_txd_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) SH_PFC_PIN_GROUP(msiof2_rxd_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) SH_PFC_PIN_GROUP(msiof3_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) SH_PFC_PIN_GROUP(msiof3_sync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) SH_PFC_PIN_GROUP(msiof3_ss1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) SH_PFC_PIN_GROUP(msiof3_ss2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) SH_PFC_PIN_GROUP(msiof3_txd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) SH_PFC_PIN_GROUP(msiof3_rxd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) SH_PFC_PIN_GROUP(msiof3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) SH_PFC_PIN_GROUP(msiof3_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) SH_PFC_PIN_GROUP(msiof3_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) SH_PFC_PIN_GROUP(msiof3_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) SH_PFC_PIN_GROUP(msiof3_txd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) SH_PFC_PIN_GROUP(msiof3_rxd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) SH_PFC_PIN_GROUP(msiof3_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) SH_PFC_PIN_GROUP(msiof3_sync_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) SH_PFC_PIN_GROUP(msiof3_txd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) SH_PFC_PIN_GROUP(msiof3_rxd_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) SH_PFC_PIN_GROUP(msiof3_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) SH_PFC_PIN_GROUP(msiof3_sync_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) SH_PFC_PIN_GROUP(msiof3_ss1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) SH_PFC_PIN_GROUP(msiof3_txd_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) SH_PFC_PIN_GROUP(msiof3_rxd_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) SH_PFC_PIN_GROUP(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) SH_PFC_PIN_GROUP(pwm1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) SH_PFC_PIN_GROUP(pwm2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) SH_PFC_PIN_GROUP(pwm3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) SH_PFC_PIN_GROUP(pwm3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) SH_PFC_PIN_GROUP(pwm4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) SH_PFC_PIN_GROUP(pwm4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) SH_PFC_PIN_GROUP(pwm5_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) SH_PFC_PIN_GROUP(pwm5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) SH_PFC_PIN_GROUP(pwm6_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) SH_PFC_PIN_GROUP(pwm6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) SH_PFC_PIN_GROUP(qspi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) SH_PFC_PIN_GROUP(qspi0_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) SH_PFC_PIN_GROUP(qspi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) SH_PFC_PIN_GROUP(qspi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) SH_PFC_PIN_GROUP(qspi1_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) SH_PFC_PIN_GROUP(qspi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) SH_PFC_PIN_GROUP(sata0_devslp_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) SH_PFC_PIN_GROUP(sata0_devslp_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) SH_PFC_PIN_GROUP(scif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) SH_PFC_PIN_GROUP(scif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) SH_PFC_PIN_GROUP(scif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) SH_PFC_PIN_GROUP(scif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) SH_PFC_PIN_GROUP(scif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) SH_PFC_PIN_GROUP(scif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) SH_PFC_PIN_GROUP(scif2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) SH_PFC_PIN_GROUP(scif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) SH_PFC_PIN_GROUP(scif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) SH_PFC_PIN_GROUP(scif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) SH_PFC_PIN_GROUP(scif3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) SH_PFC_PIN_GROUP(scif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) SH_PFC_PIN_GROUP(scif4_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) SH_PFC_PIN_GROUP(scif4_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) SH_PFC_PIN_GROUP(scif4_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) SH_PFC_PIN_GROUP(scif4_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) SH_PFC_PIN_GROUP(scif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) SH_PFC_PIN_GROUP(scif4_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) SH_PFC_PIN_GROUP(scif4_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) SH_PFC_PIN_GROUP(scif5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) SH_PFC_PIN_GROUP(scif5_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) SH_PFC_PIN_GROUP(scif_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) SH_PFC_PIN_GROUP(sdhi2_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) SH_PFC_PIN_GROUP(sdhi2_cd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) SH_PFC_PIN_GROUP(sdhi2_wp_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) SH_PFC_PIN_GROUP(sdhi2_cd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) SH_PFC_PIN_GROUP(sdhi2_wp_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) SH_PFC_PIN_GROUP(sdhi2_ds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) SH_PFC_PIN_GROUP(sdhi3_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) SH_PFC_PIN_GROUP(sdhi3_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) SH_PFC_PIN_GROUP(sdhi3_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) SH_PFC_PIN_GROUP(sdhi3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) SH_PFC_PIN_GROUP(sdhi3_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) SH_PFC_PIN_GROUP(sdhi3_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) SH_PFC_PIN_GROUP(sdhi3_ds),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) SH_PFC_PIN_GROUP(ssi0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) SH_PFC_PIN_GROUP(ssi01239_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) SH_PFC_PIN_GROUP(ssi1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) SH_PFC_PIN_GROUP(ssi1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) SH_PFC_PIN_GROUP(ssi1_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) SH_PFC_PIN_GROUP(ssi1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) SH_PFC_PIN_GROUP(ssi2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) SH_PFC_PIN_GROUP(ssi2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) SH_PFC_PIN_GROUP(ssi2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) SH_PFC_PIN_GROUP(ssi2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) SH_PFC_PIN_GROUP(ssi349_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) SH_PFC_PIN_GROUP(ssi4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) SH_PFC_PIN_GROUP(ssi4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) SH_PFC_PIN_GROUP(ssi5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) SH_PFC_PIN_GROUP(ssi5_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) SH_PFC_PIN_GROUP(ssi6_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) SH_PFC_PIN_GROUP(ssi6_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) SH_PFC_PIN_GROUP(ssi7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) SH_PFC_PIN_GROUP(ssi78_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) SH_PFC_PIN_GROUP(ssi8_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) SH_PFC_PIN_GROUP(ssi9_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) SH_PFC_PIN_GROUP(ssi9_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) SH_PFC_PIN_GROUP(ssi9_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) SH_PFC_PIN_GROUP(ssi9_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) SH_PFC_PIN_GROUP(tmu_tclk1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) SH_PFC_PIN_GROUP(tmu_tclk1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) SH_PFC_PIN_GROUP(tmu_tclk2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) SH_PFC_PIN_GROUP(tmu_tclk2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) SH_PFC_PIN_GROUP(tpu_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) SH_PFC_PIN_GROUP(tpu_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) SH_PFC_PIN_GROUP(tpu_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) SH_PFC_PIN_GROUP(tpu_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) SH_PFC_PIN_GROUP(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) SH_PFC_PIN_GROUP(usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) SH_PFC_PIN_GROUP(usb30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) SH_PFC_PIN_GROUP(usb31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) "audio_clk_a_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) "audio_clk_a_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) "audio_clk_a_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) "audio_clk_b_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) "audio_clk_b_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) "audio_clk_c_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) "audio_clk_c_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) "audio_clkout_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) "audio_clkout_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) "audio_clkout_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) "audio_clkout_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) "audio_clkout1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) "audio_clkout1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) "audio_clkout2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) "audio_clkout2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) "audio_clkout3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) "audio_clkout3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) "avb_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) "avb_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) "avb_avtp_pps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) "avb_avtp_match_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) "avb_avtp_capture_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) "avb_avtp_match_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) "avb_avtp_capture_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) "can0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) "can0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) "can1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) static const char * const can_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) static const char * const canfd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) "canfd0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) "canfd0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) static const char * const canfd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) "canfd1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) static const char * const drif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) "drif0_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) "drif0_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) "drif0_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) "drif0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) "drif0_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) "drif0_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) "drif0_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) "drif0_data0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) "drif0_data1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) static const char * const drif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) "drif1_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) "drif1_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) "drif1_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) "drif1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) "drif1_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) "drif1_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) "drif1_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) "drif1_data0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) "drif1_data1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) static const char * const drif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) "drif2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) "drif2_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) "drif2_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) "drif2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) "drif2_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) "drif2_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) static const char * const drif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) "drif3_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) "drif3_data0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) "drif3_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) "drif3_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) "drif3_data0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) "drif3_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) "du_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) "du_clk_out_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) "du_clk_out_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) "du_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) "du_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) "du_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) "hscif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) "hscif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) "hscif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) "hscif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) "hscif1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) "hscif1_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) "hscif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) "hscif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) "hscif1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) static const char * const hscif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) "hscif2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) "hscif2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) "hscif2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) "hscif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) "hscif2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) "hscif2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) static const char * const hscif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) "hscif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) "hscif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) "hscif3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) "hscif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) "hscif3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) "hscif3_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) static const char * const hscif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) "hscif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) "hscif4_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) "hscif4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) "hscif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) "i2c1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) "i2c2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) static const char * const i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) "i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) static const char * const i2c6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) "i2c6_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) "i2c6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) "i2c6_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) static const char * const intc_ex_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) "intc_ex_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) "intc_ex_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) "intc_ex_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) "intc_ex_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) "intc_ex_irq4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) "intc_ex_irq5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) "msiof0_txd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) "msiof0_rxd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) "msiof1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) "msiof1_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) "msiof1_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) "msiof1_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) "msiof1_txd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) "msiof1_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) "msiof1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) "msiof1_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) "msiof1_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) "msiof1_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) "msiof1_txd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) "msiof1_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) "msiof1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) "msiof1_sync_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) "msiof1_ss1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) "msiof1_ss2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) "msiof1_txd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) "msiof1_rxd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) "msiof1_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) "msiof1_sync_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) "msiof1_ss1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) "msiof1_ss2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) "msiof1_txd_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) "msiof1_rxd_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) "msiof1_clk_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) "msiof1_sync_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) "msiof1_ss1_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) "msiof1_ss2_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) "msiof1_txd_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) "msiof1_rxd_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) "msiof1_clk_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) "msiof1_sync_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) "msiof1_ss1_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) "msiof1_ss2_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) "msiof1_txd_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) "msiof1_rxd_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) "msiof1_clk_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) "msiof1_sync_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) "msiof1_ss1_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) "msiof1_ss2_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) "msiof1_txd_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) "msiof1_rxd_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) "msiof2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) "msiof2_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) "msiof2_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) "msiof2_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) "msiof2_txd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) "msiof2_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) "msiof2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) "msiof2_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) "msiof2_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) "msiof2_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) "msiof2_txd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) "msiof2_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) "msiof2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) "msiof2_sync_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) "msiof2_ss1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) "msiof2_ss2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) "msiof2_txd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) "msiof2_rxd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) "msiof2_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) "msiof2_sync_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) "msiof2_ss1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) "msiof2_ss2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) "msiof2_txd_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) "msiof2_rxd_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) "msiof3_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) "msiof3_sync_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) "msiof3_ss1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) "msiof3_ss2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) "msiof3_txd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) "msiof3_rxd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) "msiof3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) "msiof3_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) "msiof3_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) "msiof3_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) "msiof3_txd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) "msiof3_rxd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) "msiof3_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) "msiof3_sync_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) "msiof3_txd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) "msiof3_rxd_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) "msiof3_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) "msiof3_sync_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) "msiof3_ss1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) "msiof3_txd_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) "msiof3_rxd_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) "pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) "pwm1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) "pwm2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) "pwm3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) "pwm3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) "pwm4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) "pwm4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) "pwm5_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) "pwm5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) static const char * const pwm6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) "pwm6_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) "pwm6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) static const char * const qspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) "qspi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) "qspi0_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) "qspi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) static const char * const qspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) "qspi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) "qspi1_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) "qspi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) static const char * const sata0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) "sata0_devslp_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) "sata0_devslp_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) "scif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) "scif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) "scif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) "scif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) "scif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) "scif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) "scif2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) "scif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) "scif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) "scif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) "scif3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) "scif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) "scif4_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) "scif4_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) "scif4_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) "scif4_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) "scif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) "scif4_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) "scif4_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) "scif5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) "scif5_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) "scif_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) "sdhi2_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) "sdhi2_cd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) "sdhi2_wp_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) "sdhi2_cd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) "sdhi2_wp_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) "sdhi2_ds",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) static const char * const sdhi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) "sdhi3_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) "sdhi3_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) "sdhi3_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) "sdhi3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) "sdhi3_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) "sdhi3_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) "sdhi3_ds",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) "ssi0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) "ssi01239_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) "ssi1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) "ssi1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) "ssi1_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) "ssi1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) "ssi2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) "ssi2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) "ssi2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) "ssi2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) "ssi349_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) "ssi4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) "ssi4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) "ssi5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) "ssi5_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) "ssi6_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) "ssi6_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) "ssi7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) "ssi78_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) "ssi8_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) "ssi9_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) "ssi9_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) "ssi9_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) "ssi9_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) static const char * const tmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) "tmu_tclk1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) "tmu_tclk1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) "tmu_tclk2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) "tmu_tclk2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) static const char * const tpu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) "tpu_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) "tpu_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) "tpu_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) "tpu_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) static const char * const usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) static const char * const usb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) static const char * const usb30_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) "usb30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) static const char * const usb31_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) "usb31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) SH_PFC_FUNCTION(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) SH_PFC_FUNCTION(canfd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) SH_PFC_FUNCTION(canfd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) SH_PFC_FUNCTION(drif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) SH_PFC_FUNCTION(drif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) SH_PFC_FUNCTION(drif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) SH_PFC_FUNCTION(drif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) SH_PFC_FUNCTION(hscif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) SH_PFC_FUNCTION(hscif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) SH_PFC_FUNCTION(hscif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) SH_PFC_FUNCTION(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) SH_PFC_FUNCTION(i2c6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) SH_PFC_FUNCTION(intc_ex),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) SH_PFC_FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) SH_PFC_FUNCTION(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) SH_PFC_FUNCTION(qspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) SH_PFC_FUNCTION(qspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) SH_PFC_FUNCTION(sata0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) SH_PFC_FUNCTION(sdhi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) SH_PFC_FUNCTION(tmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) SH_PFC_FUNCTION(tpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) SH_PFC_FUNCTION(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) SH_PFC_FUNCTION(usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) SH_PFC_FUNCTION(usb30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) SH_PFC_FUNCTION(usb31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) #define F_(x, y) FN_##y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) #define FM(x) FN_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) GP_0_15_FN, GPSR0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) GP_0_14_FN, GPSR0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) GP_0_13_FN, GPSR0_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) GP_0_12_FN, GPSR0_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) GP_0_11_FN, GPSR0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) GP_0_10_FN, GPSR0_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) GP_0_9_FN, GPSR0_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) GP_0_8_FN, GPSR0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) GP_0_7_FN, GPSR0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) GP_0_6_FN, GPSR0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) GP_0_5_FN, GPSR0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) GP_0_4_FN, GPSR0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) GP_0_3_FN, GPSR0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) GP_0_2_FN, GPSR0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) GP_0_1_FN, GPSR0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) GP_0_0_FN, GPSR0_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) GP_1_27_FN, GPSR1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) GP_1_26_FN, GPSR1_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) GP_1_25_FN, GPSR1_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) GP_1_24_FN, GPSR1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) GP_1_23_FN, GPSR1_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) GP_1_22_FN, GPSR1_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) GP_1_21_FN, GPSR1_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) GP_1_20_FN, GPSR1_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) GP_1_19_FN, GPSR1_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) GP_1_18_FN, GPSR1_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) GP_1_17_FN, GPSR1_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) GP_1_16_FN, GPSR1_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) GP_1_15_FN, GPSR1_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) GP_1_14_FN, GPSR1_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) GP_1_13_FN, GPSR1_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) GP_1_12_FN, GPSR1_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) GP_1_11_FN, GPSR1_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) GP_1_10_FN, GPSR1_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) GP_1_9_FN, GPSR1_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) GP_1_8_FN, GPSR1_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) GP_1_7_FN, GPSR1_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) GP_1_6_FN, GPSR1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) GP_1_5_FN, GPSR1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) GP_1_4_FN, GPSR1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) GP_1_3_FN, GPSR1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) GP_1_2_FN, GPSR1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) GP_1_1_FN, GPSR1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) GP_1_0_FN, GPSR1_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) GP_2_14_FN, GPSR2_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) GP_2_13_FN, GPSR2_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) GP_2_12_FN, GPSR2_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) GP_2_11_FN, GPSR2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) GP_2_10_FN, GPSR2_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) GP_2_9_FN, GPSR2_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) GP_2_8_FN, GPSR2_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) GP_2_7_FN, GPSR2_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) GP_2_6_FN, GPSR2_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) GP_2_5_FN, GPSR2_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) GP_2_4_FN, GPSR2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) GP_2_3_FN, GPSR2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) GP_2_2_FN, GPSR2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) GP_2_1_FN, GPSR2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) GP_2_0_FN, GPSR2_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) GP_3_15_FN, GPSR3_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) GP_3_14_FN, GPSR3_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) GP_3_13_FN, GPSR3_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) GP_3_12_FN, GPSR3_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) GP_3_11_FN, GPSR3_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) GP_3_10_FN, GPSR3_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) GP_3_9_FN, GPSR3_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) GP_3_8_FN, GPSR3_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) GP_3_7_FN, GPSR3_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) GP_3_6_FN, GPSR3_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) GP_3_5_FN, GPSR3_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) GP_3_4_FN, GPSR3_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) GP_3_3_FN, GPSR3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) GP_3_2_FN, GPSR3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) GP_3_1_FN, GPSR3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) GP_3_0_FN, GPSR3_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) GP_4_17_FN, GPSR4_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) GP_4_16_FN, GPSR4_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) GP_4_15_FN, GPSR4_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) GP_4_14_FN, GPSR4_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) GP_4_13_FN, GPSR4_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) GP_4_12_FN, GPSR4_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) GP_4_11_FN, GPSR4_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) GP_4_10_FN, GPSR4_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) GP_4_9_FN, GPSR4_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) GP_4_8_FN, GPSR4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) GP_4_7_FN, GPSR4_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) GP_4_6_FN, GPSR4_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) GP_4_5_FN, GPSR4_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) GP_4_4_FN, GPSR4_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) GP_4_3_FN, GPSR4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) GP_4_2_FN, GPSR4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) GP_4_1_FN, GPSR4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) GP_4_0_FN, GPSR4_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) GP_5_25_FN, GPSR5_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) GP_5_24_FN, GPSR5_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) GP_5_23_FN, GPSR5_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) GP_5_22_FN, GPSR5_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) GP_5_21_FN, GPSR5_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) GP_5_20_FN, GPSR5_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) GP_5_19_FN, GPSR5_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) GP_5_18_FN, GPSR5_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) GP_5_17_FN, GPSR5_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) GP_5_16_FN, GPSR5_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) GP_5_15_FN, GPSR5_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) GP_5_14_FN, GPSR5_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) GP_5_13_FN, GPSR5_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) GP_5_12_FN, GPSR5_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) GP_5_11_FN, GPSR5_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) GP_5_10_FN, GPSR5_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) GP_5_9_FN, GPSR5_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) GP_5_8_FN, GPSR5_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) GP_5_7_FN, GPSR5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) GP_5_6_FN, GPSR5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) GP_5_5_FN, GPSR5_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) GP_5_4_FN, GPSR5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) GP_5_3_FN, GPSR5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) GP_5_2_FN, GPSR5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) GP_5_1_FN, GPSR5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) GP_5_0_FN, GPSR5_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) GP_6_31_FN, GPSR6_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) GP_6_30_FN, GPSR6_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) GP_6_29_FN, GPSR6_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) GP_6_28_FN, GPSR6_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) GP_6_27_FN, GPSR6_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) GP_6_26_FN, GPSR6_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) GP_6_25_FN, GPSR6_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) GP_6_24_FN, GPSR6_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) GP_6_23_FN, GPSR6_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) GP_6_22_FN, GPSR6_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) GP_6_21_FN, GPSR6_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) GP_6_20_FN, GPSR6_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) GP_6_19_FN, GPSR6_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) GP_6_18_FN, GPSR6_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) GP_6_17_FN, GPSR6_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) GP_6_16_FN, GPSR6_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) GP_6_15_FN, GPSR6_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) GP_6_14_FN, GPSR6_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) GP_6_13_FN, GPSR6_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) GP_6_12_FN, GPSR6_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) GP_6_11_FN, GPSR6_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) GP_6_10_FN, GPSR6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) GP_6_9_FN, GPSR6_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) GP_6_8_FN, GPSR6_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) GP_6_7_FN, GPSR6_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) GP_6_6_FN, GPSR6_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) GP_6_5_FN, GPSR6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) GP_6_4_FN, GPSR6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) GP_6_3_FN, GPSR6_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) GP_6_2_FN, GPSR6_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) GP_6_1_FN, GPSR6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) GP_6_0_FN, GPSR6_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) GP_7_3_FN, GPSR7_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) GP_7_2_FN, GPSR7_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) GP_7_1_FN, GPSR7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) GP_7_0_FN, GPSR7_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) IP0_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) IP0_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) IP0_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) IP0_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) IP0_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) IP0_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) IP0_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) IP0_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) IP1_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) IP1_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) IP1_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) IP1_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) IP1_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) IP1_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) IP1_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) IP1_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) IP2_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) IP2_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) IP2_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) IP2_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) IP2_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) IP2_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) IP2_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) IP2_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) IP3_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) IP3_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) IP3_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) IP3_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) IP3_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) IP3_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) IP3_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) IP3_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) IP4_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) IP4_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) IP4_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) IP4_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) IP4_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) IP4_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) IP4_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) IP4_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) IP5_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) IP5_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) IP5_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) IP5_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) IP5_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) IP5_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) IP5_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) IP5_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) IP6_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) IP6_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) IP6_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) IP6_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) IP6_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) IP6_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) IP6_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) IP6_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) IP7_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) IP7_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) IP7_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) IP7_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) IP7_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) IP7_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) IP7_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) IP7_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) IP8_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) IP8_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) IP8_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) IP8_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) IP8_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) IP8_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) IP8_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) IP8_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) IP9_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) IP9_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) IP9_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) IP9_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) IP9_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) IP9_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) IP9_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) IP9_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) IP10_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) IP10_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) IP10_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) IP10_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) IP10_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) IP10_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) IP10_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) IP10_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) IP11_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) IP11_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) IP11_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) IP11_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) IP11_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) IP11_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) IP11_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) IP11_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) IP12_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) IP12_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) IP12_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) IP12_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) IP12_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) IP12_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) IP12_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) IP12_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) IP13_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) IP13_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) IP13_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) IP13_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) IP13_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) IP13_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) IP13_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) IP13_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) IP14_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) IP14_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) IP14_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) IP14_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) IP14_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) IP14_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) IP14_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) IP14_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) IP15_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) IP15_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) IP15_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) IP15_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) IP15_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) IP15_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) IP15_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) IP15_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) IP16_31_28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) IP16_27_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) IP16_23_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) IP16_19_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) IP16_15_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) IP16_11_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) IP16_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) IP16_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) IP17_7_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) IP17_3_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) #undef F_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) #undef FM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) #define F_(x, y) x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) #define FM(x) FN_##x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) GROUP(1, 2, 2, 3, 1, 1, 2, 1, 1, 1, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) 0, 0, /* RESERVED 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) MOD_SEL0_30_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) MOD_SEL0_28_27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) MOD_SEL0_26_25_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) MOD_SEL0_23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) MOD_SEL0_22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) MOD_SEL0_21_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) MOD_SEL0_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) MOD_SEL0_18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) MOD_SEL0_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) MOD_SEL0_16_15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) MOD_SEL0_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) MOD_SEL0_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) MOD_SEL0_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) MOD_SEL0_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) MOD_SEL0_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) MOD_SEL0_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) MOD_SEL0_8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) MOD_SEL0_7_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) MOD_SEL0_5_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) MOD_SEL0_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) MOD_SEL0_2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) 0, 0, /* RESERVED 0 */ ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) GROUP(2, 3, 1, 2, 3, 1, 1, 2, 1, 2, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) MOD_SEL1_31_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) MOD_SEL1_29_28_27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) MOD_SEL1_26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) MOD_SEL1_25_24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) MOD_SEL1_23_22_21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) MOD_SEL1_20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) MOD_SEL1_19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) MOD_SEL1_18_17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) MOD_SEL1_16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) MOD_SEL1_15_14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) MOD_SEL1_13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) MOD_SEL1_12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) MOD_SEL1_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) MOD_SEL1_10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) MOD_SEL1_9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) 0, 0, 0, 0, /* RESERVED 8, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) MOD_SEL1_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) MOD_SEL1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) MOD_SEL1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) MOD_SEL1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) MOD_SEL1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) MOD_SEL1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) MOD_SEL1_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) GROUP(1, 1, 1, 1, 4, 4, 4, 4, 4, 4, 1, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) MOD_SEL2_31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) MOD_SEL2_30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) MOD_SEL2_29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) /* RESERVED 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) /* RESERVED 27, 26, 25, 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) /* RESERVED 23, 22, 21, 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) /* RESERVED 19, 18, 17, 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) /* RESERVED 15, 14, 13, 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) /* RESERVED 11, 10, 9, 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) /* RESERVED 7, 6, 5, 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) /* RESERVED 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) /* RESERVED 2, 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) MOD_SEL2_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) static const struct pinmux_drive_reg pinmux_drive_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) { PIN_QSPI0_SPCLK, 28, 2 }, /* QSPI0_SPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) { PIN_QSPI0_MOSI_IO0, 24, 2 }, /* QSPI0_MOSI_IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) { PIN_QSPI0_MISO_IO1, 20, 2 }, /* QSPI0_MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) { PIN_QSPI0_IO2, 16, 2 }, /* QSPI0_IO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) { PIN_QSPI0_IO3, 12, 2 }, /* QSPI0_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) { PIN_QSPI0_SSL, 8, 2 }, /* QSPI0_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) { PIN_QSPI1_SPCLK, 4, 2 }, /* QSPI1_SPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) { PIN_QSPI1_MOSI_IO0, 0, 2 }, /* QSPI1_MOSI_IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) { PIN_QSPI1_MISO_IO1, 28, 2 }, /* QSPI1_MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) { PIN_QSPI1_IO2, 24, 2 }, /* QSPI1_IO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) { PIN_QSPI1_IO3, 20, 2 }, /* QSPI1_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) { PIN_QSPI1_SSL, 16, 2 }, /* QSPI1_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) { PIN_RPC_INT_N, 12, 2 }, /* RPC_INT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) { PIN_RPC_WP_N, 8, 2 }, /* RPC_WP# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) { PIN_RPC_RESET_N, 4, 2 }, /* RPC_RESET# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) { PIN_AVB_RX_CTL, 0, 3 }, /* AVB_RX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) { PIN_AVB_RXC, 28, 3 }, /* AVB_RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) { PIN_AVB_RD0, 24, 3 }, /* AVB_RD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) { PIN_AVB_RD1, 20, 3 }, /* AVB_RD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) { PIN_AVB_RD2, 16, 3 }, /* AVB_RD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) { PIN_AVB_RD3, 12, 3 }, /* AVB_RD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) { PIN_AVB_TX_CTL, 8, 3 }, /* AVB_TX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) { PIN_AVB_TXC, 4, 3 }, /* AVB_TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) { PIN_AVB_TD0, 0, 3 }, /* AVB_TD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) { PIN_AVB_TD1, 28, 3 }, /* AVB_TD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) { PIN_AVB_TD2, 24, 3 }, /* AVB_TD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) { PIN_AVB_TD3, 20, 3 }, /* AVB_TD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) { PIN_AVB_TXCREFCLK, 16, 3 }, /* AVB_TXCREFCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) { PIN_AVB_MDIO, 12, 3 }, /* AVB_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) { PIN_CLKOUT, 28, 3 }, /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) { PIN_PRESETOUT_N, 24, 3 }, /* PRESETOUT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) { RCAR_GP_PIN(7, 2), 12, 3 }, /* GP7_02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) { RCAR_GP_PIN(7, 3), 8, 3 }, /* GP7_03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) { PIN_DU_DOTCLKIN0, 4, 2 }, /* DU_DOTCLKIN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) { PIN_DU_DOTCLKIN1, 0, 2 }, /* DU_DOTCLKIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) { PIN_DU_DOTCLKIN2, 28, 2 }, /* DU_DOTCLKIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) { PIN_DU_DOTCLKIN3, 24, 2 }, /* DU_DOTCLKIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) { PIN_FSCLKST_N, 20, 2 }, /* FSCLKST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) { PIN_TMS, 4, 2 }, /* TMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) { PIN_TDO, 28, 2 }, /* TDO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) { PIN_ASEBRK, 24, 2 }, /* ASEBRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) { PIN_MLB_REF, 4, 3 }, /* MLB_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) enum ioctrl_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) POCCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) TDSELCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) [POCCTRL] = { 0xe6060380, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) [TDSELCTRL] = { 0xe60603c0, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) static int r8a77950_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) int bit = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) bit = pin & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) bit = (pin & 0x1f) + 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) static const struct pinmux_bias_reg pinmux_bias_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) [ 0] = PIN_QSPI0_SPCLK, /* QSPI0_SPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) [ 1] = PIN_QSPI0_MOSI_IO0, /* QSPI0_MOSI_IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) [ 2] = PIN_QSPI0_MISO_IO1, /* QSPI0_MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) [ 3] = PIN_QSPI0_IO2, /* QSPI0_IO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) [ 4] = PIN_QSPI0_IO3, /* QSPI0_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) [ 5] = PIN_QSPI0_SSL, /* QSPI0_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) [ 6] = PIN_QSPI1_SPCLK, /* QSPI1_SPCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) [ 7] = PIN_QSPI1_MOSI_IO0, /* QSPI1_MOSI_IO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) [ 8] = PIN_QSPI1_MISO_IO1, /* QSPI1_MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) [ 9] = PIN_QSPI1_IO2, /* QSPI1_IO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) [10] = PIN_QSPI1_IO3, /* QSPI1_IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) [11] = PIN_QSPI1_SSL, /* QSPI1_SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) [12] = PIN_RPC_INT_N, /* RPC_INT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) [13] = PIN_RPC_WP_N, /* RPC_WP# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) [14] = PIN_RPC_RESET_N, /* RPC_RESET# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) [15] = PIN_AVB_RX_CTL, /* AVB_RX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) [16] = PIN_AVB_RXC, /* AVB_RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) [17] = PIN_AVB_RD0, /* AVB_RD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) [18] = PIN_AVB_RD1, /* AVB_RD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) [19] = PIN_AVB_RD2, /* AVB_RD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) [20] = PIN_AVB_RD3, /* AVB_RD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) [21] = PIN_AVB_TX_CTL, /* AVB_TX_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) [22] = PIN_AVB_TXC, /* AVB_TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) [23] = PIN_AVB_TD0, /* AVB_TD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) [24] = PIN_AVB_TD1, /* AVB_TD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) [25] = PIN_AVB_TD2, /* AVB_TD2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) [26] = PIN_AVB_TD3, /* AVB_TD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) [27] = PIN_AVB_TXCREFCLK, /* AVB_TXCREFCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) [28] = PIN_AVB_MDIO, /* AVB_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) [12] = RCAR_GP_PIN(1, 0), /* A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) [13] = RCAR_GP_PIN(1, 1), /* A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) [14] = RCAR_GP_PIN(1, 2), /* A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) [15] = RCAR_GP_PIN(1, 3), /* A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) [16] = RCAR_GP_PIN(1, 4), /* A4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) [17] = RCAR_GP_PIN(1, 5), /* A5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) [18] = RCAR_GP_PIN(1, 6), /* A6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) [19] = RCAR_GP_PIN(1, 7), /* A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) [20] = RCAR_GP_PIN(1, 8), /* A8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) [21] = RCAR_GP_PIN(1, 9), /* A9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) [22] = RCAR_GP_PIN(1, 10), /* A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) [23] = RCAR_GP_PIN(1, 11), /* A11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) [24] = RCAR_GP_PIN(1, 12), /* A12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) [25] = RCAR_GP_PIN(1, 13), /* A13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) [26] = RCAR_GP_PIN(1, 14), /* A14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) [27] = RCAR_GP_PIN(1, 15), /* A15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) [28] = RCAR_GP_PIN(1, 16), /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) [29] = RCAR_GP_PIN(1, 17), /* A17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) [30] = RCAR_GP_PIN(1, 18), /* A18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) [31] = RCAR_GP_PIN(1, 19), /* A19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) [ 0] = PIN_CLKOUT, /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N_A26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) [ 9] = PIN_PRESETOUT_N, /* PRESETOUT# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) [10] = RCAR_GP_PIN(0, 0), /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) [11] = RCAR_GP_PIN(0, 1), /* D1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) [12] = RCAR_GP_PIN(0, 2), /* D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) [13] = RCAR_GP_PIN(0, 3), /* D3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) [14] = RCAR_GP_PIN(0, 4), /* D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) [15] = RCAR_GP_PIN(0, 5), /* D5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) [16] = RCAR_GP_PIN(0, 6), /* D6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) [17] = RCAR_GP_PIN(0, 7), /* D7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) [18] = RCAR_GP_PIN(0, 8), /* D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) [19] = RCAR_GP_PIN(0, 9), /* D9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) [20] = RCAR_GP_PIN(0, 10), /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) [21] = RCAR_GP_PIN(0, 11), /* D11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) [22] = RCAR_GP_PIN(0, 12), /* D12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) [23] = RCAR_GP_PIN(0, 13), /* D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) [24] = RCAR_GP_PIN(0, 14), /* D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) [25] = RCAR_GP_PIN(0, 15), /* D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) [28] = RCAR_GP_PIN(7, 2), /* GP7_02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) [29] = RCAR_GP_PIN(7, 3), /* GP7_03 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) [30] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) [31] = PIN_DU_DOTCLKIN1, /* DU_DOTCLKIN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) [ 0] = PIN_DU_DOTCLKIN2, /* DU_DOTCLKIN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) [ 1] = PIN_DU_DOTCLKIN3, /* DU_DOTCLKIN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) [ 2] = PIN_FSCLKST_N, /* FSCLKST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) [ 3] = PIN_EXTALR, /* EXTALR*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) [ 4] = PIN_TRST_N, /* TRST# */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) [ 5] = PIN_TCK, /* TCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) [ 6] = PIN_TMS, /* TMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) [ 7] = PIN_TDI, /* TDI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) [ 8] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) [ 9] = PIN_ASEBRK, /* ASEBRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) [13] = RCAR_GP_PIN(5, 1), /* RX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) [14] = RCAR_GP_PIN(5, 2), /* TX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) [ 6] = PIN_MLB_REF, /* MLB_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) [ 5] = RCAR_GP_PIN(6, 30), /* USB31_PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) [ 6] = RCAR_GP_PIN(6, 31), /* USB31_OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) [ 7] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) [ 8] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) [ 9] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) [10] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) [11] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) [12] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) [13] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) [14] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) [15] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) [16] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) [17] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) [18] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) [19] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) [20] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) [21] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) [22] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) [23] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) [24] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) [25] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) [26] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) [27] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) [28] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) [29] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) [30] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) [31] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) static unsigned int r8a77950_pinmux_get_bias(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) const struct pinmux_bias_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) return PIN_CONFIG_BIAS_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) return PIN_CONFIG_BIAS_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) static void r8a77950_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) unsigned int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) const struct pinmux_bias_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) u32 enable, updown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) if (bias != PIN_CONFIG_BIAS_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) enable |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) if (bias == PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) updown |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) sh_pfc_write(pfc, reg->pud, updown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) sh_pfc_write(pfc, reg->puen, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) static const struct sh_pfc_soc_operations r8a77950_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) .pin_to_pocctrl = r8a77950_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) .get_bias = r8a77950_pinmux_get_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) .set_bias = r8a77950_pinmux_set_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) const struct sh_pfc_soc_info r8a77950_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) .name = "r8a77950_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) .ops = &r8a77950_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) .drive_regs = pinmux_drive_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) .bias_regs = pinmux_bias_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) .ioctrl_regs = pinmux_ioctrl_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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