^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7794/r8a7745 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2015 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2015-2017 Cogent Embedded, Inc. <source@cogentembedded.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_GP_32(0, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_GP_26(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_GP_32(2, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_GP_32(3, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_GP_32(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_28(5, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_1(6, 24, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_1(6, 25, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) FN_IP2_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FN_IP6_5_4, FN_IP6_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FN_IP8_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* GPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_D13, FN_SCIFA1_SCK, FN_PWM2_C, FN_TCLK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FN_A0, FN_SCIFB1_SCK, FN_PWM3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FN_A1, FN_SCIFB1_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FN_A3, FN_SCIFB0_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_A4, FN_SCIFB0_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_CAN_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FN_TPUTO2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FN_A20, FN_SPCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FN_A21, FN_MOSI_IO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FN_A22, FN_MISO_IO1, FN_ATADIR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FN_A23, FN_IO2, FN_ATAWR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FN_A24, FN_IO3, FN_EX_WAIT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FN_A25, FN_SSL, FN_ATARD1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FN_CS0_N, FN_VI1_DATA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FN_CS1_N_A26, FN_VI1_DATA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FN_EX_CS0_N, FN_VI1_DATA10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_TPUTO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FN_SCIFB2_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B, FN_BPFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FN_SCIFB2_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_FMCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FN_SCIFB2_CTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B, FN_FMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FN_SCIFB2_RTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FN_RD_N, FN_ATACS11_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FN_RD_WR_N, FN_ATAG1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FN_DU0_DR2, FN_LCDOUT18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FN_DU0_DR3, FN_LCDOUT19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FN_DU0_DR4, FN_LCDOUT20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FN_DU0_DR5, FN_LCDOUT21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FN_DU0_DR6, FN_LCDOUT22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FN_DU0_DR7, FN_LCDOUT23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FN_DU0_DG2, FN_LCDOUT10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FN_DU0_DG3, FN_LCDOUT11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FN_DU0_DG4, FN_LCDOUT12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FN_DU0_DG5, FN_LCDOUT13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FN_DU0_DG6, FN_LCDOUT14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FN_DU0_DG7, FN_LCDOUT15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D, FN_CAN0_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) FN_DU0_DB2, FN_LCDOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FN_DU0_DB3, FN_LCDOUT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FN_DU0_DB4, FN_LCDOUT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FN_DU0_DB5, FN_LCDOUT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FN_DU0_DB6, FN_LCDOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FN_DU0_DB7, FN_LCDOUT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FN_DU0_DOTCLKOUT0, FN_QCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) FN_DU0_DISP, FN_QPOLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FN_DU0_CDE, FN_QPOLB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) FN_VI0_CLK, FN_AVB_RX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FN_AVB_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D, FN_AVB_TX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FN_ADIDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D, FN_AVB_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FN_ADICS_SAMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, FN_AVB_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FN_ADICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) FN_ADICHS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FN_ADICHS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, FN_AVB_TXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FN_ADICHS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, FN_SSI_SCK5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D, FN_AVB_TXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FN_SSI_WS5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D, FN_AVB_TXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FN_SSI_SDATA5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FN_SSI_WS6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FN_DREQ0_N, FN_SCIFB1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FN_SSI_SDATA6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, FN_AVB_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FN_SSI_SCK78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FN_SSI_WS78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FN_AVB_MAGIC, FN_SSI_SDATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FN_CAN1_RX_D, FN_TPUTO0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, FN_DVC_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) FN_CAN1_TX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, FN_TS_SDATA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FN_TPUTO1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_TS_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, FN_TS_SDEN_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FN_FMCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_TS_SPSYNC_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FN_FMIN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4, FN_TPUTO1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_BPFCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_FMCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7, FN_FMIN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FN_SPEEDIN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3, FN_SSI_SCK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5, FN_SSI_SDATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3, FN_SSI_SDATA9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FN_SSI_SCK4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FN_SSI_WS4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) FN_SSI_SDATA4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FN_DREQ1_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FN_CAN1_RX_C, FN_DACK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FN_CAN1_TX_C, FN_DREQ2_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9, FN_REMOCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FN_DACK2, FN_ETH_MDIO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FN_ETH_CRS_DV_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FN_ETH_RX_ER_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_ATAWR0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FN_ETH_RXD0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_ATAG0_N, FN_ETH_RXD1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FN_ATACS00_N, FN_ETH_LINK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D, FN_VI1_DATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FN_ATACS10_N, FN_ETH_REFCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_EX_WAIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FN_ETH_TXD1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6, FN_ATARD0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FN_ETH_TX_EN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) FN_ATADIR0_N, FN_ETH_MAGIC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) FN_TS_SDATA_C, FN_ETH_TXD0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) FN_TS_SCK_C, FN_BPFCLK_E, FN_ETH_MDC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FN_TS_SDEN_C, FN_FMCLK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FN_TS_SPSYNC_C, FN_FMIN_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* MOD_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) FN_SEL_DARC_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FN_SEL_ETH_0, FN_SEL_ETH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) FN_SEL_I2C00_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FN_SEL_I2C01_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FN_SEL_I2C02_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) FN_SEL_I2C03_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) FN_SEL_I2C04_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* MOD_SEL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FN_SEL_MSI2_0, FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FN_SEL_RCN_0, FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) FN_SEL_TMU_0, FN_SEL_TMU_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* MOD_SEL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FN_SEL_SSI9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) SD1_DATA2_MARK, SD1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) D7_MARK, IRQ3_MARK, TCLK1_MARK, PWM6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) D10_MARK, HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) D13_MARK, SCIFA1_SCK_MARK, PWM2_C_MARK, TCLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) D14_MARK, SCIFA1_RXD_MARK, I2C5_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) D15_MARK, SCIFA1_TXD_MARK, I2C5_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) A1_MARK, SCIFB1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) A3_MARK, SCIFB0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) A4_MARK, SCIFB0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) A6_MARK, SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) A8_MARK, MSIOF1_RXD_MARK, SCIFA0_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) A10_MARK, MSIOF1_SCK_MARK, IIC0_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) A11_MARK, MSIOF1_SYNC_MARK, IIC0_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) A14_MARK, MSIOF2_RXD_MARK, HSCIF0_HRX_B_MARK, DREQ1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) A15_MARK, MSIOF2_TXD_MARK, HSCIF0_HTX_B_MARK, DACK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) A16_MARK, MSIOF2_SCK_MARK, HSCIF0_HSCK_B_MARK, SPEEDIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) CAN_CLK_C_MARK, TPUTO2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK, CAN1_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) A18_MARK, MSIOF2_SS1_MARK, SCIF4_TXD_E_MARK, CAN1_TX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) A19_MARK, MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) A20_MARK, SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) A21_MARK, MOSI_IO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) A22_MARK, MISO_IO1_MARK, ATADIR1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) A23_MARK, IO2_MARK, ATAWR1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) A24_MARK, IO3_MARK, EX_WAIT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) A25_MARK, SSL_MARK, ATARD1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) CS0_N_MARK, VI1_DATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) CS1_N_A26_MARK, VI1_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) EX_CS0_N_MARK, VI1_DATA10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) EX_CS1_N_MARK, TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) EX_CS2_N_MARK, PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) TPUTO3_MARK, SCIFB2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) EX_CS3_N_MARK, SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) BPFCLK_MARK, SCIFB2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) EX_CS4_N_MARK, SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) FMCLK_MARK, SCIFB2_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) EX_CS5_N_MARK, SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) FMIN_MARK, SCIFB2_RTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) BS_N_MARK, DRACK0_MARK, PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) RD_N_MARK, ATACS11_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RD_WR_N_MARK, ATAG1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK, I2C2_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DU0_DR2_MARK, LCDOUT18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DU0_DR3_MARK, LCDOUT19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DU0_DR4_MARK, LCDOUT20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DU0_DR5_MARK, LCDOUT21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DU0_DR6_MARK, LCDOUT22_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DU0_DR7_MARK, LCDOUT23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK, I2C3_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DU0_DG2_MARK, LCDOUT10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DU0_DG3_MARK, LCDOUT11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DU0_DG4_MARK, LCDOUT12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DU0_DG5_MARK, LCDOUT13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DU0_DG6_MARK, LCDOUT14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DU0_DG7_MARK, LCDOUT15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK, I2C4_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) CAN0_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DU0_DB1_MARK, LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) CAN0_TX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DU0_DB2_MARK, LCDOUT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DU0_DB3_MARK, LCDOUT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DU0_DB4_MARK, LCDOUT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DU0_DB5_MARK, LCDOUT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DU0_DB6_MARK, LCDOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DU0_DB7_MARK, LCDOUT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DU0_DOTCLKIN_MARK, QSTVA_QVS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DU0_DOTCLKOUT0_MARK, QCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DU0_DISP_MARK, QPOLA_MARK, DU0_CDE_MARK, QPOLB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) VI0_DATA3_VI0_B3_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) VI0_DATA6_VI0_B6_MARK, AVB_RXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) VI0_CLKENB_MARK, I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) AVB_RXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) AVB_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, IERX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, I2C0_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ETH_MDIO_MARK, VI0_G0_MARK, MSIOF2_RXD_B_MARK, I2C5_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) AVB_TX_CLK_MARK, ADIDATA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, I2C5_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) AVB_TXD0_MARK, ADICS_SAMP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ETH_RX_ER_MARK, VI0_G2_MARK, MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) AVB_TXD1_MARK, ADICLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, CAN0_TX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) AVB_TXD2_MARK, ADICHS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) AVB_TXD3_MARK, ADICHS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ETH_LINK_MARK, VI0_G5_MARK, MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) AVB_TXD4_MARK, ADICHS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) SSI_SCK5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, IIC0_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) AVB_TXD6_MARK, SSI_WS5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ETH_TX_EN_MARK, VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC0_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) AVB_TXD7_MARK, SSI_SDATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, AVB_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SSI_SCK6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ETH_TXD0_MARK, VI0_R2_MARK, SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DREQ0_N_MARK, SCIFB1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) CAN1_TX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, DU1_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) TS_SDATA_D_MARK, TPUTO1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, TS_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) BPFCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MSIOF0_RXD_MARK, SCIF5_RXD_MARK, I2C2_SCL_C_MARK, DU1_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) TS_SDEN_D_MARK, FMCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) TS_SPSYNC_D_MARK, FMIN_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, TPUTO1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK, BPFCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MSIOF0_SS1_MARK, SCIFA0_RXD_MARK, TS_SDEN_MARK, DU1_DR6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) FMCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) FMIN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) HSCIF1_HRX_MARK, I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) HSCIF1_HTX_MARK, I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) HSCIF1_HSCK_MARK, PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SPEEDIN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK, DU1_DG3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SSI_SCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) SSI_WS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) CAN_TXCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SCIF1_RXD_MARK, I2C5_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SCIF1_TXD_MARK, I2C5_SDA_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SCIF2_RXD_MARK, IIC0_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SCIF2_TXD_MARK, IIC0_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SCIF2_SCK_MARK, IRQ1_MARK, DU1_DB2_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK, DU1_DB3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SSI_SDATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK, DU1_DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SSI_SDATA4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) I2C2_SDA_MARK, SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, DU1_DOTCLKOUT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SSI_SCK6_MARK, SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) DU1_EXVSYNC_DU1_VSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) SSI_SDATA6_MARK, SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, I2C5_SDA_C_MARK, DU1_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SSI_WS78_MARK, SCIFA2_RXD_B_MARK, I2C5_SCL_C_MARK, DU1_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) CAN_CLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) SSI_SCK0129_MARK, MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, ADICS_SAMP_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, PWM0_B_MARK, ADICLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DREQ1_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SSI_WS34_MARK, MSIOF1_SS1_B_MARK, SCIFA1_RXD_C_MARK, ADICHS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) CAN1_RX_C_MARK, DACK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) CAN1_TX_C_MARK, DREQ2_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) DACK2_MARK, ETH_MDIO_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SSI_SCK1_MARK, SCIF1_RXD_B_MARK, IIC0_SCL_C_MARK, VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) CAN0_RX_D_MARK, ETH_CRS_DV_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC0_SDA_C_MARK, VI1_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) CAN0_TX_D_MARK, ETH_RX_ER_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, ATAWR0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ETH_RXD0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SSI_SCK2_MARK, HSCIF1_HTX_B_MARK, VI1_DATA2_MARK, ATAG0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ETH_RXD1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ATACS00_N_MARK, ETH_LINK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SSI_SDATA2_MARK, HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) VI1_DATA4_MARK, ATACS10_N_MARK, ETH_REFCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SSI_SCK9_MARK, SCIF2_SCK_B_MARK, PWM2_B_MARK, VI1_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) EX_WAIT1_MARK, ETH_TXD1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK, VI1_DATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ATARD0_N_MARK, ETH_TX_EN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SSI_SDATA9_MARK, SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ATADIR0_N_MARK, ETH_MAGIC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK, VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) TS_SDATA_C_MARK, ETH_TXD0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) TS_SCK_C_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) TS_SDEN_C_MARK, FMCLK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) TS_SPSYNC_C_MARK, FMIN_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_SINGLE(A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_SINGLE(WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_SINGLE(WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_SINGLE(DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_SINGLE(USB0_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_SINGLE(USB0_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_SINGLE(USB1_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_SINGLE(USB1_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_SINGLE(SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINMUX_SINGLE(SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_SINGLE(SD0_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_SINGLE(SD0_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_SINGLE(SD0_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_SINGLE(SD0_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_SINGLE(SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_SINGLE(SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_SINGLE(SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_SINGLE(SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_SINGLE(SD1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_SINGLE(SD1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_SINGLE(SD1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_SINGLE(SD1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_IPSR_GPSR(IP0_23_22, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_GPSR(IP0_24, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_IPSR_GPSR(IP0_25, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_GPSR(IP0_27_26, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_IPSR_GPSR(IP0_29_28, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_GPSR(IP0_31_30, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_IPSR_GPSR(IP1_1_0, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_GPSR(IP1_3_2, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_GPSR(IP1_5_4, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_GPSR(IP1_7_6, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_GPSR(IP1_10_8, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_GPSR(IP1_12_11, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_GPSR(IP1_14_13, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_IPSR_GPSR(IP1_17_15, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_GPSR(IP1_19_18, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_IPSR_MSEL(IP1_19_18, I2C5_SCL_B, SEL_I2C05_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_GPSR(IP1_21_20, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_IPSR_MSEL(IP1_21_20, I2C5_SDA_B, SEL_I2C05_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_IPSR_GPSR(IP1_23_22, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_GPSR(IP1_24, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP1_26, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_GPSR(IP1_27, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_IPSR_GPSR(IP1_29_28, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_IPSR_GPSR(IP1_31_30, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_IPSR_GPSR(IP2_1_0, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_GPSR(IP2_3_2, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_IPSR_GPSR(IP2_5_4, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_GPSR(IP2_7_6, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_MSEL(IP2_7_6, IIC0_SCL_B, SEL_IIC0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP2_9_8, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_MSEL(IP2_9_8, IIC0_SDA_B, SEL_IIC0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP2_11_10, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP2_13_12, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP2_15_14, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP2_17_16, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_GPSR(IP2_20_18, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_GPSR(IP2_23_21, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_GPSR(IP2_26_24, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_GPSR(IP2_29_27, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_GPSR(IP2_31_30, A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_GPSR(IP3_1_0, A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_GPSR(IP3_3_2, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP3_5_4, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_GPSR(IP3_5_4, IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_GPSR(IP3_7_6, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_GPSR(IP3_7_6, IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_GPSR(IP3_9_8, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_GPSR(IP3_9_8, SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_GPSR(IP3_10, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_GPSR(IP3_30, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_IPSR_MSEL(IP6_31_29, I2C5_SCL_D, SEL_I2C05_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_IPSR_MSEL(IP7_2_0, I2C5_SDA_D, SEL_I2C05_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_IPSR_MSEL(IP7_20_18, IIC0_SCL_D, SEL_IIC0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_MSEL(IP7_23_21, IIC0_SDA_D, SEL_IIC0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_IPSR_MSEL(IP10_2_0, I2C5_SCL, SEL_I2C05_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_MSEL(IP10_5_3, I2C5_SDA, SEL_I2C05_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_MSEL(IP10_8_6, IIC0_SCL, SEL_IIC0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_MSEL(IP10_11_9, IIC0_SDA, SEL_IIC0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINMUX_IPSR_MSEL(IP11_15_14, I2C5_SDA_C, SEL_I2C05_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINMUX_IPSR_MSEL(IP11_17_16, I2C5_SCL_C, SEL_I2C05_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINMUX_IPSR_MSEL(IP12_20_18, IIC0_SCL_C, SEL_IIC0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINMUX_IPSR_MSEL(IP12_23_21, IIC0_SDA_C, SEL_IIC0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINMUX_IPSR_GPSR(IP12_26_24, ATAWR0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINMUX_IPSR_GPSR(IP12_29_27, ATAG0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* - Audio Clock ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) static const unsigned int audio_clka_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static const unsigned int audio_clka_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static const unsigned int audio_clka_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) RCAR_GP_PIN(3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static const unsigned int audio_clka_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) AUDIO_CLKA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static const unsigned int audio_clka_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) /* CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) static const unsigned int audio_clka_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) AUDIO_CLKA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) static const unsigned int audio_clka_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) /* CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) static const unsigned int audio_clka_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) AUDIO_CLKA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static const unsigned int audio_clkb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* CLKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static const unsigned int audio_clkb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) AUDIO_CLKB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) static const unsigned int audio_clkb_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* CLKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static const unsigned int audio_clkb_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) AUDIO_CLKB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned int audio_clkb_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* CLKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static const unsigned int audio_clkb_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) AUDIO_CLKB_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static const unsigned int audio_clkc_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* CLKC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) RCAR_GP_PIN(5, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) static const unsigned int audio_clkc_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) AUDIO_CLKC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const unsigned int audio_clkc_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* CLKC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned int audio_clkc_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) AUDIO_CLKC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const unsigned int audio_clkc_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* CLKC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const unsigned int audio_clkc_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) AUDIO_CLKC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const unsigned int audio_clkout_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const unsigned int audio_clkout_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) AUDIO_CLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const unsigned int audio_clkout_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static const unsigned int audio_clkout_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) AUDIO_CLKOUT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static const unsigned int audio_clkout_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static const unsigned int audio_clkout_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) AUDIO_CLKOUT_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* - AVB -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int avb_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const unsigned int avb_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) AVB_MDC_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static const unsigned int avb_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const unsigned int avb_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) AVB_TXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) AVB_RXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) AVB_TX_CLK_MARK, AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const unsigned int avb_gmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static const unsigned int avb_gmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) AVB_TXD6_MARK, AVB_TXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) AVB_RXD6_MARK, AVB_RXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) /* - CAN -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static const unsigned int can0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) RCAR_GP_PIN(6, 15), RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static const unsigned int can0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) CAN0_TX_MARK, CAN0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const unsigned int can0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) static const unsigned int can0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) CAN0_TX_B_MARK, CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static const unsigned int can0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static const unsigned int can0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) CAN0_TX_C_MARK, CAN0_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const unsigned int can0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) static const unsigned int can0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) CAN0_TX_D_MARK, CAN0_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) static const unsigned int can1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static const unsigned int can1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) CAN1_TX_MARK, CAN1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static const unsigned int can1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static const unsigned int can1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) CAN1_TX_B_MARK, CAN1_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static const unsigned int can1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static const unsigned int can1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) CAN1_TX_C_MARK, CAN1_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned int can1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static const unsigned int can1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) CAN1_TX_D_MARK, CAN1_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static const unsigned int can_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const unsigned int can_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static const unsigned int can_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static const unsigned int can_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) CAN_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static const unsigned int can_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int can_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) CAN_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const unsigned int can_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const unsigned int can_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) CAN_CLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const unsigned int du0_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static const unsigned int du0_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) DU0_DR3_MARK, DU0_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) DU0_DG3_MARK, DU0_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) DU0_DB3_MARK, DU0_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static const unsigned int du0_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static const unsigned int du0_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static const unsigned int du0_clk0_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* DOTCLKOUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const unsigned int du0_clk0_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) DU0_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static const unsigned int du0_clk1_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* DOTCLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static const unsigned int du0_clk1_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) DU0_DOTCLKOUT1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static const unsigned int du0_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static const unsigned int du0_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) DU0_DOTCLKIN_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static const unsigned int du0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const unsigned int du0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static const unsigned int du0_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) /* EXODDF/ODDF/DISP/CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) RCAR_GP_PIN(2, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) static const unsigned int du0_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const unsigned int du0_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static const unsigned int du0_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) DU0_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static const unsigned int du0_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static const unsigned int du0_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) DU0_DISP_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static const unsigned int du1_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static const unsigned int du1_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) DU1_DR3_MARK, DU1_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) DU1_DG3_MARK, DU1_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) DU1_DB3_MARK, DU1_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static const unsigned int du1_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static const unsigned int du1_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static const unsigned int du1_clk0_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* DOTCLKOUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) static const unsigned int du1_clk0_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) DU1_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static const unsigned int du1_clk1_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) /* DOTCLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) static const unsigned int du1_clk1_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) DU1_DOTCLKOUT1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static const unsigned int du1_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* DOTCLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const unsigned int du1_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) DU1_DOTCLKIN_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) static const unsigned int du1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static const unsigned int du1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static const unsigned int du1_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) /* EXODDF/ODDF/DISP/CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static const unsigned int du1_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static const unsigned int du1_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static const unsigned int du1_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) DU1_CDE_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static const unsigned int du1_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static const unsigned int du1_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) DU1_DISP_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* - ETH -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const unsigned int eth_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) /* LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const unsigned int eth_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ETH_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const unsigned int eth_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) RCAR_GP_PIN(3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static const unsigned int eth_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) ETH_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static const unsigned int eth_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* MDC, MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static const unsigned int eth_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ETH_MDC_MARK, ETH_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) static const unsigned int eth_rmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static const unsigned int eth_rmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static const unsigned int eth_link_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) /* LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static const unsigned int eth_link_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ETH_LINK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const unsigned int eth_magic_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static const unsigned int eth_magic_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ETH_MAGIC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) static const unsigned int eth_mdio_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /* MDC, MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static const unsigned int eth_mdio_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static const unsigned int eth_rmii_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static const unsigned int eth_rmii_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static const unsigned int hscif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static const unsigned int hscif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static const unsigned int hscif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static const unsigned int hscif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) HSCIF0_HSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) static const unsigned int hscif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static const unsigned int hscif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) static const unsigned int hscif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) static const unsigned int hscif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) static const unsigned int hscif0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) static const unsigned int hscif0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) HSCIF0_HSCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) static const unsigned int hscif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static const unsigned int hscif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static const unsigned int hscif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) static const unsigned int hscif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) HSCIF1_HSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static const unsigned int hscif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) static const unsigned int hscif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static const unsigned int hscif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static const unsigned int hscif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) static const unsigned int hscif1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static const unsigned int hscif1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* - HSCIF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static const unsigned int hscif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static const unsigned int hscif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) static const unsigned int hscif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static const unsigned int hscif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) HSCIF2_HSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) static const unsigned int hscif2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) static const unsigned int hscif2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) /* - I2C0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) I2C0_SCL_MARK, I2C0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static const unsigned int i2c0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static const unsigned int i2c0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) static const unsigned int i2c0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static const unsigned int i2c0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static const unsigned int i2c0_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static const unsigned int i2c0_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) static const unsigned int i2c0_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static const unsigned int i2c0_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* - I2C1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static const unsigned int i2c1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static const unsigned int i2c1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) I2C1_SCL_MARK, I2C1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static const unsigned int i2c1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static const unsigned int i2c1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static const unsigned int i2c1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) static const unsigned int i2c1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static const unsigned int i2c1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static const unsigned int i2c1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static const unsigned int i2c1_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static const unsigned int i2c1_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static const unsigned int i2c2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) static const unsigned int i2c2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) I2C2_SCL_MARK, I2C2_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static const unsigned int i2c2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static const unsigned int i2c2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) static const unsigned int i2c2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static const unsigned int i2c2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) static const unsigned int i2c2_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static const unsigned int i2c2_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static const unsigned int i2c3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static const unsigned int i2c3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) I2C3_SCL_MARK, I2C3_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static const unsigned int i2c3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static const unsigned int i2c3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static const unsigned int i2c3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static const unsigned int i2c3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) static const unsigned int i2c3_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static const unsigned int i2c3_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) static const unsigned int i2c3_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static const unsigned int i2c3_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) /* - I2C4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static const unsigned int i2c4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) static const unsigned int i2c4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) I2C4_SCL_MARK, I2C4_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static const unsigned int i2c4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static const unsigned int i2c4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static const unsigned int i2c4_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static const unsigned int i2c4_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static const unsigned int i2c4_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static const unsigned int i2c4_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) static const unsigned int i2c4_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static const unsigned int i2c4_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) /* - I2C5 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) static const unsigned int i2c5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static const unsigned int i2c5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) I2C5_SCL_MARK, I2C5_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static const unsigned int i2c5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) static const unsigned int i2c5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) I2C5_SCL_B_MARK, I2C5_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static const unsigned int i2c5_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) static const unsigned int i2c5_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) I2C5_SCL_C_MARK, I2C5_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) static const unsigned int i2c5_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) static const unsigned int i2c5_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) I2C5_SCL_D_MARK, I2C5_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /* - INTC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static const unsigned int intc_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static const unsigned int intc_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static const unsigned int intc_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static const unsigned int intc_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static const unsigned int intc_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static const unsigned int intc_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) static const unsigned int intc_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const unsigned int intc_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) static const unsigned int intc_irq4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static const unsigned int intc_irq4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) IRQ4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) static const unsigned int intc_irq5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) static const unsigned int intc_irq5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) IRQ5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static const unsigned int intc_irq6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static const unsigned int intc_irq6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) IRQ6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static const unsigned int intc_irq7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static const unsigned int intc_irq7_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) IRQ7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) static const unsigned int intc_irq8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* IRQ8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static const unsigned int intc_irq8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) IRQ8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static const unsigned int intc_irq9_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) /* IRQ9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) static const unsigned int intc_irq9_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) IRQ9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) /* - MMCIF ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) static const unsigned int mmc_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static const unsigned int mmc_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) MMC_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static const unsigned int mmc_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) static const unsigned int mmc_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) static const unsigned int mmc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) static const unsigned int mmc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static const unsigned int mmc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) static const unsigned int mmc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) MMC_CLK_MARK, MMC_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static const unsigned int msiof0_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static const unsigned int msiof0_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static const unsigned int msiof0_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static const unsigned int msiof0_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) RCAR_GP_PIN(0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) RCAR_GP_PIN(0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) RCAR_GP_PIN(0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) RCAR_GP_PIN(0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) static const unsigned int msiof1_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) RCAR_GP_PIN(0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const unsigned int msiof1_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) static const unsigned int msiof1_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const unsigned int msiof1_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static const unsigned int msiof1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const unsigned int msiof1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) MSIOF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static const unsigned int msiof1_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) static const unsigned int msiof1_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) MSIOF1_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static const unsigned int msiof1_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static const unsigned int msiof1_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) MSIOF1_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) static const unsigned int msiof1_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static const unsigned int msiof1_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) MSIOF1_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) static const unsigned int msiof1_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) static const unsigned int msiof1_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) MSIOF1_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) static const unsigned int msiof1_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) static const unsigned int msiof1_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) MSIOF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static const unsigned int msiof2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static const unsigned int msiof2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) static const unsigned int msiof2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static const unsigned int msiof2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) MSIOF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static const unsigned int msiof2_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static const unsigned int msiof2_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) static const unsigned int msiof2_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static const unsigned int msiof2_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) static const unsigned int msiof2_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) RCAR_GP_PIN(0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) static const unsigned int msiof2_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static const unsigned int msiof2_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) RCAR_GP_PIN(0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static const unsigned int msiof2_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static const unsigned int msiof2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static const unsigned int msiof2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) MSIOF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) static const unsigned int msiof2_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) static const unsigned int msiof2_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) MSIOF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) static const unsigned int msiof2_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) static const unsigned int msiof2_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) MSIOF2_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) static const unsigned int msiof2_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static const unsigned int msiof2_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) MSIOF2_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) static const unsigned int msiof2_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) static const unsigned int msiof2_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) MSIOF2_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) static const unsigned int msiof2_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) static const unsigned int msiof2_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) MSIOF2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) /* - PWM -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static const unsigned int pwm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) static const unsigned int pwm0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) PWM0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static const unsigned int pwm1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static const unsigned int pwm1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) PWM1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) static const unsigned int pwm1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) static const unsigned int pwm1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) PWM1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static const unsigned int pwm2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) static const unsigned int pwm2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) PWM2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static const unsigned int pwm2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static const unsigned int pwm2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) PWM2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static const unsigned int pwm3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static const unsigned int pwm3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) PWM3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) static const unsigned int pwm3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) static const unsigned int pwm3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) PWM3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) static const unsigned int pwm4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const unsigned int pwm4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) PWM4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static const unsigned int pwm4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) static const unsigned int pwm4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) static const unsigned int pwm5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) static const unsigned int pwm5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) PWM5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static const unsigned int pwm5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static const unsigned int pwm5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) PWM5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static const unsigned int pwm5_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static const unsigned int pwm5_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) PWM5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) static const unsigned int pwm6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) static const unsigned int pwm6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) PWM6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) static const unsigned int pwm6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static const unsigned int pwm6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) PWM6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) /* - QSPI ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static const unsigned int qspi_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) static const unsigned int qspi_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) SPCLK_MARK, SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) static const unsigned int qspi_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) static const unsigned int qspi_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) MOSI_IO0_MARK, MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static const unsigned int qspi_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) static const unsigned int qspi_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) static const unsigned int scif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static const unsigned int scif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) SCIF0_RXD_MARK, SCIF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) static const unsigned int scif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) static const unsigned int scif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) static const unsigned int scif0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) static const unsigned int scif0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) static const unsigned int scif0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) static const unsigned int scif0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) static const unsigned int scif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static const unsigned int scif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) SCIF1_RXD_MARK, SCIF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) static const unsigned int scif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) static const unsigned int scif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) SCIF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static const unsigned int scif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) static const unsigned int scif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) SCIF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) static const unsigned int scif1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) static const unsigned int scif1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) static const unsigned int scif1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) static const unsigned int scif1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) SCIF1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) static const unsigned int scif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) static const unsigned int scif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) SCIF2_RXD_MARK, SCIF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static const unsigned int scif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) static const unsigned int scif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) SCIF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) static const unsigned int scif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) static const unsigned int scif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) static const unsigned int scif2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) static const unsigned int scif2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) SCIF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) static const unsigned int scif2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) static const unsigned int scif2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) static const unsigned int scif2_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) static const unsigned int scif2_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) SCIF2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) static const unsigned int scif3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) static const unsigned int scif3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) SCIF3_RXD_MARK, SCIF3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) static const unsigned int scif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static const unsigned int scif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) SCIF3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) static const unsigned int scif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static const unsigned int scif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) static const unsigned int scif3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) RCAR_GP_PIN(3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) static const unsigned int scif3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) SCIF3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) static const unsigned int scif4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static const unsigned int scif4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) SCIF4_RXD_MARK, SCIF4_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) static const unsigned int scif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static const unsigned int scif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) static const unsigned int scif4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static const unsigned int scif4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) static const unsigned int scif4_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) static const unsigned int scif4_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) static const unsigned int scif4_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static const unsigned int scif4_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) static const unsigned int scif5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) static const unsigned int scif5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) SCIF5_RXD_MARK, SCIF5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) static const unsigned int scif5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) static const unsigned int scif5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) static const unsigned int scif5_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) static const unsigned int scif5_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) static const unsigned int scif5_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) static const unsigned int scif5_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) /* - SCIFA0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) static const unsigned int scifa0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) static const unsigned int scifa0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) static const unsigned int scifa0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static const unsigned int scifa0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static const unsigned int scifa0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) static const unsigned int scifa0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static const unsigned int scifa0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) static const unsigned int scifa0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /* - SCIFA1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) static const unsigned int scifa1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static const unsigned int scifa1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static const unsigned int scifa1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) static const unsigned int scifa1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) SCIFA1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static const unsigned int scifa1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) static const unsigned int scifa1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) static const unsigned int scifa1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) static const unsigned int scifa1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) SCIFA1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) static const unsigned int scifa1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static const unsigned int scifa1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) static const unsigned int scifa1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) static const unsigned int scifa1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) SCIFA1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) /* - SCIFA2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) static const unsigned int scifa2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) static const unsigned int scifa2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static const unsigned int scifa2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) static const unsigned int scifa2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) SCIFA2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) static const unsigned int scifa2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) static const unsigned int scifa2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) static const unsigned int scifa2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) static const unsigned int scifa2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) SCIFA2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /* - SCIFA3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) static const unsigned int scifa3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static const unsigned int scifa3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) static const unsigned int scifa3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static const unsigned int scifa3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) SCIFA3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) static const unsigned int scifa3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static const unsigned int scifa3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) static const unsigned int scifa3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) static const unsigned int scifa3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) SCIFA3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) /* - SCIFA4 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) static const unsigned int scifa4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) static const unsigned int scifa4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) static const unsigned int scifa4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static const unsigned int scifa4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) static const unsigned int scifa4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static const unsigned int scifa4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) static const unsigned int scifa4_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static const unsigned int scifa4_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /* - SCIFA5 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static const unsigned int scifa5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) static const unsigned int scifa5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) static const unsigned int scifa5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static const unsigned int scifa5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) static const unsigned int scifa5_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static const unsigned int scifa5_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) static const unsigned int scifa5_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) static const unsigned int scifa5_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) /* - SCIFB0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) static const unsigned int scifb0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) static const unsigned int scifb0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) static const unsigned int scifb0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) static const unsigned int scifb0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) SCIFB0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) static const unsigned int scifb0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) static const unsigned int scifb0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) /* - SCIFB1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) static const unsigned int scifb1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static const unsigned int scifb1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) static const unsigned int scifb1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) static const unsigned int scifb1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) SCIFB1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) /* - SCIFB2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static const unsigned int scifb2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) static const unsigned int scifb2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) static const unsigned int scifb2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) static const unsigned int scifb2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) SCIFB2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) static const unsigned int scifb2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static const unsigned int scifb2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) static const unsigned int scif_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) static const unsigned int scif_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) SCIF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) RCAR_GP_PIN(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) SD0_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) SD0_CLK_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) SD0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) SD1_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) SD1_CLK_MARK, SD1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) SD2_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) SD2_CLK_MARK, SD2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static const unsigned int sdhi2_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) RCAR_GP_PIN(6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) static const unsigned int sdhi2_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) SD2_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) static const unsigned int sdhi2_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) static const unsigned int sdhi2_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) SD2_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) /* - SSI -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) static const unsigned int ssi0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) /* SDATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) static const unsigned int ssi0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) SSI_SDATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) static const unsigned int ssi0129_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* SCK0129, WS0129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) static const unsigned int ssi0129_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) SSI_SCK0129_MARK, SSI_WS0129_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) static const unsigned int ssi1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) /* SDATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) static const unsigned int ssi1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) SSI_SDATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) static const unsigned int ssi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) /* SCK1, WS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) static const unsigned int ssi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) SSI_SCK1_MARK, SSI_WS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) static const unsigned int ssi1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) /* SDATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) static const unsigned int ssi1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) static const unsigned int ssi1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) /* SCK1, WS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) static const unsigned int ssi1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) static const unsigned int ssi2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /* SDATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) static const unsigned int ssi2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) SSI_SDATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) static const unsigned int ssi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) /* SCK2, WS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) static const unsigned int ssi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) SSI_SCK2_MARK, SSI_WS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) static const unsigned int ssi2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) /* SDATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) static const unsigned int ssi2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) SSI_SDATA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) static const unsigned int ssi2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) /* SCK2, WS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) static const unsigned int ssi2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) static const unsigned int ssi3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) /* SDATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) static const unsigned int ssi3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) SSI_SDATA3_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) static const unsigned int ssi34_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) /* SCK34, WS34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) static const unsigned int ssi34_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) SSI_SCK34_MARK, SSI_WS34_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static const unsigned int ssi4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) /* SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) static const unsigned int ssi4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) SSI_SDATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) static const unsigned int ssi4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) /* SCK4, WS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) static const unsigned int ssi4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) SSI_SCK4_MARK, SSI_WS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) static const unsigned int ssi4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) /* SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) static const unsigned int ssi4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) SSI_SDATA4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) static const unsigned int ssi4_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) /* SCK4, WS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) static const unsigned int ssi4_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) static const unsigned int ssi5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) /* SDATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) static const unsigned int ssi5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) SSI_SDATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) static const unsigned int ssi5_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) /* SCK5, WS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) static const unsigned int ssi5_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) SSI_SCK5_MARK, SSI_WS5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) static const unsigned int ssi5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) /* SDATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) static const unsigned int ssi5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) SSI_SDATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) static const unsigned int ssi5_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) /* SCK5, WS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) static const unsigned int ssi5_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) static const unsigned int ssi6_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) /* SDATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) static const unsigned int ssi6_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) SSI_SDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) static const unsigned int ssi6_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) /* SCK6, WS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) static const unsigned int ssi6_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) SSI_SCK6_MARK, SSI_WS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) static const unsigned int ssi6_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) /* SDATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) RCAR_GP_PIN(3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) static const unsigned int ssi6_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) SSI_SDATA6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) static const unsigned int ssi6_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) /* SCK6, WS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) static const unsigned int ssi6_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) static const unsigned int ssi7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) /* SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) static const unsigned int ssi7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) static const unsigned int ssi78_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) /* SCK78, WS78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) static const unsigned int ssi78_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) SSI_SCK78_MARK, SSI_WS78_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) static const unsigned int ssi7_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) /* SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) static const unsigned int ssi7_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) static const unsigned int ssi78_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) /* SCK78, WS78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) static const unsigned int ssi78_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) static const unsigned int ssi8_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) /* SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) static const unsigned int ssi8_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) static const unsigned int ssi8_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) /* SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) static const unsigned int ssi8_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) SSI_SDATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) static const unsigned int ssi9_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) /* SDATA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) static const unsigned int ssi9_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) SSI_SDATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) static const unsigned int ssi9_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) /* SCK9, WS9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) static const unsigned int ssi9_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) SSI_SCK9_MARK, SSI_WS9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) static const unsigned int ssi9_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) /* SDATA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) static const unsigned int ssi9_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) SSI_SDATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) static const unsigned int ssi9_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) /* SCK9, WS9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) static const unsigned int ssi9_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) /* - TPU -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) static const unsigned int tpu_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) static const unsigned int tpu_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) TPUTO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) static const unsigned int tpu_to0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) static const unsigned int tpu_to0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) TPUTO0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) static const unsigned int tpu_to0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) static const unsigned int tpu_to0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) TPUTO0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) static const unsigned int tpu_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) static const unsigned int tpu_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) TPUTO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) static const unsigned int tpu_to1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) static const unsigned int tpu_to1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) TPUTO1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) static const unsigned int tpu_to1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) static const unsigned int tpu_to1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) TPUTO1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) static const unsigned int tpu_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) static const unsigned int tpu_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) TPUTO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) static const unsigned int tpu_to2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) static const unsigned int tpu_to2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) TPUTO2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) static const unsigned int tpu_to2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) RCAR_GP_PIN(0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) static const unsigned int tpu_to2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) TPUTO2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) static const unsigned int tpu_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) static const unsigned int tpu_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) TPUTO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) static const unsigned int tpu_to3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) static const unsigned int tpu_to3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) TPUTO3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) static const unsigned int tpu_to3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) static const unsigned int tpu_to3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) TPUTO3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) static const unsigned int usb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) RCAR_GP_PIN(5, 24), /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) RCAR_GP_PIN(5, 25), /* OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) static const unsigned int usb0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) USB0_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) USB0_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) /* - USB1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) static const unsigned int usb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) RCAR_GP_PIN(5, 26), /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) RCAR_GP_PIN(5, 27), /* OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) static const unsigned int usb1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) USB1_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) static const union vin_data vin0_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) static const union vin_data vin0_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) VI0_G0_MARK, VI0_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) VI0_R0_MARK, VI0_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) static const unsigned int vin0_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) static const unsigned int vin0_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) static const unsigned int vin0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) RCAR_GP_PIN(3, 11), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) RCAR_GP_PIN(3, 12), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) static const unsigned int vin0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) VI0_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) static const unsigned int vin0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) static const unsigned int vin0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) static const unsigned int vin0_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) static const unsigned int vin0_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) static const unsigned int vin0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) static const unsigned int vin0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /* - VIN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) static const union vin_data12 vin1_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) static const union vin_data12 vin1_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) VI1_DATA0_MARK, VI1_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) VI1_DATA2_MARK, VI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) VI1_DATA4_MARK, VI1_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) VI1_DATA6_MARK, VI1_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) VI1_DATA8_MARK, VI1_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) VI1_DATA10_MARK, VI1_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) static const unsigned int vin1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) RCAR_GP_PIN(5, 22), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) RCAR_GP_PIN(5, 23), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) static const unsigned int vin1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) VI1_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) static const unsigned int vin1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) static const unsigned int vin1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) static const unsigned int vin1_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) static const unsigned int vin1_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) static const unsigned int vin1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) static const unsigned int vin1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) SH_PFC_PIN_GROUP(audio_clka),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) SH_PFC_PIN_GROUP(audio_clka_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) SH_PFC_PIN_GROUP(audio_clka_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) SH_PFC_PIN_GROUP(audio_clka_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) SH_PFC_PIN_GROUP(audio_clkb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) SH_PFC_PIN_GROUP(audio_clkb_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) SH_PFC_PIN_GROUP(audio_clkb_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) SH_PFC_PIN_GROUP(audio_clkc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) SH_PFC_PIN_GROUP(audio_clkc_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) SH_PFC_PIN_GROUP(audio_clkc_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) SH_PFC_PIN_GROUP(audio_clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) SH_PFC_PIN_GROUP(audio_clkout_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) SH_PFC_PIN_GROUP(audio_clkout_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) SH_PFC_PIN_GROUP(avb_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) SH_PFC_PIN_GROUP(avb_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) SH_PFC_PIN_GROUP(avb_gmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) SH_PFC_PIN_GROUP(can0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) SH_PFC_PIN_GROUP(can0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) SH_PFC_PIN_GROUP(can0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) SH_PFC_PIN_GROUP(can0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) SH_PFC_PIN_GROUP(can1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) SH_PFC_PIN_GROUP(can1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) SH_PFC_PIN_GROUP(can1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) SH_PFC_PIN_GROUP(can1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) SH_PFC_PIN_GROUP(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) SH_PFC_PIN_GROUP(can_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) SH_PFC_PIN_GROUP(can_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) SH_PFC_PIN_GROUP(can_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) SH_PFC_PIN_GROUP(du0_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) SH_PFC_PIN_GROUP(du0_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) SH_PFC_PIN_GROUP(du0_clk0_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) SH_PFC_PIN_GROUP(du0_clk1_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) SH_PFC_PIN_GROUP(du0_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) SH_PFC_PIN_GROUP(du0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) SH_PFC_PIN_GROUP(du0_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) SH_PFC_PIN_GROUP(du0_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) SH_PFC_PIN_GROUP(du0_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) SH_PFC_PIN_GROUP(du1_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) SH_PFC_PIN_GROUP(du1_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) SH_PFC_PIN_GROUP(du1_clk0_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) SH_PFC_PIN_GROUP(du1_clk1_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) SH_PFC_PIN_GROUP(du1_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) SH_PFC_PIN_GROUP(du1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) SH_PFC_PIN_GROUP(du1_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) SH_PFC_PIN_GROUP(du1_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) SH_PFC_PIN_GROUP(du1_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) SH_PFC_PIN_GROUP(eth_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) SH_PFC_PIN_GROUP(eth_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) SH_PFC_PIN_GROUP(eth_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) SH_PFC_PIN_GROUP(eth_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) SH_PFC_PIN_GROUP(eth_link_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) SH_PFC_PIN_GROUP(eth_magic_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) SH_PFC_PIN_GROUP(eth_mdio_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) SH_PFC_PIN_GROUP(eth_rmii_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) SH_PFC_PIN_GROUP(hscif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) SH_PFC_PIN_GROUP(hscif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) SH_PFC_PIN_GROUP(hscif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) SH_PFC_PIN_GROUP(hscif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) SH_PFC_PIN_GROUP(hscif0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) SH_PFC_PIN_GROUP(hscif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) SH_PFC_PIN_GROUP(hscif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) SH_PFC_PIN_GROUP(hscif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) SH_PFC_PIN_GROUP(hscif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) SH_PFC_PIN_GROUP(hscif1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) SH_PFC_PIN_GROUP(hscif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) SH_PFC_PIN_GROUP(hscif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) SH_PFC_PIN_GROUP(hscif2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) SH_PFC_PIN_GROUP(i2c0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) SH_PFC_PIN_GROUP(i2c0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) SH_PFC_PIN_GROUP(i2c0_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) SH_PFC_PIN_GROUP(i2c0_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) SH_PFC_PIN_GROUP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) SH_PFC_PIN_GROUP(i2c1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) SH_PFC_PIN_GROUP(i2c1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) SH_PFC_PIN_GROUP(i2c1_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) SH_PFC_PIN_GROUP(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) SH_PFC_PIN_GROUP(i2c2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) SH_PFC_PIN_GROUP(i2c2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) SH_PFC_PIN_GROUP(i2c2_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) SH_PFC_PIN_GROUP(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) SH_PFC_PIN_GROUP(i2c3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) SH_PFC_PIN_GROUP(i2c3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) SH_PFC_PIN_GROUP(i2c3_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) SH_PFC_PIN_GROUP(i2c3_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) SH_PFC_PIN_GROUP(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) SH_PFC_PIN_GROUP(i2c4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) SH_PFC_PIN_GROUP(i2c4_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) SH_PFC_PIN_GROUP(i2c4_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) SH_PFC_PIN_GROUP(i2c4_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) SH_PFC_PIN_GROUP(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) SH_PFC_PIN_GROUP(i2c5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) SH_PFC_PIN_GROUP(i2c5_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) SH_PFC_PIN_GROUP(i2c5_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) SH_PFC_PIN_GROUP(intc_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) SH_PFC_PIN_GROUP(intc_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) SH_PFC_PIN_GROUP(intc_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) SH_PFC_PIN_GROUP(intc_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) SH_PFC_PIN_GROUP(intc_irq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) SH_PFC_PIN_GROUP(intc_irq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) SH_PFC_PIN_GROUP(intc_irq6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) SH_PFC_PIN_GROUP(intc_irq7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) SH_PFC_PIN_GROUP(intc_irq8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) SH_PFC_PIN_GROUP(intc_irq9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) SH_PFC_PIN_GROUP(msiof0_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) SH_PFC_PIN_GROUP(msiof0_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) SH_PFC_PIN_GROUP(msiof1_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) SH_PFC_PIN_GROUP(msiof1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) SH_PFC_PIN_GROUP(msiof1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) SH_PFC_PIN_GROUP(msiof1_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) SH_PFC_PIN_GROUP(msiof1_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) SH_PFC_PIN_GROUP(msiof1_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) SH_PFC_PIN_GROUP(msiof1_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) SH_PFC_PIN_GROUP(msiof1_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) SH_PFC_PIN_GROUP(msiof2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) SH_PFC_PIN_GROUP(msiof2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) SH_PFC_PIN_GROUP(msiof2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) SH_PFC_PIN_GROUP(msiof2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) SH_PFC_PIN_GROUP(msiof2_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) SH_PFC_PIN_GROUP(msiof2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) SH_PFC_PIN_GROUP(msiof2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) SH_PFC_PIN_GROUP(msiof2_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) SH_PFC_PIN_GROUP(msiof2_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) SH_PFC_PIN_GROUP(msiof2_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) SH_PFC_PIN_GROUP(msiof2_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) SH_PFC_PIN_GROUP(msiof2_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) SH_PFC_PIN_GROUP(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) SH_PFC_PIN_GROUP(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) SH_PFC_PIN_GROUP(pwm1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) SH_PFC_PIN_GROUP(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) SH_PFC_PIN_GROUP(pwm2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) SH_PFC_PIN_GROUP(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) SH_PFC_PIN_GROUP(pwm3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) SH_PFC_PIN_GROUP(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) SH_PFC_PIN_GROUP(pwm4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) SH_PFC_PIN_GROUP(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) SH_PFC_PIN_GROUP(pwm5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) SH_PFC_PIN_GROUP(pwm5_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) SH_PFC_PIN_GROUP(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) SH_PFC_PIN_GROUP(pwm6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) SH_PFC_PIN_GROUP(qspi_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) SH_PFC_PIN_GROUP(qspi_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) SH_PFC_PIN_GROUP(qspi_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) SH_PFC_PIN_GROUP(scif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) SH_PFC_PIN_GROUP(scif0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) SH_PFC_PIN_GROUP(scif0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) SH_PFC_PIN_GROUP(scif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) SH_PFC_PIN_GROUP(scif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) SH_PFC_PIN_GROUP(scif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) SH_PFC_PIN_GROUP(scif1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) SH_PFC_PIN_GROUP(scif1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) SH_PFC_PIN_GROUP(scif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) SH_PFC_PIN_GROUP(scif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) SH_PFC_PIN_GROUP(scif2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) SH_PFC_PIN_GROUP(scif2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) SH_PFC_PIN_GROUP(scif2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) SH_PFC_PIN_GROUP(scif3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) SH_PFC_PIN_GROUP(scif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) SH_PFC_PIN_GROUP(scif3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) SH_PFC_PIN_GROUP(scif4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) SH_PFC_PIN_GROUP(scif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) SH_PFC_PIN_GROUP(scif4_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) SH_PFC_PIN_GROUP(scif4_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) SH_PFC_PIN_GROUP(scif5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) SH_PFC_PIN_GROUP(scif5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) SH_PFC_PIN_GROUP(scif5_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) SH_PFC_PIN_GROUP(scif5_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) SH_PFC_PIN_GROUP(scifa0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) SH_PFC_PIN_GROUP(scifa0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) SH_PFC_PIN_GROUP(scifa0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) SH_PFC_PIN_GROUP(scifa0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) SH_PFC_PIN_GROUP(scifa1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) SH_PFC_PIN_GROUP(scifa1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) SH_PFC_PIN_GROUP(scifa1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) SH_PFC_PIN_GROUP(scifa1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) SH_PFC_PIN_GROUP(scifa1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) SH_PFC_PIN_GROUP(scifa1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) SH_PFC_PIN_GROUP(scifa2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) SH_PFC_PIN_GROUP(scifa2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) SH_PFC_PIN_GROUP(scifa2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) SH_PFC_PIN_GROUP(scifa2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) SH_PFC_PIN_GROUP(scifa3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) SH_PFC_PIN_GROUP(scifa3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) SH_PFC_PIN_GROUP(scifa3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) SH_PFC_PIN_GROUP(scifa3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) SH_PFC_PIN_GROUP(scifa4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) SH_PFC_PIN_GROUP(scifa4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) SH_PFC_PIN_GROUP(scifa4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) SH_PFC_PIN_GROUP(scifa4_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) SH_PFC_PIN_GROUP(scifa5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) SH_PFC_PIN_GROUP(scifa5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) SH_PFC_PIN_GROUP(scifa5_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) SH_PFC_PIN_GROUP(scifa5_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) SH_PFC_PIN_GROUP(scifb0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) SH_PFC_PIN_GROUP(scifb0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) SH_PFC_PIN_GROUP(scifb0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) SH_PFC_PIN_GROUP(scifb1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) SH_PFC_PIN_GROUP(scifb1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) SH_PFC_PIN_GROUP(scifb2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) SH_PFC_PIN_GROUP(scifb2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) SH_PFC_PIN_GROUP(scifb2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) SH_PFC_PIN_GROUP(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) SH_PFC_PIN_GROUP(sdhi2_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) SH_PFC_PIN_GROUP(sdhi2_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) SH_PFC_PIN_GROUP(ssi0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) SH_PFC_PIN_GROUP(ssi0129_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) SH_PFC_PIN_GROUP(ssi1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) SH_PFC_PIN_GROUP(ssi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) SH_PFC_PIN_GROUP(ssi1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) SH_PFC_PIN_GROUP(ssi1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) SH_PFC_PIN_GROUP(ssi2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) SH_PFC_PIN_GROUP(ssi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) SH_PFC_PIN_GROUP(ssi2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) SH_PFC_PIN_GROUP(ssi2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) SH_PFC_PIN_GROUP(ssi34_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) SH_PFC_PIN_GROUP(ssi4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) SH_PFC_PIN_GROUP(ssi4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) SH_PFC_PIN_GROUP(ssi4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) SH_PFC_PIN_GROUP(ssi4_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) SH_PFC_PIN_GROUP(ssi5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) SH_PFC_PIN_GROUP(ssi5_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) SH_PFC_PIN_GROUP(ssi5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) SH_PFC_PIN_GROUP(ssi5_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) SH_PFC_PIN_GROUP(ssi6_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) SH_PFC_PIN_GROUP(ssi6_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) SH_PFC_PIN_GROUP(ssi6_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) SH_PFC_PIN_GROUP(ssi6_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) SH_PFC_PIN_GROUP(ssi7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) SH_PFC_PIN_GROUP(ssi78_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) SH_PFC_PIN_GROUP(ssi7_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) SH_PFC_PIN_GROUP(ssi78_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) SH_PFC_PIN_GROUP(ssi8_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) SH_PFC_PIN_GROUP(ssi8_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) SH_PFC_PIN_GROUP(ssi9_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) SH_PFC_PIN_GROUP(ssi9_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) SH_PFC_PIN_GROUP(ssi9_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) SH_PFC_PIN_GROUP(ssi9_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) SH_PFC_PIN_GROUP(tpu_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) SH_PFC_PIN_GROUP(tpu_to0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) SH_PFC_PIN_GROUP(tpu_to0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) SH_PFC_PIN_GROUP(tpu_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) SH_PFC_PIN_GROUP(tpu_to1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) SH_PFC_PIN_GROUP(tpu_to1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) SH_PFC_PIN_GROUP(tpu_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) SH_PFC_PIN_GROUP(tpu_to2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) SH_PFC_PIN_GROUP(tpu_to2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) SH_PFC_PIN_GROUP(tpu_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) SH_PFC_PIN_GROUP(tpu_to3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) SH_PFC_PIN_GROUP(tpu_to3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) SH_PFC_PIN_GROUP(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) VIN_DATA_PIN_GROUP(vin0_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) VIN_DATA_PIN_GROUP(vin0_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) SH_PFC_PIN_GROUP(vin0_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) VIN_DATA_PIN_GROUP(vin0_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) VIN_DATA_PIN_GROUP(vin0_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) VIN_DATA_PIN_GROUP(vin0_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) VIN_DATA_PIN_GROUP(vin0_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) SH_PFC_PIN_GROUP(vin0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) SH_PFC_PIN_GROUP(vin0_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) VIN_DATA_PIN_GROUP(vin1_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) VIN_DATA_PIN_GROUP(vin1_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) VIN_DATA_PIN_GROUP(vin1_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) SH_PFC_PIN_GROUP(vin1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) SH_PFC_PIN_GROUP(vin1_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) "audio_clka",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) "audio_clka_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) "audio_clka_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) "audio_clka_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) "audio_clkb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) "audio_clkb_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) "audio_clkb_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) "audio_clkc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) "audio_clkc_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) "audio_clkc_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) "audio_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) "audio_clkout_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) "audio_clkout_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) "avb_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) "avb_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) "avb_gmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) "can0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) "can0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) "can0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) "can0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) * Retained for backwards compatibility, use can_clk_groups in new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) * designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) "can1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) "can1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) "can1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) "can1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) * Retained for backwards compatibility, use can_clk_groups in new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) * designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) * can_clk_groups allows for independent configuration, use can_clk function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) * in new designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) static const char * const can_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) static const char * const du0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) "du0_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) "du0_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) "du0_clk0_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) "du0_clk1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) "du0_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) "du0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) "du0_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) "du0_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) "du0_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) static const char * const du1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) "du1_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) "du1_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) "du1_clk0_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) "du1_clk1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) "du1_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) "du1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) "du1_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) "du1_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) "du1_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) static const char * const eth_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) "eth_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) "eth_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) "eth_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) "eth_rmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) "eth_link_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) "eth_magic_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) "eth_mdio_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) "eth_rmii_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) "hscif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) "hscif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) "hscif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) "hscif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) "hscif0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) "hscif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) "hscif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) "hscif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) "hscif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) "hscif1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) static const char * const hscif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) "hscif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) "hscif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) "hscif2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) "i2c0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) "i2c0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) "i2c0_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) "i2c0_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) "i2c1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) "i2c1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) "i2c1_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) "i2c2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) "i2c2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) "i2c2_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) "i2c3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) "i2c3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) "i2c3_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) "i2c3_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) "i2c4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) "i2c4_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) "i2c4_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) "i2c4_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) static const char * const i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) "i2c5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) "i2c5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) "i2c5_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) "i2c5_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) static const char * const intc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) "intc_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) "intc_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) "intc_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) "intc_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) "intc_irq4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) "intc_irq5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) "intc_irq6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) "intc_irq7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) "intc_irq8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) "intc_irq9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) "msiof0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) "msiof0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) "msiof1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) "msiof1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) "msiof1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) "msiof1_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) "msiof1_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) "msiof1_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) "msiof1_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) "msiof1_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) "msiof2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) "msiof2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) "msiof2_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) "msiof2_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) "msiof2_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) "msiof2_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) "msiof2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) "msiof2_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) "msiof2_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) "msiof2_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) "msiof2_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) "msiof2_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) "pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) "pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) "pwm1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) "pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) "pwm2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) "pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) "pwm3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) "pwm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) "pwm4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) "pwm5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) "pwm5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) "pwm5_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) static const char * const pwm6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) "pwm6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) "pwm6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) static const char * const qspi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) "qspi_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) "qspi_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) "qspi_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) "scif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) "scif0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) "scif0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) "scif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) "scif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) "scif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) "scif1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) "scif1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) "scif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) "scif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) "scif2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) "scif2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) "scif2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) "scif3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) "scif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) "scif3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) "scif4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) "scif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) "scif4_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) "scif4_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) "scif5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) "scif5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) "scif5_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) "scif5_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) static const char * const scifa0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) "scifa0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) "scifa0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) "scifa0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) "scifa0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) static const char * const scifa1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) "scifa1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) "scifa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) "scifa1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) "scifa1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) "scifa1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) "scifa1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) static const char * const scifa2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) "scifa2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) "scifa2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) "scifa2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) "scifa2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) static const char * const scifa3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) "scifa3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) "scifa3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) "scifa3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) "scifa3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) static const char * const scifa4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) "scifa4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) "scifa4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) "scifa4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) "scifa4_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) static const char * const scifa5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) "scifa5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) "scifa5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) "scifa5_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) "scifa5_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) static const char * const scifb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) "scifb0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) "scifb0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) "scifb0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) static const char * const scifb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) "scifb1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) "scifb1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) static const char * const scifb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) "scifb2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) "scifb2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) "scifb2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) "scif_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) "sdhi2_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) "sdhi2_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) "ssi0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) "ssi0129_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) "ssi1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) "ssi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) "ssi1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) "ssi1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) "ssi2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) "ssi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) "ssi2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) "ssi2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) "ssi34_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) "ssi4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) "ssi4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) "ssi4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) "ssi4_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) "ssi5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) "ssi5_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) "ssi5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) "ssi5_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) "ssi6_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) "ssi6_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) "ssi6_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) "ssi6_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) "ssi7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) "ssi78_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) "ssi7_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) "ssi78_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) "ssi8_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) "ssi8_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) "ssi9_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) "ssi9_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) "ssi9_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) "ssi9_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) static const char * const tpu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) "tpu_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) "tpu_to0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) "tpu_to0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) "tpu_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) "tpu_to1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) "tpu_to1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) "tpu_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) "tpu_to2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) "tpu_to2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) "tpu_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) "tpu_to3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) "tpu_to3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) static const char * const usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) "vin0_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) "vin0_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) "vin0_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) "vin0_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) "vin0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) "vin0_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) "vin0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) "vin0_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) "vin1_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) "vin1_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) "vin1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) "vin1_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) SH_PFC_FUNCTION(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) SH_PFC_FUNCTION(du0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) SH_PFC_FUNCTION(du1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) SH_PFC_FUNCTION(eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) SH_PFC_FUNCTION(hscif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) SH_PFC_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) SH_PFC_FUNCTION(i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) SH_PFC_FUNCTION(intc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) SH_PFC_FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) SH_PFC_FUNCTION(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) SH_PFC_FUNCTION(qspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) SH_PFC_FUNCTION(scifa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) SH_PFC_FUNCTION(scifa1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) SH_PFC_FUNCTION(scifa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) SH_PFC_FUNCTION(scifa3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) SH_PFC_FUNCTION(scifa4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) SH_PFC_FUNCTION(scifa5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) SH_PFC_FUNCTION(scifb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) SH_PFC_FUNCTION(scifb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) SH_PFC_FUNCTION(scifb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) SH_PFC_FUNCTION(tpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) SH_PFC_FUNCTION(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) GP_0_31_FN, FN_IP2_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) GP_0_30_FN, FN_IP2_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) GP_0_29_FN, FN_IP2_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) GP_0_28_FN, FN_IP2_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) GP_0_27_FN, FN_IP2_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) GP_0_26_FN, FN_IP2_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) GP_0_25_FN, FN_IP2_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) GP_0_24_FN, FN_IP2_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) GP_0_23_FN, FN_IP2_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) GP_0_22_FN, FN_IP1_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) GP_0_21_FN, FN_IP1_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) GP_0_20_FN, FN_IP1_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) GP_0_19_FN, FN_IP1_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) GP_0_18_FN, FN_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) GP_0_17_FN, FN_IP1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) GP_0_16_FN, FN_IP1_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) GP_0_15_FN, FN_IP1_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) GP_0_14_FN, FN_IP1_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) GP_0_13_FN, FN_IP1_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) GP_0_12_FN, FN_IP1_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) GP_0_11_FN, FN_IP1_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) GP_0_10_FN, FN_IP1_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) GP_0_9_FN, FN_IP1_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) GP_0_8_FN, FN_IP1_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) GP_0_7_FN, FN_IP1_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) GP_0_6_FN, FN_IP1_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) GP_0_5_FN, FN_IP0_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) GP_0_4_FN, FN_IP0_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) GP_0_3_FN, FN_IP0_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) GP_0_2_FN, FN_IP0_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) GP_0_1_FN, FN_IP0_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) GP_0_0_FN, FN_IP0_23_22, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) GP_1_25_FN, FN_DACK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) GP_1_24_FN, FN_IP7_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) GP_1_23_FN, FN_IP4_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) GP_1_22_FN, FN_WE1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) GP_1_21_FN, FN_WE0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) GP_1_20_FN, FN_IP3_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) GP_1_19_FN, FN_IP3_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) GP_1_18_FN, FN_IP3_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) GP_1_17_FN, FN_IP3_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) GP_1_16_FN, FN_IP3_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) GP_1_15_FN, FN_IP3_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) GP_1_14_FN, FN_IP3_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) GP_1_13_FN, FN_IP3_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) GP_1_12_FN, FN_IP3_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) GP_1_11_FN, FN_IP3_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) GP_1_10_FN, FN_IP3_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) GP_1_9_FN, FN_IP3_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) GP_1_8_FN, FN_IP3_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) GP_1_7_FN, FN_IP3_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) GP_1_6_FN, FN_IP3_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) GP_1_5_FN, FN_IP3_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) GP_1_4_FN, FN_IP2_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) GP_1_3_FN, FN_IP2_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) GP_1_2_FN, FN_IP2_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) GP_1_1_FN, FN_IP2_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) GP_1_0_FN, FN_IP2_20_18, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) GP_2_31_FN, FN_IP6_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) GP_2_30_FN, FN_IP6_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) GP_2_29_FN, FN_IP6_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) GP_2_28_FN, FN_IP6_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) GP_2_27_FN, FN_IP5_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) GP_2_26_FN, FN_IP5_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) GP_2_25_FN, FN_IP5_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) GP_2_24_FN, FN_IP5_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) GP_2_23_FN, FN_IP5_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) GP_2_22_FN, FN_IP5_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) GP_2_21_FN, FN_IP5_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) GP_2_20_FN, FN_IP5_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) GP_2_19_FN, FN_IP5_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) GP_2_18_FN, FN_IP5_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) GP_2_17_FN, FN_IP5_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) GP_2_16_FN, FN_IP5_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) GP_2_15_FN, FN_IP5_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) GP_2_14_FN, FN_IP5_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) GP_2_13_FN, FN_IP5_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) GP_2_12_FN, FN_IP4_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) GP_2_11_FN, FN_IP4_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) GP_2_10_FN, FN_IP4_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) GP_2_9_FN, FN_IP4_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) GP_2_8_FN, FN_IP4_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) GP_2_7_FN, FN_IP4_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) GP_2_6_FN, FN_IP4_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) GP_2_5_FN, FN_IP4_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) GP_2_4_FN, FN_IP4_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) GP_2_3_FN, FN_IP4_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) GP_2_2_FN, FN_IP4_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) GP_2_1_FN, FN_IP4_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) GP_2_0_FN, FN_IP4_4_2 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) GP_3_31_FN, FN_IP8_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) GP_3_30_FN, FN_IP8_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) GP_3_29_FN, FN_IP8_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) GP_3_28_FN, FN_IP8_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) GP_3_27_FN, FN_IP8_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) GP_3_26_FN, FN_IP8_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) GP_3_25_FN, FN_IP8_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) GP_3_24_FN, FN_IP8_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) GP_3_23_FN, FN_IP7_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) GP_3_22_FN, FN_IP7_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) GP_3_21_FN, FN_IP7_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) GP_3_20_FN, FN_IP7_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) GP_3_19_FN, FN_IP7_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) GP_3_18_FN, FN_IP7_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) GP_3_17_FN, FN_IP7_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) GP_3_16_FN, FN_IP7_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) GP_3_15_FN, FN_IP7_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) GP_3_14_FN, FN_IP7_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) GP_3_13_FN, FN_IP6_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) GP_3_12_FN, FN_IP6_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) GP_3_11_FN, FN_IP6_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) GP_3_10_FN, FN_IP6_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) GP_3_9_FN, FN_IP6_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) GP_3_8_FN, FN_IP6_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) GP_3_7_FN, FN_IP6_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) GP_3_6_FN, FN_IP6_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) GP_3_5_FN, FN_IP6_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) GP_3_4_FN, FN_IP6_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) GP_3_3_FN, FN_IP6_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) GP_3_2_FN, FN_IP6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) GP_3_1_FN, FN_IP6_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) GP_3_0_FN, FN_IP6_8 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) GP_4_31_FN, FN_IP11_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) GP_4_30_FN, FN_IP11_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) GP_4_29_FN, FN_IP11_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) GP_4_28_FN, FN_IP11_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) GP_4_27_FN, FN_IP11_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) GP_4_26_FN, FN_IP11_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) GP_4_25_FN, FN_IP11_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) GP_4_24_FN, FN_IP10_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) GP_4_23_FN, FN_IP10_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) GP_4_22_FN, FN_IP10_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) GP_4_21_FN, FN_IP10_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) GP_4_20_FN, FN_IP10_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) GP_4_19_FN, FN_IP10_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) GP_4_18_FN, FN_IP10_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) GP_4_17_FN, FN_IP10_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) GP_4_16_FN, FN_IP10_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) GP_4_15_FN, FN_IP10_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) GP_4_14_FN, FN_IP10_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) GP_4_13_FN, FN_IP9_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) GP_4_12_FN, FN_IP9_27_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) GP_4_11_FN, FN_IP9_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) GP_4_10_FN, FN_IP9_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) GP_4_9_FN, FN_IP9_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) GP_4_8_FN, FN_IP9_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) GP_4_7_FN, FN_IP9_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) GP_4_6_FN, FN_IP9_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) GP_4_5_FN, FN_IP9_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) GP_4_4_FN, FN_IP9_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) GP_4_3_FN, FN_IP9_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) GP_4_2_FN, FN_IP8_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) GP_4_1_FN, FN_IP8_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) GP_4_0_FN, FN_IP8_25_23 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) GP_5_27_FN, FN_USB1_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) GP_5_26_FN, FN_USB1_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) GP_5_25_FN, FN_USB0_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) GP_5_24_FN, FN_USB0_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) GP_5_23_FN, FN_IP13_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) GP_5_22_FN, FN_IP13_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) GP_5_21_FN, FN_IP13_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) GP_5_20_FN, FN_IP13_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) GP_5_19_FN, FN_IP13_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) GP_5_18_FN, FN_IP13_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) GP_5_17_FN, FN_IP13_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) GP_5_16_FN, FN_IP13_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) GP_5_15_FN, FN_IP13_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) GP_5_14_FN, FN_IP12_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) GP_5_13_FN, FN_IP12_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) GP_5_12_FN, FN_IP12_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) GP_5_11_FN, FN_IP12_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) GP_5_10_FN, FN_IP12_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) GP_5_9_FN, FN_IP12_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) GP_5_8_FN, FN_IP12_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) GP_5_7_FN, FN_IP12_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) GP_5_6_FN, FN_IP12_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) GP_5_5_FN, FN_IP12_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) GP_5_4_FN, FN_IP12_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) GP_5_3_FN, FN_IP11_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) GP_5_2_FN, FN_IP11_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) GP_5_1_FN, FN_IP11_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) GP_5_0_FN, FN_IP11_20_18 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) GP_6_25_FN, FN_IP0_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) GP_6_24_FN, FN_IP0_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) GP_6_23_FN, FN_IP0_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) GP_6_22_FN, FN_IP0_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) GP_6_21_FN, FN_IP0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) GP_6_20_FN, FN_IP0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) GP_6_19_FN, FN_IP0_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) GP_6_18_FN, FN_IP0_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) GP_6_17_FN, FN_IP0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) GP_6_16_FN, FN_IP0_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) GP_6_15_FN, FN_IP0_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) GP_6_14_FN, FN_IP0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) GP_6_13_FN, FN_SD1_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) GP_6_12_FN, FN_SD1_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) GP_6_11_FN, FN_SD1_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) GP_6_10_FN, FN_SD1_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) GP_6_9_FN, FN_SD1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) GP_6_8_FN, FN_SD1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) GP_6_7_FN, FN_SD0_WP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) GP_6_6_FN, FN_SD0_CD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) GP_6_5_FN, FN_SD0_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) GP_6_4_FN, FN_SD0_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) GP_6_3_FN, FN_SD0_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) GP_6_2_FN, FN_SD0_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) GP_6_1_FN, FN_SD0_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) GP_6_0_FN, FN_SD0_CLK ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) GROUP(2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) /* IP0_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) /* IP0_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) /* IP0_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) /* IP0_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) FN_D2, FN_SCIFA3_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) /* IP0_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) FN_D1, FN_SCIFA3_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) /* IP0_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) /* IP0_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) /* IP0_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) /* IP0_17 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) FN_MMC_D5, FN_SD2_WP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) /* IP0_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) FN_MMC_D4, FN_SD2_CD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) /* IP0_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) FN_MMC_D3, FN_SD2_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) /* IP0_14 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) FN_MMC_D2, FN_SD2_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) /* IP0_13 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) FN_MMC_D1, FN_SD2_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) /* IP0_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) FN_MMC_D0, FN_SD2_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) /* IP0_11 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) FN_MMC_CMD, FN_SD2_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) /* IP0_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) FN_MMC_CLK, FN_SD2_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) /* IP0_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) /* IP0_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) /* IP0_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) /* IP0_5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) /* IP0_4 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) /* IP0_3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) /* IP0_2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) /* IP0_1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) /* IP0_0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) FN_SD1_CD, FN_CAN0_RX, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) GROUP(2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) 3, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) /* IP1_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) /* IP1_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) /* IP1_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) FN_A4, FN_SCIFB0_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) /* IP1_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) FN_A3, FN_SCIFB0_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) /* IP1_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) /* IP1_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) FN_A1, FN_SCIFB1_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) /* IP1_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) /* IP1_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) FN_D15, FN_SCIFA1_TXD, FN_I2C5_SDA_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) /* IP1_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) FN_D14, FN_SCIFA1_RXD, FN_I2C5_SCL_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) /* IP1_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) FN_D13, FN_SCIFA1_SCK, 0, FN_PWM2_C, FN_TCLK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) /* IP1_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) /* IP1_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) /* IP1_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) /* IP1_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) /* IP1_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) /* IP1_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) /* IP1_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) GROUP(2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) /* IP2_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) FN_A20, FN_SPCLK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) /* IP2_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) /* IP2_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) /* IP2_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) /* IP2_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) 0, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) /* IP2_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) /* IP2_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) /* IP2_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) /* IP2_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) /* IP2_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) FN_A11, FN_MSIOF1_SYNC, FN_IIC0_SDA_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) /* IP2_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) FN_A10, FN_MSIOF1_SCK, FN_IIC0_SCL_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) /* IP2_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) /* IP2_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) /* IP2_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) GROUP(1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) /* IP3_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) FN_RD_WR_N, FN_ATAG1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) /* IP3_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) FN_RD_N, FN_ATACS11_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) /* IP3_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) /* IP3_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) 0, FN_FMIN, FN_SCIFB2_RTS_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) /* IP3_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) 0, FN_FMCLK, FN_SCIFB2_CTS_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) /* IP3_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) 0, FN_BPFCLK, FN_SCIFB2_SCK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) /* IP3_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) 0, FN_TPUTO3, FN_SCIFB2_TXD, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) /* IP3_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) /* IP3_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) FN_EX_CS0_N, FN_VI1_DATA10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) /* IP3_11 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) FN_CS1_N_A26, FN_VI1_DATA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) /* IP3_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) FN_CS0_N, FN_VI1_DATA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) /* IP3_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) FN_A25, FN_SSL, FN_ATARD1_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) /* IP3_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) FN_A24, FN_IO3, FN_EX_WAIT2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) /* IP3_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) FN_A23, FN_IO2, 0, FN_ATAWR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) /* IP3_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) FN_A22, FN_MISO_IO1, 0, FN_ATADIR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) /* IP3_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) FN_A21, FN_MOSI_IO0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) /* IP4_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) FN_DU0_DG4, FN_LCDOUT12, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) /* IP4_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) FN_DU0_DG3, FN_LCDOUT11, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) /* IP4_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) FN_DU0_DG2, FN_LCDOUT10, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) /* IP4_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) /* IP4_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) /* IP4_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) FN_DU0_DR7, FN_LCDOUT23, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) /* IP4_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) FN_DU0_DR6, FN_LCDOUT22, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) /* IP4_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) FN_DU0_DR5, FN_LCDOUT21, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) /* IP4_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) FN_DU0_DR4, FN_LCDOUT20, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) /* IP4_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) FN_DU0_DR3, FN_LCDOUT19, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) /* IP4_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) FN_DU0_DR2, FN_LCDOUT18, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) /* IP4_7_5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) /* IP4_4_2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) /* IP4_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) GROUP(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) /* IP5_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) /* IP5_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) /* IP5_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) FN_DU0_DOTCLKOUT0, FN_QCLK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) /* IP5_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) FN_DU0_DOTCLKIN, FN_QSTVA_QVS, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) /* IP5_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) FN_DU0_DB7, FN_LCDOUT7, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) /* IP5_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) FN_DU0_DB6, FN_LCDOUT6, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) /* IP5_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) FN_DU0_DB5, FN_LCDOUT5, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) /* IP5_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) FN_DU0_DB4, FN_LCDOUT4, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) /* IP5_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) FN_DU0_DB3, FN_LCDOUT3, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) /* IP5_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) FN_DU0_DB2, FN_LCDOUT2, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) /* IP5_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) FN_CAN0_TX_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) /* IP5_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) FN_CAN0_RX_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) /* IP5_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) FN_DU0_DG7, FN_LCDOUT15, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) /* IP5_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) FN_DU0_DG6, FN_LCDOUT14, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) /* IP5_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) FN_DU0_DG5, FN_LCDOUT13, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) GROUP(3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) 1, 1, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) /* IP6_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_I2C5_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) FN_AVB_TX_CLK, FN_ADIDATA, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) /* IP6_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) /* IP6_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) FN_AVB_COL, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) /* IP6_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) FN_AVB_RX_ER, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) /* IP6_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) FN_AVB_RXD7, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) /* IP6_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) /* IP6_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) /* IP6_14 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) /* IP6_13 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) /* IP6_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) /* IP6_11 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) /* IP6_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) /* IP6_9 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) /* IP6_8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) FN_VI0_CLK, FN_AVB_RX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) /* IP6_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) FN_DU0_CDE, FN_QPOLB, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) /* IP6_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) FN_DU0_DISP, FN_QPOLA, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) /* IP6_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) /* IP6_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) /* IP7_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) FN_DREQ0_N, FN_SCIFB1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) /* IP7_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) /* IP7_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) /* IP7_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) FN_SSI_SCK6_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) /* IP7_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC0_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) /* IP7_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC0_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) /* IP7_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) FN_SSI_SCK5_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) /* IP7_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) FN_AVB_TXD4, FN_ADICHS2, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) /* IP7_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) FN_AVB_TXD3, FN_ADICHS1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) /* IP7_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) FN_AVB_TXD2, FN_ADICHS0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) /* IP7_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) FN_AVB_TXD1, FN_ADICLK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) /* IP7_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_I2C5_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) FN_AVB_TXD0, FN_ADICS_SAMP, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) GROUP(3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) /* IP8_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) 0, FN_TS_SDEN_D, FN_FMCLK_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) /* IP8_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) 0, FN_TS_SCK_D, FN_BPFCLK_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) /* IP8_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) 0, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) /* IP8_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) /* IP8_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) /* IP8_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) /* IP8_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) /* IP8_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) /* IP8_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) /* IP8_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) /* IP8_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) GROUP(1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) /* IP9_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) /* IP9_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) FN_SSI_SDATA1_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) /* IP9_27_25 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) FN_SSI_WS1_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) /* IP9_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) FN_SSI_SCK1_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) /* IP9_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) FN_REMOCON_B, FN_SPEEDIN_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) /* IP9_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) /* IP9_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) /* IP9_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) 0, FN_FMIN_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) /* IP9_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) 0, FN_FMCLK_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) /* IP9_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) 0, FN_BPFCLK_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) /* IP9_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) 0, FN_TPUTO1_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) /* IP9_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) 0, FN_TS_SPSYNC_D, FN_FMIN_C, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) /* IP10_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) /* IP10_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) /* IP10_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) FN_SSI_SDATA4_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) /* IP10_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) /* IP10_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) /* IP10_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) FN_SSI_SDATA9_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) /* IP10_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) /* IP10_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) FN_SCIF2_TXD, FN_IIC0_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) /* IP10_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) FN_SCIF2_RXD, FN_IIC0_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) /* IP10_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) FN_SCIF1_TXD, FN_I2C5_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) /* IP10_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) FN_SCIF1_RXD, FN_I2C5_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) GROUP(2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) /* IP11_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) /* IP11_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) /* IP11_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) /* IP11_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) /* IP11_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) FN_CAN_CLK_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) /* IP11_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_I2C5_SCL_C, FN_DU1_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) /* IP11_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_I2C5_SDA_C, FN_DU1_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) /* IP11_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) /* IP11_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) /* IP11_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) /* IP11_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) /* IP11_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) GROUP(2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) /* IP12_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) /* IP12_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) FN_ATAG0_N, FN_ETH_RXD1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) /* IP12_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) FN_ATAWR0_N, FN_ETH_RXD0_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) /* IP12_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC0_SDA_C, FN_VI1_DATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) FN_CAN0_TX_D, 0, FN_ETH_RX_ER_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) /* IP12_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC0_SCL_C, FN_VI1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) FN_CAN0_RX_D, 0, FN_ETH_CRS_DV_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) /* IP12_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) /* IP12_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) /* IP12_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) /* IP12_10_9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) /* IP12_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) /* IP12_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) /* IP12_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) 0, FN_DREQ1_N_B, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) GROUP(1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) /* IP13_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) /* IP13_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) /* IP13_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) /* IP13_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) /* IP13_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) /* IP13_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) FN_TS_SPSYNC_C, 0, FN_FMIN_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) /* IP13_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) FN_TS_SDEN_C, 0, FN_FMCLK_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) /* IP13_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) FN_TS_SCK_C, 0, FN_BPFCLK_E, FN_ETH_MDC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) /* IP13_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) FN_TS_SDATA_C, 0, FN_ETH_TXD0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) /* IP13_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) /* IP13_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) /* IP13_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) 0, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) /* IP13_5_3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) FN_VI1_DATA4, 0, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) /* IP13_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) 0, FN_ATACS00_N, FN_ETH_LINK_B, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) GROUP(2, 1, 2, 3, 4, 1, 1, 3, 3, 3, 3, 3, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) /* SEL_ADG [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) /* SEL_CAN [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) /* SEL_DARC [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) FN_SEL_DARC_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) /* RESERVED [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) /* SEL_ETH [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) FN_SEL_ETH_0, FN_SEL_ETH_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) /* SEL_IC200 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) FN_SEL_I2C00_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) /* SEL_I2C01 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) FN_SEL_I2C01_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) /* SEL_I2C02 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) FN_SEL_I2C02_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) /* SEL_I2C03 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) FN_SEL_I2C03_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) /* SEL_I2C04 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) FN_SEL_I2C04_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) /* SEL_I2C05 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) FN_SEL_I2C05_0, FN_SEL_I2C05_1, FN_SEL_I2C05_2, FN_SEL_I2C05_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) GROUP(2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) 2, 2, 1, 1, 2, 2, 2, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) /* SEL_IEB [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) /* SEL_IIC0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, FN_SEL_IIC0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) /* SEL_LBS [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) FN_SEL_LBS_0, FN_SEL_LBS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) /* SEL_MSI1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) FN_SEL_MSI1_0, FN_SEL_MSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) /* SEL_MSI2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) FN_SEL_MSI2_0, FN_SEL_MSI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) /* SEL_RAD [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) FN_SEL_RAD_0, FN_SEL_RAD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) /* SEL_RCN [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) FN_SEL_RCN_0, FN_SEL_RCN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) /* SEL_RSP [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) FN_SEL_RSP_0, FN_SEL_RSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) /* SEL_SCIFA0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) FN_SEL_SCIFA0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) /* SEL_SCIFA1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) /* SEL_SCIFA2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) /* SEL_SCIFA3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) /* SEL_SCIFA4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) FN_SEL_SCIFA4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) /* SEL_SCIFA5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) FN_SEL_SCIFA5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) /* SEL_TMU [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) FN_SEL_TMU_0, FN_SEL_TMU_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) /* SEL_TSIF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) /* SEL_CAN0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) /* SEL_CAN1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) /* SEL_HSCIF0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) /* SEL_HSCIF1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) GROUP(2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) /* SEL_SCIF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) /* SEL_SCIF1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) /* SEL_SCIF2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) /* SEL_SCIF3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) /* SEL_SCIF4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) FN_SEL_SCIF4_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) /* SEL_SCIF5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) /* SEL_SSI1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) FN_SEL_SSI1_0, FN_SEL_SSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) /* SEL_SSI2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) FN_SEL_SSI2_0, FN_SEL_SSI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) /* SEL_SSI4 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) FN_SEL_SSI4_0, FN_SEL_SSI4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) /* SEL_SSI5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) FN_SEL_SSI5_0, FN_SEL_SSI5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) /* SEL_SSI6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) FN_SEL_SSI6_0, FN_SEL_SSI6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) /* SEL_SSI7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) FN_SEL_SSI7_0, FN_SEL_SSI7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) /* SEL_SSI8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) FN_SEL_SSI8_0, FN_SEL_SSI8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) /* SEL_SSI9 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) FN_SEL_SSI9_0, FN_SEL_SSI9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) static int r8a7794_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) *pocctrl = 0xe606006c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) switch (pin & 0x1f) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) case 6: return 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) case 7: return 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) case 14: return 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) case 15: return 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) case 0 ... 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) case 8 ... 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) return 22 - (pin & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) case 16 ... 23:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) return 47 - (pin & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) static const struct soc_device_attribute r8a7794_tdsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) { .soc_id = "r8a7794", .revision = "ES1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) /* Initialize TDSEL on old revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) if (soc_device_match(r8a7794_tdsel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) sh_pfc_write(pfc, 0xe6060068, 0x55555500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) static const struct sh_pfc_soc_operations r8a7794_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) .init = r8a7794_pinmux_soc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) .pin_to_pocctrl = r8a7794_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) #ifdef CONFIG_PINCTRL_PFC_R8A7745
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) const struct sh_pfc_soc_info r8a7745_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) .name = "r8a77450_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) .ops = &r8a7794_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) #ifdef CONFIG_PINCTRL_PFC_R8A7794
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) const struct sh_pfc_soc_info r8a7794_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) .name = "r8a77940_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) .ops = &r8a7794_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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