^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7791/r8a7743 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014-2017 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Pins 0-23 assigned to GPIO bank 6 can be used for SD interfaces in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * which case they support both 3.3V and 1.8V signalling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_GP_32(0, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_GP_26(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_GP_32(2, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_GP_32(3, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_32(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_32(5, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_CFG_24(6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_1(6, 24, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_1(6, 25, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_1(6, 26, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_GP_1(6, 27, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PORT_GP_1(6, 28, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PORT_GP_1(6, 29, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PORT_GP_1(6, 30, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PORT_GP_1(6, 31, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PORT_GP_26(7, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FN_IP3_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FN_IP6_5_3, FN_IP6_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FN_IP9_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* GPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FN_IP13_22, FN_IP13_24_23, FN_SD1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FN_USB1_OVC, FN_DU0_DOTCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* GPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FN_A15, FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FN_A17, FN_DACK2_B, FN_I2C0_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FN_A20, FN_SPCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FN_EX_CS1_N, FN_MSIOF2_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FN_DREQ0, FN_PWM3, FN_TPU_TO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FN_DACK0, FN_DRACK0, FN_REMOCON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B, FN_MSIOF2_SYNC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FN_GLO_I0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FN_GLO_Q1_D, FN_HCTS1_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FN_SSI_SCK4, FN_GLO_SS_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FN_SSI_WS4, FN_GLO_RFON_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FN_MSIOF2_TXD_D, FN_VI1_R3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FN_MSIOF2_SS1_D, FN_VI1_R4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FN_MSIOF2_RXD_D, FN_VI1_R5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FN_SCIFA2_RXD, FN_FMIN_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FN_SCIF_CLK_B, FN_GPS_MAG_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FN_SCIFA1_SCK, FN_SSI_SCK78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) FN_DU1_DOTCLKOUT0, FN_QCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FN_DU1_DISP, FN_QPOLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FN_TS_SDATA0_C, FN_ATACS11_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FN_TS_SCK0_C, FN_ATAG1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_I2C1_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FN_VI1_DATA7, FN_AVB_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) FN_ADICLK_B, FN_MSIOF0_SS1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FN_ADICHS2_B, FN_MSIOF0_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FN_SCIFA5_TXD_B, FN_TX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FN_SCIFA5_RXD_B, FN_RX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FN_SD1_DATA3, FN_IERX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FN_PWM5_B, FN_SCIFA3_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FN_VI1_G6_B, FN_SCIFA3_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FN_VI1_G7_B, FN_SCIFA3_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FN_TCLK2, FN_VI1_DATA3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* MOD_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FN_SEL_SSI9_0, FN_SEL_SSI9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FN_SEL_SCFA_0, FN_SEL_SCFA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FN_SEL_QSP_0, FN_SEL_QSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FN_SEL_SSI7_0, FN_SEL_SSI7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) FN_SEL_HSCIF1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FN_SEL_TMU1_0, FN_SEL_TMU1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* MOD_SEL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FN_SEL_SCIF0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FN_SEL_SCIF_0, FN_SEL_SCIF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FN_SEL_CAN0_4, FN_SEL_CAN0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FN_SEL_ADG_0, FN_SEL_ADG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) FN_SEL_SIM_0, FN_SEL_SIM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) FN_SEL_SSI8_0, FN_SEL_SSI8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* MOD_SEL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) FN_SEL_MMC_0, FN_SEL_MMC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) FN_SEL_I2C1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* MOD_SEL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) FN_SEL_SOF1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) FN_SEL_RAD_0, FN_SEL_RAD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) FN_SEL_RCN_0, FN_SEL_RCN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) FN_SEL_RSP_0, FN_SEL_RSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) FN_SEL_SCIF2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) FN_SEL_SOF2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) FN_SEL_SSI1_0, FN_SEL_SSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) FN_SEL_SSI0_0, FN_SEL_SSI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) EX_CS0_N_MARK, RD_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SD1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DU0_DOTCLKIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) D6_MARK, D7_MARK, D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, I2C0_SCL_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, I2C0_SCL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) A9_MARK, MSIOF1_SS2_MARK, I2C0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) A11_MARK, MSIOF1_RXD_MARK, I2C3_SCL_D_MARK, MSIOF1_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) A12_MARK, FMCLK_MARK, I2C3_SDA_D_MARK, MSIOF1_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) A15_MARK, BPFCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) A17_MARK, DACK2_B_MARK, I2C0_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) A20_MARK, SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) RX1_MARK, SCIFA1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) CS0_N_MARK, ATAG0_N_B_MARK, I2C1_SCL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) CS1_N_A26_MARK, ATADIR0_N_B_MARK, I2C1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) EX_CS1_N_MARK, MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) ATAG0_N_MARK, EX_WAIT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) SSI_SDATA0_MARK, I2C0_SCL_B_MARK, IIC0_SCL_B_MARK, MSIOF2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) SSI_SCK1_MARK, I2C0_SDA_B_MARK, IIC0_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) SSI_WS1_MARK, I2C1_SCL_B_MARK, IIC1_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SSI_SDATA1_MARK, I2C1_SDA_B_MARK, IIC1_SDA_B_MARK, MSIOF2_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) SSI_SCK2_MARK, I2C2_SCL_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) HSCK1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SSI_WS2_MARK, I2C2_SDA_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) GLO_Q1_D_MARK, HCTS1_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) SSI_SCK4_MARK, GLO_SS_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SSI_WS4_MARK, GLO_RFON_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) SCIF_CLK_MARK, DVC_MUTE_MARK, BPFCLK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SCIFA2_RXD_MARK, FMIN_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) IRQ3_MARK, I2C4_SCL_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) IRQ4_MARK, HRX1_C_MARK, I2C4_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) IRQ5_MARK, HTX1_C_MARK, I2C1_SCL_E_MARK, MSIOF2_SCK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) I2C1_SDA_E_MARK, MSIOF2_SYNC_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GPS_CLK_C_MARK, GPS_CLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) DU1_DB6_MARK, LCDOUT22_MARK, I2C3_SCL_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) DU1_DB7_MARK, LCDOUT23_MARK, I2C3_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) DU1_DOTCLKOUT0_MARK, QCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) TX3_B_MARK, I2C2_SCL_B_MARK, PWM4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) CAN0_RX_MARK, RX3_B_MARK, I2C2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) DU1_DISP_MARK, QPOLA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) VI0_G0_MARK, IIC1_SCL_MARK, STP_IVCXO27_0_C_MARK, I2C4_SCL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) VI0_G1_MARK, IIC1_SDA_MARK, STP_ISCLK_0_C_MARK, I2C4_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, I2C3_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, I2C3_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) TS_SDATA0_C_MARK, ATACS11_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) TS_SCK0_C_MARK, ATAG1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) I2C1_SCL_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) I2C1_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, I2C4_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) I2C4_SDA_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) TX4_B_MARK, SCIFA4_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) RX4_B_MARK, SCIFA4_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) VI1_DATA7_MARK, AVB_MDC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ETH_MDIO_MARK, AVB_RX_CLK_MARK, I2C2_SCL_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ETH_CRS_DV_MARK, AVB_LINK_MARK, I2C2_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ETH_RX_ER_MARK, AVB_CRS_MARK, I2C3_SCL_MARK, IIC0_SCL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ETH_RXD0_MARK, AVB_PHY_INT_MARK, I2C3_SDA_MARK, IIC0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) I2C2_SCL_D_MARK, MSIOF1_RXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) I2C2_SDA_D_MARK, MSIOF1_SCK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) SCIFA5_TXD_B_MARK, TX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) SCIFA5_RXD_B_MARK, RX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) SD1_DATA3_MARK, IERX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, I2C1_SCL_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SD1_WP_MARK, PWM1_B_MARK, I2C1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SD2_CD_MARK, MMC_D4_MARK, IIC1_SCL_C_MARK, TX5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) SCIFA5_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) SD2_WP_MARK, MMC_D5_MARK, IIC1_SDA_C_MARK, RX5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) SCIFA5_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) VI1_CLK_C_MARK, VI1_G0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) VI1_HSYNC_N_C_MARK, IIC0_SCL_C_MARK, VI1_G4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) VI1_VSYNC_N_C_MARK, IIC0_SDA_C_MARK, VI1_G5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PWM5_B_MARK, SCIFA3_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) TCLK1_MARK, VI1_DATA1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) TCLK2_MARK, VI1_DATA3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GLO_SS_C_MARK, VI1_DATA7_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CLK_MARK, GLO_RFON_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_SINGLE(EX_CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_SINGLE(RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_SINGLE(AUDIO_CLKA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_SINGLE(VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_SINGLE(VI0_DATA0_VI0_B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_SINGLE(VI0_DATA1_VI0_B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_SINGLE(VI0_DATA2_VI0_B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_SINGLE(VI0_DATA4_VI0_B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_SINGLE(VI0_DATA5_VI0_B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_SINGLE(VI0_DATA6_VI0_B6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_SINGLE(VI0_DATA7_VI0_B7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_SINGLE(USB0_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_SINGLE(USB0_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_SINGLE(USB1_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_SINGLE(USB1_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_SINGLE(DU0_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_SINGLE(SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_GPSR(IP0_0, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP0_1, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP0_2, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_GPSR(IP0_3, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_GPSR(IP0_4, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP0_5, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_GPSR(IP0_6, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_GPSR(IP0_7, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP0_8, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_GPSR(IP0_9, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_GPSR(IP0_10, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP0_11, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_GPSR(IP0_12, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_GPSR(IP0_13, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP0_14, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP0_15, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_GPSR(IP0_18_16, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_MSEL(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_MSEL(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_MSEL(IP0_18_16, I2C0_SCL_C, SEL_I2C0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_GPSR(IP0_18_16, PWM2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_GPSR(IP0_20_19, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_MSEL(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_GPSR(IP0_22_21, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_MSEL(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_GPSR(IP0_24_23, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_MSEL(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_GPSR(IP0_26_25, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_MSEL(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_GPSR(IP0_28_27, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_MSEL(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_GPSR(IP0_30_29, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_MSEL(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_GPSR(IP1_1_0, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_MSEL(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_GPSR(IP1_3_2, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_IPSR_MSEL(IP1_3_2, I2C0_SCL, SEL_I2C0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_GPSR(IP1_5_4, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_MSEL(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_MSEL(IP1_5_4, I2C0_SDA, SEL_I2C0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_GPSR(IP1_7_6, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_MSEL(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP1_10_8, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_IPSR_MSEL(IP1_10_8, I2C3_SCL_D, SEL_I2C3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_MSEL(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_GPSR(IP1_13_11, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_MSEL(IP1_13_11, FMCLK, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_MSEL(IP1_13_11, I2C3_SDA_D, SEL_I2C3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_MSEL(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_GPSR(IP1_16_14, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_MSEL(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_MSEL(IP1_16_14, BPFCLK, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_MSEL(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_GPSR(IP1_19_17, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_MSEL(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_MSEL(IP1_19_17, FMIN, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_MSEL(IP1_19_17, FMIN_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_MSEL(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_GPSR(IP1_22_20, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_MSEL(IP1_22_20, BPFCLK_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_GPSR(IP1_25_23, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_MSEL(IP1_25_23, DREQ2_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_MSEL(IP1_25_23, FMCLK_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_MSEL(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_GPSR(IP1_28_26, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_MSEL(IP1_28_26, DACK2_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_MSEL(IP1_28_26, I2C0_SDA_C, SEL_I2C0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_GPSR(IP1_31_29, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_MSEL(IP1_31_29, DREQ1, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_MSEL(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_MSEL(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_IPSR_GPSR(IP2_2_0, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_GPSR(IP2_2_0, DACK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_MSEL(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_GPSR(IP2_2_0, A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_MSEL(IP2_4_3, SPCLK, SEL_QSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_GPSR(IP2_6_5, A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_MSEL(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_MSEL(IP2_6_5, MOSI_IO0, SEL_QSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_GPSR(IP2_9_7, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_MSEL(IP2_9_7, MISO_IO1, SEL_QSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_MSEL(IP2_9_7, FMCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_MSEL(IP2_9_7, TX0, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_MSEL(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_GPSR(IP2_12_10, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_MSEL(IP2_12_10, IO2, SEL_QSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_MSEL(IP2_12_10, BPFCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_MSEL(IP2_12_10, RX0, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_MSEL(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP2_15_13, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP2_15_13, DREQ2, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_MSEL(IP2_15_13, IO3, SEL_QSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_MSEL(IP2_15_13, TX1, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_MSEL(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_GPSR(IP2_18_16, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_MSEL(IP2_18_16, DACK2, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_MSEL(IP2_18_16, SSL, SEL_QSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_MSEL(IP2_18_16, DREQ1_C, SEL_LBS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_MSEL(IP2_18_16, RX1, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_IPSR_MSEL(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_GPSR(IP2_20_19, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_MSEL(IP2_20_19, I2C1_SCL, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_GPSR(IP2_22_21, CS1_N_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_MSEL(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_MSEL(IP2_22_21, I2C1_SDA, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP2_24_23, EX_CS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_MSEL(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_GPSR(IP2_26_25, EX_CS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_MSEL(IP2_26_25, ATAWR0_N, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_MSEL(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_GPSR(IP2_29_27, EX_CS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_IPSR_MSEL(IP2_29_27, ATADIR0_N, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_MSEL(IP2_29_27, ATAG0_N, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_GPSR(IP2_29_27, EX_WAIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_GPSR(IP3_2_0, EX_CS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_MSEL(IP3_2_0, ATARD0_N, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_IPSR_MSEL(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_GPSR(IP3_2_0, EX_WAIT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP3_5_3, EX_CS5_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_GPSR(IP3_5_3, ATACS00_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_MSEL(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_MSEL(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_IPSR_MSEL(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINMUX_IPSR_GPSR(IP3_5_3, PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_GPSR(IP3_5_3, TPU_TO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_GPSR(IP3_8_6, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_GPSR(IP3_8_6, ATACS10_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_MSEL(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_IPSR_MSEL(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_MSEL(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_GPSR(IP3_8_6, PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP3_8_6, TPU_TO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_GPSR(IP3_11_9, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_IPSR_MSEL(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_MSEL(IP3_11_9, FMIN_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_MSEL(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_MSEL(IP3_11_9, DREQ1_D, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_GPSR(IP3_13_12, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_IPSR_MSEL(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_MSEL(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_GPSR(IP3_15_14, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_MSEL(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_MSEL(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_IPSR_MSEL(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP3_17_16, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_MSEL(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_MSEL(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_GPSR(IP3_19_18, DREQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_GPSR(IP3_19_18, PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_GPSR(IP3_19_18, TPU_TO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_IPSR_GPSR(IP3_21_20, DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_IPSR_GPSR(IP3_21_20, DRACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_MSEL(IP3_21_20, REMOCON, SEL_RCN_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_MSEL(IP3_24_22, SPEEDIN, SEL_RSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_MSEL(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_MSEL(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_IPSR_MSEL(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_MSEL(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_MSEL(IP3_24_22, DREQ2_C, SEL_LBS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_MSEL(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_MSEL(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_IPSR_MSEL(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_MSEL(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_MSEL(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_MSEL(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_MSEL(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_IPSR_MSEL(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_MSEL(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_MSEL(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_MSEL(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_MSEL(IP4_1_0, I2C0_SCL_B, SEL_I2C0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINMUX_IPSR_MSEL(IP4_1_0, IIC0_SCL_B, SEL_IIC0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_IPSR_MSEL(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_MSEL(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_MSEL(IP4_4_2, I2C0_SDA_B, SEL_I2C0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_MSEL(IP4_4_2, IIC0_SDA_B, SEL_IIC0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_MSEL(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_MSEL(IP4_4_2, GLO_I0_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_MSEL(IP4_7_5, SSI_WS1, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_MSEL(IP4_7_5, I2C1_SCL_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_MSEL(IP4_7_5, IIC1_SCL_B, SEL_IIC1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_IPSR_MSEL(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_MSEL(IP4_7_5, GLO_I1_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_MSEL(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_MSEL(IP4_9_8, I2C1_SDA_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_MSEL(IP4_9_8, IIC1_SDA_B, SEL_IIC1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_IPSR_MSEL(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_IPSR_GPSR(IP4_12_10, SSI_SCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_MSEL(IP4_12_10, I2C2_SCL, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_MSEL(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_MSEL(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_IPSR_MSEL(IP4_12_10, HSCK1_E, SEL_HSCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_GPSR(IP4_15_13, SSI_WS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_MSEL(IP4_15_13, I2C2_SDA, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_MSEL(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_IPSR_MSEL(IP4_15_13, RX2_E, SEL_SCIF2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_MSEL(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_IPSR_MSEL(IP4_15_13, HCTS1_N_E, SEL_HSCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_GPSR(IP4_18_16, SSI_SDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_MSEL(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_MSEL(IP4_18_16, TX2_E, SEL_SCIF2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_MSEL(IP4_18_16, HRTS1_N_E, SEL_HSCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_GPSR(IP4_19, SSI_SCK34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_GPSR(IP4_20, SSI_WS34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_GPSR(IP4_21, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_IPSR_GPSR(IP4_23_22, SSI_SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_MSEL(IP4_23_22, GLO_SS_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_GPSR(IP4_25_24, SSI_WS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_MSEL(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_GPSR(IP4_27_26, SSI_SDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_IPSR_MSEL(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_IPSR_GPSR(IP4_30_28, SSI_SCK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_MSEL(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_IPSR_MSEL(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_MSEL(IP4_30_28, GLO_I0, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_IPSR_MSEL(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_GPSR(IP4_30_28, VI1_R2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_GPSR(IP5_2_0, SSI_WS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_MSEL(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_IPSR_MSEL(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_MSEL(IP5_2_0, GLO_I1, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_IPSR_MSEL(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_IPSR_GPSR(IP5_2_0, VI1_R3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_GPSR(IP5_5_3, SSI_SDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_MSEL(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_MSEL(IP5_5_3, GLO_Q0, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_IPSR_MSEL(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_IPSR_GPSR(IP5_5_3, VI1_R4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_GPSR(IP5_8_6, SSI_SCK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_MSEL(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_MSEL(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_MSEL(IP5_8_6, GLO_Q1, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_IPSR_MSEL(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_GPSR(IP5_8_6, VI1_R5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_GPSR(IP5_11_9, SSI_WS6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_MSEL(IP5_11_9, GLO_SCLK, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_MSEL(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_GPSR(IP5_11_9, VI1_R6_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_IPSR_GPSR(IP5_14_12, SSI_SDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_MSEL(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_MSEL(IP5_14_12, GLO_SDATA, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_GPSR(IP5_14_12, VI1_R7_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_MSEL(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_IPSR_MSEL(IP5_16_15, GLO_SS, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_MSEL(IP5_19_17, SSI_WS78, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_IPSR_MSEL(IP5_19_17, TX0_D, SEL_SCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_MSEL(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_MSEL(IP5_19_17, GLO_RFON, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_MSEL(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_IPSR_MSEL(IP5_21_20, RX0_D, SEL_SCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_MSEL(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_MSEL(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_MSEL(IP5_23_22, TX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_MSEL(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_IPSR_MSEL(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_MSEL(IP5_25_24, RX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_MSEL(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_MSEL(IP5_28_26, SSI_WS9, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_MSEL(IP5_28_26, TX3_D, SEL_SCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_IPSR_MSEL(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_MSEL(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_MSEL(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_IPSR_MSEL(IP5_31_29, RX3_D, SEL_SCIF3_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINMUX_IPSR_MSEL(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_IPSR_MSEL(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_MSEL(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_MSEL(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_GPSR(IP6_2_0, DVC_MUTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_MSEL(IP6_2_0, BPFCLK_E, SEL_FM_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_IPSR_GPSR(IP6_5_3, AUDIO_CLKC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_MSEL(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_MSEL(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_MSEL(IP6_5_3, RX2, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_IPSR_MSEL(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_MSEL(IP6_5_3, FMIN_E, SEL_FM_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_GPSR(IP6_7_6, AUDIO_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_MSEL(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_MSEL(IP6_7_6, TX2, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_MSEL(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_GPSR(IP6_9_8, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_MSEL(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_GPSR(IP6_9_8, INTC_IRQ0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_GPSR(IP6_11_10, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_MSEL(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_GPSR(IP6_11_10, INTC_IRQ1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_GPSR(IP6_13_12, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PINMUX_IPSR_MSEL(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_GPSR(IP6_13_12, INTC_IRQ2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_IPSR_GPSR(IP6_15_14, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_MSEL(IP6_15_14, I2C4_SCL_C, SEL_I2C4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_IPSR_MSEL(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_IPSR_GPSR(IP6_15_14, INTC_IRQ4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_GPSR(IP6_18_16, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_IPSR_MSEL(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINMUX_IPSR_MSEL(IP6_18_16, I2C4_SDA_C, SEL_I2C4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_MSEL(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_IPSR_GPSR(IP6_18_16, INTC_IRQ4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_GPSR(IP6_20_19, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_MSEL(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_IPSR_MSEL(IP6_20_19, I2C1_SCL_E, SEL_I2C1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_IPSR_MSEL(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINMUX_IPSR_GPSR(IP6_23_21, IRQ6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_IPSR_MSEL(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_MSEL(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_IPSR_MSEL(IP6_23_21, I2C1_SDA_E, SEL_I2C1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_MSEL(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINMUX_IPSR_GPSR(IP6_26_24, IRQ7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_IPSR_MSEL(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_IPSR_MSEL(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_IPSR_MSEL(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_IPSR_GPSR(IP6_29_27, IRQ8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_MSEL(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_MSEL(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_IPSR_MSEL(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_GPSR(IP7_2_0, IRQ9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_MSEL(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_MSEL(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_IPSR_MSEL(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_MSEL(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_IPSR_GPSR(IP7_5_3, DU1_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_GPSR(IP7_5_3, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINMUX_IPSR_MSEL(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_IPSR_MSEL(IP7_5_3, TX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINMUX_IPSR_MSEL(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_IPSR_GPSR(IP7_8_6, DU1_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_GPSR(IP7_8_6, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_IPSR_MSEL(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_IPSR_MSEL(IP7_8_6, RX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_IPSR_MSEL(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_IPSR_GPSR(IP7_10_9, DU1_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_IPSR_GPSR(IP7_10_9, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_IPSR_MSEL(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_IPSR_GPSR(IP7_12_11, DU1_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_GPSR(IP7_12_11, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_IPSR_MSEL(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_IPSR_GPSR(IP7_14_13, DU1_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_GPSR(IP7_14_13, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_IPSR_MSEL(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_GPSR(IP7_16_15, DU1_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINMUX_IPSR_GPSR(IP7_16_15, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_IPSR_MSEL(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_IPSR_GPSR(IP7_18_17, DU1_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_GPSR(IP7_18_17, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_IPSR_MSEL(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_IPSR_GPSR(IP7_20_19, DU1_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_GPSR(IP7_20_19, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_IPSR_MSEL(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_IPSR_GPSR(IP7_23_21, DU1_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_IPSR_GPSR(IP7_23_21, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_MSEL(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_MSEL(IP7_23_21, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_IPSR_MSEL(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_MSEL(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_IPSR_GPSR(IP7_26_24, DU1_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_GPSR(IP7_26_24, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINMUX_IPSR_MSEL(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_IPSR_MSEL(IP7_26_24, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_MSEL(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_MSEL(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_IPSR_GPSR(IP7_29_27, DU1_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_GPSR(IP7_29_27, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_MSEL(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_IPSR_GPSR(IP7_29_27, SCIF1_SCK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_MSEL(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINMUX_IPSR_MSEL(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_IPSR_GPSR(IP8_2_0, DU1_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_GPSR(IP8_2_0, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_IPSR_MSEL(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_MSEL(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINMUX_IPSR_GPSR(IP8_5_3, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_IPSR_MSEL(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINMUX_IPSR_MSEL(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_MSEL(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_MSEL(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINMUX_IPSR_GPSR(IP8_8_6, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_IPSR_MSEL(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_MSEL(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_IPSR_MSEL(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_MSEL(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_IPSR_GPSR(IP8_11_9, DU1_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_IPSR_GPSR(IP8_11_9, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_IPSR_MSEL(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINMUX_IPSR_MSEL(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINMUX_IPSR_MSEL(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_IPSR_GPSR(IP8_14_12, DU1_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_IPSR_GPSR(IP8_14_12, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_MSEL(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_IPSR_MSEL(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_MSEL(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_GPSR(IP8_17_15, DU1_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINMUX_IPSR_GPSR(IP8_17_15, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINMUX_IPSR_MSEL(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_MSEL(IP8_17_15, TX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_IPSR_MSEL(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_IPSR_MSEL(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_GPSR(IP8_20_18, DU1_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_GPSR(IP8_20_18, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_IPSR_MSEL(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_IPSR_MSEL(IP8_20_18, RX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_IPSR_MSEL(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_IPSR_MSEL(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_IPSR_GPSR(IP8_23_21, DU1_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_IPSR_GPSR(IP8_23_21, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_IPSR_MSEL(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_IPSR_GPSR(IP8_23_21, SCIF2_SCK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_IPSR_MSEL(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINMUX_IPSR_MSEL(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_IPSR_GPSR(IP8_25_24, DU1_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINMUX_IPSR_GPSR(IP8_25_24, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_IPSR_MSEL(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_IPSR_GPSR(IP8_27_26, DU1_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINMUX_IPSR_GPSR(IP8_27_26, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINMUX_IPSR_MSEL(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_IPSR_MSEL(IP8_27_26, CAN1_RX, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINMUX_IPSR_GPSR(IP8_30_28, DU1_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_IPSR_GPSR(IP8_30_28, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_IPSR_MSEL(IP8_30_28, TX3, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINMUX_IPSR_MSEL(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINMUX_IPSR_MSEL(IP8_30_28, CAN1_TX, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_IPSR_GPSR(IP9_2_0, DU1_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_IPSR_GPSR(IP9_2_0, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINMUX_IPSR_MSEL(IP9_2_0, I2C3_SCL_C, SEL_I2C3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_IPSR_MSEL(IP9_2_0, RX3, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_IPSR_MSEL(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINMUX_IPSR_GPSR(IP9_5_3, DU1_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINMUX_IPSR_GPSR(IP9_5_3, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINMUX_IPSR_MSEL(IP9_5_3, I2C3_SDA_C, SEL_I2C3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINMUX_IPSR_MSEL(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINMUX_IPSR_MSEL(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_IPSR_MSEL(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINMUX_IPSR_GPSR(IP9_6, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINMUX_IPSR_GPSR(IP9_7, DU1_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PINMUX_IPSR_GPSR(IP9_7, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINMUX_IPSR_GPSR(IP9_10_8, DU1_DOTCLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINMUX_IPSR_GPSR(IP9_10_8, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_IPSR_MSEL(IP9_10_8, CAN0_TX, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINMUX_IPSR_MSEL(IP9_10_8, TX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PINMUX_IPSR_MSEL(IP9_10_8, I2C2_SCL_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_IPSR_GPSR(IP9_10_8, PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINMUX_IPSR_GPSR(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PINMUX_IPSR_GPSR(IP9_11, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINMUX_IPSR_GPSR(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINMUX_IPSR_GPSR(IP9_12, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINMUX_IPSR_GPSR(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINMUX_IPSR_GPSR(IP9_15_13, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINMUX_IPSR_MSEL(IP9_15_13, CAN0_RX, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PINMUX_IPSR_MSEL(IP9_15_13, RX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINMUX_IPSR_MSEL(IP9_15_13, I2C2_SDA_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINMUX_IPSR_GPSR(IP9_16, DU1_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINMUX_IPSR_GPSR(IP9_16, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINMUX_IPSR_GPSR(IP9_18_17, DU1_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINMUX_IPSR_GPSR(IP9_18_17, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PINMUX_IPSR_GPSR(IP9_18_17, PWM4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINMUX_IPSR_GPSR(IP9_20_19, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINMUX_IPSR_MSEL(IP9_20_19, TX4, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINMUX_IPSR_MSEL(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINMUX_IPSR_MSEL(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINMUX_IPSR_GPSR(IP9_22_21, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINMUX_IPSR_MSEL(IP9_22_21, RX4, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINMUX_IPSR_MSEL(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINMUX_IPSR_MSEL(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PINMUX_IPSR_GPSR(IP9_24_23, VI0_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINMUX_IPSR_MSEL(IP9_24_23, TX5, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_IPSR_MSEL(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINMUX_IPSR_MSEL(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINMUX_IPSR_GPSR(IP9_26_25, VI0_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINMUX_IPSR_MSEL(IP9_26_25, RX5, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINMUX_IPSR_MSEL(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINMUX_IPSR_MSEL(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINMUX_IPSR_GPSR(IP9_28_27, VI0_DATA3_VI0_B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINMUX_IPSR_MSEL(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINMUX_IPSR_MSEL(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINMUX_IPSR_GPSR(IP9_31_29, VI0_G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINMUX_IPSR_MSEL(IP9_31_29, IIC1_SCL, SEL_IIC1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINMUX_IPSR_MSEL(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINMUX_IPSR_MSEL(IP9_31_29, I2C4_SCL, SEL_I2C4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINMUX_IPSR_MSEL(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINMUX_IPSR_MSEL(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINMUX_IPSR_GPSR(IP9_31_29, ATAWR1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINMUX_IPSR_GPSR(IP10_2_0, VI0_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINMUX_IPSR_MSEL(IP10_2_0, IIC1_SDA, SEL_IIC1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINMUX_IPSR_MSEL(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINMUX_IPSR_MSEL(IP10_2_0, I2C4_SDA, SEL_I2C4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) PINMUX_IPSR_MSEL(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINMUX_IPSR_MSEL(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINMUX_IPSR_GPSR(IP10_2_0, ATADIR1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINMUX_IPSR_GPSR(IP10_5_3, VI0_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINMUX_IPSR_GPSR(IP10_5_3, VI2_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINMUX_IPSR_MSEL(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINMUX_IPSR_MSEL(IP10_5_3, I2C3_SCL_B, SEL_I2C3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINMUX_IPSR_MSEL(IP10_5_3, HSCK2, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINMUX_IPSR_MSEL(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINMUX_IPSR_GPSR(IP10_5_3, ATARD1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINMUX_IPSR_GPSR(IP10_8_6, VI0_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINMUX_IPSR_GPSR(IP10_8_6, VI2_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINMUX_IPSR_MSEL(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINMUX_IPSR_MSEL(IP10_8_6, I2C3_SDA_B, SEL_I2C3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINMUX_IPSR_MSEL(IP10_8_6, HRX2, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINMUX_IPSR_MSEL(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINMUX_IPSR_GPSR(IP10_8_6, ATACS01_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINMUX_IPSR_GPSR(IP10_11_9, VI0_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINMUX_IPSR_GPSR(IP10_11_9, VI2_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINMUX_IPSR_MSEL(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINMUX_IPSR_MSEL(IP10_11_9, HTX2, SEL_HSCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINMUX_IPSR_MSEL(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINMUX_IPSR_MSEL(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINMUX_IPSR_GPSR(IP10_14_12, VI0_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINMUX_IPSR_GPSR(IP10_14_12, VI2_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINMUX_IPSR_MSEL(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINMUX_IPSR_MSEL(IP10_14_12, FMCLK_D, SEL_FM_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINMUX_IPSR_MSEL(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINMUX_IPSR_MSEL(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINMUX_IPSR_MSEL(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINMUX_IPSR_GPSR(IP10_16_15, VI0_G6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINMUX_IPSR_GPSR(IP10_16_15, VI2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINMUX_IPSR_MSEL(IP10_16_15, BPFCLK_D, SEL_FM_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINMUX_IPSR_GPSR(IP10_18_17, VI0_G7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINMUX_IPSR_GPSR(IP10_18_17, VI2_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINMUX_IPSR_MSEL(IP10_18_17, FMIN_D, SEL_FM_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINMUX_IPSR_GPSR(IP10_21_19, VI0_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINMUX_IPSR_GPSR(IP10_21_19, VI2_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINMUX_IPSR_MSEL(IP10_21_19, GLO_I0_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINMUX_IPSR_MSEL(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINMUX_IPSR_GPSR(IP10_21_19, ATACS11_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINMUX_IPSR_GPSR(IP10_24_22, VI0_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINMUX_IPSR_GPSR(IP10_24_22, VI2_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINMUX_IPSR_MSEL(IP10_24_22, GLO_I1_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINMUX_IPSR_MSEL(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINMUX_IPSR_GPSR(IP10_24_22, ATAG1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINMUX_IPSR_GPSR(IP10_26_25, VI0_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINMUX_IPSR_GPSR(IP10_26_25, VI2_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINMUX_IPSR_MSEL(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINMUX_IPSR_MSEL(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINMUX_IPSR_GPSR(IP10_28_27, VI0_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINMUX_IPSR_GPSR(IP10_28_27, VI2_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINMUX_IPSR_MSEL(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINMUX_IPSR_MSEL(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINMUX_IPSR_GPSR(IP10_31_29, VI0_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINMUX_IPSR_GPSR(IP10_31_29, VI2_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINMUX_IPSR_MSEL(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINMUX_IPSR_MSEL(IP10_31_29, TX0_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINMUX_IPSR_MSEL(IP10_31_29, I2C1_SCL_D, SEL_I2C1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINMUX_IPSR_GPSR(IP11_2_0, VI0_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINMUX_IPSR_GPSR(IP11_2_0, VI2_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINMUX_IPSR_MSEL(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINMUX_IPSR_MSEL(IP11_2_0, RX0_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINMUX_IPSR_MSEL(IP11_2_0, I2C1_SDA_D, SEL_I2C1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINMUX_IPSR_GPSR(IP11_5_3, VI0_R6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINMUX_IPSR_GPSR(IP11_5_3, VI2_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINMUX_IPSR_MSEL(IP11_5_3, GLO_SS_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINMUX_IPSR_MSEL(IP11_5_3, TX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINMUX_IPSR_MSEL(IP11_5_3, I2C4_SCL_B, SEL_I2C4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINMUX_IPSR_GPSR(IP11_8_6, VI0_R7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINMUX_IPSR_MSEL(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINMUX_IPSR_MSEL(IP11_8_6, RX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINMUX_IPSR_MSEL(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINMUX_IPSR_MSEL(IP11_8_6, I2C4_SDA_B, SEL_I2C4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINMUX_IPSR_MSEL(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINMUX_IPSR_MSEL(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINMUX_IPSR_MSEL(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINMUX_IPSR_GPSR(IP11_11_9, AVB_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINMUX_IPSR_MSEL(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINMUX_IPSR_MSEL(IP11_11_9, TX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINMUX_IPSR_MSEL(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINMUX_IPSR_MSEL(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINMUX_IPSR_GPSR(IP11_14_12, AVB_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINMUX_IPSR_MSEL(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINMUX_IPSR_MSEL(IP11_14_12, RX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINMUX_IPSR_MSEL(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINMUX_IPSR_MSEL(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINMUX_IPSR_GPSR(IP11_16_15, AVB_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINMUX_IPSR_MSEL(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINMUX_IPSR_MSEL(IP11_18_17, VI1_FIELD, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINMUX_IPSR_GPSR(IP11_18_17, AVB_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINMUX_IPSR_MSEL(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINMUX_IPSR_MSEL(IP11_19, VI1_CLK, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINMUX_IPSR_GPSR(IP11_19, AVB_RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINMUX_IPSR_MSEL(IP11_20, VI1_DATA0, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINMUX_IPSR_GPSR(IP11_20, AVB_RXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINMUX_IPSR_MSEL(IP11_21, VI1_DATA1, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINMUX_IPSR_GPSR(IP11_21, AVB_RXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINMUX_IPSR_MSEL(IP11_22, VI1_DATA2, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINMUX_IPSR_GPSR(IP11_22, AVB_RXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINMUX_IPSR_MSEL(IP11_23, VI1_DATA3, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PINMUX_IPSR_GPSR(IP11_23, AVB_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINMUX_IPSR_MSEL(IP11_24, VI1_DATA4, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PINMUX_IPSR_GPSR(IP11_24, AVB_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PINMUX_IPSR_MSEL(IP11_25, VI1_DATA5, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PINMUX_IPSR_GPSR(IP11_25, AVB_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PINMUX_IPSR_MSEL(IP11_26, VI1_DATA6, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PINMUX_IPSR_GPSR(IP11_26, AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PINMUX_IPSR_MSEL(IP11_27, VI1_DATA7, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PINMUX_IPSR_GPSR(IP11_27, AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PINMUX_IPSR_GPSR(IP11_29_28, ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINMUX_IPSR_GPSR(IP11_29_28, AVB_RX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PINMUX_IPSR_MSEL(IP11_29_28, I2C2_SCL_C, SEL_I2C2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PINMUX_IPSR_GPSR(IP11_31_30, ETH_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) PINMUX_IPSR_GPSR(IP11_31_30, AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PINMUX_IPSR_MSEL(IP11_31_30, I2C2_SDA_C, SEL_I2C2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) PINMUX_IPSR_GPSR(IP12_1_0, ETH_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PINMUX_IPSR_GPSR(IP12_1_0, AVB_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PINMUX_IPSR_MSEL(IP12_1_0, I2C3_SCL, SEL_I2C3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PINMUX_IPSR_MSEL(IP12_1_0, IIC0_SCL, SEL_IIC0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PINMUX_IPSR_GPSR(IP12_3_2, ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PINMUX_IPSR_GPSR(IP12_3_2, AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PINMUX_IPSR_MSEL(IP12_3_2, I2C3_SDA, SEL_I2C3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PINMUX_IPSR_MSEL(IP12_3_2, IIC0_SDA, SEL_IIC0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PINMUX_IPSR_GPSR(IP12_6_4, ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PINMUX_IPSR_GPSR(IP12_6_4, AVB_GTXREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PINMUX_IPSR_MSEL(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PINMUX_IPSR_MSEL(IP12_6_4, I2C2_SCL_D, SEL_I2C2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) PINMUX_IPSR_MSEL(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PINMUX_IPSR_GPSR(IP12_9_7, ETH_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PINMUX_IPSR_GPSR(IP12_9_7, AVB_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PINMUX_IPSR_MSEL(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PINMUX_IPSR_MSEL(IP12_9_7, I2C2_SDA_D, SEL_I2C2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PINMUX_IPSR_MSEL(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PINMUX_IPSR_GPSR(IP12_12_10, ETH_REFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PINMUX_IPSR_GPSR(IP12_12_10, AVB_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PINMUX_IPSR_MSEL(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PINMUX_IPSR_MSEL(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PINMUX_IPSR_MSEL(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PINMUX_IPSR_GPSR(IP12_15_13, ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PINMUX_IPSR_GPSR(IP12_15_13, AVB_TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PINMUX_IPSR_MSEL(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PINMUX_IPSR_MSEL(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PINMUX_IPSR_MSEL(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PINMUX_IPSR_GPSR(IP12_17_16, ETH_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) PINMUX_IPSR_GPSR(IP12_17_16, AVB_TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PINMUX_IPSR_MSEL(IP12_17_16, TCLK1_B, SEL_TMU1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PINMUX_IPSR_MSEL(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) PINMUX_IPSR_GPSR(IP12_19_18, ETH_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PINMUX_IPSR_GPSR(IP12_19_18, AVB_TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PINMUX_IPSR_MSEL(IP12_19_18, IETX_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) PINMUX_IPSR_GPSR(IP12_21_20, ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PINMUX_IPSR_GPSR(IP12_21_20, AVB_TXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PINMUX_IPSR_MSEL(IP12_21_20, IECLK_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PINMUX_IPSR_GPSR(IP12_23_22, ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) PINMUX_IPSR_GPSR(IP12_23_22, AVB_TXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PINMUX_IPSR_MSEL(IP12_23_22, IERX_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PINMUX_IPSR_MSEL(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PINMUX_IPSR_GPSR(IP12_26_24, AVB_TXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) PINMUX_IPSR_MSEL(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PINMUX_IPSR_MSEL(IP12_26_24, ADIDATA_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PINMUX_IPSR_MSEL(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PINMUX_IPSR_MSEL(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PINMUX_IPSR_GPSR(IP12_29_27, AVB_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) PINMUX_IPSR_MSEL(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PINMUX_IPSR_MSEL(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PINMUX_IPSR_MSEL(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) PINMUX_IPSR_MSEL(IP13_2_0, STP_ISD_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) PINMUX_IPSR_GPSR(IP13_2_0, AVB_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) PINMUX_IPSR_MSEL(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) PINMUX_IPSR_MSEL(IP13_2_0, ADICLK_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) PINMUX_IPSR_MSEL(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PINMUX_IPSR_MSEL(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) PINMUX_IPSR_GPSR(IP13_4_3, AVB_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) PINMUX_IPSR_MSEL(IP13_4_3, ADICHS0_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) PINMUX_IPSR_MSEL(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) PINMUX_IPSR_MSEL(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) PINMUX_IPSR_GPSR(IP13_6_5, AVB_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) PINMUX_IPSR_MSEL(IP13_6_5, ADICHS1_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) PINMUX_IPSR_MSEL(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) PINMUX_IPSR_MSEL(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) PINMUX_IPSR_GPSR(IP13_9_7, AVB_GTX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) PINMUX_IPSR_GPSR(IP13_9_7, PWM0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) PINMUX_IPSR_MSEL(IP13_9_7, ADICHS2_B, SEL_RAD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) PINMUX_IPSR_MSEL(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) PINMUX_IPSR_GPSR(IP13_10, SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) PINMUX_IPSR_MSEL(IP13_10, SPCLK_B, SEL_QSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) PINMUX_IPSR_GPSR(IP13_11, SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) PINMUX_IPSR_MSEL(IP13_11, MOSI_IO0_B, SEL_QSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) PINMUX_IPSR_GPSR(IP13_12, SD0_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) PINMUX_IPSR_MSEL(IP13_12, MISO_IO1_B, SEL_QSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) PINMUX_IPSR_GPSR(IP13_13, SD0_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) PINMUX_IPSR_MSEL(IP13_13, IO2_B, SEL_QSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) PINMUX_IPSR_GPSR(IP13_14, SD0_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) PINMUX_IPSR_MSEL(IP13_14, IO3_B, SEL_QSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) PINMUX_IPSR_GPSR(IP13_15, SD0_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) PINMUX_IPSR_MSEL(IP13_15, SSL_B, SEL_QSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) PINMUX_IPSR_GPSR(IP13_18_16, SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) PINMUX_IPSR_MSEL(IP13_18_16, MMC_D6_B, SEL_MMC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) PINMUX_IPSR_MSEL(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) PINMUX_IPSR_MSEL(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) PINMUX_IPSR_MSEL(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) PINMUX_IPSR_MSEL(IP13_18_16, TX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) PINMUX_IPSR_GPSR(IP13_21_19, SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) PINMUX_IPSR_MSEL(IP13_21_19, MMC_D7_B, SEL_MMC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) PINMUX_IPSR_MSEL(IP13_21_19, SIM0_D_B, SEL_SIM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) PINMUX_IPSR_MSEL(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) PINMUX_IPSR_MSEL(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) PINMUX_IPSR_MSEL(IP13_21_19, RX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) PINMUX_IPSR_GPSR(IP13_22, SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) PINMUX_IPSR_MSEL(IP13_22, REMOCON_B, SEL_RCN_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) PINMUX_IPSR_GPSR(IP13_24_23, SD1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) PINMUX_IPSR_MSEL(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) PINMUX_IPSR_GPSR(IP13_25, SD1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) PINMUX_IPSR_MSEL(IP13_25, IETX_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) PINMUX_IPSR_GPSR(IP13_26, SD1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) PINMUX_IPSR_MSEL(IP13_26, IECLK_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) PINMUX_IPSR_GPSR(IP13_27, SD1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) PINMUX_IPSR_MSEL(IP13_27, IERX_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) PINMUX_IPSR_GPSR(IP13_30_28, SD1_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) PINMUX_IPSR_GPSR(IP13_30_28, PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) PINMUX_IPSR_GPSR(IP13_30_28, TPU_TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) PINMUX_IPSR_MSEL(IP13_30_28, I2C1_SCL_C, SEL_I2C1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) PINMUX_IPSR_GPSR(IP14_1_0, SD1_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) PINMUX_IPSR_GPSR(IP14_1_0, PWM1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) PINMUX_IPSR_MSEL(IP14_1_0, I2C1_SDA_C, SEL_I2C1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) PINMUX_IPSR_GPSR(IP14_2, SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) PINMUX_IPSR_GPSR(IP14_2, MMC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) PINMUX_IPSR_GPSR(IP14_3, SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) PINMUX_IPSR_GPSR(IP14_3, MMC_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) PINMUX_IPSR_GPSR(IP14_4, SD2_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) PINMUX_IPSR_GPSR(IP14_4, MMC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) PINMUX_IPSR_GPSR(IP14_5, SD2_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) PINMUX_IPSR_GPSR(IP14_5, MMC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) PINMUX_IPSR_GPSR(IP14_6, SD2_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) PINMUX_IPSR_GPSR(IP14_6, MMC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) PINMUX_IPSR_GPSR(IP14_7, SD2_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) PINMUX_IPSR_GPSR(IP14_7, MMC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) PINMUX_IPSR_GPSR(IP14_10_8, SD2_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) PINMUX_IPSR_GPSR(IP14_10_8, MMC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) PINMUX_IPSR_MSEL(IP14_10_8, IIC1_SCL_C, SEL_IIC1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) PINMUX_IPSR_MSEL(IP14_10_8, TX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) PINMUX_IPSR_MSEL(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) PINMUX_IPSR_GPSR(IP14_13_11, SD2_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) PINMUX_IPSR_GPSR(IP14_13_11, MMC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) PINMUX_IPSR_MSEL(IP14_13_11, IIC1_SDA_C, SEL_IIC1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) PINMUX_IPSR_MSEL(IP14_13_11, RX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) PINMUX_IPSR_MSEL(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) PINMUX_IPSR_MSEL(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) PINMUX_IPSR_MSEL(IP14_16_14, RX2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) PINMUX_IPSR_MSEL(IP14_16_14, ADIDATA, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) PINMUX_IPSR_MSEL(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) PINMUX_IPSR_GPSR(IP14_16_14, VI1_G0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) PINMUX_IPSR_MSEL(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) PINMUX_IPSR_MSEL(IP14_19_17, TX2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) PINMUX_IPSR_MSEL(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) PINMUX_IPSR_MSEL(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) PINMUX_IPSR_GPSR(IP14_19_17, VI1_G1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) PINMUX_IPSR_MSEL(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) PINMUX_IPSR_MSEL(IP14_22_20, ADICLK, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) PINMUX_IPSR_MSEL(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) PINMUX_IPSR_GPSR(IP14_22_20, VI1_G2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) PINMUX_IPSR_MSEL(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) PINMUX_IPSR_MSEL(IP14_25_23, ADICHS0, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) PINMUX_IPSR_MSEL(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) PINMUX_IPSR_GPSR(IP14_25_23, VI1_G3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) PINMUX_IPSR_MSEL(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) PINMUX_IPSR_MSEL(IP14_28_26, MMC_D6, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) PINMUX_IPSR_MSEL(IP14_28_26, ADICHS1, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) PINMUX_IPSR_MSEL(IP14_28_26, TX0_E, SEL_SCIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) PINMUX_IPSR_MSEL(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) PINMUX_IPSR_MSEL(IP14_28_26, IIC0_SCL_C, SEL_IIC0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) PINMUX_IPSR_GPSR(IP14_28_26, VI1_G4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) PINMUX_IPSR_MSEL(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) PINMUX_IPSR_MSEL(IP14_31_29, MMC_D7, SEL_MMC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) PINMUX_IPSR_MSEL(IP14_31_29, ADICHS2, SEL_RAD_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) PINMUX_IPSR_MSEL(IP14_31_29, RX0_E, SEL_SCIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) PINMUX_IPSR_MSEL(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) PINMUX_IPSR_MSEL(IP14_31_29, IIC0_SDA_C, SEL_IIC0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) PINMUX_IPSR_GPSR(IP14_31_29, VI1_G5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) PINMUX_IPSR_MSEL(IP15_1_0, SIM0_RST, SEL_SIM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) PINMUX_IPSR_MSEL(IP15_1_0, IETX, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) PINMUX_IPSR_MSEL(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) PINMUX_IPSR_GPSR(IP15_3_2, SIM0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) PINMUX_IPSR_MSEL(IP15_3_2, IECLK, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) PINMUX_IPSR_MSEL(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) PINMUX_IPSR_MSEL(IP15_5_4, SIM0_D, SEL_SIM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) PINMUX_IPSR_MSEL(IP15_5_4, IERX, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) PINMUX_IPSR_MSEL(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) PINMUX_IPSR_MSEL(IP15_8_6, GPS_CLK, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) PINMUX_IPSR_MSEL(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) PINMUX_IPSR_MSEL(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) PINMUX_IPSR_GPSR(IP15_8_6, PWM5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) PINMUX_IPSR_MSEL(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) PINMUX_IPSR_MSEL(IP15_11_9, GPS_SIGN, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) PINMUX_IPSR_MSEL(IP15_11_9, TX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) PINMUX_IPSR_MSEL(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) PINMUX_IPSR_GPSR(IP15_11_9, PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) PINMUX_IPSR_GPSR(IP15_11_9, VI1_G6_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) PINMUX_IPSR_MSEL(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) PINMUX_IPSR_MSEL(IP15_14_12, GPS_MAG, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) PINMUX_IPSR_MSEL(IP15_14_12, RX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) PINMUX_IPSR_MSEL(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) PINMUX_IPSR_GPSR(IP15_14_12, PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) PINMUX_IPSR_GPSR(IP15_14_12, VI1_G7_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) PINMUX_IPSR_MSEL(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) PINMUX_IPSR_MSEL(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) PINMUX_IPSR_MSEL(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) PINMUX_IPSR_MSEL(IP15_17_15, GLO_I0_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) PINMUX_IPSR_MSEL(IP15_17_15, TCLK1, SEL_TMU1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) PINMUX_IPSR_MSEL(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) PINMUX_IPSR_MSEL(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) PINMUX_IPSR_MSEL(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) PINMUX_IPSR_MSEL(IP15_20_18, GLO_I1_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) PINMUX_IPSR_MSEL(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) PINMUX_IPSR_MSEL(IP15_23_21, HSCK0, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) PINMUX_IPSR_MSEL(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) PINMUX_IPSR_MSEL(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) PINMUX_IPSR_MSEL(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) PINMUX_IPSR_GPSR(IP15_23_21, TCLK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) PINMUX_IPSR_MSEL(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) PINMUX_IPSR_MSEL(IP15_26_24, HRX0, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) PINMUX_IPSR_MSEL(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) PINMUX_IPSR_MSEL(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) PINMUX_IPSR_MSEL(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) PINMUX_IPSR_MSEL(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) PINMUX_IPSR_MSEL(IP15_29_27, HTX0, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) PINMUX_IPSR_MSEL(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) PINMUX_IPSR_MSEL(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) PINMUX_IPSR_MSEL(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) PINMUX_IPSR_MSEL(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) PINMUX_IPSR_MSEL(IP16_2_0, HRX1, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) PINMUX_IPSR_MSEL(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) PINMUX_IPSR_GPSR(IP16_2_0, VI1_R0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) PINMUX_IPSR_MSEL(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) PINMUX_IPSR_MSEL(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) PINMUX_IPSR_MSEL(IP16_5_3, HTX1, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) PINMUX_IPSR_MSEL(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) PINMUX_IPSR_GPSR(IP16_5_3, VI1_R1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) PINMUX_IPSR_MSEL(IP16_5_3, GLO_SS_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) PINMUX_IPSR_MSEL(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) PINMUX_IPSR_MSEL(IP16_7_6, HSCK1, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) PINMUX_IPSR_MSEL(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) PINMUX_IPSR_GPSR(IP16_7_6, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) PINMUX_IPSR_MSEL(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) PINMUX_IPSR_MSEL(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) PINMUX_IPSR_GPSR(IP16_9_8, SCIFB1_CTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) PINMUX_IPSR_GPSR(IP16_9_8, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) PINMUX_IPSR_MSEL(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) PINMUX_IPSR_MSEL(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) PINMUX_IPSR_GPSR(IP16_11_10, SCIFB1_RTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) PINMUX_IPSR_GPSR(IP16_11_10, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) PINMUX_IPSR_MSEL(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /* - ADI -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static const unsigned int adi_common_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) /* ADIDATA, ADICS/SAMP, ADICLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static const unsigned int adi_common_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /* ADIDATA, ADICS/SAMP, ADICLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ADIDATA_MARK, ADICS_SAMP_MARK, ADICLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static const unsigned int adi_chsel0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* ADICHS 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const unsigned int adi_chsel0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) /* ADICHS 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) ADICHS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static const unsigned int adi_chsel1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* ADICHS 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static const unsigned int adi_chsel1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /* ADICHS 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ADICHS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static const unsigned int adi_chsel2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* ADICHS 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static const unsigned int adi_chsel2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) /* ADICHS 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) ADICHS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static const unsigned int adi_common_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) /* ADIDATA B, ADICS/SAMP B, ADICLK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static const unsigned int adi_common_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* ADIDATA B, ADICS/SAMP B, ADICLK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) ADIDATA_B_MARK, ADICS_SAMP_B_MARK, ADICLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const unsigned int adi_chsel0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* ADICHS B 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) RCAR_GP_PIN(5, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) static const unsigned int adi_chsel0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* ADICHS B 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) ADICHS0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static const unsigned int adi_chsel1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* ADICHS B 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static const unsigned int adi_chsel1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* ADICHS B 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ADICHS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static const unsigned int adi_chsel2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* ADICHS B 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) RCAR_GP_PIN(5, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static const unsigned int adi_chsel2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* ADICHS B 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) ADICHS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) /* - Audio Clock ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const unsigned int audio_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) RCAR_GP_PIN(2, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static const unsigned int audio_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static const unsigned int audio_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) RCAR_GP_PIN(2, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static const unsigned int audio_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) AUDIO_CLKB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static const unsigned int audio_clk_b_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) RCAR_GP_PIN(7, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const unsigned int audio_clk_b_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) AUDIO_CLKB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) static const unsigned int audio_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const unsigned int audio_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) AUDIO_CLKC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned int audio_clkout_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static const unsigned int audio_clkout_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) AUDIO_CLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* - AVB -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static const unsigned int avb_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static const unsigned int avb_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) AVB_MDC_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static const unsigned int avb_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) static const unsigned int avb_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) AVB_TXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) AVB_RXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) AVB_TX_CLK_MARK, AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const unsigned int avb_gmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static const unsigned int avb_gmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) AVB_TXD6_MARK, AVB_TXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) AVB_RXD6_MARK, AVB_RXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) /* - CAN -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static const unsigned int can0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const unsigned int can0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) CAN0_TX_MARK, CAN0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) static const unsigned int can0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) RCAR_GP_PIN(7, 4), RCAR_GP_PIN(7, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static const unsigned int can0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) CAN0_TX_B_MARK, CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const unsigned int can0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static const unsigned int can0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) CAN0_TX_C_MARK, CAN0_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static const unsigned int can0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static const unsigned int can0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) CAN0_TX_D_MARK, CAN0_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) static const unsigned int can0_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const unsigned int can0_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) CAN0_TX_E_MARK, CAN0_RX_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static const unsigned int can0_data_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static const unsigned int can0_data_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) CAN0_TX_F_MARK, CAN0_RX_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static const unsigned int can1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) static const unsigned int can1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) CAN1_TX_MARK, CAN1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static const unsigned int can1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static const unsigned int can1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) CAN1_TX_B_MARK, CAN1_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const unsigned int can1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) static const unsigned int can1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) CAN1_TX_C_MARK, CAN1_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static const unsigned int can1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* TX, RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static const unsigned int can1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) CAN1_TX_D_MARK, CAN1_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static const unsigned int can_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) RCAR_GP_PIN(7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static const unsigned int can_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static const unsigned int can_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static const unsigned int can_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) CAN_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) static const unsigned int can_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static const unsigned int can_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) CAN_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static const unsigned int can_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) RCAR_GP_PIN(7, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static const unsigned int can_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) CAN_CLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) DU1_DR3_MARK, DU1_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) DU1_DG3_MARK, DU1_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) DU1_DB3_MARK, DU1_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static const unsigned int du_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static const unsigned int du_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static const unsigned int du_clk_out_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) RCAR_GP_PIN(3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static const unsigned int du_clk_out_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) DU1_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static const unsigned int du_clk_out_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) static const unsigned int du_clk_out_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) DU1_DOTCLKOUT1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static const unsigned int du_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static const unsigned int du_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) static const unsigned int du_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* EXDISP/EXODDF/EXCDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) static const unsigned int du_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) DU1_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static const unsigned int du_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static const unsigned int du_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) DU1_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static const unsigned int du0_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) RCAR_GP_PIN(6, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static const unsigned int du0_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) DU0_DOTCLKIN_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static const unsigned int du1_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) RCAR_GP_PIN(3, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static const unsigned int du1_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) DU1_DOTCLKIN_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static const unsigned int du1_clk_in_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) RCAR_GP_PIN(7, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static const unsigned int du1_clk_in_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) DU1_DOTCLKIN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static const unsigned int du1_clk_in_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) RCAR_GP_PIN(7, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static const unsigned int du1_clk_in_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) DU1_DOTCLKIN_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) /* - ETH -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static const unsigned int eth_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) /* LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) static const unsigned int eth_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) ETH_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static const unsigned int eth_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /* MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) RCAR_GP_PIN(5, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) static const unsigned int eth_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ETH_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) static const unsigned int eth_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* MDC, MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) static const unsigned int eth_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ETH_MDC_MARK, ETH_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) static const unsigned int eth_rmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static const unsigned int eth_rmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static const unsigned int hscif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static const unsigned int hscif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) HRX0_MARK, HTX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) static const unsigned int hscif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) RCAR_GP_PIN(7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static const unsigned int hscif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) HSCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) static const unsigned int hscif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) static const unsigned int hscif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) HRTS0_N_MARK, HCTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static const unsigned int hscif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) static const unsigned int hscif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) HRX0_B_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static const unsigned int hscif0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static const unsigned int hscif0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) HRTS0_N_B_MARK, HCTS0_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) static const unsigned int hscif0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static const unsigned int hscif0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) HRX0_C_MARK, HTX0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static const unsigned int hscif0_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static const unsigned int hscif0_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) HSCK0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static const unsigned int hscif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static const unsigned int hscif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) HRX1_MARK, HTX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) static const unsigned int hscif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) RCAR_GP_PIN(7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) static const unsigned int hscif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) HSCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) static const unsigned int hscif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) static const unsigned int hscif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) HRTS1_N_MARK, HCTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static const unsigned int hscif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) static const unsigned int hscif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) HRX1_B_MARK, HTX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static const unsigned int hscif1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static const unsigned int hscif1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) HRX1_C_MARK, HTX1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static const unsigned int hscif1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) RCAR_GP_PIN(7, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static const unsigned int hscif1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) HSCK1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) static const unsigned int hscif1_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) RCAR_GP_PIN(7, 18), RCAR_GP_PIN(7, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static const unsigned int hscif1_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) HRTS1_N_C_MARK, HCTS1_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) static const unsigned int hscif1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static const unsigned int hscif1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) HRX1_D_MARK, HTX1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static const unsigned int hscif1_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) RCAR_GP_PIN(7, 14), RCAR_GP_PIN(7, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static const unsigned int hscif1_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) HRX1_C_MARK, HTX1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) static const unsigned int hscif1_clk_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static const unsigned int hscif1_clk_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) HSCK1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) static const unsigned int hscif1_ctrl_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const unsigned int hscif1_ctrl_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) HRTS1_N_E_MARK, HCTS1_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) /* - HSCIF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static const unsigned int hscif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) static const unsigned int hscif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) HRX2_MARK, HTX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static const unsigned int hscif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) static const unsigned int hscif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) HSCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) static const unsigned int hscif2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static const unsigned int hscif2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) HRTS2_N_MARK, HCTS2_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static const unsigned int hscif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) static const unsigned int hscif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) HRX2_B_MARK, HTX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static const unsigned int hscif2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static const unsigned int hscif2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) HRTS2_N_B_MARK, HCTS2_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static const unsigned int hscif2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static const unsigned int hscif2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) HRX2_C_MARK, HTX2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) static const unsigned int hscif2_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static const unsigned int hscif2_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) HSCK2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static const unsigned int hscif2_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) static const unsigned int hscif2_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) HRX2_B_MARK, HTX2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* - I2C0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) I2C0_SCL_MARK, I2C0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) static const unsigned int i2c0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static const unsigned int i2c0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) static const unsigned int i2c0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) static const unsigned int i2c0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /* - I2C1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static const unsigned int i2c1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static const unsigned int i2c1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) I2C1_SCL_MARK, I2C1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static const unsigned int i2c1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static const unsigned int i2c1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static const unsigned int i2c1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static const unsigned int i2c1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static const unsigned int i2c1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static const unsigned int i2c1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) static const unsigned int i2c1_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static const unsigned int i2c1_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static const unsigned int i2c2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static const unsigned int i2c2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) I2C2_SCL_MARK, I2C2_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) static const unsigned int i2c2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const unsigned int i2c2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) static const unsigned int i2c2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static const unsigned int i2c2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) static const unsigned int i2c3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static const unsigned int i2c3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) I2C3_SCL_MARK, I2C3_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const unsigned int i2c3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) static const unsigned int i2c3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static const unsigned int i2c3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static const unsigned int i2c3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const unsigned int i2c3_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) static const unsigned int i2c3_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) /* - I2C4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) static const unsigned int i2c4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) static const unsigned int i2c4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) I2C4_SCL_MARK, I2C4_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static const unsigned int i2c4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) static const unsigned int i2c4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static const unsigned int i2c4_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static const unsigned int i2c4_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) /* - I2C7 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const unsigned int i2c7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static const unsigned int i2c7_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) IIC0_SCL_MARK, IIC0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static const unsigned int i2c7_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static const unsigned int i2c7_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) IIC0_SCL_B_MARK, IIC0_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) static const unsigned int i2c7_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static const unsigned int i2c7_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) IIC0_SCL_C_MARK, IIC0_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) /* - I2C8 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) static const unsigned int i2c8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static const unsigned int i2c8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) IIC1_SCL_MARK, IIC1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static const unsigned int i2c8_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) static const unsigned int i2c8_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) static const unsigned int i2c8_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) static const unsigned int i2c8_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* - INTC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static const unsigned int intc_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) RCAR_GP_PIN(7, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static const unsigned int intc_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static const unsigned int intc_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) RCAR_GP_PIN(7, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static const unsigned int intc_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) static const unsigned int intc_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) RCAR_GP_PIN(7, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) static const unsigned int intc_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) static const unsigned int intc_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) RCAR_GP_PIN(7, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) static const unsigned int intc_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /* - MLB+ ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) static const unsigned int mlb_3pin_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) RCAR_GP_PIN(7, 7), RCAR_GP_PIN(7, 8), RCAR_GP_PIN(7, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) static const unsigned int mlb_3pin_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) /* - MMCIF ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) static const unsigned int mmc_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) static const unsigned int mmc_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) MMC_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static const unsigned int mmc_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static const unsigned int mmc_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) static const unsigned int mmc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) static const unsigned int mmc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static const unsigned int mmc_data8_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) static const unsigned int mmc_data8_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) MMC_D4_MARK, MMC_D5_MARK, MMC_D6_B_MARK, MMC_D7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static const unsigned int mmc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) static const unsigned int mmc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) MMC_CLK_MARK, MMC_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) RCAR_GP_PIN(6, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static const unsigned int msiof0_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const unsigned int msiof0_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static const unsigned int msiof0_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) RCAR_GP_PIN(6, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static const unsigned int msiof0_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) static const unsigned int msiof0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static const unsigned int msiof0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) MSIOF0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static const unsigned int msiof0_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static const unsigned int msiof0_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) MSIOF0_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static const unsigned int msiof0_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static const unsigned int msiof0_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) MSIOF0_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static const unsigned int msiof0_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static const unsigned int msiof0_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) MSIOF0_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const unsigned int msiof0_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static const unsigned int msiof0_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) MSIOF0_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static const unsigned int msiof0_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static const unsigned int msiof0_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) MSIOF0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) static const unsigned int msiof0_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) RCAR_GP_PIN(5, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) static const unsigned int msiof0_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) MSIOF0_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static const unsigned int msiof0_sync_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) static const unsigned int msiof0_sync_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) MSIOF0_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) static const unsigned int msiof0_ss1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) static const unsigned int msiof0_ss1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) MSIOF0_SS1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static const unsigned int msiof0_ss2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) RCAR_GP_PIN(5, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static const unsigned int msiof0_ss2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) MSIOF0_SS2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static const unsigned int msiof0_rx_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static const unsigned int msiof0_rx_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) MSIOF0_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static const unsigned int msiof0_tx_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) RCAR_GP_PIN(5, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static const unsigned int msiof0_tx_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) MSIOF0_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) RCAR_GP_PIN(0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) RCAR_GP_PIN(0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) RCAR_GP_PIN(0, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) static const unsigned int msiof1_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) RCAR_GP_PIN(0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) static const unsigned int msiof1_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) static const unsigned int msiof1_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) RCAR_GP_PIN(0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) static const unsigned int msiof1_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) static const unsigned int msiof1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) RCAR_GP_PIN(2, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) static const unsigned int msiof1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) MSIOF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) static const unsigned int msiof1_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) static const unsigned int msiof1_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) MSIOF1_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) static const unsigned int msiof1_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) static const unsigned int msiof1_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) MSIOF1_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) static const unsigned int msiof1_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) RCAR_GP_PIN(7, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) static const unsigned int msiof1_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) MSIOF1_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) static const unsigned int msiof1_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) RCAR_GP_PIN(7, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) static const unsigned int msiof1_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) MSIOF1_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) static const unsigned int msiof1_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) RCAR_GP_PIN(7, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) static const unsigned int msiof1_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) MSIOF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) static const unsigned int msiof1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) static const unsigned int msiof1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) MSIOF1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) static const unsigned int msiof1_sync_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) static const unsigned int msiof1_sync_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) MSIOF1_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) static const unsigned int msiof1_rx_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) static const unsigned int msiof1_rx_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) MSIOF1_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) static const unsigned int msiof1_tx_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) static const unsigned int msiof1_tx_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) MSIOF1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static const unsigned int msiof1_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) RCAR_GP_PIN(0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) static const unsigned int msiof1_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) MSIOF1_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) static const unsigned int msiof1_sync_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) RCAR_GP_PIN(0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) static const unsigned int msiof1_sync_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) MSIOF1_SYNC_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) static const unsigned int msiof1_ss1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) RCAR_GP_PIN(0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) static const unsigned int msiof1_ss1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) MSIOF1_SS1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) static const unsigned int msiof1_rx_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) RCAR_GP_PIN(0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) static const unsigned int msiof1_rx_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) MSIOF1_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) static const unsigned int msiof1_tx_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) RCAR_GP_PIN(0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) static const unsigned int msiof1_tx_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) MSIOF1_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) static const unsigned int msiof1_clk_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) static const unsigned int msiof1_clk_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) MSIOF1_SCK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) static const unsigned int msiof1_sync_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) static const unsigned int msiof1_sync_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) MSIOF1_SYNC_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) static const unsigned int msiof1_rx_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) static const unsigned int msiof1_rx_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) MSIOF1_RXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) static const unsigned int msiof1_tx_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static const unsigned int msiof1_tx_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) MSIOF1_TXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) static const unsigned int msiof2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) static const unsigned int msiof2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) static const unsigned int msiof2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) static const unsigned int msiof2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) MSIOF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) static const unsigned int msiof2_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) static const unsigned int msiof2_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) static const unsigned int msiof2_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) static const unsigned int msiof2_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) static const unsigned int msiof2_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) static const unsigned int msiof2_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) static const unsigned int msiof2_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) static const unsigned int msiof2_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) static const unsigned int msiof2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) static const unsigned int msiof2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) MSIOF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) static const unsigned int msiof2_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) static const unsigned int msiof2_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) MSIOF2_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) static const unsigned int msiof2_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) static const unsigned int msiof2_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) MSIOF2_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) static const unsigned int msiof2_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) static const unsigned int msiof2_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) MSIOF2_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) static const unsigned int msiof2_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static const unsigned int msiof2_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) MSIOF2_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) static const unsigned int msiof2_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) static const unsigned int msiof2_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) MSIOF2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) static const unsigned int msiof2_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) static const unsigned int msiof2_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) MSIOF2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) static const unsigned int msiof2_sync_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) static const unsigned int msiof2_sync_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) MSIOF2_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static const unsigned int msiof2_rx_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) static const unsigned int msiof2_rx_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) MSIOF2_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) static const unsigned int msiof2_tx_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) static const unsigned int msiof2_tx_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) MSIOF2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) static const unsigned int msiof2_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) static const unsigned int msiof2_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) MSIOF2_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) static const unsigned int msiof2_sync_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static const unsigned int msiof2_sync_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) MSIOF2_SYNC_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) static const unsigned int msiof2_ss1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) static const unsigned int msiof2_ss1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) MSIOF2_SS1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) static const unsigned int msiof2_ss2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) static const unsigned int msiof2_ss2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) MSIOF2_SS2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) static const unsigned int msiof2_rx_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) static const unsigned int msiof2_rx_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) MSIOF2_RXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static const unsigned int msiof2_tx_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static const unsigned int msiof2_tx_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) MSIOF2_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) static const unsigned int msiof2_clk_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) RCAR_GP_PIN(7, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) static const unsigned int msiof2_clk_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) MSIOF2_SCK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) static const unsigned int msiof2_sync_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) RCAR_GP_PIN(7, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) static const unsigned int msiof2_sync_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) MSIOF2_SYNC_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) static const unsigned int msiof2_rx_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) RCAR_GP_PIN(7, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) static const unsigned int msiof2_rx_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) MSIOF2_RXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) static const unsigned int msiof2_tx_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) RCAR_GP_PIN(7, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) static const unsigned int msiof2_tx_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) MSIOF2_TXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) /* - PWM -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) static const unsigned int pwm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) static const unsigned int pwm0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) PWM0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) RCAR_GP_PIN(5, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) static const unsigned int pwm1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) static const unsigned int pwm1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) PWM1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) static const unsigned int pwm2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) static const unsigned int pwm2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) PWM2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) static const unsigned int pwm2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static const unsigned int pwm2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) PWM2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static const unsigned int pwm3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) static const unsigned int pwm3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) PWM3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) static const unsigned int pwm4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) static const unsigned int pwm4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) PWM4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) static const unsigned int pwm4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) static const unsigned int pwm4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) PWM4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) static const unsigned int pwm5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) RCAR_GP_PIN(7, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) static const unsigned int pwm5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) PWM5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) static const unsigned int pwm5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) RCAR_GP_PIN(7, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) static const unsigned int pwm5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) PWM5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) static const unsigned int pwm6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) RCAR_GP_PIN(7, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) static const unsigned int pwm6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) PWM6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) /* - QSPI ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) static const unsigned int qspi_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) static const unsigned int qspi_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) SPCLK_MARK, SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) static const unsigned int qspi_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) static const unsigned int qspi_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) MOSI_IO0_MARK, MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) static const unsigned int qspi_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) static const unsigned int qspi_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) static const unsigned int qspi_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static const unsigned int qspi_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) SPCLK_B_MARK, SSL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) static const unsigned int qspi_data2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) static const unsigned int qspi_data2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) MOSI_IO0_B_MARK, MISO_IO1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) static const unsigned int qspi_data4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) RCAR_GP_PIN(6, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) static const unsigned int qspi_data4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) MOSI_IO0_B_MARK, MISO_IO1_B_MARK, IO2_B_MARK, IO3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) static const unsigned int scif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) static const unsigned int scif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) RX0_MARK, TX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) static const unsigned int scif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) static const unsigned int scif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) RX0_B_MARK, TX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) static const unsigned int scif0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) static const unsigned int scif0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) RX0_C_MARK, TX0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) static const unsigned int scif0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) static const unsigned int scif0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) RX0_D_MARK, TX0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) static const unsigned int scif0_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) static const unsigned int scif0_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) RX0_E_MARK, TX0_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) static const unsigned int scif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) static const unsigned int scif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) RX1_MARK, TX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) static const unsigned int scif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) static const unsigned int scif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) SCIF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) static const unsigned int scif1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) static const unsigned int scif1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) RX1_C_MARK, TX1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) static const unsigned int scif1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) static const unsigned int scif1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) RX1_D_MARK, TX1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) static const unsigned int scif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) static const unsigned int scif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) RX2_MARK, TX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) static const unsigned int scif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) static const unsigned int scif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) RX2_B_MARK, TX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) static const unsigned int scif2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) static const unsigned int scif2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) SCIF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) static const unsigned int scif2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) static const unsigned int scif2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) RX2_C_MARK, TX2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) static const unsigned int scif2_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) static const unsigned int scif2_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) RX2_E_MARK, TX2_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) static const unsigned int scif3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) static const unsigned int scif3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) RX3_MARK, TX3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) static const unsigned int scif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) RCAR_GP_PIN(3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) static const unsigned int scif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) SCIF3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) static const unsigned int scif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) static const unsigned int scif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) RX3_B_MARK, TX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) static const unsigned int scif3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) static const unsigned int scif3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) SCIF3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) static const unsigned int scif3_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) static const unsigned int scif3_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) RX3_C_MARK, TX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) static const unsigned int scif3_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) static const unsigned int scif3_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) RX3_D_MARK, TX3_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) static const unsigned int scif4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static const unsigned int scif4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) RX4_MARK, TX4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) static const unsigned int scif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) static const unsigned int scif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) RX4_B_MARK, TX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) static const unsigned int scif4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) static const unsigned int scif4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) RX4_C_MARK, TX4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) static const unsigned int scif5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) static const unsigned int scif5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) RX5_MARK, TX5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) static const unsigned int scif5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) static const unsigned int scif5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) RX5_B_MARK, TX5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) /* - SCIFA0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) static const unsigned int scifa0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) static const unsigned int scifa0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) static const unsigned int scifa0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) static const unsigned int scifa0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) /* - SCIFA1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) static const unsigned int scifa1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) static const unsigned int scifa1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) static const unsigned int scifa1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) static const unsigned int scifa1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) SCIFA1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) static const unsigned int scifa1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static const unsigned int scifa1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) static const unsigned int scifa1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) static const unsigned int scifa1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) SCIFA1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) static const unsigned int scifa1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) static const unsigned int scifa1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) /* - SCIFA2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) static const unsigned int scifa2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) static const unsigned int scifa2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) static const unsigned int scifa2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) static const unsigned int scifa2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) SCIFA2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) static const unsigned int scifa2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) static const unsigned int scifa2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) /* - SCIFA3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) static const unsigned int scifa3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) static const unsigned int scifa3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) static const unsigned int scifa3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) RCAR_GP_PIN(3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) static const unsigned int scifa3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) SCIFA3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) static const unsigned int scifa3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) static const unsigned int scifa3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) static const unsigned int scifa3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) static const unsigned int scifa3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) SCIFA3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) static const unsigned int scifa3_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) static const unsigned int scifa3_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) static const unsigned int scifa3_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) RCAR_GP_PIN(7, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) static const unsigned int scifa3_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) SCIFA3_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) /* - SCIFA4 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) static const unsigned int scifa4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) static const unsigned int scifa4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) static const unsigned int scifa4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) static const unsigned int scifa4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) static const unsigned int scifa4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) static const unsigned int scifa4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) /* - SCIFA5 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) static const unsigned int scifa5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) static const unsigned int scifa5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) static const unsigned int scifa5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) static const unsigned int scifa5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) static const unsigned int scifa5_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) static const unsigned int scifa5_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) /* - SCIFB0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) static const unsigned int scifb0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) static const unsigned int scifb0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) static const unsigned int scifb0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) RCAR_GP_PIN(7, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) static const unsigned int scifb0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) SCIFB0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) static const unsigned int scifb0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) static const unsigned int scifb0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) static const unsigned int scifb0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) static const unsigned int scifb0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) static const unsigned int scifb0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) static const unsigned int scifb0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) SCIFB0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) static const unsigned int scifb0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) static const unsigned int scifb0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) static const unsigned int scifb0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) static const unsigned int scifb0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) static const unsigned int scifb0_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) static const unsigned int scifb0_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) SCIFB0_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) static const unsigned int scifb0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) static const unsigned int scifb0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) static const unsigned int scifb0_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) static const unsigned int scifb0_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) SCIFB0_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /* - SCIFB1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) static const unsigned int scifb1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static const unsigned int scifb1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) static const unsigned int scifb1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) RCAR_GP_PIN(7, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) static const unsigned int scifb1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) SCIFB1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) static const unsigned int scifb1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) static const unsigned int scifb1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) static const unsigned int scifb1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) static const unsigned int scifb1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) static const unsigned int scifb1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) static const unsigned int scifb1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) SCIFB1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) static const unsigned int scifb1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) static const unsigned int scifb1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) static const unsigned int scifb1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) RCAR_GP_PIN(7, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) static const unsigned int scifb1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) SCIFB1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) static const unsigned int scifb1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) static const unsigned int scifb1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) /* - SCIFB2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) static const unsigned int scifb2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) static const unsigned int scifb2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) static const unsigned int scifb2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) static const unsigned int scifb2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) SCIFB2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) static const unsigned int scifb2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) static const unsigned int scifb2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) static const unsigned int scifb2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) static const unsigned int scifb2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) static const unsigned int scifb2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) static const unsigned int scifb2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) SCIFB2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) static const unsigned int scifb2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) static const unsigned int scifb2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) static const unsigned int scifb2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) static const unsigned int scifb2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) static const unsigned int scifb2_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) static const unsigned int scifb2_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) SCIFB2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) static const unsigned int scifb2_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) static const unsigned int scifb2_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) static const unsigned int scif_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) RCAR_GP_PIN(2, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) static const unsigned int scif_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) SCIF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) RCAR_GP_PIN(7, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) RCAR_GP_PIN(6, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) SD0_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) SD0_CLK_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) RCAR_GP_PIN(6, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) SD0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) RCAR_GP_PIN(6, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) RCAR_GP_PIN(6, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) SD1_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) SD1_CLK_MARK, SD1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) RCAR_GP_PIN(6, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) RCAR_GP_PIN(6, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) SD2_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) SD2_CLK_MARK, SD2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) static const unsigned int sdhi2_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) RCAR_GP_PIN(6, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) static const unsigned int sdhi2_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) SD2_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) static const unsigned int sdhi2_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) RCAR_GP_PIN(6, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) static const unsigned int sdhi2_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) SD2_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) /* - SSI -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) static const unsigned int ssi0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) static const unsigned int ssi0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) SSI_SDATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) static const unsigned int ssi0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) static const unsigned int ssi0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) SSI_SDATA0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) static const unsigned int ssi0129_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) static const unsigned int ssi0129_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) SSI_SCK0129_MARK, SSI_WS0129_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) static const unsigned int ssi0129_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) static const unsigned int ssi0129_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) SSI_SCK0129_B_MARK, SSI_WS0129_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) static const unsigned int ssi1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) static const unsigned int ssi1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) SSI_SDATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) static const unsigned int ssi1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) static const unsigned int ssi1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) static const unsigned int ssi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) static const unsigned int ssi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) SSI_SCK1_MARK, SSI_WS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) static const unsigned int ssi1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) static const unsigned int ssi1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) static const unsigned int ssi2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) static const unsigned int ssi2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) SSI_SDATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) static const unsigned int ssi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) static const unsigned int ssi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) SSI_SCK2_MARK, SSI_WS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) static const unsigned int ssi3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) static const unsigned int ssi3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) SSI_SDATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) static const unsigned int ssi34_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) static const unsigned int ssi34_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) SSI_SCK34_MARK, SSI_WS34_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) static const unsigned int ssi4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) static const unsigned int ssi4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) SSI_SDATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) static const unsigned int ssi4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) static const unsigned int ssi4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) SSI_SCK4_MARK, SSI_WS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) static const unsigned int ssi5_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) static const unsigned int ssi5_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) SSI_SDATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) static const unsigned int ssi5_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) static const unsigned int ssi5_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) SSI_SCK5_MARK, SSI_WS5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) static const unsigned int ssi6_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) static const unsigned int ssi6_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) SSI_SDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) static const unsigned int ssi6_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) static const unsigned int ssi6_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) SSI_SCK6_MARK, SSI_WS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) static const unsigned int ssi7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) static const unsigned int ssi7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) static const unsigned int ssi7_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) static const unsigned int ssi7_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) static const unsigned int ssi78_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) static const unsigned int ssi78_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) SSI_SCK78_MARK, SSI_WS78_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) static const unsigned int ssi78_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) static const unsigned int ssi78_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) static const unsigned int ssi8_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) static const unsigned int ssi8_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) static const unsigned int ssi8_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) static const unsigned int ssi8_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) SSI_SDATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) static const unsigned int ssi9_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) static const unsigned int ssi9_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) SSI_SDATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) static const unsigned int ssi9_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) /* SDATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) static const unsigned int ssi9_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) SSI_SDATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) static const unsigned int ssi9_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) static const unsigned int ssi9_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) SSI_SCK9_MARK, SSI_WS9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) static const unsigned int ssi9_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) static const unsigned int ssi9_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) /* - TPU -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) static const unsigned int tpu_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) RCAR_GP_PIN(6, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) static const unsigned int tpu_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) TPU_TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) static const unsigned int tpu_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) static const unsigned int tpu_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) TPU_TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) static const unsigned int tpu_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) static const unsigned int tpu_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) TPU_TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) static const unsigned int tpu_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) static const unsigned int tpu_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) TPU_TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) static const unsigned int usb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) RCAR_GP_PIN(7, 23), /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) RCAR_GP_PIN(7, 24), /* OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) static const unsigned int usb0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) USB0_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) USB0_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) /* - USB1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) static const unsigned int usb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) RCAR_GP_PIN(7, 25), /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) RCAR_GP_PIN(6, 30), /* OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) static const unsigned int usb1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) USB1_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) static const union vin_data vin0_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) static const union vin_data vin0_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) VI0_G0_MARK, VI0_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) VI0_R0_MARK, VI0_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) static const unsigned int vin0_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) static const unsigned int vin0_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) static const unsigned int vin0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) RCAR_GP_PIN(4, 3), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) RCAR_GP_PIN(4, 4), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) static const unsigned int vin0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) VI0_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) static const unsigned int vin0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) static const unsigned int vin0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) static const unsigned int vin0_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) static const unsigned int vin0_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) static const unsigned int vin0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) static const unsigned int vin0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) /* - VIN1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) static const unsigned int vin1_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) static const unsigned int vin1_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) VI1_DATA0_MARK, VI1_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) VI1_DATA2_MARK, VI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) VI1_DATA4_MARK, VI1_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) VI1_DATA6_MARK, VI1_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) static const unsigned int vin1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) RCAR_GP_PIN(5, 0), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) RCAR_GP_PIN(5, 1), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) static const unsigned int vin1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) VI1_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) static const unsigned int vin1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) static const unsigned int vin1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) static const unsigned int vin1_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) static const unsigned int vin1_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) static const unsigned int vin1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) static const unsigned int vin1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) static const union vin_data vin1_data_b_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) static const union vin_data vin1_data_b_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346) VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) VI1_G0_B_MARK, VI1_G1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) VI1_G2_B_MARK, VI1_G3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) VI1_G4_B_MARK, VI1_G5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) VI1_G6_B_MARK, VI1_G7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) VI1_R0_B_MARK, VI1_R1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) VI1_R2_B_MARK, VI1_R3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) VI1_R4_B_MARK, VI1_R5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) VI1_R6_B_MARK, VI1_R7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) static const unsigned int vin1_data18_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) static const unsigned int vin1_data18_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) VI1_G2_B_MARK, VI1_G3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) VI1_G4_B_MARK, VI1_G5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) VI1_G6_B_MARK, VI1_G7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) VI1_R2_B_MARK, VI1_R3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) VI1_R4_B_MARK, VI1_R5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) VI1_R6_B_MARK, VI1_R7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) static const unsigned int vin1_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) RCAR_GP_PIN(3, 17), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) RCAR_GP_PIN(3, 18), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) static const unsigned int vin1_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) VI1_HSYNC_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) VI1_VSYNC_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) static const unsigned int vin1_field_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) static const unsigned int vin1_field_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) VI1_FIELD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) static const unsigned int vin1_clkenb_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) static const unsigned int vin1_clkenb_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) VI1_CLKENB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) static const unsigned int vin1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) static const unsigned int vin1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) VI1_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) /* - VIN2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) static const unsigned int vin2_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) static const unsigned int vin2_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) VI2_DATA0_MARK, VI2_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) VI2_DATA2_MARK, VI2_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) VI2_DATA4_MARK, VI2_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) VI2_DATA6_MARK, VI2_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) static const unsigned int vin2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) RCAR_GP_PIN(4, 15), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) RCAR_GP_PIN(4, 16), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) static const unsigned int vin2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) VI2_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) VI2_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) static const unsigned int vin2_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) static const unsigned int vin2_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) VI2_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) static const unsigned int vin2_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) static const unsigned int vin2_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) VI2_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) static const unsigned int vin2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) static const unsigned int vin2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) VI2_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) struct sh_pfc_pin_group common[346];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) struct sh_pfc_pin_group automotive[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) } pinmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) SH_PFC_PIN_GROUP(audio_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) SH_PFC_PIN_GROUP(audio_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) SH_PFC_PIN_GROUP(audio_clk_b_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) SH_PFC_PIN_GROUP(audio_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) SH_PFC_PIN_GROUP(audio_clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) SH_PFC_PIN_GROUP(avb_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) SH_PFC_PIN_GROUP(avb_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) SH_PFC_PIN_GROUP(avb_gmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) SH_PFC_PIN_GROUP(can0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470) SH_PFC_PIN_GROUP(can0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) SH_PFC_PIN_GROUP(can0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) SH_PFC_PIN_GROUP(can0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) SH_PFC_PIN_GROUP(can0_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) SH_PFC_PIN_GROUP(can0_data_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) SH_PFC_PIN_GROUP(can1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) SH_PFC_PIN_GROUP(can1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) SH_PFC_PIN_GROUP(can1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) SH_PFC_PIN_GROUP(can1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) SH_PFC_PIN_GROUP(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) SH_PFC_PIN_GROUP(can_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) SH_PFC_PIN_GROUP(can_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) SH_PFC_PIN_GROUP(can_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) SH_PFC_PIN_GROUP(du_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) SH_PFC_PIN_GROUP(du_clk_out_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) SH_PFC_PIN_GROUP(du_clk_out_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) SH_PFC_PIN_GROUP(du_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) SH_PFC_PIN_GROUP(du_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) SH_PFC_PIN_GROUP(du_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) SH_PFC_PIN_GROUP(du0_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) SH_PFC_PIN_GROUP(du1_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) SH_PFC_PIN_GROUP(du1_clk_in_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) SH_PFC_PIN_GROUP(du1_clk_in_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) SH_PFC_PIN_GROUP(eth_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) SH_PFC_PIN_GROUP(eth_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) SH_PFC_PIN_GROUP(eth_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) SH_PFC_PIN_GROUP(eth_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) SH_PFC_PIN_GROUP(hscif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) SH_PFC_PIN_GROUP(hscif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) SH_PFC_PIN_GROUP(hscif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) SH_PFC_PIN_GROUP(hscif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) SH_PFC_PIN_GROUP(hscif0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) SH_PFC_PIN_GROUP(hscif0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) SH_PFC_PIN_GROUP(hscif0_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) SH_PFC_PIN_GROUP(hscif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) SH_PFC_PIN_GROUP(hscif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) SH_PFC_PIN_GROUP(hscif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) SH_PFC_PIN_GROUP(hscif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) SH_PFC_PIN_GROUP(hscif1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) SH_PFC_PIN_GROUP(hscif1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) SH_PFC_PIN_GROUP(hscif1_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) SH_PFC_PIN_GROUP(hscif1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) SH_PFC_PIN_GROUP(hscif1_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) SH_PFC_PIN_GROUP(hscif1_clk_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) SH_PFC_PIN_GROUP(hscif1_ctrl_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) SH_PFC_PIN_GROUP(hscif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) SH_PFC_PIN_GROUP(hscif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) SH_PFC_PIN_GROUP(hscif2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) SH_PFC_PIN_GROUP(hscif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) SH_PFC_PIN_GROUP(hscif2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) SH_PFC_PIN_GROUP(hscif2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) SH_PFC_PIN_GROUP(hscif2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) SH_PFC_PIN_GROUP(hscif2_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) SH_PFC_PIN_GROUP(i2c0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) SH_PFC_PIN_GROUP(i2c0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) SH_PFC_PIN_GROUP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) SH_PFC_PIN_GROUP(i2c1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) SH_PFC_PIN_GROUP(i2c1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) SH_PFC_PIN_GROUP(i2c1_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) SH_PFC_PIN_GROUP(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) SH_PFC_PIN_GROUP(i2c2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) SH_PFC_PIN_GROUP(i2c2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) SH_PFC_PIN_GROUP(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) SH_PFC_PIN_GROUP(i2c3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) SH_PFC_PIN_GROUP(i2c3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) SH_PFC_PIN_GROUP(i2c3_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) SH_PFC_PIN_GROUP(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) SH_PFC_PIN_GROUP(i2c4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) SH_PFC_PIN_GROUP(i2c4_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) SH_PFC_PIN_GROUP(i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) SH_PFC_PIN_GROUP(i2c7_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) SH_PFC_PIN_GROUP(i2c7_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) SH_PFC_PIN_GROUP(i2c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) SH_PFC_PIN_GROUP(i2c8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) SH_PFC_PIN_GROUP(i2c8_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) SH_PFC_PIN_GROUP(intc_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) SH_PFC_PIN_GROUP(intc_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) SH_PFC_PIN_GROUP(intc_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) SH_PFC_PIN_GROUP(intc_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) SH_PFC_PIN_GROUP(mmc_data8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563) SH_PFC_PIN_GROUP(msiof0_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) SH_PFC_PIN_GROUP(msiof0_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) SH_PFC_PIN_GROUP(msiof0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) SH_PFC_PIN_GROUP(msiof0_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) SH_PFC_PIN_GROUP(msiof0_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) SH_PFC_PIN_GROUP(msiof0_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) SH_PFC_PIN_GROUP(msiof0_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) SH_PFC_PIN_GROUP(msiof0_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571) SH_PFC_PIN_GROUP(msiof0_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) SH_PFC_PIN_GROUP(msiof0_sync_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) SH_PFC_PIN_GROUP(msiof0_ss1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) SH_PFC_PIN_GROUP(msiof0_ss2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) SH_PFC_PIN_GROUP(msiof0_rx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) SH_PFC_PIN_GROUP(msiof0_tx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) SH_PFC_PIN_GROUP(msiof1_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) SH_PFC_PIN_GROUP(msiof1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) SH_PFC_PIN_GROUP(msiof1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) SH_PFC_PIN_GROUP(msiof1_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) SH_PFC_PIN_GROUP(msiof1_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) SH_PFC_PIN_GROUP(msiof1_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) SH_PFC_PIN_GROUP(msiof1_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) SH_PFC_PIN_GROUP(msiof1_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) SH_PFC_PIN_GROUP(msiof1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) SH_PFC_PIN_GROUP(msiof1_sync_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) SH_PFC_PIN_GROUP(msiof1_rx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) SH_PFC_PIN_GROUP(msiof1_tx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) SH_PFC_PIN_GROUP(msiof1_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) SH_PFC_PIN_GROUP(msiof1_sync_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) SH_PFC_PIN_GROUP(msiof1_ss1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) SH_PFC_PIN_GROUP(msiof1_rx_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) SH_PFC_PIN_GROUP(msiof1_tx_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) SH_PFC_PIN_GROUP(msiof1_clk_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) SH_PFC_PIN_GROUP(msiof1_sync_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) SH_PFC_PIN_GROUP(msiof1_rx_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) SH_PFC_PIN_GROUP(msiof1_tx_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) SH_PFC_PIN_GROUP(msiof2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) SH_PFC_PIN_GROUP(msiof2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) SH_PFC_PIN_GROUP(msiof2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) SH_PFC_PIN_GROUP(msiof2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) SH_PFC_PIN_GROUP(msiof2_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) SH_PFC_PIN_GROUP(msiof2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) SH_PFC_PIN_GROUP(msiof2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) SH_PFC_PIN_GROUP(msiof2_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) SH_PFC_PIN_GROUP(msiof2_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) SH_PFC_PIN_GROUP(msiof2_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) SH_PFC_PIN_GROUP(msiof2_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) SH_PFC_PIN_GROUP(msiof2_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) SH_PFC_PIN_GROUP(msiof2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) SH_PFC_PIN_GROUP(msiof2_sync_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) SH_PFC_PIN_GROUP(msiof2_rx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) SH_PFC_PIN_GROUP(msiof2_tx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) SH_PFC_PIN_GROUP(msiof2_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) SH_PFC_PIN_GROUP(msiof2_sync_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) SH_PFC_PIN_GROUP(msiof2_ss1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) SH_PFC_PIN_GROUP(msiof2_ss2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) SH_PFC_PIN_GROUP(msiof2_rx_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) SH_PFC_PIN_GROUP(msiof2_tx_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) SH_PFC_PIN_GROUP(msiof2_clk_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) SH_PFC_PIN_GROUP(msiof2_sync_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) SH_PFC_PIN_GROUP(msiof2_rx_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) SH_PFC_PIN_GROUP(msiof2_tx_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) SH_PFC_PIN_GROUP(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) SH_PFC_PIN_GROUP(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) SH_PFC_PIN_GROUP(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) SH_PFC_PIN_GROUP(pwm2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) SH_PFC_PIN_GROUP(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) SH_PFC_PIN_GROUP(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) SH_PFC_PIN_GROUP(pwm4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) SH_PFC_PIN_GROUP(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) SH_PFC_PIN_GROUP(pwm5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) SH_PFC_PIN_GROUP(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) SH_PFC_PIN_GROUP(qspi_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) SH_PFC_PIN_GROUP(qspi_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) SH_PFC_PIN_GROUP(qspi_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) SH_PFC_PIN_GROUP(qspi_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) SH_PFC_PIN_GROUP(qspi_data2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) SH_PFC_PIN_GROUP(qspi_data4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) SH_PFC_PIN_GROUP(scif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) SH_PFC_PIN_GROUP(scif0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) SH_PFC_PIN_GROUP(scif0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) SH_PFC_PIN_GROUP(scif0_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) SH_PFC_PIN_GROUP(scif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) SH_PFC_PIN_GROUP(scif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) SH_PFC_PIN_GROUP(scif1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) SH_PFC_PIN_GROUP(scif1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) SH_PFC_PIN_GROUP(scif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) SH_PFC_PIN_GROUP(scif2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) SH_PFC_PIN_GROUP(scif2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) SH_PFC_PIN_GROUP(scif2_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) SH_PFC_PIN_GROUP(scif3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) SH_PFC_PIN_GROUP(scif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) SH_PFC_PIN_GROUP(scif3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665) SH_PFC_PIN_GROUP(scif3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) SH_PFC_PIN_GROUP(scif3_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) SH_PFC_PIN_GROUP(scif4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) SH_PFC_PIN_GROUP(scif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) SH_PFC_PIN_GROUP(scif5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) SH_PFC_PIN_GROUP(scif5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) SH_PFC_PIN_GROUP(scifa0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) SH_PFC_PIN_GROUP(scifa0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) SH_PFC_PIN_GROUP(scifa1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) SH_PFC_PIN_GROUP(scifa1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) SH_PFC_PIN_GROUP(scifa1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) SH_PFC_PIN_GROUP(scifa1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) SH_PFC_PIN_GROUP(scifa1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) SH_PFC_PIN_GROUP(scifa2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) SH_PFC_PIN_GROUP(scifa2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) SH_PFC_PIN_GROUP(scifa2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) SH_PFC_PIN_GROUP(scifa3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) SH_PFC_PIN_GROUP(scifa3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) SH_PFC_PIN_GROUP(scifa3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) SH_PFC_PIN_GROUP(scifa3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) SH_PFC_PIN_GROUP(scifa3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) SH_PFC_PIN_GROUP(scifa3_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) SH_PFC_PIN_GROUP(scifa4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) SH_PFC_PIN_GROUP(scifa4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) SH_PFC_PIN_GROUP(scifa4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) SH_PFC_PIN_GROUP(scifa5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) SH_PFC_PIN_GROUP(scifa5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) SH_PFC_PIN_GROUP(scifa5_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) SH_PFC_PIN_GROUP(scifb0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) SH_PFC_PIN_GROUP(scifb0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) SH_PFC_PIN_GROUP(scifb0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) SH_PFC_PIN_GROUP(scifb0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) SH_PFC_PIN_GROUP(scifb0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) SH_PFC_PIN_GROUP(scifb0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) SH_PFC_PIN_GROUP(scifb0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) SH_PFC_PIN_GROUP(scifb0_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) SH_PFC_PIN_GROUP(scifb0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) SH_PFC_PIN_GROUP(scifb0_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704) SH_PFC_PIN_GROUP(scifb1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) SH_PFC_PIN_GROUP(scifb1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) SH_PFC_PIN_GROUP(scifb1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) SH_PFC_PIN_GROUP(scifb1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) SH_PFC_PIN_GROUP(scifb1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) SH_PFC_PIN_GROUP(scifb1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) SH_PFC_PIN_GROUP(scifb1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) SH_PFC_PIN_GROUP(scifb1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) SH_PFC_PIN_GROUP(scifb2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) SH_PFC_PIN_GROUP(scifb2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) SH_PFC_PIN_GROUP(scifb2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) SH_PFC_PIN_GROUP(scifb2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) SH_PFC_PIN_GROUP(scifb2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) SH_PFC_PIN_GROUP(scifb2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) SH_PFC_PIN_GROUP(scifb2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) SH_PFC_PIN_GROUP(scifb2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) SH_PFC_PIN_GROUP(scifb2_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) SH_PFC_PIN_GROUP(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) SH_PFC_PIN_GROUP(sdhi2_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) SH_PFC_PIN_GROUP(sdhi2_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) SH_PFC_PIN_GROUP(ssi0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) SH_PFC_PIN_GROUP(ssi0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) SH_PFC_PIN_GROUP(ssi0129_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) SH_PFC_PIN_GROUP(ssi0129_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) SH_PFC_PIN_GROUP(ssi1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) SH_PFC_PIN_GROUP(ssi1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) SH_PFC_PIN_GROUP(ssi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) SH_PFC_PIN_GROUP(ssi1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) SH_PFC_PIN_GROUP(ssi2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) SH_PFC_PIN_GROUP(ssi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) SH_PFC_PIN_GROUP(ssi34_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) SH_PFC_PIN_GROUP(ssi4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) SH_PFC_PIN_GROUP(ssi4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) SH_PFC_PIN_GROUP(ssi5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) SH_PFC_PIN_GROUP(ssi5_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) SH_PFC_PIN_GROUP(ssi6_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) SH_PFC_PIN_GROUP(ssi6_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) SH_PFC_PIN_GROUP(ssi7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) SH_PFC_PIN_GROUP(ssi7_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) SH_PFC_PIN_GROUP(ssi78_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) SH_PFC_PIN_GROUP(ssi78_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) SH_PFC_PIN_GROUP(ssi8_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) SH_PFC_PIN_GROUP(ssi8_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) SH_PFC_PIN_GROUP(ssi9_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) SH_PFC_PIN_GROUP(ssi9_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) SH_PFC_PIN_GROUP(ssi9_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) SH_PFC_PIN_GROUP(ssi9_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) SH_PFC_PIN_GROUP(tpu_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) SH_PFC_PIN_GROUP(tpu_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) SH_PFC_PIN_GROUP(tpu_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) SH_PFC_PIN_GROUP(tpu_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) SH_PFC_PIN_GROUP(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) VIN_DATA_PIN_GROUP(vin0_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) VIN_DATA_PIN_GROUP(vin0_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) SH_PFC_PIN_GROUP(vin0_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) VIN_DATA_PIN_GROUP(vin0_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) VIN_DATA_PIN_GROUP(vin0_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) VIN_DATA_PIN_GROUP(vin0_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) VIN_DATA_PIN_GROUP(vin0_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) SH_PFC_PIN_GROUP(vin0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) SH_PFC_PIN_GROUP(vin0_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) SH_PFC_PIN_GROUP(vin1_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) SH_PFC_PIN_GROUP(vin1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) SH_PFC_PIN_GROUP(vin1_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) VIN_DATA_PIN_GROUP(vin1_data, 24, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) VIN_DATA_PIN_GROUP(vin1_data, 20, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) SH_PFC_PIN_GROUP(vin1_data18_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) VIN_DATA_PIN_GROUP(vin1_data, 16, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792) VIN_DATA_PIN_GROUP(vin1_data, 12, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) VIN_DATA_PIN_GROUP(vin1_data, 10, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) VIN_DATA_PIN_GROUP(vin1_data, 8, _b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) SH_PFC_PIN_GROUP(vin1_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) SH_PFC_PIN_GROUP(vin1_field_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) SH_PFC_PIN_GROUP(vin1_clkenb_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) SH_PFC_PIN_GROUP(vin1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) SH_PFC_PIN_GROUP(vin2_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) SH_PFC_PIN_GROUP(vin2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) SH_PFC_PIN_GROUP(vin2_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) SH_PFC_PIN_GROUP(vin2_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) SH_PFC_PIN_GROUP(vin2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) .automotive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) SH_PFC_PIN_GROUP(adi_common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) SH_PFC_PIN_GROUP(adi_chsel0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) SH_PFC_PIN_GROUP(adi_chsel1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) SH_PFC_PIN_GROUP(adi_chsel2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) SH_PFC_PIN_GROUP(adi_common_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) SH_PFC_PIN_GROUP(adi_chsel0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) SH_PFC_PIN_GROUP(adi_chsel1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) SH_PFC_PIN_GROUP(adi_chsel2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) SH_PFC_PIN_GROUP(mlb_3pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) static const char * const adi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) "adi_common",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) "adi_chsel0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) "adi_chsel1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) "adi_chsel2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) "adi_common_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) "adi_chsel0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) "adi_chsel1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) "adi_chsel2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) "audio_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) "audio_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) "audio_clk_b_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) "audio_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) "audio_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) "avb_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) "avb_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) "avb_gmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) "can0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) "can0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) "can0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) "can0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) "can0_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) "can0_data_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) * Retained for backwards compatibility, use can_clk_groups in new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) * designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) "can1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) "can1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) "can1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) "can1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) * Retained for backwards compatibility, use can_clk_groups in new
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) * designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) * can_clk_groups allows for independent configuration, use can_clk function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) * in new designs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) static const char * const can_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) "du_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) "du_clk_out_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) "du_clk_out_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) "du_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) "du_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) "du_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) static const char * const du0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) "du0_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) static const char * const du1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) "du1_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) "du1_clk_in_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) "du1_clk_in_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) static const char * const eth_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) "eth_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) "eth_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) "eth_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) "eth_rmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) "hscif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) "hscif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) "hscif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) "hscif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) "hscif0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) "hscif0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) "hscif0_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) "hscif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) "hscif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) "hscif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) "hscif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) "hscif1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) "hscif1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) "hscif1_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) "hscif1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) "hscif1_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) "hscif1_clk_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) "hscif1_ctrl_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) static const char * const hscif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) "hscif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) "hscif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) "hscif2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) "hscif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) "hscif2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) "hscif2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) "hscif2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) "hscif2_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) "i2c0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) "i2c0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) "i2c1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) "i2c1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) "i2c1_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) "i2c2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) "i2c2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) "i2c3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) "i2c3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) "i2c3_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) "i2c4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) "i2c4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) "i2c4_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) static const char * const i2c7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) "i2c7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) "i2c7_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) "i2c7_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) static const char * const i2c8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) "i2c8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) "i2c8_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) "i2c8_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) static const char * const intc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) "intc_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) "intc_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) "intc_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) "intc_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) static const char * const mlb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) "mlb_3pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) "mmc_data8_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) "msiof0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) "msiof0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) "msiof0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) "msiof0_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) "msiof0_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) "msiof0_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) "msiof0_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) "msiof0_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) "msiof0_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) "msiof0_sync_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) "msiof0_ss1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) "msiof0_ss2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) "msiof0_rx_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) "msiof0_tx_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) "msiof1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) "msiof1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) "msiof1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) "msiof1_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) "msiof1_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) "msiof1_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) "msiof1_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) "msiof1_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) "msiof1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) "msiof1_sync_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) "msiof1_rx_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) "msiof1_tx_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) "msiof1_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) "msiof1_sync_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) "msiof1_ss1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) "msiof1_rx_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) "msiof1_tx_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) "msiof1_clk_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) "msiof1_sync_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) "msiof1_rx_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) "msiof1_tx_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) "msiof2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) "msiof2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) "msiof2_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) "msiof2_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) "msiof2_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) "msiof2_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) "msiof2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) "msiof2_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) "msiof2_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) "msiof2_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) "msiof2_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) "msiof2_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) "msiof2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) "msiof2_sync_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) "msiof2_rx_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) "msiof2_tx_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) "msiof2_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) "msiof2_sync_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) "msiof2_ss1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) "msiof2_ss2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) "msiof2_rx_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) "msiof2_tx_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) "msiof2_clk_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) "msiof2_sync_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) "msiof2_rx_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) "msiof2_tx_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) "pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) "pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) "pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) "pwm2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) "pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) "pwm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) "pwm4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) "pwm5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) "pwm5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) static const char * const pwm6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) "pwm6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) static const char * const qspi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) "qspi_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) "qspi_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) "qspi_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) "qspi_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) "qspi_data2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) "qspi_data4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) "scif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) "scif0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) "scif0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) "scif0_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) "scif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) "scif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) "scif1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) "scif1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) "scif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) "scif2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) "scif2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) "scif2_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) "scif3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) "scif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) "scif3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) "scif3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) "scif3_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) "scif4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) "scif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) "scif5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) "scif5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) static const char * const scifa0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) "scifa0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) "scifa0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) static const char * const scifa1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) "scifa1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) "scifa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) "scifa1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) "scifa1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) "scifa1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) static const char * const scifa2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) "scifa2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) "scifa2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) "scifa2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) static const char * const scifa3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) "scifa3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) "scifa3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) "scifa3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) "scifa3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) "scifa3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) "scifa3_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) static const char * const scifa4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) "scifa4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) "scifa4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) "scifa4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) static const char * const scifa5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) "scifa5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) "scifa5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) "scifa5_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) static const char * const scifb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) "scifb0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) "scifb0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) "scifb0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) "scifb0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) "scifb0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) "scifb0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) "scifb0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) "scifb0_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) "scifb0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) "scifb0_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) static const char * const scifb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) "scifb1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) "scifb1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) "scifb1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) "scifb1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) "scifb1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) "scifb1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) "scifb1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) "scifb1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) static const char * const scifb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) "scifb2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) "scifb2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) "scifb2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) "scifb2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) "scifb2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) "scifb2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) "scifb2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) "scifb2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) "scifb2_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) "scif_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) "sdhi2_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) "sdhi2_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) "ssi0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) "ssi0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) "ssi0129_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) "ssi0129_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) "ssi1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) "ssi1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) "ssi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) "ssi1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) "ssi2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) "ssi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) "ssi34_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) "ssi4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) "ssi4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) "ssi5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) "ssi5_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) "ssi6_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) "ssi6_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) "ssi7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) "ssi7_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) "ssi78_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) "ssi78_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) "ssi8_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) "ssi8_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) "ssi9_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) "ssi9_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) "ssi9_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) "ssi9_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) static const char * const tpu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) "tpu_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) "tpu_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) "tpu_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) "tpu_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) static const char * const usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) "vin0_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) "vin0_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) "vin0_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) "vin0_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) "vin0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) "vin0_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) "vin0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) "vin0_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) "vin1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) "vin1_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) "vin1_data24_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) "vin1_data20_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) "vin1_data18_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) "vin1_data16_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) "vin1_data12_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) "vin1_data10_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) "vin1_data8_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) "vin1_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) "vin1_field_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) "vin1_clkenb_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) "vin1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) static const char * const vin2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) "vin2_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) "vin2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) "vin2_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) "vin2_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) "vin2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) struct sh_pfc_function common[58];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) struct sh_pfc_function automotive[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) } pinmux_functions = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) SH_PFC_FUNCTION(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) SH_PFC_FUNCTION(du0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) SH_PFC_FUNCTION(du1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) SH_PFC_FUNCTION(eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) SH_PFC_FUNCTION(hscif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) SH_PFC_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) SH_PFC_FUNCTION(i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) SH_PFC_FUNCTION(i2c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) SH_PFC_FUNCTION(intc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) SH_PFC_FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) SH_PFC_FUNCTION(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) SH_PFC_FUNCTION(qspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) SH_PFC_FUNCTION(scifa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) SH_PFC_FUNCTION(scifa1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) SH_PFC_FUNCTION(scifa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) SH_PFC_FUNCTION(scifa3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) SH_PFC_FUNCTION(scifa4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) SH_PFC_FUNCTION(scifa5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) SH_PFC_FUNCTION(scifb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) SH_PFC_FUNCTION(scifb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) SH_PFC_FUNCTION(scifb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) SH_PFC_FUNCTION(tpu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) SH_PFC_FUNCTION(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) SH_PFC_FUNCTION(vin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) .automotive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) SH_PFC_FUNCTION(adi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) SH_PFC_FUNCTION(mlb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) GP_0_31_FN, FN_IP1_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) GP_0_30_FN, FN_IP1_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) GP_0_29_FN, FN_IP1_16_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) GP_0_28_FN, FN_IP1_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) GP_0_27_FN, FN_IP1_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) GP_0_26_FN, FN_IP1_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) GP_0_25_FN, FN_IP1_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) GP_0_24_FN, FN_IP1_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) GP_0_23_FN, FN_IP1_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) GP_0_22_FN, FN_IP0_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) GP_0_21_FN, FN_IP0_28_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) GP_0_20_FN, FN_IP0_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) GP_0_19_FN, FN_IP0_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) GP_0_18_FN, FN_IP0_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) GP_0_17_FN, FN_IP0_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) GP_0_16_FN, FN_IP0_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) GP_0_15_FN, FN_IP0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) GP_0_14_FN, FN_IP0_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) GP_0_13_FN, FN_IP0_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) GP_0_12_FN, FN_IP0_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) GP_0_11_FN, FN_IP0_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) GP_0_10_FN, FN_IP0_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) GP_0_9_FN, FN_IP0_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) GP_0_8_FN, FN_IP0_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) GP_0_7_FN, FN_IP0_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) GP_0_6_FN, FN_IP0_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) GP_0_5_FN, FN_IP0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) GP_0_4_FN, FN_IP0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) GP_0_3_FN, FN_IP0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) GP_0_2_FN, FN_IP0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) GP_0_1_FN, FN_IP0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) GP_0_0_FN, FN_IP0_0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) GP_1_25_FN, FN_IP3_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) GP_1_24_FN, FN_IP3_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) GP_1_23_FN, FN_IP3_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) GP_1_22_FN, FN_IP3_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) GP_1_21_FN, FN_IP3_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) GP_1_20_FN, FN_IP3_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) GP_1_19_FN, FN_RD_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) GP_1_18_FN, FN_IP3_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) GP_1_17_FN, FN_IP3_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) GP_1_16_FN, FN_IP3_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) GP_1_15_FN, FN_IP2_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) GP_1_14_FN, FN_IP2_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) GP_1_13_FN, FN_IP2_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) GP_1_12_FN, FN_EX_CS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) GP_1_11_FN, FN_IP2_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) GP_1_10_FN, FN_IP2_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) GP_1_9_FN, FN_IP2_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) GP_1_8_FN, FN_IP2_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) GP_1_7_FN, FN_IP2_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) GP_1_6_FN, FN_IP2_9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) GP_1_5_FN, FN_IP2_6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) GP_1_4_FN, FN_IP2_4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) GP_1_3_FN, FN_IP2_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) GP_1_2_FN, FN_IP1_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) GP_1_1_FN, FN_IP1_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) GP_1_0_FN, FN_IP1_25_23, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) GP_2_31_FN, FN_IP6_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) GP_2_30_FN, FN_IP6_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) GP_2_29_FN, FN_IP6_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) GP_2_28_FN, FN_AUDIO_CLKA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) GP_2_27_FN, FN_IP5_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) GP_2_26_FN, FN_IP5_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) GP_2_25_FN, FN_IP5_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) GP_2_24_FN, FN_IP5_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) GP_2_23_FN, FN_IP5_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) GP_2_22_FN, FN_IP5_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) GP_2_21_FN, FN_IP5_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) GP_2_20_FN, FN_IP5_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) GP_2_19_FN, FN_IP5_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) GP_2_18_FN, FN_IP5_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) GP_2_17_FN, FN_IP5_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) GP_2_16_FN, FN_IP5_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) GP_2_15_FN, FN_IP4_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) GP_2_14_FN, FN_IP4_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) GP_2_13_FN, FN_IP4_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) GP_2_12_FN, FN_IP4_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) GP_2_11_FN, FN_IP4_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) GP_2_10_FN, FN_IP4_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) GP_2_9_FN, FN_IP4_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) GP_2_8_FN, FN_IP4_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) GP_2_7_FN, FN_IP4_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) GP_2_6_FN, FN_IP4_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) GP_2_5_FN, FN_IP4_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) GP_2_4_FN, FN_IP4_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) GP_2_3_FN, FN_IP4_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) GP_2_2_FN, FN_IP4_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) GP_2_1_FN, FN_IP3_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) GP_2_0_FN, FN_IP3_27_25 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) GP_3_31_FN, FN_IP9_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) GP_3_30_FN, FN_IP9_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) GP_3_29_FN, FN_IP9_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) GP_3_28_FN, FN_IP9_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) GP_3_27_FN, FN_IP9_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) GP_3_26_FN, FN_IP9_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) GP_3_25_FN, FN_IP9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) GP_3_24_FN, FN_IP9_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) GP_3_23_FN, FN_IP9_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) GP_3_22_FN, FN_IP9_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) GP_3_21_FN, FN_IP8_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) GP_3_20_FN, FN_IP8_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) GP_3_19_FN, FN_IP8_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) GP_3_18_FN, FN_IP8_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) GP_3_17_FN, FN_IP8_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) GP_3_16_FN, FN_IP8_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) GP_3_15_FN, FN_IP8_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) GP_3_14_FN, FN_IP8_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) GP_3_13_FN, FN_IP8_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) GP_3_12_FN, FN_IP8_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) GP_3_11_FN, FN_IP8_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) GP_3_10_FN, FN_IP7_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) GP_3_9_FN, FN_IP7_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) GP_3_8_FN, FN_IP7_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) GP_3_7_FN, FN_IP7_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) GP_3_6_FN, FN_IP7_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) GP_3_5_FN, FN_IP7_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) GP_3_4_FN, FN_IP7_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) GP_3_3_FN, FN_IP7_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) GP_3_2_FN, FN_IP7_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) GP_3_1_FN, FN_IP7_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) GP_3_0_FN, FN_IP7_5_3 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) GP_4_31_FN, FN_IP15_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) GP_4_30_FN, FN_IP15_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) GP_4_29_FN, FN_IP15_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) GP_4_28_FN, FN_IP11_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) GP_4_27_FN, FN_IP11_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) GP_4_26_FN, FN_IP11_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) GP_4_25_FN, FN_IP10_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) GP_4_24_FN, FN_IP10_28_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) GP_4_23_FN, FN_IP10_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) GP_4_22_FN, FN_IP10_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) GP_4_21_FN, FN_IP10_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) GP_4_20_FN, FN_IP10_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) GP_4_19_FN, FN_IP10_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) GP_4_18_FN, FN_IP10_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) GP_4_17_FN, FN_IP10_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) GP_4_16_FN, FN_IP10_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) GP_4_15_FN, FN_IP10_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) GP_4_14_FN, FN_IP10_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) GP_4_13_FN, FN_IP9_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) GP_4_8_FN, FN_IP9_28_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) GP_4_4_FN, FN_IP9_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) GP_4_3_FN, FN_IP9_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) GP_4_2_FN, FN_IP9_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) GP_4_1_FN, FN_IP9_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) GP_4_0_FN, FN_VI0_CLK ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) GP_5_31_FN, FN_IP3_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) GP_5_30_FN, FN_IP13_9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) GP_5_29_FN, FN_IP13_6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) GP_5_28_FN, FN_IP13_4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) GP_5_27_FN, FN_IP13_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) GP_5_26_FN, FN_IP12_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) GP_5_25_FN, FN_IP12_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) GP_5_24_FN, FN_IP12_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) GP_5_23_FN, FN_IP12_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) GP_5_22_FN, FN_IP12_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) GP_5_21_FN, FN_IP12_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) GP_5_20_FN, FN_IP12_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) GP_5_19_FN, FN_IP12_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) GP_5_18_FN, FN_IP12_9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) GP_5_17_FN, FN_IP12_6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) GP_5_16_FN, FN_IP12_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) GP_5_15_FN, FN_IP12_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) GP_5_14_FN, FN_IP11_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) GP_5_13_FN, FN_IP11_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) GP_5_12_FN, FN_IP11_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) GP_5_11_FN, FN_IP11_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) GP_5_10_FN, FN_IP11_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) GP_5_9_FN, FN_IP11_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) GP_5_8_FN, FN_IP11_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) GP_5_7_FN, FN_IP11_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) GP_5_6_FN, FN_IP11_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) GP_5_5_FN, FN_IP11_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) GP_5_4_FN, FN_IP11_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) GP_5_3_FN, FN_IP11_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) GP_5_2_FN, FN_IP11_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) GP_5_1_FN, FN_IP11_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) GP_5_0_FN, FN_IP11_11_9 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) GP_6_31_FN, FN_DU0_DOTCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) GP_6_30_FN, FN_USB1_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) GP_6_29_FN, FN_IP14_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) GP_6_28_FN, FN_IP14_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) GP_6_27_FN, FN_IP14_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) GP_6_26_FN, FN_IP14_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) GP_6_25_FN, FN_IP14_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) GP_6_24_FN, FN_IP14_16_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) GP_6_23_FN, FN_IP14_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) GP_6_22_FN, FN_IP14_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) GP_6_21_FN, FN_IP14_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) GP_6_20_FN, FN_IP14_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) GP_6_19_FN, FN_IP14_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) GP_6_18_FN, FN_IP14_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) GP_6_17_FN, FN_IP14_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) GP_6_16_FN, FN_IP14_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) GP_6_15_FN, FN_IP14_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) GP_6_14_FN, FN_IP13_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) GP_6_13_FN, FN_IP13_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) GP_6_12_FN, FN_IP13_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) GP_6_11_FN, FN_IP13_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) GP_6_10_FN, FN_IP13_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) GP_6_9_FN, FN_IP13_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) GP_6_8_FN, FN_SD1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) GP_6_7_FN, FN_IP13_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) GP_6_6_FN, FN_IP13_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) GP_6_5_FN, FN_IP13_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) GP_6_4_FN, FN_IP13_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) GP_6_3_FN, FN_IP13_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) GP_6_2_FN, FN_IP13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) GP_6_1_FN, FN_IP13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) GP_6_0_FN, FN_IP13_10 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) GP_7_25_FN, FN_USB1_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) GP_7_24_FN, FN_USB0_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) GP_7_23_FN, FN_USB0_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) GP_7_22_FN, FN_IP15_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) GP_7_21_FN, FN_IP15_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) GP_7_20_FN, FN_IP15_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) GP_7_19_FN, FN_IP7_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) GP_7_18_FN, FN_IP6_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) GP_7_17_FN, FN_IP6_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) GP_7_16_FN, FN_IP6_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) GP_7_15_FN, FN_IP6_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) GP_7_14_FN, FN_IP6_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) GP_7_13_FN, FN_IP6_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) GP_7_12_FN, FN_IP6_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) GP_7_11_FN, FN_IP6_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) GP_7_10_FN, FN_IP6_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) GP_7_9_FN, FN_IP16_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) GP_7_8_FN, FN_IP16_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) GP_7_7_FN, FN_IP16_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) GP_7_6_FN, FN_IP16_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) GP_7_5_FN, FN_IP16_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) GP_7_4_FN, FN_IP15_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) GP_7_3_FN, FN_IP15_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) GP_7_2_FN, FN_IP15_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) GP_7_1_FN, FN_IP15_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) GP_7_0_FN, FN_IP15_17_15 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) GROUP(1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) /* IP0_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) /* IP0_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) FN_A6, FN_MSIOF1_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) /* IP0_28_27 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) FN_A5, FN_MSIOF0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) /* IP0_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) FN_A4, FN_MSIOF0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) /* IP0_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) FN_A3, FN_MSIOF0_SS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) /* IP0_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) FN_A2, FN_MSIOF0_SS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) /* IP0_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) FN_A1, FN_MSIOF0_SYNC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) /* IP0_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_I2C0_SCL_C, FN_PWM2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) /* IP0_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) FN_D15, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) /* IP0_14 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) FN_D14, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) /* IP0_13 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) FN_D13, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) /* IP0_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) FN_D12, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) /* IP0_11 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) FN_D11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) /* IP0_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) FN_D10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) /* IP0_9 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) FN_D9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) /* IP0_8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) FN_D8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) /* IP0_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) FN_D7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) /* IP0_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) FN_D6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) /* IP0_5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) FN_D5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) /* IP0_4 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) FN_D4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) /* IP0_3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) FN_D3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) /* IP0_2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) FN_D2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) /* IP0_1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) FN_D1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) /* IP0_0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) FN_D0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) GROUP(3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) /* IP1_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) /* IP1_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) FN_A17, FN_DACK2_B, 0, FN_I2C0_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) /* IP1_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) /* IP1_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) FN_A15, FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) /* IP1_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) /* IP1_16_14 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) /* IP1_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) FN_A12, FN_FMCLK, FN_I2C3_SDA_D, FN_MSIOF1_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) /* IP1_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) FN_A11, FN_MSIOF1_RXD, FN_I2C3_SCL_D, FN_MSIOF1_RXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) /* IP1_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) /* IP1_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) FN_A9, FN_MSIOF1_SS2, FN_I2C0_SDA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) /* IP1_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) FN_A8, FN_MSIOF1_SS1, FN_I2C0_SCL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) /* IP1_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) FN_A7, FN_MSIOF1_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) GROUP(2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) /* IP2_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) /* IP2_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) FN_ATAG0_N, 0, FN_EX_WAIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) /* IP2_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) /* IP2_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) /* IP2_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) FN_CS1_N_A26, FN_ATADIR0_N_B, FN_I2C1_SDA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) /* IP2_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) FN_CS0_N, FN_ATAG0_N_B, FN_I2C1_SCL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) /* IP2_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) /* IP2_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) /* IP2_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) /* IP2_9_7 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) /* IP2_6_5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) /* IP2_4_3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) FN_A20, FN_SPCLK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) /* IP2_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) GROUP(1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840) /* IP3_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) /* IP3_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) /* IP3_27_25 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) /* IP3_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) /* IP3_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) /* IP3_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) /* IP3_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) /* IP3_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) /* IP3_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) /* IP3_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) /* IP3_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869) /* IP3_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) /* IP3_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) GROUP(1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) 3, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) /* IP4_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) /* IP4_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) /* IP4_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) /* IP4_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) /* IP4_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) /* IP4_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) FN_SSI_SDATA3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) /* IP4_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) FN_SSI_WS34, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) /* IP4_19 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) FN_SSI_SCK34, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) /* IP4_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) /* IP4_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) FN_SSI_WS2, FN_I2C2_SDA, FN_GPS_SIGN_B, FN_RX2_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) FN_GLO_Q1_D, FN_HCTS1_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) /* IP4_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) FN_SSI_SCK2, FN_I2C2_SCL, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) /* IP4_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) FN_SSI_SDATA1, FN_I2C1_SDA_B, FN_IIC1_SDA_B, FN_MSIOF2_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) /* IP4_7_5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) FN_SSI_WS1, FN_I2C1_SCL_B, FN_IIC1_SCL_B, FN_MSIOF2_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) FN_GLO_I1_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) /* IP4_4_2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) FN_SSI_SCK1, FN_I2C0_SDA_B, FN_IIC0_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) /* IP4_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) FN_SSI_SDATA0, FN_I2C0_SCL_B, FN_IIC0_SCL_B, FN_MSIOF2_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) GROUP(3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) /* IP5_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) /* IP5_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930) /* IP5_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) /* IP5_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) /* IP5_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) /* IP5_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937) FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) /* IP5_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) /* IP5_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) /* IP5_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) /* IP5_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) FN_MSIOF2_RXD_D, FN_VI1_R5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951) /* IP5_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) FN_MSIOF2_SS1_D, FN_VI1_R4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) /* IP5_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) FN_MSIOF2_TXD_D, FN_VI1_R3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) GROUP(2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) /* IP6_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965) /* IP6_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) FN_GPS_SIGN_C, FN_GPS_SIGN_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) /* IP6_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) FN_GPS_CLK_C, FN_GPS_CLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973) /* IP6_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) FN_I2C1_SDA_E, FN_MSIOF2_SYNC_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) /* IP6_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) FN_IRQ5, FN_HTX1_C, FN_I2C1_SCL_E, FN_MSIOF2_SCK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) /* IP6_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) FN_IRQ4, FN_HRX1_C, FN_I2C4_SDA_C, FN_MSIOF2_RXD_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) FN_INTC_IRQ4_N, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) /* IP6_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) FN_IRQ3, FN_I2C4_SCL_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) /* IP6_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986) /* IP6_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) /* IP6_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) /* IP6_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) /* IP6_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) FN_SCIFA2_RXD, FN_FMIN_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) /* IP6_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) FN_SCIF_CLK, FN_DVC_MUTE, FN_BPFCLK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002) GROUP(2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) /* IP7_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) /* IP7_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) FN_SCIFA1_SCK, FN_SSI_SCK78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) /* IP7_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) /* IP7_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015) FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) /* IP7_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) /* IP7_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) /* IP7_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) /* IP7_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025) FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) /* IP7_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) /* IP7_10_9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) /* IP7_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) /* IP7_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) /* IP7_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039) FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) FN_SCIF_CLK_B, FN_GPS_MAG_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) GROUP(1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) /* IP8_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) /* IP8_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) /* IP8_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) /* IP8_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) /* IP8_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) /* IP8_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) /* IP8_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) /* IP8_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) /* IP8_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) /* IP8_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076) FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) /* IP8_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083) /* IP8_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) GROUP(3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) 1, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) /* IP9_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) FN_VI0_G0, FN_IIC1_SCL, FN_STP_IVCXO27_0_C, FN_I2C4_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) /* IP9_28_27 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) /* IP9_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097) FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) /* IP9_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) /* IP9_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) /* IP9_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104) /* IP9_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) /* IP9_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) FN_DU1_DISP, FN_QPOLA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) /* IP9_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) FN_CAN0_RX, FN_RX3_B, FN_I2C2_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) /* IP9_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) /* IP9_11 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) /* IP9_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118) FN_TX3_B, FN_I2C2_SCL_B, FN_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) /* IP9_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) FN_DU1_DOTCLKOUT0, FN_QCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) /* IP9_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) /* IP9_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125) FN_DU1_DB7, FN_LCDOUT23, FN_I2C3_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) FN_SCIF3_SCK, FN_SCIFA3_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) /* IP9_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) FN_DU1_DB6, FN_LCDOUT22, FN_I2C3_SCL_C, FN_RX3, FN_SCIFA3_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130) 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) GROUP(3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) /* IP10_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_I2C1_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) /* IP10_28_27 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139) FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) /* IP10_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) /* IP10_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) /* IP10_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) FN_TS_SDATA0_C, FN_ATACS11_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) /* IP10_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) /* IP10_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152) FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) /* IP10_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) /* IP10_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) /* IP10_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_I2C3_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) /* IP10_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_I2C3_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) /* IP10_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) FN_VI0_G1, FN_IIC1_SDA, FN_STP_ISCLK_0_C, FN_I2C4_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168) FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) GROUP(2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) 2, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) /* IP11_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) FN_ETH_CRS_DV, FN_AVB_LINK, FN_I2C2_SDA_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) /* IP11_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) FN_ETH_MDIO, FN_AVB_RX_CLK, FN_I2C2_SCL_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) /* IP11_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) FN_VI1_DATA7, FN_AVB_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) /* IP11_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181) FN_VI1_DATA6, FN_AVB_MAGIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) /* IP11_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) FN_VI1_DATA5, FN_AVB_RX_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) /* IP11_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) FN_VI1_DATA4, FN_AVB_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) /* IP11_23 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) FN_VI1_DATA3, FN_AVB_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) /* IP11_22 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) FN_VI1_DATA2, FN_AVB_RXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) /* IP11_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191) FN_VI1_DATA1, FN_AVB_RXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) /* IP11_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) FN_VI1_DATA0, FN_AVB_RXD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) /* IP11_19 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) FN_VI1_CLK, FN_AVB_RXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) /* IP11_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) /* IP11_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199) FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) /* IP11_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) FN_RX4_B, FN_SCIFA4_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) /* IP11_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205) FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) FN_TX4_B, FN_SCIFA4_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) /* IP11_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) FN_I2C4_SDA_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) /* IP11_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_I2C4_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) /* IP11_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) FN_I2C1_SDA_D, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) GROUP(2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) /* IP12_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) /* IP12_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) /* IP12_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228) FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) /* IP12_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) /* IP12_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) /* IP12_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) /* IP12_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) /* IP12_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) /* IP12_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) /* IP12_9_7 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249) FN_I2C2_SDA_D, FN_MSIOF1_SCK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251) /* IP12_6_4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253) FN_I2C2_SCL_D, FN_MSIOF1_RXD_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) /* IP12_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) FN_ETH_RXD0, FN_AVB_PHY_INT, FN_I2C3_SDA, FN_IIC0_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) /* IP12_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) FN_ETH_RX_ER, FN_AVB_CRS, FN_I2C3_SCL, FN_IIC0_SCL, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) GROUP(1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262) 1, 1, 1, 3, 2, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) /* IP13_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) /* IP13_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267) FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_I2C1_SCL_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) /* IP13_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270) FN_SD1_DATA3, FN_IERX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) /* IP13_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) FN_SD1_DATA2, FN_IECLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) /* IP13_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274) FN_SD1_DATA1, FN_IETX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) /* IP13_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) /* IP13_22 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) FN_SD1_CMD, FN_REMOCON_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279) /* IP13_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) FN_SCIFA5_RXD_B, FN_RX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) /* IP13_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) FN_SCIFA5_TXD_B, FN_TX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) /* IP13_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288) FN_SD0_DATA3, FN_SSL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) /* IP13_14 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) FN_SD0_DATA2, FN_IO3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291) /* IP13_13 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) FN_SD0_DATA1, FN_IO2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) /* IP13_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294) FN_SD0_DATA0, FN_MISO_IO1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) /* IP13_11 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) FN_SD0_CMD, FN_MOSI_IO0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) /* IP13_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298) FN_SD0_CLK, FN_SPCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) /* IP13_9_7 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) FN_ADICHS2_B, FN_MSIOF0_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) /* IP13_6_5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305) /* IP13_4_3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) /* IP13_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308) FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) FN_ADICLK_B, FN_MSIOF0_SS1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) GROUP(3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) /* IP14_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) FN_VI1_VSYNC_N_C, FN_IIC0_SDA_C, FN_VI1_G5_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) /* IP14_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) FN_VI1_HSYNC_N_C, FN_IIC0_SCL_C, FN_VI1_G4_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) /* IP14_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) /* IP14_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) /* IP14_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) FN_VI1_CLKENB_C, FN_VI1_G1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) /* IP14_16_14 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) FN_VI1_CLK_C, FN_VI1_G0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) /* IP14_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) FN_SD2_WP, FN_MMC_D5, FN_IIC1_SDA_C, FN_RX5_B, FN_SCIFA5_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) /* IP14_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340) FN_SD2_CD, FN_MMC_D4, FN_IIC1_SCL_C, FN_TX5_B, FN_SCIFA5_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) /* IP14_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) FN_SD2_DATA3, FN_MMC_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) /* IP14_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) FN_SD2_DATA2, FN_MMC_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) /* IP14_5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) FN_SD2_DATA1, FN_MMC_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) /* IP14_4 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) FN_SD2_DATA0, FN_MMC_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) /* IP14_3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) FN_SD2_CMD, FN_MMC_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) /* IP14_2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353) FN_SD2_CLK, FN_MMC_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) /* IP14_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) FN_SD1_WP, FN_PWM1_B, FN_I2C1_SDA_C, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) /* IP15_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) /* IP15_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363) FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) FN_CAN0_TX_B, FN_VI1_DATA5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) /* IP15_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) FN_CAN0_RX_B, FN_VI1_DATA4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) /* IP15_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371) FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) FN_TCLK2, FN_VI1_DATA3_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) /* IP15_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) /* IP15_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377) FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) FN_TCLK1, FN_VI1_DATA1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) /* IP15_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) FN_VI1_G7_B, FN_SCIFA3_SCK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) /* IP15_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) FN_VI1_G6_B, FN_SCIFA3_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) /* IP15_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) FN_PWM5_B, FN_SCIFA3_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392) /* IP15_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) /* IP15_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) /* IP15_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399) { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) GROUP(4, 4, 4, 4, 4, 2, 2, 2, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) /* IP16_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) /* IP16_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) /* IP16_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) /* IP16_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) /* IP16_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) /* IP16_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418) FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419) /* IP16_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) /* IP16_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422) FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CLK, FN_GLO_RFON_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) /* IP16_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425) FN_GLO_SS_C, FN_VI1_DATA7_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427) /* IP16_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429) FN_GLO_SDATA_C, FN_VI1_DATA6_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433) GROUP(1, 2, 2, 2, 3, 2, 1, 1, 1, 1, 3, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) 2, 2, 1, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) /* SEL_SCIF1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) /* SEL_SCIFB [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442) /* SEL_SCIFB2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445) /* SEL_SCIFB1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447) FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449) /* SEL_SCIFA1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451) /* SEL_SSI9 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) FN_SEL_SSI9_0, FN_SEL_SSI9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) /* SEL_SCFA [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) FN_SEL_SCFA_0, FN_SEL_SCFA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) /* SEL_QSP [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) FN_SEL_QSP_0, FN_SEL_QSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) /* SEL_SSI7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) FN_SEL_SSI7_0, FN_SEL_SSI7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) /* SEL_HSCIF1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465) /* SEL_VI1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) /* SEL_TMU [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470) FN_SEL_TMU1_0, FN_SEL_TMU1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) /* SEL_LBS [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472) FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) /* SEL_TSIF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474) FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) /* SEL_SOF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) GROUP(3, 1, 1, 3, 2, 1, 1, 2, 2, 1, 3, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) 1, 2, 2, 2, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) /* SEL_SCIF0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) /* SEL_SCIF [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) FN_SEL_SCIF_0, FN_SEL_SCIF_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490) /* SEL_CAN0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) FN_SEL_CAN0_4, FN_SEL_CAN0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) /* SEL_CAN1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) /* SEL_SCIFA2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) /* SEL_SCIF4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) /* SEL_ADG [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) FN_SEL_ADG_0, FN_SEL_ADG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) /* SEL_FM [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) FN_SEL_FM_3, FN_SEL_FM_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) /* SEL_SCIFA5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) /* SEL_GPS [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) /* SEL_SCIFA4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) /* SEL_SCIFA3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) /* SEL_SIM [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) FN_SEL_SIM_0, FN_SEL_SIM_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) /* SEL_SSI8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) FN_SEL_SSI8_0, FN_SEL_SSI8_1, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) GROUP(2, 2, 2, 2, 2, 2, 2, 2, 1, 1, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) 3, 2, 2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) /* SEL_HSCIF2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532) FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) /* SEL_CANCLK [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536) FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) /* SEL_IIC1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538) FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) /* SEL_IIC0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540) FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) /* SEL_I2C4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) FN_SEL_I2C4_0, FN_SEL_I2C4_1, FN_SEL_I2C4_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) /* SEL_I2C3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) FN_SEL_I2C3_0, FN_SEL_I2C3_1, FN_SEL_I2C3_2, FN_SEL_I2C3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545) /* SEL_SCIF3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) /* SEL_IEB [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548) FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) /* SEL_MMC [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) FN_SEL_MMC_0, FN_SEL_MMC_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) /* SEL_SCIF5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) /* SEL_I2C2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556) FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) /* SEL_I2C1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559) FN_SEL_I2C1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) /* SEL_I2C0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) FN_SEL_I2C0_0, FN_SEL_I2C0_1, FN_SEL_I2C0_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571) GROUP(3, 2, 2, 1, 1, 1, 1, 3, 2, 2, 3, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) 1, 1, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) /* SEL_SOF1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) FN_SEL_SOF1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) /* SEL_HSCIF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580) /* SEL_DIS [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) /* SEL_RAD [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) FN_SEL_RAD_0, FN_SEL_RAD_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) /* SEL_RCN [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) FN_SEL_RCN_0, FN_SEL_RCN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) /* SEL_RSP [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) FN_SEL_RSP_0, FN_SEL_RSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590) /* SEL_SCIF2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) /* SEL_SOF2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) FN_SEL_SOF2_3, FN_SEL_SOF2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) /* SEL_SSI1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605) FN_SEL_SSI1_0, FN_SEL_SSI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) /* SEL_SSI0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) FN_SEL_SSI0_0, FN_SEL_SSI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) /* SEL_SSP [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) static int r8a7791_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) if (pin < RCAR_GP_PIN(6, 0) || pin > RCAR_GP_PIN(6, 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) *pocctrl = 0xe606008c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627) return 31 - (pin & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) static const struct sh_pfc_soc_operations r8a7791_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) .pin_to_pocctrl = r8a7791_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) #ifdef CONFIG_PINCTRL_PFC_R8A7743
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635) const struct sh_pfc_soc_info r8a7743_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636) .name = "r8a77430_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) .ops = &r8a7791_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) .nr_groups = ARRAY_SIZE(pinmux_groups.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) .nr_functions = ARRAY_SIZE(pinmux_functions.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) #ifdef CONFIG_PINCTRL_PFC_R8A7744
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) const struct sh_pfc_soc_info r8a7744_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) .name = "r8a77440_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) .ops = &r8a7791_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667) .nr_groups = ARRAY_SIZE(pinmux_groups.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) .nr_functions = ARRAY_SIZE(pinmux_functions.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) #ifdef CONFIG_PINCTRL_PFC_R8A7791
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679) const struct sh_pfc_soc_info r8a7791_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) .name = "r8a77910_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) .ops = &r8a7791_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) ARRAY_SIZE(pinmux_groups.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692) .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) ARRAY_SIZE(pinmux_functions.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) #ifdef CONFIG_PINCTRL_PFC_R8A7793
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) const struct sh_pfc_soc_info r8a7793_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) .name = "r8a77930_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) .ops = &r8a7791_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) ARRAY_SIZE(pinmux_groups.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) ARRAY_SIZE(pinmux_functions.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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