^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A7790 processor support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Renesas Electronics Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/sys_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * All pins assigned to GPIO bank 3 can be used for SD interfaces in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * which case they support both 3.3V and 1.8V signalling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_32(0, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_30(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_30(2, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_32(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_GP_32(5, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CPU_ALL_NOGP(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PIN_NOGP(IIC0_SDA, "AF15", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PIN_NOGP(IIC0_SCL, "AG15", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PIN_NOGP(IIC3_SDA, "AH15", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PIN_NOGP(IIC3_SCL, "AJ15", fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FN_IP3_14_12, FN_IP3_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_IP14_15_12, FN_IP14_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FN_SCIFA1_TXD_C, FN_AVB_TXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FN_A0, FN_PWM3, FN_A1, FN_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FN_SSI_WS78_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FN_I2C2_SCL_E, FN_ETH_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FN_HRX0_E, FN_STP_ISSYNC_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FN_ETH_REF_CLK, FN_HCTS0_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) FN_STP_IVCXO27_1_B, FN_HRX0_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FN_ETH_MDIO, FN_HRTS0_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FN_HTX0_F, FN_BPFCLK_G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FN_ETH_TX_EN, FN_SIM0_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FN_HRTS0_N_F, FN_ETH_MAGIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FN_SIM0_RST_C, FN_ETH_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FN_ETH_MDC, FN_STP_ISD_1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FN_ATACS00_N, FN_AVB_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FN_VI1_CLK, FN_AVB_RX_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) FN_SCIFA1_RXD_D, FN_AVB_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FN_AVB_TX_EN, FN_SD1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FN_SD1_DAT0, FN_AVB_TX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FN_SCIFB0_TXD_B, FN_SD1_DAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FN_AVB_COL, FN_SCIFB0_CTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FN_SD1_DAT3, FN_AVB_RXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FN_VI3_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FN_GLO_I0_B, FN_VI3_DATA6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FN_FMIN_E, FN_FMIN_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FN_I2C2_SDA_B, FN_MLB_DAT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FN_SSI_SCK0129, FN_CAN_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FN_MOUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) FN_CAN_DEBUGOUT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) FN_SCIFB1_CTS_N, FN_BPFCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) FN_BPFCLK_F, FN_SSI_WS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) FN_BPFCLK_E, FN_SSI_SDATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) FN_FMIN_G, FN_SSI_SDATA8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) FN_HRTS0_N_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) FN_DU2_DG6, FN_LCDOUT14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) FN_TCLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) FN_SEL_SCIF1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) FN_SEL_SCIFB1_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) FN_SEL_SCFA_0, FN_SEL_SCFA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) FN_SEL_SOF1_0, FN_SEL_SOF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) FN_SEL_SSI6_0, FN_SEL_SSI6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) FN_SEL_VI3_0, FN_SEL_VI3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) FN_SEL_VI2_0, FN_SEL_VI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) FN_SEL_VI1_0, FN_SEL_VI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) FN_SEL_VI0_0, FN_SEL_VI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) FN_SEL_LBS_0, FN_SEL_LBS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) FN_SEL_SOF3_0, FN_SEL_SOF3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) FN_SEL_SOF0_0, FN_SEL_SOF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FN_SEL_TMU1_0, FN_SEL_TMU1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) FN_SEL_CAN1_0, FN_SEL_CAN1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) FN_SEL_ADI_0, FN_SEL_ADI_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) FN_SEL_SSP_0, FN_SEL_SSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) FN_SEL_IIC0_0, FN_SEL_IIC0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) FN_SEL_IIC2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) FN_SEL_I2C2_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) VI1_DATA7_VI1_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) SSI_WS78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ETH_MDIO_MARK, HRTS0_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) HTX0_F_MARK, BPFCLK_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) HRTS0_N_F_MARK, ETH_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SIM0_RST_C_MARK, ETH_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ETH_MDC_MARK, STP_ISD_1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ATACS00_N_MARK, AVB_RXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) VI1_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) AVB_TX_EN_MARK, SD1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SD1_DAT0_MARK, AVB_TX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SD1_DAT3_MARK, AVB_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) VI3_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) GLO_I0_B_MARK, VI3_DATA6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) FMIN_E_MARK, FMIN_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) I2C2_SDA_B_MARK, MLB_DAT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) SSI_SCK0129_MARK, CAN_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MOUT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) CAN_DEBUGOUT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) BPFCLK_F_MARK, SSI_WS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) FMIN_G_MARK, SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) HRTS0_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) DU2_DG6_MARK, LCDOUT14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) TCLK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_SINGLE(VI1_DATA7_VI1_B7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_SINGLE(USB0_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_SINGLE(USB0_OVC_VBUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_SINGLE(USB2_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_SINGLE(USB2_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_SINGLE(AVS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_SINGLE(AVS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_SINGLE(DU_DOTCLKIN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_SINGLE(DU_DOTCLKIN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_IPSR_GPSR(IP0_2_0, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_IPSR_GPSR(IP0_5_3, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP0_8_6, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_GPSR(IP0_11_9, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_GPSR(IP0_15_12, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_GPSR(IP0_19_16, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_GPSR(IP0_22_20, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_GPSR(IP0_26_23, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_IPSR_GPSR(IP0_30_27, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP1_3_0, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_GPSR(IP1_7_4, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_GPSR(IP1_11_8, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_GPSR(IP1_14_12, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_GPSR(IP1_17_15, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_GPSR(IP1_21_18, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_GPSR(IP1_25_22, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_GPSR(IP1_27_26, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_GPSR(IP1_29_28, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_GPSR(IP2_2_0, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_GPSR(IP2_5_3, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_GPSR(IP2_8_6, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_GPSR(IP2_11_9, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_GPSR(IP2_14_12, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_GPSR(IP2_17_15, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_GPSR(IP2_21_18, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_IPSR_GPSR(IP2_25_22, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_IPSR_GPSR(IP2_28_26, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINMUX_IPSR_GPSR(IP3_3_0, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_GPSR(IP3_7_4, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_GPSR(IP3_11_8, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_GPSR(IP3_14_12, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_GPSR(IP3_17_15, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_GPSR(IP3_19_18, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_GPSR(IP3_22_20, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_GPSR(IP3_25_23, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_GPSR(IP3_28_26, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_GPSR(IP3_31_29, A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_IPSR_GPSR(IP4_2_0, A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_GPSR(IP4_5_3, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_GPSR(IP4_8_6, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_GPSR(IP4_8_6, IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_GPSR(IP4_11_9, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_GPSR(IP4_11_9, IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_GPSR(IP4_14_12, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_GPSR(IP4_14_12, SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINMUX_IPSR_GPSR(IP11_17_15, VSP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * Pins not associated with a GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) GP_ASSIGN_LAST(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) PINMUX_NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) /* - AUDIO CLOCK ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static const unsigned int audio_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* CLK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const unsigned int audio_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static const unsigned int audio_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* CLK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static const unsigned int audio_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) AUDIO_CLKB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) static const unsigned int audio_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* CLK C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static const unsigned int audio_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) AUDIO_CLKC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static const unsigned int audio_clkout_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* CLK OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) static const unsigned int audio_clkout_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) AUDIO_CLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static const unsigned int audio_clkout_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* CLK OUT B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) RCAR_GP_PIN(0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static const unsigned int audio_clkout_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) AUDIO_CLKOUT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const unsigned int audio_clkout_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* CLK OUT C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static const unsigned int audio_clkout_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) AUDIO_CLKOUT_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const unsigned int audio_clkout_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* CLK OUT D */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const unsigned int audio_clkout_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) AUDIO_CLKOUT_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) /* - AVB -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) RCAR_GP_PIN(2, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static const unsigned int avb_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static const unsigned int avb_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) AVB_MDC_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static const unsigned int avb_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static const unsigned int avb_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) AVB_TXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) AVB_RXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) AVB_TX_CLK_MARK, AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const unsigned int avb_gmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) static const unsigned int avb_gmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) AVB_TXD6_MARK, AVB_TXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) AVB_RXD6_MARK, AVB_RXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* - CAN0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const unsigned int can0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* CAN0 RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) /* CAN0 TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static const unsigned int can0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) CAN0_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) CAN0_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) static const unsigned int can0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* CAN0 RXB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* CAN0 TXB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static const unsigned int can0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) CAN0_TX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) static const unsigned int can0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* CAN0 RXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) /* CAN0 TXC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const unsigned int can0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) CAN0_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) CAN0_TX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static const unsigned int can0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* CAN0 RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) /* CAN0 TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const unsigned int can0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) CAN0_RX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) CAN0_TX_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* - CAN1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static const unsigned int can1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* CAN1 RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) /* CAN1 TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static const unsigned int can1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) CAN1_RX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) CAN1_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) static const unsigned int can1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* CAN1 RXB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) /* CAN1 TXB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const unsigned int can1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) CAN1_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) CAN1_TX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) /* - CAN Clock -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) static const unsigned int can_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const unsigned int can_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) CAN_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) static const unsigned int can_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) static const unsigned int can_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) CAN_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /* - DU RGB ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static const unsigned int du_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) static const unsigned int du_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) DU2_DR3_MARK, DU2_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) DU2_DG3_MARK, DU2_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) DU2_DB3_MARK, DU2_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static const unsigned int du_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static const unsigned int du_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static const unsigned int du_clk_out_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const unsigned int du_clk_out_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) DU0_DOTCLKOUT_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static const unsigned int du_clk_out_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static const unsigned int du_clk_out_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) DU1_DOTCLKOUT_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const unsigned int du_sync_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* VSYNC, HSYNC, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static const unsigned int du_sync_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static const unsigned int du_sync_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* VSYNC, HSYNC, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) static const unsigned int du_sync_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) DU2_DISP_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) static const unsigned int du_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static const unsigned int du_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) DU2_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) /* - DU0 -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static const unsigned int du0_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) RCAR_GP_PIN(5, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static const unsigned int du0_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) DU_DOTCLKIN0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) /* - DU1 -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static const unsigned int du1_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) static const unsigned int du1_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) DU_DOTCLKIN1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /* - DU2 -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static const unsigned int du2_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) RCAR_GP_PIN(5, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static const unsigned int du2_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) DU_DOTCLKIN2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* - ETH -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static const unsigned int eth_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static const unsigned int eth_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) ETH_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) static const unsigned int eth_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /* MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static const unsigned int eth_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ETH_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static const unsigned int eth_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* MDC, MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static const unsigned int eth_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ETH_MDC_MARK, ETH_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static const unsigned int eth_rmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static const unsigned int eth_rmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static const unsigned int hscif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static const unsigned int hscif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) HRX0_MARK, HTX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static const unsigned int hscif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static const unsigned int hscif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) HSCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static const unsigned int hscif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static const unsigned int hscif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) HRTS0_N_MARK, HCTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static const unsigned int hscif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static const unsigned int hscif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) HRX0_B_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static const unsigned int hscif0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static const unsigned int hscif0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) HRTS0_N_B_MARK, HCTS0_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static const unsigned int hscif0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static const unsigned int hscif0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) HRX0_C_MARK, HTX0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) static const unsigned int hscif0_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static const unsigned int hscif0_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) HRTS0_N_C_MARK, HCTS0_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static const unsigned int hscif0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) static const unsigned int hscif0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) HRX0_D_MARK, HTX0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) static const unsigned int hscif0_ctrl_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) static const unsigned int hscif0_ctrl_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) HRTS0_N_D_MARK, HCTS0_N_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static const unsigned int hscif0_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static const unsigned int hscif0_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) HRX0_E_MARK, HTX0_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static const unsigned int hscif0_ctrl_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) static const unsigned int hscif0_ctrl_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) HRTS0_N_E_MARK, HCTS0_N_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) static const unsigned int hscif0_data_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static const unsigned int hscif0_data_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) HRX0_F_MARK, HTX0_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) static const unsigned int hscif0_ctrl_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) static const unsigned int hscif0_ctrl_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) HRTS0_N_F_MARK, HCTS0_N_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static const unsigned int hscif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static const unsigned int hscif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) HRX1_MARK, HTX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) static const unsigned int hscif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static const unsigned int hscif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) HSCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) static const unsigned int hscif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static const unsigned int hscif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) HRTS1_N_MARK, HCTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static const unsigned int hscif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) static const unsigned int hscif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) HRX1_B_MARK, HTX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static const unsigned int hscif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) RCAR_GP_PIN(1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static const unsigned int hscif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) HSCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static const unsigned int hscif1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static const unsigned int hscif1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) HRTS1_N_B_MARK, HCTS1_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) /* - I2C0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) static const unsigned int i2c0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) PIN_IIC0_SCL, PIN_IIC0_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static const unsigned int i2c0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) I2C0_SCL_MARK, I2C0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* - I2C1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) static const unsigned int i2c1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) static const unsigned int i2c1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) I2C1_SCL_MARK, I2C1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static const unsigned int i2c1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) static const unsigned int i2c1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) static const unsigned int i2c1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static const unsigned int i2c1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) static const unsigned int i2c2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) static const unsigned int i2c2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) I2C2_SCL_MARK, I2C2_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) static const unsigned int i2c2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static const unsigned int i2c2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) static const unsigned int i2c2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) static const unsigned int i2c2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static const unsigned int i2c2_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) static const unsigned int i2c2_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) static const unsigned int i2c3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) PIN_IIC3_SCL, PIN_IIC3_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) static const unsigned int i2c3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) I2C3_SCL_MARK, I2C3_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /* - IIC0 (I2C4) ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static const unsigned int iic0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) PIN_IIC0_SCL, PIN_IIC0_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static const unsigned int iic0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) IIC0_SCL_MARK, IIC0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) /* - IIC1 (I2C5) ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static const unsigned int iic1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static const unsigned int iic1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) IIC1_SCL_MARK, IIC1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static const unsigned int iic1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static const unsigned int iic1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) static const unsigned int iic1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static const unsigned int iic1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* - IIC2 (I2C6) ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static const unsigned int iic2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static const unsigned int iic2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) IIC2_SCL_MARK, IIC2_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) static const unsigned int iic2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static const unsigned int iic2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static const unsigned int iic2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) static const unsigned int iic2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) static const unsigned int iic2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) static const unsigned int iic2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) static const unsigned int iic2_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) static const unsigned int iic2_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* - IIC3 (I2C7) ------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) static const unsigned int iic3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) PIN_IIC3_SCL, PIN_IIC3_SDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) static const unsigned int iic3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) IIC3_SCL_MARK, IIC3_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /* - INTC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) static const unsigned int intc_irq0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static const unsigned int intc_irq0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) IRQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) static const unsigned int intc_irq1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) RCAR_GP_PIN(1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) static const unsigned int intc_irq1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) static const unsigned int intc_irq2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) RCAR_GP_PIN(1, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static const unsigned int intc_irq2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) IRQ2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static const unsigned int intc_irq3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static const unsigned int intc_irq3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) IRQ3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* - MLB+ ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static const unsigned int mlb_3pin_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) static const unsigned int mlb_3pin_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* - MMCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) static const unsigned int mmc0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) static const unsigned int mmc0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) MMC0_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) static const unsigned int mmc0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) static const unsigned int mmc0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) static const unsigned int mmc0_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) static const unsigned int mmc0_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) static const unsigned int mmc0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static const unsigned int mmc0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) MMC0_CLK_MARK, MMC0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) /* - MMCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static const unsigned int mmc1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) static const unsigned int mmc1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) MMC1_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static const unsigned int mmc1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) static const unsigned int mmc1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) static const unsigned int mmc1_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) static const unsigned int mmc1_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static const unsigned int mmc1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static const unsigned int mmc1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) MMC1_CLK_MARK, MMC1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) /* - MSIOF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static const unsigned int msiof0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) static const unsigned int msiof0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) MSIOF0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) static const unsigned int msiof0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) static const unsigned int msiof0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) MSIOF0_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) static const unsigned int msiof0_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) static const unsigned int msiof0_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) MSIOF0_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) static const unsigned int msiof0_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static const unsigned int msiof0_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) MSIOF0_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) static const unsigned int msiof0_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) static const unsigned int msiof0_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static const unsigned int msiof0_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) static const unsigned int msiof0_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) MSIOF0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static const unsigned int msiof0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) static const unsigned int msiof0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) MSIOF0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static const unsigned int msiof0_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static const unsigned int msiof0_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) MSIOF0_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) static const unsigned int msiof0_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) static const unsigned int msiof0_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) MSIOF0_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) static const unsigned int msiof0_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) RCAR_GP_PIN(1, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) static const unsigned int msiof0_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) MSIOF0_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static const unsigned int msiof0_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) RCAR_GP_PIN(1, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static const unsigned int msiof0_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) MSIOF0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* - MSIOF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) static const unsigned int msiof1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) static const unsigned int msiof1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) MSIOF1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static const unsigned int msiof1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static const unsigned int msiof1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) MSIOF1_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) static const unsigned int msiof1_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) static const unsigned int msiof1_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) MSIOF1_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static const unsigned int msiof1_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static const unsigned int msiof1_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) MSIOF1_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) static const unsigned int msiof1_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static const unsigned int msiof1_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) MSIOF1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) static const unsigned int msiof1_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static const unsigned int msiof1_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) MSIOF1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) static const unsigned int msiof1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) RCAR_GP_PIN(1, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static const unsigned int msiof1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) MSIOF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static const unsigned int msiof1_ss1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) static const unsigned int msiof1_ss1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) MSIOF1_SS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static const unsigned int msiof1_ss2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) static const unsigned int msiof1_ss2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) MSIOF1_SS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static const unsigned int msiof1_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) RCAR_GP_PIN(1, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static const unsigned int msiof1_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) MSIOF1_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static const unsigned int msiof1_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static const unsigned int msiof1_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) MSIOF1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* - MSIOF2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static const unsigned int msiof2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) RCAR_GP_PIN(0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static const unsigned int msiof2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) MSIOF2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static const unsigned int msiof2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) RCAR_GP_PIN(0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const unsigned int msiof2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) MSIOF2_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static const unsigned int msiof2_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) RCAR_GP_PIN(0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static const unsigned int msiof2_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static const unsigned int msiof2_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) RCAR_GP_PIN(0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static const unsigned int msiof2_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) MSIOF2_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) static const unsigned int msiof2_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) RCAR_GP_PIN(0, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static const unsigned int msiof2_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) MSIOF2_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) static const unsigned int msiof2_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) RCAR_GP_PIN(0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static const unsigned int msiof2_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) MSIOF2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) /* - MSIOF3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static const unsigned int msiof3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static const unsigned int msiof3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) MSIOF3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const unsigned int msiof3_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static const unsigned int msiof3_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) MSIOF3_SYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static const unsigned int msiof3_ss1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* SS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static const unsigned int msiof3_ss1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) MSIOF3_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static const unsigned int msiof3_ss2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /* SS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static const unsigned int msiof3_ss2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) MSIOF3_SS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static const unsigned int msiof3_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) static const unsigned int msiof3_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) MSIOF3_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static const unsigned int msiof3_tx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static const unsigned int msiof3_tx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) MSIOF3_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static const unsigned int msiof3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) RCAR_GP_PIN(0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static const unsigned int msiof3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) MSIOF3_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static const unsigned int msiof3_sync_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /* SYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static const unsigned int msiof3_sync_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) MSIOF3_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static const unsigned int msiof3_rx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* RXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) RCAR_GP_PIN(0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static const unsigned int msiof3_rx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) MSIOF3_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static const unsigned int msiof3_tx_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static const unsigned int msiof3_tx_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) MSIOF3_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) /* - PWM -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) static const unsigned int pwm0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) static const unsigned int pwm0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) PWM0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) static const unsigned int pwm0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) static const unsigned int pwm0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) PWM0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) static const unsigned int pwm1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) RCAR_GP_PIN(5, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) static const unsigned int pwm1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) PWM1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) static const unsigned int pwm1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) RCAR_GP_PIN(4, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) static const unsigned int pwm1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) PWM1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) static const unsigned int pwm2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) static const unsigned int pwm2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) PWM2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) static const unsigned int pwm3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) static const unsigned int pwm3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) PWM3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) static const unsigned int pwm4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) RCAR_GP_PIN(0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) static const unsigned int pwm4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) PWM4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) static const unsigned int pwm5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) static const unsigned int pwm5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) PWM5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static const unsigned int pwm6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static const unsigned int pwm6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) PWM6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) /* - QSPI ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) static const unsigned int qspi_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) static const unsigned int qspi_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) SPCLK_MARK, SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) static const unsigned int qspi_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) static const unsigned int qspi_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) MOSI_IO0_MARK, MISO_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) static const unsigned int qspi_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) static const unsigned int qspi_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) static const unsigned int scif0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) static const unsigned int scif0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) RX0_MARK, TX0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) static const unsigned int scif0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) static const unsigned int scif0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) SCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) static const unsigned int scif0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) static const unsigned int scif0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) RTS0_N_MARK, CTS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) static const unsigned int scif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) static const unsigned int scif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) RX0_B_MARK, TX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static const unsigned int scif1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) static const unsigned int scif1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) RX1_MARK, TX1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) static const unsigned int scif1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) static const unsigned int scif1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) SCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static const unsigned int scif1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) static const unsigned int scif1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) RTS1_N_MARK, CTS1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) static const unsigned int scif1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) static const unsigned int scif1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) RX1_C_MARK, TX1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) static const unsigned int scif1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) static const unsigned int scif1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) RX1_D_MARK, TX1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) static const unsigned int scif1_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) static const unsigned int scif1_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) SCK1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) static const unsigned int scif1_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) static const unsigned int scif1_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) RX1_E_MARK, TX1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) static const unsigned int scif1_clk_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) static const unsigned int scif1_clk_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) SCK1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) static const unsigned int scif2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) static const unsigned int scif2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) RX2_MARK, TX2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) static const unsigned int scif2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) static const unsigned int scif2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) SCK2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) static const unsigned int scif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) static const unsigned int scif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) RX2_B_MARK, TX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) /* - SCIFA0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) static const unsigned int scifa0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) static const unsigned int scifa0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) static const unsigned int scifa0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) RCAR_GP_PIN(4, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static const unsigned int scifa0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) SCIFA0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) static const unsigned int scifa0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static const unsigned int scifa0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) static const unsigned int scifa0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) static const unsigned int scifa0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) static const unsigned int scifa0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) static const unsigned int scifa0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) SCIFA0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) static const unsigned int scifa0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) static const unsigned int scifa0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) /* - SCIFA1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) static const unsigned int scifa1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) static const unsigned int scifa1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) static const unsigned int scifa1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) static const unsigned int scifa1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) SCIFA1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) static const unsigned int scifa1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) static const unsigned int scifa1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) static const unsigned int scifa1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) static const unsigned int scifa1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) static const unsigned int scifa1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) RCAR_GP_PIN(0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) static const unsigned int scifa1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) SCIFA1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static const unsigned int scifa1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) static const unsigned int scifa1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) static const unsigned int scifa1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) static const unsigned int scifa1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) static const unsigned int scifa1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) static const unsigned int scifa1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) SCIFA1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) static const unsigned int scifa1_ctrl_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) static const unsigned int scifa1_ctrl_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) static const unsigned int scifa1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) static const unsigned int scifa1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) static const unsigned int scifa1_clk_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) static const unsigned int scifa1_clk_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) SCIFA1_SCK_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) static const unsigned int scifa1_ctrl_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) static const unsigned int scifa1_ctrl_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) /* - SCIFA2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) static const unsigned int scifa2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) static const unsigned int scifa2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) static const unsigned int scifa2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) static const unsigned int scifa2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) SCIFA2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) static const unsigned int scifa2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) static const unsigned int scifa2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) static const unsigned int scifa2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) static const unsigned int scifa2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) static const unsigned int scifa2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) static const unsigned int scifa2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) static const unsigned int scifa2_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) static const unsigned int scifa2_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) SCIFA2_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) /* - SCIFB0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static const unsigned int scifb0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) static const unsigned int scifb0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) static const unsigned int scifb0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) static const unsigned int scifb0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) SCIFB0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) static const unsigned int scifb0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static const unsigned int scifb0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) static const unsigned int scifb0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) static const unsigned int scifb0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) static const unsigned int scifb0_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) static const unsigned int scifb0_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) SCIFB0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) static const unsigned int scifb0_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) static const unsigned int scifb0_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) static const unsigned int scifb0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) static const unsigned int scifb0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /* - SCIFB1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) static const unsigned int scifb1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) static const unsigned int scifb1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) static const unsigned int scifb1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) static const unsigned int scifb1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) SCIFB1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) static const unsigned int scifb1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) static const unsigned int scifb1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) static const unsigned int scifb1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) static const unsigned int scifb1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static const unsigned int scifb1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) static const unsigned int scifb1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) SCIFB1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) static const unsigned int scifb1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) static const unsigned int scifb1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) static const unsigned int scifb1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static const unsigned int scifb1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) static const unsigned int scifb1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) static const unsigned int scifb1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) static const unsigned int scifb1_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) static const unsigned int scifb1_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) static const unsigned int scifb1_clk_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) static const unsigned int scifb1_clk_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) SCIFB1_SCK_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) static const unsigned int scifb1_data_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) static const unsigned int scifb1_data_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) static const unsigned int scifb1_data_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) static const unsigned int scifb1_data_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) static const unsigned int scifb1_clk_g_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) RCAR_GP_PIN(2, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) static const unsigned int scifb1_clk_g_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) SCIFB1_SCK_G_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) /* - SCIFB2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) static const unsigned int scifb2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) static const unsigned int scifb2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) static const unsigned int scifb2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) static const unsigned int scifb2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) SCIFB2_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) static const unsigned int scifb2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) static const unsigned int scifb2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) static const unsigned int scifb2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) static const unsigned int scifb2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) static const unsigned int scifb2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) RCAR_GP_PIN(0, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) static const unsigned int scifb2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) SCIFB2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) static const unsigned int scifb2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) static const unsigned int scifb2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) static const unsigned int scifb2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) static const unsigned int scifb2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) static const unsigned int scif_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) RCAR_GP_PIN(4, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) static const unsigned int scif_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) SCIF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) SD0_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) SD0_CLK_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) SD0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) RCAR_GP_PIN(3, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) SD1_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) SD1_CLK_MARK, SD1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) RCAR_GP_PIN(3, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) SD2_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) SD2_CLK_MARK, SD2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) static const unsigned int sdhi2_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) RCAR_GP_PIN(3, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) static const unsigned int sdhi2_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) SD2_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) static const unsigned int sdhi2_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) RCAR_GP_PIN(3, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) static const unsigned int sdhi2_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) SD2_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) /* - SDHI3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) static const unsigned int sdhi3_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) static const unsigned int sdhi3_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) SD3_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) static const unsigned int sdhi3_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) static const unsigned int sdhi3_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) static const unsigned int sdhi3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) static const unsigned int sdhi3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) SD3_CLK_MARK, SD3_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) static const unsigned int sdhi3_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) static const unsigned int sdhi3_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) SD3_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) static const unsigned int sdhi3_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) RCAR_GP_PIN(3, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) static const unsigned int sdhi3_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) SD3_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) /* - SSI -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) static const unsigned int ssi0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) /* SDATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) static const unsigned int ssi0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) SSI_SDATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) static const unsigned int ssi0129_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) static const unsigned int ssi0129_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) SSI_SCK0129_MARK, SSI_WS0129_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) static const unsigned int ssi1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) /* SDATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) static const unsigned int ssi1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) SSI_SDATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) static const unsigned int ssi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) static const unsigned int ssi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) SSI_SCK1_MARK, SSI_WS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) static const unsigned int ssi2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) /* SDATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) static const unsigned int ssi2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) SSI_SDATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) static const unsigned int ssi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) static const unsigned int ssi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) SSI_SCK2_MARK, SSI_WS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) static const unsigned int ssi3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) /* SDATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) static const unsigned int ssi3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) SSI_SDATA3_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) static const unsigned int ssi34_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) static const unsigned int ssi34_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) SSI_SCK34_MARK, SSI_WS34_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) static const unsigned int ssi4_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) /* SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) RCAR_GP_PIN(4, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) static const unsigned int ssi4_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) SSI_SDATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) static const unsigned int ssi4_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) static const unsigned int ssi4_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) SSI_SCK4_MARK, SSI_WS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) static const unsigned int ssi5_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) /* SDATA5, SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) static const unsigned int ssi5_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) static const unsigned int ssi5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /* SDATA5, SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) static const unsigned int ssi5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) static const unsigned int ssi5_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) /* SDATA5, SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) static const unsigned int ssi5_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) static const unsigned int ssi6_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) /* SDATA6, SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) static const unsigned int ssi6_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) static const unsigned int ssi6_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) /* SDATA6, SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) static const unsigned int ssi6_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) static const unsigned int ssi7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) /* SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) static const unsigned int ssi7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) static const unsigned int ssi7_b_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) /* SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) static const unsigned int ssi7_b_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) static const unsigned int ssi7_c_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) /* SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) RCAR_GP_PIN(1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) static const unsigned int ssi7_c_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) SSI_SDATA7_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) static const unsigned int ssi78_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) static const unsigned int ssi78_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) SSI_SCK78_MARK, SSI_WS78_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) static const unsigned int ssi78_b_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) static const unsigned int ssi78_b_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) static const unsigned int ssi78_c_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) static const unsigned int ssi78_c_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) static const unsigned int ssi8_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) /* SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) static const unsigned int ssi8_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) static const unsigned int ssi8_b_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) /* SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) static const unsigned int ssi8_b_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) SSI_SDATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) static const unsigned int ssi8_c_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) /* SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) RCAR_GP_PIN(1, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) static const unsigned int ssi8_c_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) SSI_SDATA8_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) static const unsigned int ssi9_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) /* SDATA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) RCAR_GP_PIN(4, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) static const unsigned int ssi9_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) SSI_SDATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) static const unsigned int ssi9_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) /* SCK, WS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) static const unsigned int ssi9_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) SSI_SCK9_MARK, SSI_WS9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /* - TPU0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) static const unsigned int tpu0_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static const unsigned int tpu0_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) TPU0TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) static const unsigned int tpu0_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) RCAR_GP_PIN(0, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) static const unsigned int tpu0_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) static const unsigned int tpu0_to2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) RCAR_GP_PIN(0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) static const unsigned int tpu0_to2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) TPU0TO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) static const unsigned int tpu0_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) RCAR_GP_PIN(0, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) static const unsigned int tpu0_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) static const unsigned int usb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) /* PWEN, OVC/VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) static const unsigned int usb0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) static const unsigned int usb0_ovc_vbus_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) /* OVC/VBUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) static const unsigned int usb0_ovc_vbus_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) USB0_OVC_VBUS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) /* - USB1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) static const unsigned int usb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) static const unsigned int usb1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) USB1_PWEN_MARK, USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) static const unsigned int usb1_pwen_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) static const unsigned int usb1_pwen_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) USB1_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) /* - USB2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) static const unsigned int usb2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) /* PWEN, OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) static const unsigned int usb2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) USB2_PWEN_MARK, USB2_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) static const union vin_data vin0_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) static const union vin_data vin0_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) VI0_G0_MARK, VI0_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) VI0_R0_MARK, VI0_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) static const unsigned int vin0_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) static const unsigned int vin0_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) static const unsigned int vin0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) RCAR_GP_PIN(0, 12), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) RCAR_GP_PIN(0, 13), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) static const unsigned int vin0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) VI0_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) static const unsigned int vin0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) static const unsigned int vin0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) static const unsigned int vin0_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) static const unsigned int vin0_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) static const unsigned int vin0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) static const unsigned int vin0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) /* - VIN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) static const union vin_data vin1_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) static const union vin_data vin1_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) VI1_G0_MARK, VI1_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) VI1_G2_MARK, VI1_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) VI1_G4_MARK, VI1_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) VI1_G6_MARK, VI1_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) VI1_R0_MARK, VI1_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) VI1_R2_MARK, VI1_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) VI1_R4_MARK, VI1_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) VI1_R6_MARK, VI1_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) static const unsigned int vin1_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) static const unsigned int vin1_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) VI1_G2_MARK, VI1_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) VI1_G4_MARK, VI1_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) VI1_G6_MARK, VI1_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) VI1_R2_MARK, VI1_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) VI1_R4_MARK, VI1_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) VI1_R6_MARK, VI1_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) static const unsigned int vin1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) RCAR_GP_PIN(1, 24), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) RCAR_GP_PIN(1, 25), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) static const unsigned int vin1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) VI1_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) static const unsigned int vin1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) static const unsigned int vin1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) static const unsigned int vin1_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) RCAR_GP_PIN(1, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) static const unsigned int vin1_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) static const unsigned int vin1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) static const unsigned int vin1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) /* - VIN2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) static const union vin_data vin2_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) static const union vin_data vin2_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) VI2_G0_MARK, VI2_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) VI2_G2_MARK, VI2_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) VI2_G4_MARK, VI2_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) VI2_G6_MARK, VI2_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) VI2_R0_MARK, VI2_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) VI2_R2_MARK, VI2_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930) VI2_R4_MARK, VI2_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) VI2_R6_MARK, VI2_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) static const unsigned int vin2_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) static const unsigned int vin2_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) VI2_G2_MARK, VI2_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) VI2_G4_MARK, VI2_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) VI2_G6_MARK, VI2_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) VI2_R2_MARK, VI2_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) VI2_R4_MARK, VI2_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) VI2_R6_MARK, VI2_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) static const unsigned int vin2_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) RCAR_GP_PIN(1, 16), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) RCAR_GP_PIN(1, 21), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) static const unsigned int vin2_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) VI2_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) VI2_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) static const unsigned int vin2_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) static const unsigned int vin2_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) VI2_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) static const unsigned int vin2_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) static const unsigned int vin2_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) VI2_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) static const unsigned int vin2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) RCAR_GP_PIN(1, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) static const unsigned int vin2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) VI2_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) /* - VIN3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) static const unsigned int vin3_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) static const unsigned int vin3_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) VI3_DATA0_MARK, VI3_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) VI3_DATA2_MARK, VI3_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) VI3_DATA4_MARK, VI3_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) VI3_DATA6_MARK, VI3_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) static const unsigned int vin3_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) RCAR_GP_PIN(1, 16), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) RCAR_GP_PIN(1, 17), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) static const unsigned int vin3_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) VI3_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) VI3_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) static const unsigned int vin3_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) static const unsigned int vin3_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) VI3_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) static const unsigned int vin3_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) static const unsigned int vin3_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) VI3_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) static const unsigned int vin3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) RCAR_GP_PIN(1, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) static const unsigned int vin3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) VI3_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) struct sh_pfc_pin_group common[298];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) struct sh_pfc_pin_group automotive[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) } pinmux_groups = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) SH_PFC_PIN_GROUP(audio_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) SH_PFC_PIN_GROUP(audio_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) SH_PFC_PIN_GROUP(audio_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) SH_PFC_PIN_GROUP(audio_clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) SH_PFC_PIN_GROUP(audio_clkout_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) SH_PFC_PIN_GROUP(audio_clkout_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) SH_PFC_PIN_GROUP(audio_clkout_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) SH_PFC_PIN_GROUP(avb_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) SH_PFC_PIN_GROUP(avb_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) SH_PFC_PIN_GROUP(avb_gmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) SH_PFC_PIN_GROUP(can0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) SH_PFC_PIN_GROUP(can0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) SH_PFC_PIN_GROUP(can0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) SH_PFC_PIN_GROUP(can0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) SH_PFC_PIN_GROUP(can1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) SH_PFC_PIN_GROUP(can1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) SH_PFC_PIN_GROUP(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) SH_PFC_PIN_GROUP(can_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) SH_PFC_PIN_GROUP(du_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) SH_PFC_PIN_GROUP(du_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) SH_PFC_PIN_GROUP(du_clk_out_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) SH_PFC_PIN_GROUP(du_clk_out_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) SH_PFC_PIN_GROUP(du_sync_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) SH_PFC_PIN_GROUP(du_sync_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) SH_PFC_PIN_GROUP(du_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) SH_PFC_PIN_GROUP(du0_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) SH_PFC_PIN_GROUP(du1_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) SH_PFC_PIN_GROUP(du2_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) SH_PFC_PIN_GROUP(eth_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) SH_PFC_PIN_GROUP(eth_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) SH_PFC_PIN_GROUP(eth_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) SH_PFC_PIN_GROUP(eth_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) SH_PFC_PIN_GROUP(hscif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) SH_PFC_PIN_GROUP(hscif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) SH_PFC_PIN_GROUP(hscif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) SH_PFC_PIN_GROUP(hscif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) SH_PFC_PIN_GROUP(hscif0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) SH_PFC_PIN_GROUP(hscif0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) SH_PFC_PIN_GROUP(hscif0_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) SH_PFC_PIN_GROUP(hscif0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) SH_PFC_PIN_GROUP(hscif0_ctrl_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) SH_PFC_PIN_GROUP(hscif0_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) SH_PFC_PIN_GROUP(hscif0_ctrl_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) SH_PFC_PIN_GROUP(hscif0_data_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) SH_PFC_PIN_GROUP(hscif0_ctrl_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) SH_PFC_PIN_GROUP(hscif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) SH_PFC_PIN_GROUP(hscif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) SH_PFC_PIN_GROUP(hscif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) SH_PFC_PIN_GROUP(hscif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) SH_PFC_PIN_GROUP(hscif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) SH_PFC_PIN_GROUP(hscif1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) SH_PFC_PIN_GROUP(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) SH_PFC_PIN_GROUP(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) SH_PFC_PIN_GROUP(i2c1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) SH_PFC_PIN_GROUP(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) SH_PFC_PIN_GROUP(i2c2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) SH_PFC_PIN_GROUP(i2c2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) SH_PFC_PIN_GROUP(i2c2_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) SH_PFC_PIN_GROUP(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) SH_PFC_PIN_GROUP(iic0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) SH_PFC_PIN_GROUP(iic1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) SH_PFC_PIN_GROUP(iic1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) SH_PFC_PIN_GROUP(iic1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101) SH_PFC_PIN_GROUP(iic2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) SH_PFC_PIN_GROUP(iic2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) SH_PFC_PIN_GROUP(iic2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) SH_PFC_PIN_GROUP(iic2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) SH_PFC_PIN_GROUP(iic2_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) SH_PFC_PIN_GROUP(iic3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) SH_PFC_PIN_GROUP(intc_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) SH_PFC_PIN_GROUP(intc_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) SH_PFC_PIN_GROUP(intc_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) SH_PFC_PIN_GROUP(intc_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) SH_PFC_PIN_GROUP(mmc0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) SH_PFC_PIN_GROUP(mmc0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) SH_PFC_PIN_GROUP(mmc0_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) SH_PFC_PIN_GROUP(mmc0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) SH_PFC_PIN_GROUP(mmc1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) SH_PFC_PIN_GROUP(mmc1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) SH_PFC_PIN_GROUP(mmc1_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) SH_PFC_PIN_GROUP(mmc1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) SH_PFC_PIN_GROUP(msiof0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) SH_PFC_PIN_GROUP(msiof0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) SH_PFC_PIN_GROUP(msiof0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) SH_PFC_PIN_GROUP(msiof0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) SH_PFC_PIN_GROUP(msiof0_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124) SH_PFC_PIN_GROUP(msiof0_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) SH_PFC_PIN_GROUP(msiof0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) SH_PFC_PIN_GROUP(msiof0_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) SH_PFC_PIN_GROUP(msiof0_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) SH_PFC_PIN_GROUP(msiof0_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129) SH_PFC_PIN_GROUP(msiof0_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) SH_PFC_PIN_GROUP(msiof1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) SH_PFC_PIN_GROUP(msiof1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132) SH_PFC_PIN_GROUP(msiof1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) SH_PFC_PIN_GROUP(msiof1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) SH_PFC_PIN_GROUP(msiof1_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) SH_PFC_PIN_GROUP(msiof1_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) SH_PFC_PIN_GROUP(msiof1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) SH_PFC_PIN_GROUP(msiof1_ss1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138) SH_PFC_PIN_GROUP(msiof1_ss2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) SH_PFC_PIN_GROUP(msiof1_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) SH_PFC_PIN_GROUP(msiof1_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) SH_PFC_PIN_GROUP(msiof2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) SH_PFC_PIN_GROUP(msiof2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) SH_PFC_PIN_GROUP(msiof2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144) SH_PFC_PIN_GROUP(msiof2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) SH_PFC_PIN_GROUP(msiof2_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) SH_PFC_PIN_GROUP(msiof2_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147) SH_PFC_PIN_GROUP(msiof3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) SH_PFC_PIN_GROUP(msiof3_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) SH_PFC_PIN_GROUP(msiof3_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150) SH_PFC_PIN_GROUP(msiof3_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) SH_PFC_PIN_GROUP(msiof3_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) SH_PFC_PIN_GROUP(msiof3_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153) SH_PFC_PIN_GROUP(msiof3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) SH_PFC_PIN_GROUP(msiof3_sync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) SH_PFC_PIN_GROUP(msiof3_rx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156) SH_PFC_PIN_GROUP(msiof3_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) SH_PFC_PIN_GROUP(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) SH_PFC_PIN_GROUP(pwm0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159) SH_PFC_PIN_GROUP(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) SH_PFC_PIN_GROUP(pwm1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) SH_PFC_PIN_GROUP(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162) SH_PFC_PIN_GROUP(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) SH_PFC_PIN_GROUP(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) SH_PFC_PIN_GROUP(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165) SH_PFC_PIN_GROUP(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) SH_PFC_PIN_GROUP(qspi_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) SH_PFC_PIN_GROUP(qspi_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168) SH_PFC_PIN_GROUP(qspi_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169) SH_PFC_PIN_GROUP(scif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) SH_PFC_PIN_GROUP(scif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) SH_PFC_PIN_GROUP(scif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) SH_PFC_PIN_GROUP(scif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) SH_PFC_PIN_GROUP(scif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) SH_PFC_PIN_GROUP(scif1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) SH_PFC_PIN_GROUP(scif1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) SH_PFC_PIN_GROUP(scif1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) SH_PFC_PIN_GROUP(scif1_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) SH_PFC_PIN_GROUP(scif1_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) SH_PFC_PIN_GROUP(scif1_clk_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) SH_PFC_PIN_GROUP(scif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) SH_PFC_PIN_GROUP(scif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185) SH_PFC_PIN_GROUP(scifa0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) SH_PFC_PIN_GROUP(scifa0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) SH_PFC_PIN_GROUP(scifa0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) SH_PFC_PIN_GROUP(scifa0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) SH_PFC_PIN_GROUP(scifa0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) SH_PFC_PIN_GROUP(scifa0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) SH_PFC_PIN_GROUP(scifa1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192) SH_PFC_PIN_GROUP(scifa1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) SH_PFC_PIN_GROUP(scifa1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194) SH_PFC_PIN_GROUP(scifa1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195) SH_PFC_PIN_GROUP(scifa1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) SH_PFC_PIN_GROUP(scifa1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) SH_PFC_PIN_GROUP(scifa1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) SH_PFC_PIN_GROUP(scifa1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) SH_PFC_PIN_GROUP(scifa1_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) SH_PFC_PIN_GROUP(scifa1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) SH_PFC_PIN_GROUP(scifa1_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) SH_PFC_PIN_GROUP(scifa1_ctrl_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) SH_PFC_PIN_GROUP(scifa2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) SH_PFC_PIN_GROUP(scifa2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) SH_PFC_PIN_GROUP(scifa2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) SH_PFC_PIN_GROUP(scifa2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) SH_PFC_PIN_GROUP(scifa2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) SH_PFC_PIN_GROUP(scifa2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) SH_PFC_PIN_GROUP(scifb0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) SH_PFC_PIN_GROUP(scifb0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211) SH_PFC_PIN_GROUP(scifb0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) SH_PFC_PIN_GROUP(scifb0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) SH_PFC_PIN_GROUP(scifb0_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214) SH_PFC_PIN_GROUP(scifb0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) SH_PFC_PIN_GROUP(scifb0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) SH_PFC_PIN_GROUP(scifb1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) SH_PFC_PIN_GROUP(scifb1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218) SH_PFC_PIN_GROUP(scifb1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) SH_PFC_PIN_GROUP(scifb1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) SH_PFC_PIN_GROUP(scifb1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) SH_PFC_PIN_GROUP(scifb1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) SH_PFC_PIN_GROUP(scifb1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) SH_PFC_PIN_GROUP(scifb1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) SH_PFC_PIN_GROUP(scifb1_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) SH_PFC_PIN_GROUP(scifb1_clk_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) SH_PFC_PIN_GROUP(scifb1_data_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) SH_PFC_PIN_GROUP(scifb1_data_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) SH_PFC_PIN_GROUP(scifb1_clk_g),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229) SH_PFC_PIN_GROUP(scifb2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) SH_PFC_PIN_GROUP(scifb2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) SH_PFC_PIN_GROUP(scifb2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) SH_PFC_PIN_GROUP(scifb2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) SH_PFC_PIN_GROUP(scifb2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234) SH_PFC_PIN_GROUP(scifb2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) SH_PFC_PIN_GROUP(scifb2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) SH_PFC_PIN_GROUP(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) SH_PFC_PIN_GROUP(sdhi2_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) SH_PFC_PIN_GROUP(sdhi2_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) SH_PFC_PIN_GROUP(sdhi3_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) SH_PFC_PIN_GROUP(sdhi3_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) SH_PFC_PIN_GROUP(sdhi3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) SH_PFC_PIN_GROUP(sdhi3_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) SH_PFC_PIN_GROUP(sdhi3_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258) SH_PFC_PIN_GROUP(ssi0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) SH_PFC_PIN_GROUP(ssi0129_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) SH_PFC_PIN_GROUP(ssi1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) SH_PFC_PIN_GROUP(ssi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) SH_PFC_PIN_GROUP(ssi2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) SH_PFC_PIN_GROUP(ssi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) SH_PFC_PIN_GROUP(ssi34_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) SH_PFC_PIN_GROUP(ssi4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) SH_PFC_PIN_GROUP(ssi4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) SH_PFC_PIN_GROUP(ssi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269) SH_PFC_PIN_GROUP(ssi5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) SH_PFC_PIN_GROUP(ssi5_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) SH_PFC_PIN_GROUP(ssi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) SH_PFC_PIN_GROUP(ssi6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273) SH_PFC_PIN_GROUP(ssi7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274) SH_PFC_PIN_GROUP(ssi7_b_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) SH_PFC_PIN_GROUP(ssi7_c_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) SH_PFC_PIN_GROUP(ssi78_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) SH_PFC_PIN_GROUP(ssi78_b_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) SH_PFC_PIN_GROUP(ssi78_c_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) SH_PFC_PIN_GROUP(ssi8_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) SH_PFC_PIN_GROUP(ssi8_b_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) SH_PFC_PIN_GROUP(ssi8_c_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) SH_PFC_PIN_GROUP(ssi9_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) SH_PFC_PIN_GROUP(ssi9_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) SH_PFC_PIN_GROUP(tpu0_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) SH_PFC_PIN_GROUP(tpu0_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) SH_PFC_PIN_GROUP(tpu0_to2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) SH_PFC_PIN_GROUP(tpu0_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) SH_PFC_PIN_GROUP(usb0_ovc_vbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) SH_PFC_PIN_GROUP(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) SH_PFC_PIN_GROUP(usb1_pwen),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292) SH_PFC_PIN_GROUP(usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) VIN_DATA_PIN_GROUP(vin0_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) VIN_DATA_PIN_GROUP(vin0_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) SH_PFC_PIN_GROUP(vin0_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) VIN_DATA_PIN_GROUP(vin0_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) VIN_DATA_PIN_GROUP(vin0_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) VIN_DATA_PIN_GROUP(vin0_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) VIN_DATA_PIN_GROUP(vin0_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) VIN_DATA_PIN_GROUP(vin0_data, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) SH_PFC_PIN_GROUP(vin0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) SH_PFC_PIN_GROUP(vin0_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) VIN_DATA_PIN_GROUP(vin1_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) VIN_DATA_PIN_GROUP(vin1_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) SH_PFC_PIN_GROUP(vin1_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) VIN_DATA_PIN_GROUP(vin1_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) VIN_DATA_PIN_GROUP(vin1_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) VIN_DATA_PIN_GROUP(vin1_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) VIN_DATA_PIN_GROUP(vin1_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) VIN_DATA_PIN_GROUP(vin1_data, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) SH_PFC_PIN_GROUP(vin1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) SH_PFC_PIN_GROUP(vin1_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) VIN_DATA_PIN_GROUP(vin2_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) SH_PFC_PIN_GROUP(vin2_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) VIN_DATA_PIN_GROUP(vin2_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) VIN_DATA_PIN_GROUP(vin2_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) VIN_DATA_PIN_GROUP(vin2_data, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) SH_PFC_PIN_GROUP(vin2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) SH_PFC_PIN_GROUP(vin2_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) SH_PFC_PIN_GROUP(vin2_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) SH_PFC_PIN_GROUP(vin2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) SH_PFC_PIN_GROUP(vin3_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) SH_PFC_PIN_GROUP(vin3_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) SH_PFC_PIN_GROUP(vin3_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) SH_PFC_PIN_GROUP(vin3_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) SH_PFC_PIN_GROUP(vin3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) .automotive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) SH_PFC_PIN_GROUP(mlb_3pin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) "audio_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) "audio_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340) "audio_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) "audio_clkout",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) "audio_clkout_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343) "audio_clkout_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) "audio_clkout_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) "avb_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) "avb_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353) "avb_gmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357) "can0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) "can0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) "can0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) "can0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) "can1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) "can1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368) static const char * const can_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) "can_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) static const char * const du_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) "du_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) "du_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) "du_clk_out_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) "du_clk_out_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) "du_sync_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) "du_sync_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) "du_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) static const char * const du0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) "du0_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) static const char * const du1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) "du1_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) static const char * const du2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) "du2_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) static const char * const eth_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) "eth_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) "eth_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) "eth_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) "eth_rmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) "hscif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404) "hscif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) "hscif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) "hscif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) "hscif0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) "hscif0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) "hscif0_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) "hscif0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411) "hscif0_ctrl_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) "hscif0_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) "hscif0_ctrl_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) "hscif0_data_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) "hscif0_ctrl_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) "hscif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) "hscif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) "hscif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) "hscif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) "hscif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) "hscif1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) "i2c0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432) "i2c1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) "i2c1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) "i2c2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) "i2c2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) "i2c2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) "i2c2_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446) "i2c3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) static const char * const iic0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) "iic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453) static const char * const iic1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454) "iic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455) "iic1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) "iic1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) static const char * const iic2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) "iic2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) "iic2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) "iic2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) "iic2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) "iic2_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) static const char * const iic3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) "iic3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) static const char * const intc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) "intc_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) "intc_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) "intc_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) "intc_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) static const char * const mlb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) "mlb_3pin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) static const char * const mmc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) "mmc0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) "mmc0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) "mmc0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) "mmc0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) static const char * const mmc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490) "mmc1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) "mmc1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) "mmc1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) "mmc1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496) static const char * const msiof0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) "msiof0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) "msiof0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) "msiof0_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) "msiof0_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) "msiof0_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502) "msiof0_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) "msiof0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) "msiof0_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505) "msiof0_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) "msiof0_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) "msiof0_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) static const char * const msiof1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) "msiof1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) "msiof1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) "msiof1_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) "msiof1_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) "msiof1_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) "msiof1_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) "msiof1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) "msiof1_ss1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) "msiof1_ss2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) "msiof1_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) "msiof1_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) static const char * const msiof2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) "msiof2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) "msiof2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) "msiof2_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528) "msiof2_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) "msiof2_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) "msiof2_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) static const char * const msiof3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534) "msiof3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) "msiof3_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) "msiof3_ss1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) "msiof3_ss2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538) "msiof3_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) "msiof3_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) "msiof3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541) "msiof3_sync_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) "msiof3_rx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) "msiof3_tx_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547) "pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) "pwm0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) "pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) "pwm1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) static const char * const pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) "pwm2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560) static const char * const pwm3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) "pwm3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) static const char * const pwm4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) "pwm4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) static const char * const pwm5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) "pwm5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572) static const char * const pwm6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573) "pwm6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) static const char * const qspi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) "qspi_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) "qspi_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) "qspi_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) "scif0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) "scif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) "scif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) "scif1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591) "scif1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) "scif1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) "scif1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) "scif1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) "scif1_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) "scif1_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) "scif1_clk_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) "scif2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) "scif2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) static const char * const scifa0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) "scifa0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) "scifa0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) "scifa0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611) "scifa0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) "scifa0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) "scifa0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) static const char * const scifa1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) "scifa1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) "scifa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619) "scifa1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) "scifa1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) "scifa1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) "scifa1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623) "scifa1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) "scifa1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) "scifa1_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) "scifa1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) "scifa1_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) "scifa1_ctrl_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) static const char * const scifa2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) "scifa2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) "scifa2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) "scifa2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) "scifa2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) "scifa2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637) "scifa2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) static const char * const scifb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) "scifb0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) "scifb0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) "scifb0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644) "scifb0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645) "scifb0_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) "scifb0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) "scifb0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) static const char * const scifb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) "scifb1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) "scifb1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) "scifb1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) "scifb1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) "scifb1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) "scifb1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) "scifb1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) "scifb1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) "scifb1_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660) "scifb1_clk_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) "scifb1_data_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) "scifb1_data_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663) "scifb1_clk_g",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) static const char * const scifb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) "scifb2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) "scifb2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669) "scifb2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) "scifb2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671) "scifb2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) "scifb2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) "scifb2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) "scif_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) "sdhi2_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) "sdhi2_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) static const char * const sdhi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) "sdhi3_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) "sdhi3_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) "sdhi3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) "sdhi3_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) "sdhi3_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) "ssi0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715) "ssi0129_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) "ssi1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) "ssi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) "ssi2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) "ssi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) "ssi34_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) "ssi4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) "ssi4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) "ssi5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) "ssi5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) "ssi5_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) "ssi6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) "ssi6_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) "ssi7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) "ssi7_b_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) "ssi7_c_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) "ssi78_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) "ssi78_b_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) "ssi78_c_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) "ssi8_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) "ssi8_b_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) "ssi8_c_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) "ssi9_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) "ssi9_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) static const char * const tpu0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) "tpu0_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) "tpu0_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) "tpu0_to2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) "tpu0_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) "usb0_ovc_vbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) static const char * const usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) "usb1_pwen",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) static const char * const usb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) "usb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) "vin0_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765) "vin0_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) "vin0_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) "vin0_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768) "vin0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) "vin0_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) "vin0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) "vin0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) "vin0_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779) "vin1_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) "vin1_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) "vin1_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) "vin1_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) "vin1_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) "vin1_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) "vin1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) "vin1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) "vin1_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) static const char * const vin2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) "vin2_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) "vin2_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) "vin2_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) "vin2_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) "vin2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799) "vin2_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) "vin2_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) "vin2_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) "vin2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) static const char * const vin3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) "vin3_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) "vin3_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) "vin3_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) "vin3_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810) "vin3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814) struct sh_pfc_function common[58];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) struct sh_pfc_function automotive[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) } pinmux_functions = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) .common = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) SH_PFC_FUNCTION(du),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) SH_PFC_FUNCTION(can_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) SH_PFC_FUNCTION(du0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) SH_PFC_FUNCTION(du1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) SH_PFC_FUNCTION(du2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) SH_PFC_FUNCTION(eth),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) SH_PFC_FUNCTION(iic0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835) SH_PFC_FUNCTION(iic1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836) SH_PFC_FUNCTION(iic2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837) SH_PFC_FUNCTION(iic3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) SH_PFC_FUNCTION(intc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) SH_PFC_FUNCTION(mmc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) SH_PFC_FUNCTION(mmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) SH_PFC_FUNCTION(msiof0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) SH_PFC_FUNCTION(msiof1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) SH_PFC_FUNCTION(msiof2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) SH_PFC_FUNCTION(msiof3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) SH_PFC_FUNCTION(pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) SH_PFC_FUNCTION(pwm3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) SH_PFC_FUNCTION(pwm4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) SH_PFC_FUNCTION(pwm5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) SH_PFC_FUNCTION(pwm6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) SH_PFC_FUNCTION(qspi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856) SH_PFC_FUNCTION(scifa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) SH_PFC_FUNCTION(scifa1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) SH_PFC_FUNCTION(scifa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) SH_PFC_FUNCTION(scifb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) SH_PFC_FUNCTION(scifb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) SH_PFC_FUNCTION(scifb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) SH_PFC_FUNCTION(sdhi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868) SH_PFC_FUNCTION(tpu0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) SH_PFC_FUNCTION(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) SH_PFC_FUNCTION(usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) SH_PFC_FUNCTION(vin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) SH_PFC_FUNCTION(vin3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) .automotive = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) SH_PFC_FUNCTION(mlb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) GP_0_31_FN, FN_IP3_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) GP_0_30_FN, FN_IP3_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) GP_0_29_FN, FN_IP3_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) GP_0_28_FN, FN_IP3_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) GP_0_27_FN, FN_IP3_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) GP_0_26_FN, FN_IP2_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) GP_0_25_FN, FN_IP2_25_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) GP_0_24_FN, FN_IP2_21_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) GP_0_23_FN, FN_IP2_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) GP_0_22_FN, FN_IP2_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) GP_0_21_FN, FN_IP2_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895) GP_0_20_FN, FN_IP2_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) GP_0_19_FN, FN_IP2_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) GP_0_18_FN, FN_IP2_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) GP_0_17_FN, FN_IP1_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) GP_0_16_FN, FN_IP1_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) GP_0_15_FN, FN_IP1_25_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) GP_0_14_FN, FN_IP1_21_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) GP_0_13_FN, FN_IP1_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) GP_0_12_FN, FN_IP1_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904) GP_0_11_FN, FN_IP1_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) GP_0_10_FN, FN_IP1_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) GP_0_9_FN, FN_IP1_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) GP_0_8_FN, FN_IP0_30_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908) GP_0_7_FN, FN_IP0_26_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) GP_0_6_FN, FN_IP0_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) GP_0_5_FN, FN_IP0_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) GP_0_4_FN, FN_IP0_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912) GP_0_3_FN, FN_IP0_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) GP_0_2_FN, FN_IP0_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) GP_0_1_FN, FN_IP0_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) GP_0_0_FN, FN_IP0_2_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920) GP_1_29_FN, FN_IP6_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) GP_1_28_FN, FN_IP6_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) GP_1_27_FN, FN_IP6_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) GP_1_26_FN, FN_IP6_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924) GP_1_25_FN, FN_IP6_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) GP_1_24_FN, FN_IP5_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) GP_1_23_FN, FN_IP5_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) GP_1_22_FN, FN_IP5_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928) GP_1_21_FN, FN_IP5_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) GP_1_20_FN, FN_IP5_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) GP_1_19_FN, FN_IP5_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) GP_1_18_FN, FN_IP5_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932) GP_1_17_FN, FN_IP5_9_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) GP_1_16_FN, FN_IP5_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) GP_1_15_FN, FN_IP5_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935) GP_1_14_FN, FN_IP4_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) GP_1_13_FN, FN_IP4_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) GP_1_12_FN, FN_IP4_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938) GP_1_11_FN, FN_IP4_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) GP_1_10_FN, FN_IP4_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) GP_1_9_FN, FN_IP4_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) GP_1_8_FN, FN_IP4_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942) GP_1_7_FN, FN_IP4_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) GP_1_6_FN, FN_IP4_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) GP_1_5_FN, FN_IP4_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) GP_1_4_FN, FN_IP3_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) GP_1_3_FN, FN_IP3_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) GP_1_2_FN, FN_IP3_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) GP_1_1_FN, FN_IP3_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) GP_1_0_FN, FN_IP3_19_18, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) GP_2_29_FN, FN_IP7_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) GP_2_28_FN, FN_IP7_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) GP_2_27_FN, FN_IP7_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) GP_2_26_FN, FN_IP7_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) GP_2_25_FN, FN_IP7_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) GP_2_24_FN, FN_IP7_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) GP_2_23_FN, FN_IP6_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) GP_2_22_FN, FN_IP6_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) GP_2_21_FN, FN_IP6_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) GP_2_20_FN, FN_IP6_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) GP_2_19_FN, FN_IP6_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) GP_2_18_FN, FN_IP6_16_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) GP_2_16_FN, FN_IP8_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) GP_2_15_FN, FN_IP8_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) GP_2_14_FN, FN_IP8_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) GP_2_13_FN, FN_IP8_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) GP_2_12_FN, FN_IP8_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) GP_2_11_FN, FN_IP8_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) GP_2_10_FN, FN_IP8_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) GP_2_9_FN, FN_IP8_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) GP_2_8_FN, FN_IP8_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) GP_2_7_FN, FN_IP8_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) GP_2_6_FN, FN_IP8_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) GP_2_5_FN, FN_IP8_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) GP_2_4_FN, FN_IP8_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) GP_2_3_FN, FN_IP8_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) GP_2_2_FN, FN_IP8_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) GP_2_1_FN, FN_IP7_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) GP_2_0_FN, FN_IP7_28_27 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) GP_3_31_FN, FN_IP11_21_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) GP_3_30_FN, FN_IP11_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) GP_3_29_FN, FN_IP11_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) GP_3_28_FN, FN_IP11_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) GP_3_27_FN, FN_IP11_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) GP_3_26_FN, FN_IP11_8_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) GP_3_25_FN, FN_IP11_6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) GP_3_24_FN, FN_IP11_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) GP_3_23_FN, FN_IP11_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) GP_3_22_FN, FN_IP10_29_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) GP_3_21_FN, FN_IP10_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) GP_3_20_FN, FN_IP10_22_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) GP_3_19_FN, FN_IP10_18_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) GP_3_18_FN, FN_IP10_14_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) GP_3_17_FN, FN_IP10_10_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) GP_3_16_FN, FN_IP10_6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) GP_3_15_FN, FN_IP10_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) GP_3_14_FN, FN_IP9_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) GP_3_13_FN, FN_IP9_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) GP_3_12_FN, FN_IP9_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) GP_3_11_FN, FN_IP9_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) GP_3_10_FN, FN_IP9_21_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) GP_3_9_FN, FN_IP9_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) GP_3_8_FN, FN_IP9_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) GP_3_7_FN, FN_IP9_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) GP_3_6_FN, FN_IP9_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) GP_3_5_FN, FN_IP9_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) GP_3_4_FN, FN_IP9_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) GP_3_3_FN, FN_IP9_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) GP_3_2_FN, FN_IP9_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) GP_3_1_FN, FN_IP8_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) GP_3_0_FN, FN_IP8_28 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) GP_4_31_FN, FN_IP14_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) GP_4_30_FN, FN_IP14_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) GP_4_29_FN, FN_IP14_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) GP_4_28_FN, FN_IP14_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) GP_4_27_FN, FN_IP14_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) GP_4_26_FN, FN_IP14_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) GP_4_25_FN, FN_IP13_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) GP_4_24_FN, FN_IP13_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) GP_4_23_FN, FN_IP13_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) GP_4_22_FN, FN_IP13_22_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) GP_4_21_FN, FN_IP13_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) GP_4_20_FN, FN_IP13_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) GP_4_19_FN, FN_IP13_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) GP_4_18_FN, FN_IP13_9_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) GP_4_17_FN, FN_IP13_6_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) GP_4_16_FN, FN_IP13_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) GP_4_15_FN, FN_IP12_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) GP_4_14_FN, FN_IP12_27_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) GP_4_13_FN, FN_IP12_24_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) GP_4_12_FN, FN_IP12_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) GP_4_11_FN, FN_IP12_19_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) GP_4_10_FN, FN_IP12_16_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) GP_4_9_FN, FN_IP12_13_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) GP_4_8_FN, FN_IP12_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) GP_4_7_FN, FN_IP12_7_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) GP_4_6_FN, FN_IP12_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) GP_4_5_FN, FN_IP12_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) GP_4_4_FN, FN_IP12_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) GP_4_3_FN, FN_IP11_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) GP_4_2_FN, FN_IP11_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) GP_4_1_FN, FN_IP11_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) GP_4_0_FN, FN_IP11_23_22 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) GP_5_31_FN, FN_IP7_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) GP_5_30_FN, FN_IP7_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) GP_5_29_FN, FN_IP7_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) GP_5_28_FN, FN_DU_DOTCLKIN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) GP_5_27_FN, FN_IP7_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) GP_5_26_FN, FN_DU_DOTCLKIN0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) GP_5_25_FN, FN_AVS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) GP_5_24_FN, FN_AVS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) GP_5_23_FN, FN_USB2_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) GP_5_22_FN, FN_USB2_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) GP_5_21_FN, FN_IP16_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) GP_5_20_FN, FN_IP16_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) GP_5_19_FN, FN_USB0_OVC_VBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) GP_5_18_FN, FN_USB0_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) GP_5_17_FN, FN_IP16_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) GP_5_16_FN, FN_IP16_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) GP_5_15_FN, FN_IP15_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) GP_5_14_FN, FN_IP15_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) GP_5_13_FN, FN_IP15_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) GP_5_12_FN, FN_IP15_22_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) GP_5_11_FN, FN_IP15_19_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) GP_5_10_FN, FN_IP15_17_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) GP_5_9_FN, FN_IP15_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) GP_5_8_FN, FN_IP15_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) GP_5_7_FN, FN_IP15_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) GP_5_6_FN, FN_IP15_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) GP_5_5_FN, FN_IP15_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) GP_5_4_FN, FN_IP15_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) GP_5_3_FN, FN_IP14_30_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) GP_5_2_FN, FN_IP14_27_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) GP_5_1_FN, FN_IP14_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) GP_5_0_FN, FN_IP14_21_19 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) GROUP(1, 4, 4, 3, 4, 4, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) /* IP0_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) /* IP0_30_27 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) /* IP0_26_23 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) /* IP0_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) FN_I2C2_SCL_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) /* IP0_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) /* IP0_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) /* IP0_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) /* IP0_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) /* IP0_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) /* IP0_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) GROUP(2, 2, 2, 4, 4, 3, 3, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) /* IP1_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) /* IP1_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) FN_A1, FN_PWM4, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) /* IP1_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) FN_A0, FN_PWM3, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) /* IP1_25_22 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) /* IP1_21_18 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) /* IP1_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143) FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) /* IP1_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) /* IP1_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153) /* IP1_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) /* IP1_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163) GROUP(3, 3, 4, 4, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) /* IP2_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) /* IP2_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) /* IP2_25_22 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) /* IP2_21_18 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) /* IP2_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) /* IP2_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) /* IP2_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) /* IP2_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) /* IP2_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) /* IP2_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) GROUP(3, 3, 3, 3, 2, 3, 3, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) /* IP3_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) /* IP3_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) /* IP3_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) /* IP3_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) /* IP3_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) FN_A16, FN_ATAWR1_N, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) /* IP3_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) /* IP3_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) /* IP3_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) /* IP3_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) /* IP3_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) GROUP(2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) /* IP4_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) /* IP4_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) /* IP4_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237) /* IP4_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) /* IP4_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) /* IP4_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) /* IP4_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) FN_VI2_FIELD_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) /* IP4_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) FN_VI2_CLKENB_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) /* IP4_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) /* IP4_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) /* IP4_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) GROUP(2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) /* IP5_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) /* IP5_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268) /* IP5_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) FN_MSIOF0_SCK_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) /* IP5_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) /* IP5_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276) FN_WE0_N, FN_IECLK, FN_CAN_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) /* IP5_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) FN_INTC_IRQ4_N, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281) /* IP5_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) /* IP5_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284) FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) /* IP5_9_6 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) /* IP5_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) FN_INTC_EN0_N, FN_I2C1_SCL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294) /* IP5_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) FN_VI2_R3, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298) { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) GROUP(3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) /* IP6_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302) FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) /* IP6_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) FN_ETH_LINK, 0, FN_HTX0_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306) FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) /* IP6_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310) /* IP6_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) /* IP6_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314) FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) /* IP6_16_14 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318) FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) FN_I2C2_SCL_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) /* IP6_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322) FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) /* IP6_10_9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) /* IP6_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326) FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) FN_SSI_SDATA8_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) /* IP6_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) /* IP6_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336) GROUP(1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) /* IP7_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340) /* IP7_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) /* IP7_28_27 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344) /* IP7_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) /* IP7_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) /* IP7_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352) /* IP7_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) FN_GLO_SS_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) /* IP7_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356) FN_ETH_MDC, 0, FN_STP_ISD_1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) /* IP7_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360) FN_GLO_SCLK_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) /* IP7_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) /* IP7_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364) FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) /* IP7_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) /* IP7_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368) FN_ETH_MDIO, 0, FN_HRTS0_N_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) GROUP(1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) 2, 2, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) /* IP8_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) /* IP8_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378) FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) /* IP8_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) /* IP8_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382) FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) /* IP8_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) /* IP8_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386) FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) FN_AVB_MAGIC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) /* IP8_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390) /* IP8_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) /* IP8_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394) /* IP8_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) /* IP8_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398) /* IP8_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) /* IP8_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402) /* IP8_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) /* IP8_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406) /* IP8_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) /* IP8_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410) /* IP8_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) GROUP(4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) /* IP9_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420) /* IP9_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) /* IP9_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424) /* IP9_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) /* IP9_21_20 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428) /* IP9_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) /* IP9_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432) /* IP9_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436) /* IP9_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440) /* IP9_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) /* IP9_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444) /* IP9_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) /* IP9_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) GROUP(2, 4, 3, 4, 4, 4, 4, 3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452) /* IP10_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) /* IP10_29_26 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) /* IP10_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) /* IP10_22_19 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462) FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) /* IP10_18_15 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466) FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470) /* IP10_14_11 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) /* IP10_10_7 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478) FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) /* IP10_6_4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482) FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) FN_VI3_DATA0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) /* IP10_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486) FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490) GROUP(2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) /* IP11_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494) /* IP11_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) /* IP11_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) /* IP11_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) /* IP11_21_18 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504) 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) /* IP11_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508) /* IP11_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) /* IP11_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512) /* IP11_10_9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) /* IP11_8_7 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516) /* IP11_6_5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) /* IP11_4 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) FN_SD3_CLK, FN_MMC1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520) /* IP11_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) GROUP(1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528) /* IP12_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) /* IP12_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532) FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) FN_CAN_DEBUGOUT4, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) /* IP12_27_25 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) FN_SSI_SCK5, FN_SCIFB1_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536) FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) FN_CAN_DEBUGOUT3, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) /* IP12_24_23 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) FN_CAN_DEBUGOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) /* IP12_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) /* IP12_19_17 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546) FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) /* IP12_16_14 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) FN_SSI_SDATA3, FN_STP_ISCLK_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550) /* IP12_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) FN_CAN_STEP0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) /* IP12_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554) FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) /* IP12_7_6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558) /* IP12_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) /* IP12_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562) /* IP12_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566) GROUP(1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) /* IP13_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570) /* IP13_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) /* IP13_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574) FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) /* IP13_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578) /* IP13_22_19 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) /* IP13_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) /* IP13_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588) /* IP13_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) FN_CAN_DEBUGOUT8, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) /* IP13_9_7 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592) FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) /* IP13_6_3 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596) FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) /* IP13_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600) FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) GROUP(1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) /* IP14_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) /* IP14_30_28 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608) FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) FN_HRTS0_N_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) /* IP14_27_25 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612) FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) /* IP14_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616) FN_LCDOUT9, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) /* IP14_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620) /* IP14_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) /* IP14_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) /* IP14_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) /* IP14_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633) /* IP14_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) /* IP14_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) FN_REMOCON, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) GROUP(2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) /* IP15_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) /* IP15_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) /* IP15_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650) /* IP15_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) /* IP15_22_20 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) /* IP15_19_18 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) /* IP15_17_16 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) /* IP15_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) /* IP15_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) /* IP15_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) /* IP15_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) FN_IIC2_SDA, FN_I2C2_SDA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) /* IP15_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) FN_IIC2_SCL, FN_I2C2_SCL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) /* IP15_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) FN_LCDOUT15, FN_SCIF_CLK_B, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) GROUP(4, 4, 4, 4, 4, 4, 1, 1, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) /* IP16_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) /* IP16_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) /* IP16_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689) /* IP16_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) /* IP16_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) /* IP16_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) /* IP16_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) FN_USB1_OVC, FN_TCLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) /* IP16_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) /* IP16_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703) FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) /* IP16_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) GROUP(3, 2, 2, 3, 2, 1, 1, 1, 2, 1, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) 1, 1, 1, 2, 1, 1, 2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) /* SEL_SCIF1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) FN_SEL_SCIF1_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) /* SEL_SCIFB [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718) /* SEL_SCIFB2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) /* SEL_SCIFB1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) FN_SEL_SCIFB1_6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) /* SEL_SCIFA1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725) FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) FN_SEL_SCIFA1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727) /* SEL_SCIF0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) /* SEL_SCIFA [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) FN_SEL_SCFA_0, FN_SEL_SCFA_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) /* SEL_SOF1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) FN_SEL_SOF1_0, FN_SEL_SOF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) /* SEL_SSI7 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) /* SEL_SSI6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) FN_SEL_SSI6_0, FN_SEL_SSI6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) /* SEL_SSI5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) /* SEL_VI3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) FN_SEL_VI3_0, FN_SEL_VI3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) /* SEL_VI2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) FN_SEL_VI2_0, FN_SEL_VI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) /* SEL_VI1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) FN_SEL_VI1_0, FN_SEL_VI1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745) /* SEL_VI0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) FN_SEL_VI0_0, FN_SEL_VI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) /* SEL_TSIF1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) /* SEL_LBS [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) FN_SEL_LBS_0, FN_SEL_LBS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) /* SEL_TSIF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) /* SEL_SOF3 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) FN_SEL_SOF3_0, FN_SEL_SOF3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) /* SEL_SOF0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) FN_SEL_SOF0_0, FN_SEL_SOF0_1, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761) GROUP(3, 1, 1, 1, 2, 1, 2, 1, 2, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) 3, 3, 2, 3, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) /* RESERVED [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) /* SEL_TMU1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) FN_SEL_TMU1_0, FN_SEL_TMU1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) /* SEL_HSCIF1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) /* SEL_SCIFCLK [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) /* SEL_CAN0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774) /* SEL_CANCLK [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) /* SEL_SCIFA2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) /* SEL_CAN1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) FN_SEL_CAN1_0, FN_SEL_CAN1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) /* SEL_SCIF2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784) /* SEL_ADI [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) FN_SEL_ADI_0, FN_SEL_ADI_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) /* SEL_SSP [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) FN_SEL_SSP_0, FN_SEL_SSP_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) /* SEL_FM [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) /* SEL_HSCIF0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) /* SEL_GPS [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) /* RESERVED [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798) /* SEL_SIM [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) /* SEL_SSI8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) GROUP(1, 1, 2, 4, 4, 2, 2, 4, 2, 3, 2, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) /* SEL_IICDVFS [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) /* SEL_IIC0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) FN_SEL_IIC0_0, FN_SEL_IIC0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) /* RESERVED [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) /* RESERVED [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820) /* SEL_IEB [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822) /* RESERVED [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) /* SEL_IIC2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) FN_SEL_IIC2_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) /* SEL_IIC1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) /* SEL_I2C2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) FN_SEL_I2C2_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) /* SEL_I2C1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) static int r8a7790_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) if (pin < RCAR_GP_PIN(3, 0) || pin > RCAR_GP_PIN(3, 31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) *pocctrl = 0xe606008c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) return 31 - (pin & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) static const struct soc_device_attribute r8a7790_tdsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) { .soc_id = "r8a7790", .revision = "ES1.0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856) static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) /* Initialize TDSEL on old revisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) if (soc_device_match(r8a7790_tdsel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) sh_pfc_write(pfc, 0xe6060088, 0x00155554);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) static const struct sh_pfc_soc_operations r8a7790_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) .init = r8a7790_pinmux_soc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) .pin_to_pocctrl = r8a7790_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) #ifdef CONFIG_PINCTRL_PFC_R8A7742
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) const struct sh_pfc_soc_info r8a7742_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) .name = "r8a77420_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) .ops = &r8a7790_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) .nr_groups = ARRAY_SIZE(pinmux_groups.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) .nr_functions = ARRAY_SIZE(pinmux_functions.common),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) #ifdef CONFIG_PINCTRL_PFC_R8A7790
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893) const struct sh_pfc_soc_info r8a7790_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) .name = "r8a77900_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) .ops = &r8a7790_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) .groups = pinmux_groups.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) .nr_groups = ARRAY_SIZE(pinmux_groups.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) ARRAY_SIZE(pinmux_groups.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) .functions = pinmux_functions.common,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) .nr_functions = ARRAY_SIZE(pinmux_functions.common) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) ARRAY_SIZE(pinmux_functions.automotive),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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