^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * r8a7778 processor support - PFC hardware block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2013 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2013 Cogent Embedded, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2015 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2011 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2011 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PORT_GP_PUP_1(bank, pin, fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_CFG_1(bank, pin, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_CFG_32(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_GP_CFG_32(3, fn, sfx, SH_PFC_PIN_CFG_PULL_UP), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PORT_GP_CFG_27(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CPU_ALL_NOGP(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PIN_NOGP(CLKOUT, "B25", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PIN_NOGP(CS0, "A20", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PIN_NOGP(CS1_A26, "C20", fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FN_IP0_1_0, FN_PENC0, FN_PENC1, FN_IP0_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FN_IP0_7_5, FN_IP0_11_8, FN_IP0_14_12, FN_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) FN_A2, FN_A3, FN_IP0_15, FN_IP0_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) FN_IP0_17, FN_IP0_18, FN_IP0_19, FN_IP0_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FN_IP0_21, FN_IP0_22, FN_IP0_23, FN_IP0_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FN_IP0_25, FN_IP0_26, FN_IP0_27, FN_IP0_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FN_IP0_29, FN_IP0_30, FN_IP1_0, FN_IP1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FN_IP1_4_2, FN_IP1_7_5, FN_IP1_10_8, FN_IP1_14_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FN_IP1_23_21, FN_WE0, FN_IP1_24, FN_IP1_27_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) FN_IP2_11_9, FN_IP2_13_12, FN_IP2_16_14, FN_IP2_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) FN_IP2_30, FN_IP2_31, FN_IP3_1_0, FN_IP3_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FN_IP3_7_5, FN_IP3_9_8, FN_IP3_12_10, FN_IP3_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FN_IP3_18_16, FN_IP3_20_19, FN_IP3_23_21, FN_IP3_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FN_IP3_27, FN_IP3_28, FN_IP3_29, FN_IP3_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FN_IP3_31, FN_IP4_0, FN_IP4_3_1, FN_IP4_6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FN_IP4_7, FN_IP4_8, FN_IP4_10_9, FN_IP4_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FN_IP4_14_13, FN_IP4_16_15, FN_IP4_20_17, FN_IP4_24_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FN_IP4_26_25, FN_IP4_28_27, FN_IP4_30_29, FN_IP5_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FN_IP5_3_2, FN_IP5_5_4, FN_IP5_6, FN_IP5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FN_IP5_9_8, FN_IP5_11_10, FN_IP5_12, FN_IP5_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) FN_IP5_17_15, FN_IP5_20_18, FN_AUDIO_CLKA, FN_AUDIO_CLKB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FN_IP5_22_21, FN_IP5_25_23, FN_IP5_28_26, FN_IP5_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FN_IP6_1_0, FN_IP6_4_2, FN_IP6_6_5, FN_IP6_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FN_IP6_8, FN_IP6_9, FN_SSI_SCK34, FN_IP6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FN_IP6_12_11, FN_IP6_13, FN_IP6_15_14, FN_IP6_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FN_IP6_18_17, FN_IP6_20_19, FN_IP6_21, FN_IP6_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FN_IP6_25_24, FN_IP6_27_26, FN_IP6_29_28, FN_IP6_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_IP7_1_0, FN_IP7_3_2, FN_IP7_5_4, FN_IP7_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FN_IP7_21, FN_IP7_24_22, FN_IP7_28_25, FN_IP7_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) FN_IP8_13_11, FN_IP8_15_14, FN_IP8_18_16, FN_IP8_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FN_IP8_23_22, FN_IP8_26_24, FN_IP8_29_27, FN_IP9_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FN_IP9_5_3, FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_IP9_17_15, FN_IP9_20_18, FN_IP9_23_21, FN_IP9_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_IP9_29_27, FN_IP10_2_0, FN_IP10_5_3, FN_IP10_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FN_IP10_12_9, FN_IP10_15_13, FN_IP10_18_16, FN_IP10_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FN_IP10_24_22, FN_AVS1, FN_AVS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_PRESETOUT, FN_PWM1, FN_AUDATA0, FN_ARM_TRACEDATA_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FN_GPSCLK_C, FN_USB_OVC0, FN_TX2_E, FN_SDA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FN_USB_OVC1, FN_RX2_E, FN_SCL2_B, FN_SD1_DAT2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_MMC_D2, FN_BS, FN_ATADIR0_A, FN_SDSELF_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FN_PWM4_B, FN_SD1_DAT3_A, FN_MMC_D3, FN_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FN_ATAG0_A, FN_REMOCON_B, FN_A4, FN_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FN_A6, FN_A7, FN_A8, FN_A9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FN_A10, FN_A11, FN_A12, FN_A13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FN_A14, FN_A15, FN_A16, FN_A17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FN_A18, FN_A19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_A20, FN_HSPI_CS1_B, FN_A21, FN_HSPI_CLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_TS_SDEN0_A, FN_SD1_CD_A, FN_MMC_D6, FN_A24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_DREQ1_A, FN_HRX0_B, FN_TS_SPSYNC0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_SD1_WP_A, FN_MMC_D7, FN_A25, FN_DACK1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FN_HCTS0_B, FN_RX3_C, FN_TS_SDAT0_A, FN_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FN_HSPI_TX1_B, FN_PWM0_B, FN_CS0, FN_HSPI_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FN_SCK2_B, FN_MMC_D5, FN_ATADIR0_B, FN_RD_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_WE1, FN_ATAWR0_B, FN_SSI_WS1_B, FN_EX_CS0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FN_SCL2_A, FN_TX3_C, FN_TS_SCK0_A, FN_EX_CS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FN_MMC_D4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FN_SD1_CLK_A, FN_MMC_CLK, FN_ATACS00, FN_EX_CS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_SD1_CMD_A, FN_MMC_CMD, FN_ATACS10, FN_EX_CS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FN_SD1_DAT0_A, FN_MMC_D0, FN_ATARD0, FN_EX_CS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FN_EX_WAIT1_A, FN_SD1_DAT1_A, FN_MMC_D1, FN_ATAWR0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_EX_CS5, FN_EX_WAIT2_A, FN_DREQ0_A, FN_RX3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FN_DACK0, FN_TX3_A, FN_DRACK0, FN_EX_WAIT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) FN_PWM0_C, FN_D0, FN_D1, FN_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) FN_D3, FN_D4, FN_D5, FN_D6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FN_D7, FN_D8, FN_D9, FN_D10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FN_D11, FN_RD_WR_B, FN_IRQ0, FN_MLB_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FN_IRQ1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FN_SDSELF_B, FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) FN_CAN_CLK_B, FN_SDA3_B, FN_SD1_CLK_B, FN_HTX0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) FN_TX0_A, FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, FN_SD1_DAT3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FN_HRTS0_A, FN_RTS0, FN_SSI_SCK4, FN_DU0_DR0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FN_LCDOUT0, FN_AUDATA2, FN_ARM_TRACEDATA_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B, FN_SSI_WS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3, FN_ARM_TRACEDATA_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FN_DU0_DR2, FN_LCDOUT2, FN_DU0_DR3, FN_LCDOUT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) FN_DU0_DR4, FN_LCDOUT4, FN_DU0_DR5, FN_LCDOUT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) FN_DU0_DR6, FN_LCDOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FN_DU0_DR7, FN_LCDOUT7, FN_DU0_DG0, FN_LCDOUT8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FN_AUDATA4, FN_ARM_TRACEDATA_4, FN_TX1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FN_CAN0_TX_A, FN_ADICHS0, FN_DU0_DG1, FN_LCDOUT9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FN_AUDATA5, FN_ARM_TRACEDATA_5, FN_RX1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FN_CAN0_RX_A, FN_ADIDATA, FN_DU0_DG2, FN_LCDOUT10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FN_DU0_DG3, FN_LCDOUT11, FN_DU0_DG4, FN_LCDOUT12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FN_RX0_B, FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, FN_DU0_DG7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FN_LCDOUT15, FN_TX4_A, FN_SSI_SCK2_B, FN_VI0_R0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FN_DU0_DB0, FN_LCDOUT16, FN_AUDATA6, FN_ARM_TRACEDATA_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FN_GPSCLK_A, FN_PWM0_A, FN_ADICLK, FN_TS_SDAT0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FN_ADICS_SAMP, FN_TS_SCK0_B, FN_VI0_R2_B, FN_DU0_DB2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FN_LCDOUT18, FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, FN_VI1_DATA10_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FN_DU0_DB6, FN_LCDOUT22, FN_VI1_DATA11_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FN_DU0_DB7, FN_LCDOUT23, FN_DU0_DOTCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FN_QSTVA_QVS, FN_DU0_DOTCLKO_UT0, FN_QCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE, FN_AUDIO_CLKOUT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FN_REMOCON_C, FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FN_QSTH_QHS, FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FN_QCPV_QDE, FN_FMCLK_D, FN_SSI_SCK1_A, FN_DU0_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FN_QPOLA, FN_AUDCK, FN_ARM_TRACECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FN_BPFCLK_D, FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FN_AUDSYNC, FN_ARM_TRACECTL, FN_FMIN_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FN_CAN_CLK_D, FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FN_TX2_A, FN_CAN0_TX_B, FN_SSI_SDATA7, FN_HSPI_TX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FN_RX2_A, FN_CAN0_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) FN_SSI_SCK6, FN_HSPI_RX2_A, FN_FMCLK_B, FN_CAN1_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FN_SSI_WS6, FN_HSPI_CLK2_A, FN_BPFCLK_B, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FN_SSI_SDATA6, FN_HSPI_TX2_A, FN_FMIN_B, FN_SSI_SCK5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FN_RX4_C, FN_SSI_WS5, FN_TX4_C, FN_SSI_SDATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FN_RX0_D, FN_SSI_WS34, FN_ARM_TRACEDATA_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FN_SSI_SDATA4, FN_SSI_WS2_A, FN_ARM_TRACEDATA_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FN_TX0_D, FN_SSI_WS012, FN_ARM_TRACEDATA_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) FN_SSI_SDATA2, FN_HSPI_CS2_A, FN_ARM_TRACEDATA_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) FN_SDA1_A, FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FN_SCL1_A, FN_SCK2_A, FN_SSI_SDATA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FN_ARM_TRACEDATA_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FN_SD0_CLK, FN_SUB_TDO, FN_SD0_CMD, FN_SUB_TRST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FN_SD0_DAT0, FN_SUB_TMS, FN_SD0_DAT1, FN_SUB_TCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FN_SD0_DAT2, FN_SUB_TDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FN_SD0_DAT3, FN_IRQ1_B, FN_SD0_CD, FN_TX5_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) FN_SD0_WP, FN_RX5_A, FN_VI1_CLKENB, FN_HSPI_CLK0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) FN_HTX1_A, FN_RTS1_C, FN_VI1_FIELD, FN_HSPI_CS0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FN_HRX1_A, FN_SCK1_C, FN_VI1_HSYNC, FN_HSPI_RX0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FN_HRTS1_A, FN_FMCLK_A, FN_RX1_C, FN_VI1_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A, FN_TX1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, FN_IRQ2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FN_CTS1_C, FN_SPEEDIN, FN_VI0_CLK, FN_CAN_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FN_HSPI_RX1_A, FN_RX4_B, FN_VI0_FIELD, FN_SD2_DAT3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FN_VI0_R3_C, FN_VI1_DATA1, FN_DU1_DG7, FN_HSPI_CLK1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) FN_TX4_B, FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) FN_DU1_DR2, FN_HSPI_CS1_A, FN_RX3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FN_HSPI_TX1_A, FN_TX3_B, FN_VI0_DATA0_VI0_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D, FN_VI0_DATA1_VI0_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D, FN_VI0_DATA2_VI0_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FN_DU1_DG4, FN_RX0_C, FN_VI0_DATA3_VI0_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FN_DU1_DG5, FN_TX1_A, FN_TX0_C, FN_VI0_DATA4_VI0_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) FN_DU1_DB2, FN_RX1_A, FN_VI0_DATA5_VI0_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) FN_DU1_DB3, FN_SCK1_A, FN_PWM4, FN_HSCK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FN_VI0_DATA6_VI0_G0, FN_DU1_DB4, FN_CTS1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FN_PWM5, FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FN_RTS1_A, FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FN_DU1_DR4, FN_HTX1_B, FN_VI0_G3, FN_SD2_CMD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FN_VI1_DATA5, FN_DU1_DR5, FN_HRX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) FN_HRTS1_B, FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) FN_DU1_DR7, FN_HCTS1_B, FN_VI0_R0_A, FN_VI1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FN_ETH_REF_CLK, FN_DU1_DOTCLKIN, FN_VI0_R1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0, FN_PWM2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FN_TCLK1, FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FN_ETH_TXD1, FN_PWM3, FN_VI0_R3_A, FN_ETH_CRS_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FN_IECLK, FN_SCK2_C, FN_VI0_R4_A, FN_ETH_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FN_IETX, FN_TX2_C, FN_VI0_R5_A, FN_ETH_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FN_FMCLK_C, FN_IERX, FN_RX2_C, FN_VI1_DATA10_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FN_DU1_DOTCLKOUT, FN_ETH_RXD0, FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) FN_TX2_D, FN_SDA2_C, FN_VI1_DATA11_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) FN_DU1_EXHSYNC_DU1_HSYNC, FN_ETH_RXD1, FN_FMIN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FN_RX2_D, FN_SCL2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC, FN_ATARD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) FN_ETH_MDC, FN_SDA1_B, FN_SD2_CMD_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_ATAWR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FN_ETH_MDIO, FN_SCL1_B, FN_SD2_DAT0_A, FN_DU1_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FN_ATACS01, FN_DREQ1_B, FN_ETH_LINK, FN_CAN1_RX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) FN_ETH_MAGIC, FN_CAN1_TX_A, FN_PWM6, FN_SD2_DAT2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1, FN_HSPI_CLK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FN_GPSCLK_B, FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FN_ATAG1, FN_HSPI_CS2_B, FN_GPSIN_B, FN_SD2_CD_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B, FN_HSPI_RX2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FN_REMOCON_A, FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FN_DACK0_B, FN_HSPI_TX2_B, FN_CAN_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FN_SEL_SSI2_A, FN_SEL_SSI2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FN_SEL_SSI1_A, FN_SEL_SSI1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FN_SEL_VI1_A, FN_SEL_VI1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FN_SEL_VI0_A, FN_SEL_VI0_B, FN_SEL_VI0_C, FN_SEL_VI0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) FN_SEL_SD2_A, FN_SEL_SD2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FN_SEL_SD1_A, FN_SEL_SD1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FN_SEL_IRQ2_A, FN_SEL_IRQ2_B, FN_SEL_IRQ2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) FN_SEL_CAN1_A, FN_SEL_CAN1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) FN_SEL_CAN0_A, FN_SEL_CAN0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FN_SEL_REMOCON_A, FN_SEL_REMOCON_B, FN_SEL_REMOCON_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FN_SEL_FM_A, FN_SEL_FM_B, FN_SEL_FM_C, FN_SEL_FM_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FN_SEL_GPS_A, FN_SEL_GPS_B, FN_SEL_GPS_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FN_SEL_I2C3_A, FN_SEL_I2C3_B, FN_SEL_I2C3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FN_SEL_I2C2_A, FN_SEL_I2C2_B, FN_SEL_I2C2_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FN_SEL_I2C1_A, FN_SEL_I2C1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PENC0_MARK, PENC1_MARK, A1_MARK, A2_MARK, A3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) WE0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) AUDIO_CLKA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) AUDIO_CLKB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) SSI_SCK34_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) AVS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) AVS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) VI0_R0_C_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) VI0_R1_C_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) VI0_R2_C_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* VI0_R3_C_MARK, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) VI0_R4_C_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) VI0_R5_C_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) VI0_R0_D_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) VI0_R1_D_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) VI0_R2_D_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) VI0_R3_D_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) VI0_R4_D_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) VI0_R5_D_MARK, /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PRESETOUT_MARK, PWM1_MARK, AUDATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ARM_TRACEDATA_0_MARK, GPSCLK_C_MARK, USB_OVC0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) TX2_E_MARK, SDA2_B_MARK, AUDATA1_MARK, ARM_TRACEDATA_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) GPSIN_C_MARK, USB_OVC1_MARK, RX2_E_MARK, SCL2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SD1_DAT2_A_MARK, MMC_D2_MARK, BS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ATADIR0_A_MARK, SDSELF_A_MARK, PWM4_B_MARK, SD1_DAT3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MMC_D3_MARK, A0_MARK, ATAG0_A_MARK, REMOCON_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) A4_MARK, A5_MARK, A6_MARK, A7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) A8_MARK, A9_MARK, A10_MARK, A11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) A12_MARK, A13_MARK, A14_MARK, A15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) A16_MARK, A17_MARK, A18_MARK, A19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) A20_MARK, HSPI_CS1_B_MARK, A21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) HSPI_CLK1_B_MARK, A22_MARK, HRTS0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) RX2_B_MARK, DREQ2_A_MARK, A23_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) TX2_B_MARK, DACK2_A_MARK, TS_SDEN0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SD1_CD_A_MARK, MMC_D6_MARK, A24_MARK, DREQ1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) HRX0_B_MARK, TS_SPSYNC0_A_MARK, SD1_WP_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MMC_D7_MARK, A25_MARK, DACK1_A_MARK, HCTS0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) RX3_C_MARK, TS_SDAT0_A_MARK, CLKOUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) HSPI_TX1_B_MARK, PWM0_B_MARK, CS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) HSPI_RX1_B_MARK, SSI_SCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ATAG0_B_MARK, CS1_A26_MARK, SDA2_A_MARK, SCK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MMC_D5_MARK, ATADIR0_B_MARK, RD_WR_MARK, WE1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ATAWR0_B_MARK, SSI_WS1_B_MARK, EX_CS0_MARK, SCL2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) TX3_C_MARK, TS_SCK0_A_MARK, EX_CS1_MARK, MMC_D4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) SD1_CLK_A_MARK, MMC_CLK_MARK, ATACS00_MARK, EX_CS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SD1_CMD_A_MARK, MMC_CMD_MARK, ATACS10_MARK, EX_CS3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) SD1_DAT0_A_MARK, MMC_D0_MARK, ATARD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) EX_CS4_MARK, EX_WAIT1_A_MARK, SD1_DAT1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MMC_D1_MARK, ATAWR0_A_MARK, EX_CS5_MARK, EX_WAIT2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DREQ0_A_MARK, RX3_A_MARK, DACK0_MARK, TX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DRACK0_MARK, EX_WAIT0_MARK, PWM0_C_MARK, D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) D1_MARK, D2_MARK, D3_MARK, D4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) D5_MARK, D6_MARK, D7_MARK, D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) D9_MARK, D10_MARK, D11_MARK, RD_WR_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) IRQ0_MARK, MLB_CLK_MARK, IRQ1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) MLB_SIG_MARK, RX5_B_MARK, SDA3_A_MARK, IRQ2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MLB_DAT_MARK, TX5_B_MARK, SCL3_A_MARK, IRQ3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) SDSELF_B_MARK, SD1_CMD_B_MARK, SCIF_CLK_MARK, AUDIO_CLKOUT_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) CAN_CLK_B_MARK, SDA3_B_MARK, SD1_CLK_B_MARK, HTX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) TX0_A_MARK, SD1_DAT0_B_MARK, HRX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) RX0_A_MARK, SD1_DAT1_B_MARK, HSCK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) SCK0_MARK, SCL3_B_MARK, SD1_DAT2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) HCTS0_A_MARK, CTS0_MARK, SD1_DAT3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) HRTS0_A_MARK, RTS0_MARK, SSI_SCK4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DU0_DR0_MARK, LCDOUT0_MARK, AUDATA2_MARK, ARM_TRACEDATA_2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SDA3_C_MARK, ADICHS1_MARK, TS_SDEN0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) SSI_WS4_MARK, DU0_DR1_MARK, LCDOUT1_MARK, AUDATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ARM_TRACEDATA_3_MARK, SCL3_C_MARK, ADICHS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) TS_SPSYNC0_B_MARK, DU0_DR2_MARK, LCDOUT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DU0_DR3_MARK, LCDOUT3_MARK, DU0_DR4_MARK, LCDOUT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DU0_DR5_MARK, LCDOUT5_MARK, DU0_DR6_MARK, LCDOUT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DU0_DR7_MARK, LCDOUT7_MARK, DU0_DG0_MARK, LCDOUT8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) AUDATA4_MARK, ARM_TRACEDATA_4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) TX1_D_MARK, CAN0_TX_A_MARK, ADICHS0_MARK, DU0_DG1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) LCDOUT9_MARK, AUDATA5_MARK, ARM_TRACEDATA_5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) RX1_D_MARK, CAN0_RX_A_MARK, ADIDATA_MARK, DU0_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) LCDOUT10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, DU0_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) LCDOUT12_MARK, RX0_B_MARK, DU0_DG5_MARK, LCDOUT13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) TX0_B_MARK, DU0_DG6_MARK, LCDOUT14_MARK, RX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DU0_DG7_MARK, LCDOUT15_MARK, TX4_A_MARK, SSI_SCK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) VI0_R0_B_MARK, DU0_DB0_MARK, LCDOUT16_MARK, AUDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ARM_TRACEDATA_6_MARK, GPSCLK_A_MARK, PWM0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ADICLK_MARK, TS_SDAT0_B_MARK, AUDIO_CLKC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) VI0_R1_B_MARK, DU0_DB1_MARK, LCDOUT17_MARK, AUDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ARM_TRACEDATA_7_MARK, GPSIN_A_MARK, ADICS_SAMP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) TS_SCK0_B_MARK, VI0_R2_B_MARK, DU0_DB2_MARK, LCDOUT18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) VI0_R3_B_MARK, DU0_DB3_MARK, LCDOUT19_MARK, VI0_R4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DU0_DB4_MARK, LCDOUT20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) VI0_R5_B_MARK, DU0_DB5_MARK, LCDOUT21_MARK, VI1_DATA10_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DU0_DB6_MARK, LCDOUT22_MARK, VI1_DATA11_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DU0_DB7_MARK, LCDOUT23_MARK, DU0_DOTCLKIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) QCLK_MARK, DU0_DOTCLKO_UT1_MARK, QSTVB_QVE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) AUDIO_CLKOUT_A_MARK, REMOCON_C_MARK, SSI_WS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) QCPV_QDE_MARK, FMCLK_D_MARK, SSI_SCK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DU0_DISP_MARK, QPOLA_MARK, AUDCK_MARK, ARM_TRACECLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) BPFCLK_D_MARK, SSI_WS1_A_MARK, DU0_CDE_MARK, QPOLB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) AUDSYNC_MARK, ARM_TRACECTL_MARK, FMIN_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) SD1_CD_B_MARK, SSI_SCK78_MARK, HSPI_RX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) TX1_B_MARK, SD1_WP_B_MARK, SSI_WS78_MARK, HSPI_CLK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) RX1_B_MARK, CAN_CLK_D_MARK, SSI_SDATA8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) SSI_SCK2_A_MARK, HSPI_CS0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) TX2_A_MARK, CAN0_TX_B_MARK, SSI_SDATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) HSPI_TX0_B_MARK, RX2_A_MARK, CAN0_RX_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) SSI_SCK6_MARK, HSPI_RX2_A_MARK, FMCLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CAN1_TX_B_MARK, SSI_WS6_MARK, HSPI_CLK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) BPFCLK_B_MARK, CAN1_RX_B_MARK, SSI_SDATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) HSPI_TX2_A_MARK, FMIN_B_MARK, SSI_SCK5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) RX4_C_MARK, SSI_WS5_MARK, TX4_C_MARK, SSI_SDATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) RX0_D_MARK, SSI_WS34_MARK, ARM_TRACEDATA_8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SSI_SDATA4_MARK, SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SSI_SDATA3_MARK, ARM_TRACEDATA_10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SSI_SCK012_MARK, ARM_TRACEDATA_11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) TX0_D_MARK, SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) SSI_SDATA2_MARK, HSPI_CS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ARM_TRACEDATA_13_MARK, SDA1_A_MARK, SSI_SDATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ARM_TRACEDATA_14_MARK, SCL1_A_MARK, SCK2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SSI_SDATA0_MARK, ARM_TRACEDATA_15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) SD0_CLK_MARK, SUB_TDO_MARK, SD0_CMD_MARK, SUB_TRST_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) SD0_DAT0_MARK, SUB_TMS_MARK, SD0_DAT1_MARK, SUB_TCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SD0_DAT2_MARK, SUB_TDI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) SD0_DAT3_MARK, IRQ1_B_MARK, SD0_CD_MARK, TX5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) SD0_WP_MARK, RX5_A_MARK, VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) HSPI_CLK0_A_MARK, HTX1_A_MARK, RTS1_C_MARK, VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) HSPI_CS0_A_MARK, HRX1_A_MARK, SCK1_C_MARK, VI1_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) HSPI_RX0_A_MARK, HRTS1_A_MARK, FMCLK_A_MARK, RX1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) VI1_VSYNC_MARK, HSPI_TX0_MARK, HCTS1_A_MARK, BPFCLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) TX1_C_MARK, TCLK0_MARK, HSCK1_A_MARK, FMIN_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) IRQ2_C_MARK, CTS1_C_MARK, SPEEDIN_MARK, VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CAN_CLK_A_MARK, VI0_CLKENB_MARK, SD2_DAT2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) VI1_DATA0_MARK, DU1_DG6_MARK, HSPI_RX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) RX4_B_MARK, VI0_FIELD_MARK, SD2_DAT3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) VI0_R3_C_MARK, VI1_DATA1_MARK, DU1_DG7_MARK, HSPI_CLK1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) TX4_B_MARK, VI0_HSYNC_MARK, SD2_CD_B_MARK, VI1_DATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DU1_DR2_MARK, HSPI_CS1_A_MARK, RX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) VI0_VSYNC_MARK, SD2_WP_B_MARK, VI1_DATA3_MARK, DU1_DR3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) HSPI_TX1_A_MARK, TX3_B_MARK, VI0_DATA0_VI0_B0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DU1_DG2_MARK, IRQ2_B_MARK, RX3_D_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DU1_DG3_MARK, IRQ3_B_MARK, TX3_D_MARK, VI0_DATA2_VI0_B2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DU1_DG4_MARK, RX0_C_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DU1_DG5_MARK, TX1_A_MARK, TX0_C_MARK, VI0_DATA4_VI0_B4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DU1_DB2_MARK, RX1_A_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DU1_DB3_MARK, SCK1_A_MARK, PWM4_MARK, HSCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) VI0_DATA6_VI0_G0_MARK, DU1_DB4_MARK, CTS1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PWM5_MARK, VI0_DATA7_VI0_G1_MARK, DU1_DB5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) RTS1_A_MARK, VI0_G2_MARK, SD2_CLK_B_MARK, VI1_DATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DU1_DR4_MARK, HTX1_B_MARK, VI0_G3_MARK, SD2_CMD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) VI1_DATA5_MARK, DU1_DR5_MARK, HRX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) VI0_G4_MARK, SD2_DAT0_B_MARK, VI1_DATA6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DU1_DR6_MARK, HRTS1_B_MARK, VI0_G5_MARK, SD2_DAT1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) VI1_DATA7_MARK, DU1_DR7_MARK, HCTS1_B_MARK, VI0_R0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) VI1_CLK_MARK, ETH_REF_CLK_MARK, DU1_DOTCLKIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) VI0_R1_A_MARK, VI1_DATA8_MARK, DU1_DB6_MARK, ETH_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PWM2_MARK, TCLK1_MARK, VI0_R2_A_MARK, VI1_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DU1_DB7_MARK, ETH_TXD1_MARK, PWM3_MARK, VI0_R3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) ETH_CRS_DV_MARK, IECLK_MARK, SCK2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) VI0_R4_A_MARK, ETH_TX_EN_MARK, IETX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) TX2_C_MARK, VI0_R5_A_MARK, ETH_RX_ER_MARK, FMCLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) IERX_MARK, RX2_C_MARK, VI1_DATA10_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DU1_DOTCLKOUT_MARK, ETH_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) BPFCLK_C_MARK, TX2_D_MARK, SDA2_C_MARK, VI1_DATA11_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DU1_EXHSYNC_DU1_HSYNC_MARK, ETH_RXD1_MARK, FMIN_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) RX2_D_MARK, SCL2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK, ATARD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ETH_MDC_MARK, SDA1_B_MARK, SD2_CMD_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, ATAWR1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ETH_MDIO_MARK, SCL1_B_MARK, SD2_DAT0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DU1_DISP_MARK, ATACS01_MARK, DREQ1_B_MARK, ETH_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) CAN1_RX_A_MARK, SD2_DAT1_A_MARK, DU1_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ATACS11_MARK, DACK1_B_MARK, ETH_MAGIC_MARK, CAN1_TX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PWM6_MARK, SD2_DAT2_A_MARK, VI1_DATA12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DREQ2_B_MARK, ATADIR1_MARK, HSPI_CLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) GPSCLK_B_MARK, SD2_DAT3_A_MARK, VI1_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DACK2_B_MARK, ATAG1_MARK, HSPI_CS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) GPSIN_B_MARK, SD2_CD_A_MARK, VI1_DATA14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) EX_WAIT1_B_MARK, DREQ0_B_MARK, HSPI_RX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) REMOCON_A_MARK, SD2_WP_A_MARK, VI1_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) EX_WAIT2_B_MARK, DACK0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) HSPI_TX2_B_MARK, CAN_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_SINGLE(PENC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_SINGLE(PENC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_SINGLE(A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_SINGLE(A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_SINGLE(A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINMUX_SINGLE(WE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_SINGLE(AUDIO_CLKA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_SINGLE(AUDIO_CLKB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINMUX_SINGLE(SSI_SCK34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINMUX_SINGLE(AVS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINMUX_SINGLE(AVS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_IPSR_GPSR(IP0_1_0, PRESETOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_IPSR_GPSR(IP0_1_0, PWM1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_IPSR_GPSR(IP0_4_2, AUDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_IPSR_GPSR(IP0_4_2, ARM_TRACEDATA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_IPSR_MSEL(IP0_4_2, GPSCLK_C, SEL_GPS_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINMUX_IPSR_GPSR(IP0_4_2, USB_OVC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINMUX_IPSR_GPSR(IP0_4_2, TX2_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_MSEL(IP0_4_2, SDA2_B, SEL_I2C2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINMUX_IPSR_GPSR(IP0_7_5, AUDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINMUX_IPSR_GPSR(IP0_7_5, ARM_TRACEDATA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_IPSR_MSEL(IP0_7_5, GPSIN_C, SEL_GPS_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_IPSR_GPSR(IP0_7_5, USB_OVC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_MSEL(IP0_7_5, RX2_E, SEL_SCIF2_E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINMUX_IPSR_MSEL(IP0_7_5, SCL2_B, SEL_I2C2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_IPSR_MSEL(IP0_11_8, SD1_DAT2_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_IPSR_GPSR(IP0_11_8, MMC_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINMUX_IPSR_GPSR(IP0_11_8, BS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_IPSR_GPSR(IP0_11_8, ATADIR0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINMUX_IPSR_GPSR(IP0_11_8, SDSELF_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_IPSR_GPSR(IP0_11_8, PWM4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_IPSR_MSEL(IP0_14_12, SD1_DAT3_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_GPSR(IP0_14_12, MMC_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_GPSR(IP0_14_12, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINMUX_IPSR_GPSR(IP0_14_12, ATAG0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_MSEL(IP0_14_12, REMOCON_B, SEL_REMOCON_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_IPSR_GPSR(IP0_15, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_IPSR_GPSR(IP0_16, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_IPSR_GPSR(IP0_17, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_IPSR_GPSR(IP0_18, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_IPSR_GPSR(IP0_19, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_IPSR_GPSR(IP0_20, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_IPSR_GPSR(IP0_21, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_IPSR_GPSR(IP0_22, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_IPSR_GPSR(IP0_23, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_IPSR_GPSR(IP0_24, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_IPSR_GPSR(IP0_25, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_IPSR_GPSR(IP0_26, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_GPSR(IP0_27, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_IPSR_GPSR(IP0_28, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINMUX_IPSR_GPSR(IP0_29, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_GPSR(IP0_30, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_IPSR_GPSR(IP1_0, A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_IPSR_MSEL(IP1_0, HSPI_CS1_B, SEL_HSPI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_IPSR_GPSR(IP1_1, A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_IPSR_MSEL(IP1_1, HSPI_CLK1_B, SEL_HSPI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_IPSR_GPSR(IP1_4_2, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_IPSR_MSEL(IP1_4_2, HRTS0_B, SEL_HSCIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_MSEL(IP1_4_2, RX2_B, SEL_SCIF2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_IPSR_MSEL(IP1_4_2, DREQ2_A, SEL_DREQ2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_IPSR_GPSR(IP1_7_5, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_GPSR(IP1_7_5, HTX0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_GPSR(IP1_7_5, TX2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_IPSR_GPSR(IP1_7_5, DACK2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_IPSR_MSEL(IP1_7_5, TS_SDEN0_A, SEL_TSIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR_MSEL(IP1_10_8, SD1_CD_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_GPSR(IP1_10_8, MMC_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_IPSR_GPSR(IP1_10_8, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_MSEL(IP1_10_8, DREQ1_A, SEL_DREQ1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_IPSR_MSEL(IP1_10_8, HRX0_B, SEL_HSCIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_IPSR_MSEL(IP1_10_8, TS_SPSYNC0_A, SEL_TSIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINMUX_IPSR_MSEL(IP1_14_11, SD1_WP_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_GPSR(IP1_14_11, MMC_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_IPSR_GPSR(IP1_14_11, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_GPSR(IP1_14_11, DACK1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINMUX_IPSR_MSEL(IP1_14_11, HCTS0_B, SEL_HSCIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_MSEL(IP1_14_11, RX3_C, SEL_SCIF3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_IPSR_MSEL(IP1_14_11, TS_SDAT0_A, SEL_TSIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_IPSR_NOGP(IP1_16_15, CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_NOGP(IP1_16_15, HSPI_TX1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_IPSR_NOGP(IP1_16_15, PWM0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_IPSR_NOGP(IP1_17, CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_NOGM(IP1_17, HSPI_RX1_B, SEL_HSPI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_IPSR_NOGM(IP1_20_18, SSI_SCK1_B, SEL_SSI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_IPSR_NOGP(IP1_20_18, ATAG0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_IPSR_NOGP(IP1_20_18, CS1_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_IPSR_NOGM(IP1_20_18, SDA2_A, SEL_I2C2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_IPSR_NOGM(IP1_20_18, SCK2_B, SEL_SCIF2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_GPSR(IP1_23_21, MMC_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_IPSR_GPSR(IP1_23_21, ATADIR0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_GPSR(IP1_23_21, RD_WR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_GPSR(IP1_24, WE1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_GPSR(IP1_24, ATAWR0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_IPSR_MSEL(IP1_27_25, SSI_WS1_B, SEL_SSI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_GPSR(IP1_27_25, EX_CS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_MSEL(IP1_27_25, SCL2_A, SEL_I2C2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_GPSR(IP1_27_25, TX3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_IPSR_MSEL(IP1_27_25, TS_SCK0_A, SEL_TSIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_GPSR(IP1_29_28, EX_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_IPSR_GPSR(IP1_29_28, MMC_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_GPSR(IP2_2_0, SD1_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_GPSR(IP2_2_0, MMC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_IPSR_GPSR(IP2_2_0, ATACS00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_GPSR(IP2_2_0, EX_CS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_IPSR_MSEL(IP2_5_3, SD1_CMD_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINMUX_IPSR_GPSR(IP2_5_3, MMC_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_GPSR(IP2_5_3, ATACS10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_GPSR(IP2_5_3, EX_CS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_MSEL(IP2_8_6, SD1_DAT0_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_IPSR_GPSR(IP2_8_6, MMC_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_GPSR(IP2_8_6, ATARD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP2_8_6, EX_CS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_MSEL(IP2_8_6, EX_WAIT1_A, SEL_WAIT1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_MSEL(IP2_11_9, SD1_DAT1_A, SEL_SD1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_GPSR(IP2_11_9, MMC_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINMUX_IPSR_GPSR(IP2_11_9, ATAWR0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_GPSR(IP2_11_9, EX_CS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_MSEL(IP2_11_9, EX_WAIT2_A, SEL_WAIT2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_MSEL(IP2_13_12, DREQ0_A, SEL_DREQ0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_MSEL(IP2_13_12, RX3_A, SEL_SCIF3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_IPSR_GPSR(IP2_16_14, DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_IPSR_GPSR(IP2_16_14, TX3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_GPSR(IP2_16_14, DRACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_GPSR(IP2_17, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_GPSR(IP2_17, PWM0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_IPSR_NOGP(IP2_18, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_NOGP(IP2_19, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_NOGP(IP2_20, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_IPSR_NOGP(IP2_21, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_NOGP(IP2_22, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_IPSR_NOGP(IP2_23, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_IPSR_NOGP(IP2_24, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_NOGP(IP2_25, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_IPSR_NOGP(IP2_26, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_IPSR_NOGP(IP2_27, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_NOGP(IP2_28, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_NOGP(IP2_29, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_GPSR(IP2_30, RD_WR_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_IPSR_GPSR(IP2_30, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_GPSR(IP2_31, MLB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_MSEL(IP2_31, IRQ1_A, SEL_IRQ1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_GPSR(IP3_1_0, MLB_SIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_IPSR_MSEL(IP3_1_0, RX5_B, SEL_SCIF5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_MSEL(IP3_1_0, SDA3_A, SEL_I2C3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_MSEL(IP3_1_0, IRQ2_A, SEL_IRQ2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_IPSR_GPSR(IP3_4_2, MLB_DAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_GPSR(IP3_4_2, TX5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_MSEL(IP3_4_2, SCL3_A, SEL_I2C3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_MSEL(IP3_4_2, IRQ3_A, SEL_IRQ3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_GPSR(IP3_4_2, SDSELF_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_IPSR_MSEL(IP3_7_5, SD1_CMD_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_GPSR(IP3_7_5, SCIF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_GPSR(IP3_7_5, AUDIO_CLKOUT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_MSEL(IP3_7_5, CAN_CLK_B, SEL_CANCLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_MSEL(IP3_7_5, SDA3_B, SEL_I2C3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_IPSR_GPSR(IP3_9_8, SD1_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_IPSR_GPSR(IP3_9_8, HTX0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_GPSR(IP3_9_8, TX0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_IPSR_MSEL(IP3_12_10, SD1_DAT0_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_MSEL(IP3_12_10, HRX0_A, SEL_HSCIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_MSEL(IP3_12_10, RX0_A, SEL_SCIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_IPSR_MSEL(IP3_15_13, SD1_DAT1_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_MSEL(IP3_15_13, HSCK0, SEL_HSCIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_GPSR(IP3_15_13, SCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_IPSR_MSEL(IP3_15_13, SCL3_B, SEL_I2C3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_IPSR_MSEL(IP3_18_16, SD1_DAT2_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_MSEL(IP3_18_16, HCTS0_A, SEL_HSCIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_GPSR(IP3_18_16, CTS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_MSEL(IP3_20_19, SD1_DAT3_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_IPSR_MSEL(IP3_20_19, HRTS0_A, SEL_HSCIF0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_IPSR_GPSR(IP3_20_19, RTS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_IPSR_GPSR(IP3_23_21, SSI_SCK4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_IPSR_GPSR(IP3_23_21, DU0_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_GPSR(IP3_23_21, LCDOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_GPSR(IP3_23_21, AUDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_IPSR_GPSR(IP3_23_21, ARM_TRACEDATA_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_MSEL(IP3_23_21, SDA3_C, SEL_I2C3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_GPSR(IP3_23_21, ADICHS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN0_B, SEL_TSIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_IPSR_GPSR(IP3_26_24, SSI_WS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_GPSR(IP3_26_24, DU0_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_IPSR_GPSR(IP3_26_24, LCDOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_GPSR(IP3_26_24, AUDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_GPSR(IP3_26_24, ARM_TRACEDATA_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_MSEL(IP3_26_24, SCL3_C, SEL_I2C3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_IPSR_GPSR(IP3_26_24, ADICHS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC0_B, SEL_TSIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_GPSR(IP3_27, DU0_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_GPSR(IP3_27, LCDOUT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_GPSR(IP3_28, DU0_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_GPSR(IP3_28, LCDOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_GPSR(IP3_29, DU0_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_GPSR(IP3_29, LCDOUT4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_GPSR(IP3_30, DU0_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_GPSR(IP3_30, LCDOUT5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_IPSR_GPSR(IP3_31, DU0_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_GPSR(IP3_31, LCDOUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_GPSR(IP4_0, DU0_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_IPSR_GPSR(IP4_0, LCDOUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_GPSR(IP4_3_1, DU0_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_GPSR(IP4_3_1, LCDOUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_GPSR(IP4_3_1, AUDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_IPSR_GPSR(IP4_3_1, ARM_TRACEDATA_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP4_3_1, TX1_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_IPSR_GPSR(IP4_3_1, CAN0_TX_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_GPSR(IP4_3_1, ADICHS0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_IPSR_GPSR(IP4_6_4, DU0_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_GPSR(IP4_6_4, LCDOUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_GPSR(IP4_6_4, AUDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_GPSR(IP4_6_4, ARM_TRACEDATA_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_IPSR_MSEL(IP4_6_4, RX1_D, SEL_SCIF1_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_MSEL(IP4_6_4, CAN0_RX_A, SEL_CAN0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_GPSR(IP4_6_4, ADIDATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_IPSR_GPSR(IP4_7, DU0_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_IPSR_GPSR(IP4_7, LCDOUT10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_IPSR_GPSR(IP4_8, DU0_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_GPSR(IP4_8, LCDOUT11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_GPSR(IP4_10_9, DU0_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_GPSR(IP4_10_9, LCDOUT12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_IPSR_MSEL(IP4_10_9, RX0_B, SEL_SCIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_GPSR(IP4_12_11, DU0_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_GPSR(IP4_12_11, LCDOUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_GPSR(IP4_12_11, TX0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_GPSR(IP4_14_13, DU0_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_GPSR(IP4_14_13, LCDOUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_MSEL(IP4_14_13, RX4_A, SEL_SCIF4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_GPSR(IP4_16_15, DU0_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_GPSR(IP4_16_15, LCDOUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP4_16_15, TX4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_MSEL(IP4_20_17, SSI_SCK2_B, SEL_SSI2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_DATA(VI0_R0_B_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_B), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_DATA(VI0_R0_D_MARK, FN_IP4_20_17, FN_VI0_R0_B, FN_SEL_VI0_D), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_GPSR(IP4_20_17, DU0_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP4_20_17, LCDOUT16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP4_20_17, AUDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_GPSR(IP4_20_17, ARM_TRACEDATA_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_MSEL(IP4_20_17, GPSCLK_A, SEL_GPS_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_GPSR(IP4_20_17, PWM0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_GPSR(IP4_20_17, ADICLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_MSEL(IP4_20_17, TS_SDAT0_B, SEL_TSIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_IPSR_GPSR(IP4_24_21, AUDIO_CLKC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_DATA(VI0_R1_B_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_B), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_DATA(VI0_R1_D_MARK, FN_IP4_24_21, FN_VI0_R1_B, FN_SEL_VI0_D), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_GPSR(IP4_24_21, DU0_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_GPSR(IP4_24_21, LCDOUT17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_GPSR(IP4_24_21, AUDATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_GPSR(IP4_24_21, ARM_TRACEDATA_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_MSEL(IP4_24_21, GPSIN_A, SEL_GPS_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_GPSR(IP4_24_21, ADICS_SAMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_MSEL(IP4_24_21, TS_SCK0_B, SEL_TSIF0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_DATA(VI0_R2_B_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_B), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_DATA(VI0_R2_D_MARK, FN_IP4_26_25, FN_VI0_R2_B, FN_SEL_VI0_D), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_GPSR(IP4_26_25, DU0_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_GPSR(IP4_26_25, LCDOUT18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP4_28_27, VI0_R3_B, SEL_VI0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_IPSR_GPSR(IP4_28_27, DU0_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_GPSR(IP4_28_27, LCDOUT19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_DATA(VI0_R4_B_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_B), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_DATA(VI0_R4_D_MARK, FN_IP4_30_29, FN_VI0_R4_B, FN_SEL_VI0_D), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_GPSR(IP4_30_29, DU0_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_GPSR(IP4_30_29, LCDOUT20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_DATA(VI0_R5_B_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_B), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_DATA(VI0_R5_D_MARK, FN_IP5_1_0, FN_VI0_R5_B, FN_SEL_VI0_D), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_GPSR(IP5_1_0, DU0_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_MSEL(IP5_3_2, VI1_DATA10_B, SEL_VI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_GPSR(IP5_3_2, DU0_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_MSEL(IP5_5_4, VI1_DATA11_B, SEL_VI1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_GPSR(IP5_5_4, DU0_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_GPSR(IP5_6, DU0_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_GPSR(IP5_6, QSTVA_QVS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) PINMUX_IPSR_GPSR(IP5_7, DU0_DOTCLKO_UT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_IPSR_GPSR(IP5_7, QCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_GPSR(IP5_9_8, DU0_DOTCLKO_UT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_GPSR(IP5_9_8, QSTVB_QVE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_GPSR(IP5_9_8, AUDIO_CLKOUT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_MSEL(IP5_9_8, REMOCON_C, SEL_REMOCON_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_MSEL(IP5_11_10, SSI_WS2_B, SEL_SSI2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_GPSR(IP5_11_10, DU0_EXHSYNC_DU0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_GPSR(IP5_11_10, QSTH_QHS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_GPSR(IP5_12, DU0_EXVSYNC_DU0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_GPSR(IP5_12, QSTB_QHE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_GPSR(IP5_14_13, DU0_EXODDF_DU0_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_GPSR(IP5_14_13, QCPV_QDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_MSEL(IP5_14_13, FMCLK_D, SEL_FM_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_MSEL(IP5_17_15, SSI_SCK1_A, SEL_SSI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_GPSR(IP5_17_15, DU0_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_GPSR(IP5_17_15, QPOLA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_GPSR(IP5_17_15, AUDCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_GPSR(IP5_17_15, ARM_TRACECLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_GPSR(IP5_17_15, BPFCLK_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_MSEL(IP5_20_18, SSI_WS1_A, SEL_SSI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_GPSR(IP5_20_18, DU0_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP5_20_18, QPOLB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_GPSR(IP5_20_18, AUDSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_GPSR(IP5_20_18, ARM_TRACECTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_MSEL(IP5_20_18, FMIN_D, SEL_FM_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_MSEL(IP5_22_21, SD1_CD_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP5_22_21, SSI_SCK78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP5_22_21, HSPI_RX0_B, SEL_HSPI0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_GPSR(IP5_22_21, TX1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_MSEL(IP5_25_23, SD1_WP_B, SEL_SD1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_GPSR(IP5_25_23, SSI_WS78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_MSEL(IP5_25_23, HSPI_CLK0_B, SEL_HSPI0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_MSEL(IP5_25_23, RX1_B, SEL_SCIF1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_MSEL(IP5_25_23, CAN_CLK_D, SEL_CANCLK_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_IPSR_GPSR(IP5_28_26, SSI_SDATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_IPSR_MSEL(IP5_28_26, SSI_SCK2_A, SEL_SSI2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP5_28_26, HSPI_CS0_B, SEL_HSPI0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_GPSR(IP5_28_26, TX2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_GPSR(IP5_28_26, CAN0_TX_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_GPSR(IP5_30_29, SSI_SDATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP5_30_29, HSPI_TX0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_MSEL(IP5_30_29, RX2_A, SEL_SCIF2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_MSEL(IP5_30_29, CAN0_RX_B, SEL_CAN0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_GPSR(IP6_1_0, SSI_SCK6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_IPSR_MSEL(IP6_1_0, HSPI_RX2_A, SEL_HSPI2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_MSEL(IP6_1_0, FMCLK_B, SEL_FM_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_GPSR(IP6_1_0, CAN1_TX_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_IPSR_GPSR(IP6_4_2, SSI_WS6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_IPSR_MSEL(IP6_4_2, HSPI_CLK2_A, SEL_HSPI2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_GPSR(IP6_4_2, BPFCLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_MSEL(IP6_4_2, CAN1_RX_B, SEL_CAN1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_GPSR(IP6_6_5, SSI_SDATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP6_6_5, HSPI_TX2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_MSEL(IP6_6_5, FMIN_B, SEL_FM_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_GPSR(IP6_7, SSI_SCK5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_IPSR_MSEL(IP6_7, RX4_C, SEL_SCIF4_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_GPSR(IP6_8, SSI_WS5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_GPSR(IP6_8, TX4_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_GPSR(IP6_9, SSI_SDATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_IPSR_MSEL(IP6_9, RX0_D, SEL_SCIF0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_GPSR(IP6_10, SSI_WS34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP6_10, ARM_TRACEDATA_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_IPSR_GPSR(IP6_12_11, SSI_SDATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_IPSR_MSEL(IP6_12_11, SSI_WS2_A, SEL_SSI2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_GPSR(IP6_12_11, ARM_TRACEDATA_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_GPSR(IP6_13, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_IPSR_GPSR(IP6_13, ARM_TRACEDATA_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_GPSR(IP6_15_14, SSI_SCK012),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_GPSR(IP6_15_14, ARM_TRACEDATA_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_GPSR(IP6_15_14, TX0_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP6_16, SSI_WS012),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_GPSR(IP6_16, ARM_TRACEDATA_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_GPSR(IP6_18_17, SSI_SDATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_MSEL(IP6_18_17, HSPI_CS2_A, SEL_HSPI2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_GPSR(IP6_18_17, ARM_TRACEDATA_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_IPSR_MSEL(IP6_18_17, SDA1_A, SEL_I2C1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_GPSR(IP6_20_19, SSI_SDATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_GPSR(IP6_20_19, ARM_TRACEDATA_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_MSEL(IP6_20_19, SCL1_A, SEL_I2C1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_MSEL(IP6_20_19, SCK2_A, SEL_SCIF2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_GPSR(IP6_21, SSI_SDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_GPSR(IP6_21, ARM_TRACEDATA_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_GPSR(IP6_23_22, SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_GPSR(IP6_23_22, SUB_TDO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_GPSR(IP6_25_24, SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_GPSR(IP6_25_24, SUB_TRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_GPSR(IP6_27_26, SD0_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_IPSR_GPSR(IP6_27_26, SUB_TMS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_GPSR(IP6_29_28, SD0_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_IPSR_GPSR(IP6_29_28, SUB_TCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_GPSR(IP6_31_30, SD0_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_GPSR(IP6_31_30, SUB_TDI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_GPSR(IP7_1_0, SD0_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_MSEL(IP7_1_0, IRQ1_B, SEL_IRQ1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_GPSR(IP7_3_2, SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_GPSR(IP7_3_2, TX5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_GPSR(IP7_5_4, SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_MSEL(IP7_5_4, RX5_A, SEL_SCIF5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_GPSR(IP7_8_6, VI1_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_MSEL(IP7_8_6, HSPI_CLK0_A, SEL_HSPI0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_GPSR(IP7_8_6, HTX1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_MSEL(IP7_8_6, RTS1_C, SEL_SCIF1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_IPSR_GPSR(IP7_11_9, VI1_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_MSEL(IP7_11_9, HSPI_CS0_A, SEL_HSPI0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_MSEL(IP7_11_9, HRX1_A, SEL_HSCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_MSEL(IP7_11_9, SCK1_C, SEL_SCIF1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_GPSR(IP7_14_12, VI1_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_MSEL(IP7_14_12, HSPI_RX0_A, SEL_HSPI0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINMUX_IPSR_MSEL(IP7_14_12, HRTS1_A, SEL_HSCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_IPSR_MSEL(IP7_14_12, FMCLK_A, SEL_FM_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_MSEL(IP7_14_12, RX1_C, SEL_SCIF1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_GPSR(IP7_17_15, VI1_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_GPSR(IP7_17_15, HSPI_TX0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_MSEL(IP7_17_15, HCTS1_A, SEL_HSCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_GPSR(IP7_17_15, BPFCLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_GPSR(IP7_17_15, TX1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_GPSR(IP7_20_18, TCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_IPSR_MSEL(IP7_20_18, HSCK1_A, SEL_HSCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_MSEL(IP7_20_18, FMIN_A, SEL_FM_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_MSEL(IP7_20_18, IRQ2_C, SEL_IRQ2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_MSEL(IP7_20_18, CTS1_C, SEL_SCIF1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_GPSR(IP7_20_18, SPEEDIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_IPSR_GPSR(IP7_21, VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_MSEL(IP7_21, CAN_CLK_A, SEL_CANCLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_GPSR(IP7_24_22, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_IPSR_MSEL(IP7_24_22, SD2_DAT2_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_GPSR(IP7_24_22, VI1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_IPSR_GPSR(IP7_24_22, DU1_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_IPSR_MSEL(IP7_24_22, HSPI_RX1_A, SEL_HSPI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_MSEL(IP7_24_22, RX4_B, SEL_SCIF4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_IPSR_GPSR(IP7_28_25, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_MSEL(IP7_28_25, SD2_DAT3_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_DATA(VI0_R3_C_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_C), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_DATA(VI0_R3_D_MARK, FN_IP7_28_25, FN_VI0_R3_C, FN_SEL_VI0_D), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_GPSR(IP7_28_25, VI1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_IPSR_GPSR(IP7_28_25, DU1_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_MSEL(IP7_28_25, HSPI_CLK1_A, SEL_HSPI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_GPSR(IP7_28_25, TX4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_IPSR_GPSR(IP7_31_29, VI0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) PINMUX_IPSR_MSEL(IP7_31_29, SD2_CD_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) PINMUX_IPSR_GPSR(IP7_31_29, VI1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_GPSR(IP7_31_29, DU1_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_MSEL(IP7_31_29, HSPI_CS1_A, SEL_HSPI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_IPSR_MSEL(IP7_31_29, RX3_B, SEL_SCIF3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_GPSR(IP8_2_0, VI0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_MSEL(IP8_2_0, SD2_WP_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_GPSR(IP8_2_0, VI1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_IPSR_GPSR(IP8_2_0, DU1_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_GPSR(IP8_2_0, HSPI_TX1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_GPSR(IP8_2_0, TX3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_GPSR(IP8_5_3, VI0_DATA0_VI0_B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_GPSR(IP8_5_3, DU1_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_IPSR_MSEL(IP8_5_3, IRQ2_B, SEL_IRQ2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_MSEL(IP8_5_3, RX3_D, SEL_SCIF3_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_GPSR(IP8_8_6, VI0_DATA1_VI0_B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_GPSR(IP8_8_6, DU1_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_MSEL(IP8_8_6, IRQ3_B, SEL_IRQ3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_IPSR_GPSR(IP8_8_6, TX3_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_GPSR(IP8_10_9, VI0_DATA2_VI0_B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_GPSR(IP8_10_9, DU1_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_MSEL(IP8_10_9, RX0_C, SEL_SCIF0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_GPSR(IP8_13_11, VI0_DATA3_VI0_B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_GPSR(IP8_13_11, DU1_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_GPSR(IP8_13_11, TX1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_GPSR(IP8_13_11, TX0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_GPSR(IP8_15_14, VI0_DATA4_VI0_B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_GPSR(IP8_15_14, DU1_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_IPSR_MSEL(IP8_15_14, RX1_A, SEL_SCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_IPSR_GPSR(IP8_18_16, VI0_DATA5_VI0_B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_IPSR_GPSR(IP8_18_16, DU1_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_IPSR_MSEL(IP8_18_16, SCK1_A, SEL_SCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_GPSR(IP8_18_16, PWM4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_MSEL(IP8_18_16, HSCK1_B, SEL_HSCIF1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_GPSR(IP8_21_19, VI0_DATA6_VI0_G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_GPSR(IP8_21_19, DU1_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_IPSR_MSEL(IP8_21_19, CTS1_A, SEL_SCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_GPSR(IP8_21_19, PWM5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_GPSR(IP8_23_22, VI0_DATA7_VI0_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_IPSR_GPSR(IP8_23_22, DU1_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_MSEL(IP8_23_22, RTS1_A, SEL_SCIF1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_GPSR(IP8_26_24, VI0_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_GPSR(IP8_26_24, SD2_CLK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_GPSR(IP8_26_24, VI1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_GPSR(IP8_26_24, DU1_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_GPSR(IP8_26_24, HTX1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_GPSR(IP8_29_27, VI0_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_MSEL(IP8_29_27, SD2_CMD_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_GPSR(IP8_29_27, VI1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_GPSR(IP8_29_27, DU1_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PINMUX_IPSR_MSEL(IP8_29_27, HRX1_B, SEL_HSCIF1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_IPSR_GPSR(IP9_2_0, VI0_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_IPSR_MSEL(IP9_2_0, SD2_DAT0_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_IPSR_GPSR(IP9_2_0, VI1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_IPSR_MSEL(IP9_2_0, HRTS1_B, SEL_HSCIF1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_IPSR_GPSR(IP9_5_3, VI0_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_IPSR_MSEL(IP9_5_3, SD2_DAT1_B, SEL_SD2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_IPSR_GPSR(IP9_5_3, VI1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_IPSR_MSEL(IP9_5_3, HCTS1_B, SEL_HSCIF1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINMUX_DATA(VI0_R0_A_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_A), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINMUX_DATA(VI0_R0_C_MARK, FN_IP9_8_6, FN_VI0_R0_A, FN_SEL_VI0_C), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_IPSR_GPSR(IP9_8_6, VI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_IPSR_GPSR(IP9_8_6, ETH_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINMUX_IPSR_GPSR(IP9_8_6, DU1_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_DATA(VI0_R1_A_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_A), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_DATA(VI0_R1_C_MARK, FN_IP9_11_9, FN_VI0_R1_A, FN_SEL_VI0_C), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_IPSR_GPSR(IP9_11_9, VI1_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_IPSR_GPSR(IP9_11_9, DU1_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_IPSR_GPSR(IP9_11_9, ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_IPSR_GPSR(IP9_11_9, PWM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_IPSR_GPSR(IP9_11_9, TCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_DATA(VI0_R2_A_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_A), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_DATA(VI0_R2_C_MARK, FN_IP9_14_12, FN_VI0_R2_A, FN_SEL_VI0_C), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINMUX_IPSR_GPSR(IP9_14_12, VI1_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_IPSR_GPSR(IP9_14_12, DU1_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_IPSR_GPSR(IP9_14_12, ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_IPSR_GPSR(IP9_14_12, PWM3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_IPSR_MSEL(IP9_17_15, VI0_R3_A, SEL_VI0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_IPSR_GPSR(IP9_17_15, ETH_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_IPSR_GPSR(IP9_17_15, IECLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_IPSR_MSEL(IP9_17_15, SCK2_C, SEL_SCIF2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_DATA(VI0_R4_A_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_A), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINMUX_DATA(VI0_R3_C_MARK, FN_IP9_20_18, FN_VI0_R4_A, FN_SEL_VI0_C), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINMUX_IPSR_GPSR(IP9_20_18, ETH_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_IPSR_GPSR(IP9_20_18, IETX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_IPSR_GPSR(IP9_20_18, TX2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_DATA(VI0_R5_A_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_A), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_DATA(VI0_R5_C_MARK, FN_IP9_23_21, FN_VI0_R5_A, FN_SEL_VI0_C), /* see sel_vi0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_IPSR_GPSR(IP9_23_21, ETH_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_IPSR_MSEL(IP9_23_21, FMCLK_C, SEL_FM_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_IPSR_GPSR(IP9_23_21, IERX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_IPSR_MSEL(IP9_23_21, RX2_C, SEL_SCIF2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_IPSR_MSEL(IP9_26_24, VI1_DATA10_A, SEL_VI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_IPSR_GPSR(IP9_26_24, DU1_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_IPSR_GPSR(IP9_26_24, ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_IPSR_GPSR(IP9_26_24, BPFCLK_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_IPSR_GPSR(IP9_26_24, TX2_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_IPSR_MSEL(IP9_26_24, SDA2_C, SEL_I2C2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_IPSR_MSEL(IP9_29_27, VI1_DATA11_A, SEL_VI1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_IPSR_GPSR(IP9_29_27, DU1_EXHSYNC_DU1_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_IPSR_GPSR(IP9_29_27, ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_IPSR_MSEL(IP9_29_27, FMIN_C, SEL_FM_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_IPSR_MSEL(IP9_29_27, RX2_D, SEL_SCIF2_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_IPSR_MSEL(IP9_29_27, SCL2_C, SEL_I2C2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_IPSR_GPSR(IP10_2_0, SD2_CLK_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINMUX_IPSR_GPSR(IP10_2_0, DU1_EXVSYNC_DU1_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINMUX_IPSR_GPSR(IP10_2_0, ATARD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_IPSR_GPSR(IP10_2_0, ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_IPSR_MSEL(IP10_2_0, SDA1_B, SEL_I2C1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_IPSR_MSEL(IP10_5_3, SD2_CMD_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINMUX_IPSR_GPSR(IP10_5_3, DU1_EXODDF_DU1_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_IPSR_GPSR(IP10_5_3, ATAWR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_IPSR_GPSR(IP10_5_3, ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_IPSR_MSEL(IP10_5_3, SCL1_B, SEL_I2C1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_IPSR_MSEL(IP10_8_6, SD2_DAT0_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_IPSR_GPSR(IP10_8_6, DU1_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_IPSR_GPSR(IP10_8_6, ATACS01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_IPSR_MSEL(IP10_8_6, DREQ1_B, SEL_DREQ1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINMUX_IPSR_GPSR(IP10_8_6, ETH_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINMUX_IPSR_MSEL(IP10_8_6, CAN1_RX_A, SEL_CAN1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_IPSR_MSEL(IP10_12_9, SD2_DAT1_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_IPSR_GPSR(IP10_12_9, DU1_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_IPSR_GPSR(IP10_12_9, ATACS11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_IPSR_GPSR(IP10_12_9, DACK1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_IPSR_GPSR(IP10_12_9, ETH_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINMUX_IPSR_GPSR(IP10_12_9, CAN1_TX_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_IPSR_GPSR(IP10_12_9, PWM6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_IPSR_MSEL(IP10_15_13, SD2_DAT2_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_IPSR_GPSR(IP10_15_13, VI1_DATA12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_IPSR_MSEL(IP10_15_13, DREQ2_B, SEL_DREQ2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINMUX_IPSR_GPSR(IP10_15_13, ATADIR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_IPSR_MSEL(IP10_15_13, HSPI_CLK2_B, SEL_HSPI2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_IPSR_MSEL(IP10_15_13, GPSCLK_B, SEL_GPS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_IPSR_MSEL(IP10_18_16, SD2_DAT3_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_IPSR_GPSR(IP10_18_16, VI1_DATA13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_IPSR_GPSR(IP10_18_16, DACK2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_IPSR_GPSR(IP10_18_16, ATAG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINMUX_IPSR_MSEL(IP10_18_16, HSPI_CS2_B, SEL_HSPI2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINMUX_IPSR_MSEL(IP10_18_16, GPSIN_B, SEL_GPS_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_IPSR_MSEL(IP10_21_19, SD2_CD_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_IPSR_GPSR(IP10_21_19, VI1_DATA14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_IPSR_MSEL(IP10_21_19, EX_WAIT1_B, SEL_WAIT1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_IPSR_MSEL(IP10_21_19, DREQ0_B, SEL_DREQ0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_IPSR_MSEL(IP10_21_19, HSPI_RX2_B, SEL_HSPI2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINMUX_IPSR_MSEL(IP10_21_19, REMOCON_A, SEL_REMOCON_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_IPSR_MSEL(IP10_24_22, SD2_WP_A, SEL_SD2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_IPSR_GPSR(IP10_24_22, VI1_DATA15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_IPSR_MSEL(IP10_24_22, EX_WAIT2_B, SEL_WAIT2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_IPSR_GPSR(IP10_24_22, DACK0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_IPSR_GPSR(IP10_24_22, HSPI_TX2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_IPSR_MSEL(IP10_24_22, CAN_CLK_C, SEL_CANCLK_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * Pins not associated with a GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) GP_ASSIGN_LAST(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* - macro */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define SH_PFC_PINS(name, args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const unsigned int name ##_pins[] = { args }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define SH_PFC_MUX1(name, arg1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static const unsigned int name ##_mux[] = { arg1##_MARK }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define SH_PFC_MUX2(name, arg1, arg2) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define SH_PFC_MUX3(name, arg1, arg2, arg3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) arg3##_MARK }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) arg3##_MARK, arg4##_MARK }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static const unsigned int name ##_mux[] = { arg1##_MARK, arg2##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) arg3##_MARK, arg4##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) arg5##_MARK, arg6##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) arg7##_MARK, arg8##_MARK, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) /* - AUDIO macro -------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* - AUDIO clock -------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* - CAN macro --------_----------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* - CAN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* - CAN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* - CAN_CLK --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) CAN_PFC_CLK(can_clk_a, CAN_CLK_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) CAN_PFC_CLK(can_clk_b, CAN_CLK_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) CAN_PFC_CLK(can_clk_c, CAN_CLK_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) CAN_PFC_CLK(can_clk_d, CAN_CLK_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* - Ether ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static const unsigned int ether_rmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ETH_MDIO_MARK, ETH_MDC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) SH_PFC_PINS(ether_link, RCAR_GP_PIN(4, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) SH_PFC_MUX1(ether_link, ETH_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SH_PFC_PINS(ether_magic, RCAR_GP_PIN(4, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) SH_PFC_MUX1(ether_magic, ETH_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* - SCIF macro ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define SCIF_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define SCIF_PFC_DAT(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define SCIF_PFC_CTR(name, cts, rts) SH_PFC_MUX2(name, cts, rts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define SCIF_PFC_CLK(name, sck) SH_PFC_MUX1(name, sck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* - HSCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) SCIF_PFC_PIN(hscif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) SCIF_PFC_DAT(hscif0_data_a, HTX0_A, HRX0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) SCIF_PFC_PIN(hscif0_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SCIF_PFC_DAT(hscif0_data_b, HTX0_B, HRX0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) SCIF_PFC_PIN(hscif0_ctrl_a, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SCIF_PFC_CTR(hscif0_ctrl_a, HCTS0_A, HRTS0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) SCIF_PFC_PIN(hscif0_ctrl_b, RCAR_GP_PIN(0, 31), RCAR_GP_PIN(0, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) SCIF_PFC_CTR(hscif0_ctrl_b, HCTS0_B, HRTS0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) SCIF_PFC_PIN(hscif0_clk, RCAR_GP_PIN(1, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SCIF_PFC_CLK(hscif0_clk, HSCK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /* - HSCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) SCIF_PFC_PIN(hscif1_data_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) SCIF_PFC_DAT(hscif1_data_a, HTX1_A, HRX1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) SCIF_PFC_PIN(hscif1_data_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) SCIF_PFC_DAT(hscif1_data_b, HTX1_B, HRX1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) SCIF_PFC_PIN(hscif1_ctrl_a, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) SCIF_PFC_CTR(hscif1_ctrl_a, HCTS1_A, HRTS1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) SCIF_PFC_PIN(hscif1_ctrl_b, RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SCIF_PFC_CTR(hscif1_ctrl_b, HCTS1_B, HRTS1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) SCIF_PFC_PIN(hscif1_clk_a, RCAR_GP_PIN(3, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) SCIF_PFC_CLK(hscif1_clk_a, HSCK1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) SCIF_PFC_PIN(hscif1_clk_b, RCAR_GP_PIN(4, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) SCIF_PFC_CLK(hscif1_clk_b, HSCK1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* - HSPI macro --------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define HSPI_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define HSPI_PFC_DAT(name, clk, cs, rx, tx) SH_PFC_MUX4(name, clk, cs, rx, tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* - HSPI0 -------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) HSPI_PFC_PIN(hspi0_a, RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) HSPI_PFC_DAT(hspi0_a, HSPI_CLK0_A, HSPI_CS0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) HSPI_RX0_A, HSPI_TX0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) HSPI_PFC_PIN(hspi0_b, RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) HSPI_PFC_DAT(hspi0_b, HSPI_CLK0_B, HSPI_CS0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) HSPI_RX0_B, HSPI_TX0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* - HSPI1 -------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) HSPI_PFC_PIN(hspi1_a, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) HSPI_PFC_DAT(hspi1_a, HSPI_CLK1_A, HSPI_CS1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) HSPI_RX1_A, HSPI_TX1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) HSPI_PFC_PIN(hspi1_b, RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PIN_CS0, PIN_CLKOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) HSPI_PFC_DAT(hspi1_b, HSPI_CLK1_B, HSPI_CS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) HSPI_RX1_B, HSPI_TX1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* - HSPI2 -------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) HSPI_PFC_PIN(hspi2_a, RCAR_GP_PIN(2, 29), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) HSPI_PFC_DAT(hspi2_a, HSPI_CLK2_A, HSPI_CS2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) HSPI_RX2_A, HSPI_TX2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) HSPI_PFC_PIN(hspi2_b, RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) HSPI_PFC_DAT(hspi2_b, HSPI_CLK2_B, HSPI_CS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) HSPI_RX2_B, HSPI_TX2_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* - I2C macro ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define I2C_PFC_PIN(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define I2C_PFC_MUX(name, sda, scl) SH_PFC_MUX2(name, sda, scl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* - I2C1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) I2C_PFC_PIN(i2c1_a, RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) I2C_PFC_MUX(i2c1_a, SDA1_A, SCL1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) I2C_PFC_PIN(i2c1_b, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) I2C_PFC_MUX(i2c1_b, SDA1_B, SCL1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* - I2C2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) I2C_PFC_PIN(i2c2_a, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) I2C_PFC_MUX(i2c2_a, SDA2_A, SCL2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) I2C_PFC_PIN(i2c2_b, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) I2C_PFC_MUX(i2c2_b, SDA2_B, SCL2_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) I2C_PFC_PIN(i2c2_c, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) I2C_PFC_MUX(i2c2_c, SDA2_C, SCL2_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* - I2C3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) I2C_PFC_PIN(i2c3_a, RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) I2C_PFC_MUX(i2c3_a, SDA3_A, SCL3_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) I2C_PFC_PIN(i2c3_b, RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) I2C_PFC_MUX(i2c3_b, SDA3_B, SCL3_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) I2C_PFC_PIN(i2c3_c, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) I2C_PFC_MUX(i2c3_c, SDA3_C, SCL3_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) /* - MMC macro -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define MMC_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define MMC_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define MMC_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define MMC_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) #define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) /* - MMC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) MMC_PFC_PINS(mmc_ctrl, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) MMC_PFC_CTRL(mmc_ctrl, MMC_CLK, MMC_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) MMC_PFC_PINS(mmc_data1, RCAR_GP_PIN(1, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) MMC_PFC_DAT1(mmc_data1, MMC_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) MMC_PFC_PINS(mmc_data4, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) MMC_PFC_DAT4(mmc_data4, MMC_D0, MMC_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) MMC_D2, MMC_D3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) MMC_PFC_PINS(mmc_data8, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) MMC_PFC_DAT8(mmc_data8, MMC_D0, MMC_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) MMC_D2, MMC_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) MMC_D4, MMC_D5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) MMC_D6, MMC_D7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* - SCIF CLOCK ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) SCIF_PFC_PIN(scif_clk, RCAR_GP_PIN(1, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) SCIF_PFC_CLK(scif_clk, SCIF_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) SCIF_PFC_PIN(scif0_data_a, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) SCIF_PFC_PIN(scif0_data_b, RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) SCIF_PFC_DAT(scif0_data_b, TX0_B, RX0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SCIF_PFC_PIN(scif0_data_c, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(3, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) SCIF_PFC_DAT(scif0_data_c, TX0_C, RX0_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) SCIF_PFC_PIN(scif0_data_d, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) SCIF_PFC_DAT(scif0_data_d, TX0_D, RX0_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) SCIF_PFC_PIN(scif0_ctrl, RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) SCIF_PFC_CTR(scif0_ctrl, CTS0, RTS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) SCIF_PFC_PIN(scif0_clk, RCAR_GP_PIN(1, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) SCIF_PFC_CLK(scif0_clk, SCK0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) SCIF_PFC_PIN(scif1_data_a, RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) SCIF_PFC_DAT(scif1_data_a, TX1_A, RX1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) SCIF_PFC_PIN(scif1_data_b, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) SCIF_PFC_DAT(scif1_data_b, TX1_B, RX1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) SCIF_PFC_PIN(scif1_data_c, RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) SCIF_PFC_DAT(scif1_data_c, TX1_C, RX1_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) SCIF_PFC_PIN(scif1_data_d, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) SCIF_PFC_DAT(scif1_data_d, TX1_D, RX1_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) SCIF_PFC_PIN(scif1_ctrl_a, RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SCIF_PFC_CTR(scif1_ctrl_a, CTS1_A, RTS1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) SCIF_PFC_PIN(scif1_ctrl_c, RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) SCIF_PFC_CTR(scif1_ctrl_c, CTS1_C, RTS1_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) SCIF_PFC_PIN(scif1_clk_a, RCAR_GP_PIN(4, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) SCIF_PFC_CLK(scif1_clk_a, SCK1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) SCIF_PFC_PIN(scif1_clk_c, RCAR_GP_PIN(3, 20));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) SCIF_PFC_CLK(scif1_clk_c, SCK1_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) SCIF_PFC_PIN(scif2_data_a, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) SCIF_PFC_DAT(scif2_data_a, TX2_A, RX2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) SCIF_PFC_PIN(scif2_data_b, RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SCIF_PFC_DAT(scif2_data_b, TX2_B, RX2_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) SCIF_PFC_PIN(scif2_data_c, RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) SCIF_PFC_DAT(scif2_data_c, TX2_C, RX2_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) SCIF_PFC_PIN(scif2_data_d, RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) SCIF_PFC_DAT(scif2_data_d, TX2_D, RX2_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) SCIF_PFC_PIN(scif2_data_e, RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) SCIF_PFC_DAT(scif2_data_e, TX2_E, RX2_E);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) SCIF_PFC_PIN(scif2_clk_a, RCAR_GP_PIN(3, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) SCIF_PFC_CLK(scif2_clk_a, SCK2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) SCIF_PFC_PIN(scif2_clk_b, PIN_CS1_A26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) SCIF_PFC_CLK(scif2_clk_b, SCK2_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) SCIF_PFC_PIN(scif2_clk_c, RCAR_GP_PIN(4, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SCIF_PFC_CLK(scif2_clk_c, SCK2_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) SCIF_PFC_PIN(scif3_data_a, RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) SCIF_PFC_DAT(scif3_data_a, TX3_A, RX3_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) SCIF_PFC_PIN(scif3_data_b, RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) SCIF_PFC_DAT(scif3_data_b, TX3_B, RX3_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) SCIF_PFC_PIN(scif3_data_c, RCAR_GP_PIN(1, 3), RCAR_GP_PIN(0, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) SCIF_PFC_DAT(scif3_data_c, TX3_C, RX3_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) SCIF_PFC_PIN(scif3_data_d, RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) SCIF_PFC_DAT(scif3_data_d, TX3_D, RX3_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) SCIF_PFC_PIN(scif4_data_a, RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) SCIF_PFC_DAT(scif4_data_a, TX4_A, RX4_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SCIF_PFC_PIN(scif4_data_b, RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SCIF_PFC_DAT(scif4_data_b, TX4_B, RX4_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SCIF_PFC_PIN(scif4_data_c, RCAR_GP_PIN(3, 0), RCAR_GP_PIN(2, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) SCIF_PFC_DAT(scif4_data_c, TX4_C, RX4_C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) SCIF_PFC_PIN(scif5_data_a, RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) SCIF_PFC_DAT(scif5_data_a, TX5_A, RX5_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) SCIF_PFC_PIN(scif5_data_b, RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) SCIF_PFC_DAT(scif5_data_b, TX5_B, RX5_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* - SDHI macro ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define SDHI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define SDHI_PFC_DAT1(name, d0) SH_PFC_MUX1(name, d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define SDHI_PFC_DAT4(name, d0, d1, d2, d3) SH_PFC_MUX4(name, d0, d1, d2, d3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define SDHI_PFC_CTRL(name, clk, cmd) SH_PFC_MUX2(name, clk, cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define SDHI_PFC_CDPN(name, cd) SH_PFC_MUX1(name, cd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define SDHI_PFC_WPPN(name, wp) SH_PFC_MUX1(name, wp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) SDHI_PFC_PINS(sdhi0_cd, RCAR_GP_PIN(3, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SDHI_PFC_CDPN(sdhi0_cd, SD0_CD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SDHI_PFC_PINS(sdhi0_ctrl, RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) SDHI_PFC_CTRL(sdhi0_ctrl, SD0_CLK, SD0_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) SDHI_PFC_PINS(sdhi0_data1, RCAR_GP_PIN(3, 13));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) SDHI_PFC_DAT1(sdhi0_data1, SD0_DAT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) SDHI_PFC_PINS(sdhi0_data4, RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) SDHI_PFC_DAT4(sdhi0_data4, SD0_DAT0, SD0_DAT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) SD0_DAT2, SD0_DAT3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) SDHI_PFC_PINS(sdhi0_wp, RCAR_GP_PIN(3, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SDHI_PFC_WPPN(sdhi0_wp, SD0_WP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) SDHI_PFC_PINS(sdhi1_cd_a, RCAR_GP_PIN(0, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) SDHI_PFC_CDPN(sdhi1_cd_a, SD1_CD_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) SDHI_PFC_PINS(sdhi1_cd_b, RCAR_GP_PIN(2, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SDHI_PFC_CDPN(sdhi1_cd_b, SD1_CD_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SDHI_PFC_PINS(sdhi1_ctrl_a, RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) SDHI_PFC_CTRL(sdhi1_ctrl_a, SD1_CLK_A, SD1_CMD_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) SDHI_PFC_PINS(sdhi1_ctrl_b, RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) SDHI_PFC_CTRL(sdhi1_ctrl_b, SD1_CLK_B, SD1_CMD_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) SDHI_PFC_PINS(sdhi1_data1_a, RCAR_GP_PIN(1, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) SDHI_PFC_DAT1(sdhi1_data1_a, SD1_DAT0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) SDHI_PFC_PINS(sdhi1_data1_b, RCAR_GP_PIN(1, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) SDHI_PFC_DAT1(sdhi1_data1_b, SD1_DAT0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) SDHI_PFC_PINS(sdhi1_data4_a, RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) SDHI_PFC_DAT4(sdhi1_data4_a, SD1_DAT0_A, SD1_DAT1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) SD1_DAT2_A, SD1_DAT3_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) SDHI_PFC_PINS(sdhi1_data4_b, RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) SDHI_PFC_DAT4(sdhi1_data4_b, SD1_DAT0_B, SD1_DAT1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) SD1_DAT2_B, SD1_DAT3_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) SDHI_PFC_PINS(sdhi1_wp_a, RCAR_GP_PIN(0, 31));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) SDHI_PFC_WPPN(sdhi1_wp_a, SD1_WP_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) SDHI_PFC_PINS(sdhi1_wp_b, RCAR_GP_PIN(2, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) SDHI_PFC_WPPN(sdhi1_wp_b, SD1_WP_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) /* - SDH2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SDHI_PFC_PINS(sdhi2_cd_a, RCAR_GP_PIN(4, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) SDHI_PFC_CDPN(sdhi2_cd_a, SD2_CD_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) SDHI_PFC_PINS(sdhi2_cd_b, RCAR_GP_PIN(3, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SDHI_PFC_CDPN(sdhi2_cd_b, SD2_CD_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) SDHI_PFC_PINS(sdhi2_ctrl_a, RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) SDHI_PFC_CTRL(sdhi2_ctrl_a, SD2_CLK_A, SD2_CMD_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) SDHI_PFC_PINS(sdhi2_ctrl_b, RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) SDHI_PFC_CTRL(sdhi2_ctrl_b, SD2_CLK_B, SD2_CMD_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) SDHI_PFC_PINS(sdhi2_data1_a, RCAR_GP_PIN(4, 19));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SDHI_PFC_DAT1(sdhi2_data1_a, SD2_DAT0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) SDHI_PFC_PINS(sdhi2_data1_b, RCAR_GP_PIN(4, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) SDHI_PFC_DAT1(sdhi2_data1_b, SD2_DAT0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) SDHI_PFC_PINS(sdhi2_data4_a, RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) SDHI_PFC_DAT4(sdhi2_data4_a, SD2_DAT0_A, SD2_DAT1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) SD2_DAT2_A, SD2_DAT3_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) SDHI_PFC_PINS(sdhi2_data4_b, RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) SDHI_PFC_DAT4(sdhi2_data4_b, SD2_DAT0_B, SD2_DAT1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) SD2_DAT2_B, SD2_DAT3_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) SDHI_PFC_PINS(sdhi2_wp_a, RCAR_GP_PIN(4, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* - SSI macro -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* - SSI 0/1/2 -------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) SSI_PFC_PINS(ssi1_b_ctrl, PIN_CS1_A26, RCAR_GP_PIN(1, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) SSI_PFC_DATA(ssi2_data, SSI_SDATA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* - SSI 3/4 ---------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) SSI_PFC_DATA(ssi3_data, SSI_SDATA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) SSI_PFC_DATA(ssi4_data, SSI_SDATA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* - SSI 5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) SSI_PFC_DATA(ssi5_data, SSI_SDATA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* - SSI 6 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) SSI_PFC_DATA(ssi6_data, SSI_SDATA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* - SSI 7/8 --------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) SSI_PFC_DATA(ssi7_data, SSI_SDATA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) SSI_PFC_DATA(ssi8_data, SSI_SDATA8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) SH_PFC_MUX1(usb0, PENC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) SH_PFC_PINS(usb0_ovc, RCAR_GP_PIN(0, 3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) SH_PFC_MUX1(usb0_ovc, USB_OVC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) /* - USB1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) SH_PFC_PINS(usb1, RCAR_GP_PIN(0, 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) SH_PFC_MUX1(usb1, PENC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) SH_PFC_PINS(usb1_ovc, RCAR_GP_PIN(0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) SH_PFC_MUX1(usb1_ovc, USB_OVC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* - VIN macros ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define VIN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define VIN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define VIN_PFC_SYNC(name, hsync, vsync) SH_PFC_MUX2(name, hsync, vsync)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) VIN_PFC_PINS(vin0_data8, RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) RCAR_GP_PIN(3, 31), RCAR_GP_PIN(4, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) VIN_PFC_DAT8(vin0_data8, VI0_DATA0_VI0_B0, VI0_DATA1_VI0_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) VI0_DATA2_VI0_B2, VI0_DATA3_VI0_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) VI0_DATA4_VI0_B4, VI0_DATA5_VI0_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) VI0_DATA6_VI0_G0, VI0_DATA7_VI0_G1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) VIN_PFC_PINS(vin0_clk, RCAR_GP_PIN(3, 24));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) VIN_PFC_CLK(vin0_clk, VI0_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) VIN_PFC_PINS(vin0_sync, RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) VIN_PFC_SYNC(vin0_sync, VI0_HSYNC, VI0_VSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* - VIN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) VIN_PFC_PINS(vin1_data8, RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) VIN_PFC_DAT8(vin1_data8, VI1_DATA0, VI1_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) VI1_DATA2, VI1_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) VI1_DATA4, VI1_DATA5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) VI1_DATA6, VI1_DATA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) VIN_PFC_PINS(vin1_clk, RCAR_GP_PIN(4, 9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) VIN_PFC_CLK(vin1_clk, VI1_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) SH_PFC_PIN_GROUP(audio_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) SH_PFC_PIN_GROUP(audio_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) SH_PFC_PIN_GROUP(audio_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) SH_PFC_PIN_GROUP(audio_clkout_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) SH_PFC_PIN_GROUP(audio_clkout_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) SH_PFC_PIN_GROUP(can0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) SH_PFC_PIN_GROUP(can0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) SH_PFC_PIN_GROUP(can1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) SH_PFC_PIN_GROUP(can1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) SH_PFC_PIN_GROUP(can_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SH_PFC_PIN_GROUP(can_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) SH_PFC_PIN_GROUP(can_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) SH_PFC_PIN_GROUP(can_clk_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) SH_PFC_PIN_GROUP(ether_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) SH_PFC_PIN_GROUP(ether_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) SH_PFC_PIN_GROUP(ether_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) SH_PFC_PIN_GROUP(hscif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) SH_PFC_PIN_GROUP(hscif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) SH_PFC_PIN_GROUP(hscif0_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) SH_PFC_PIN_GROUP(hscif0_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) SH_PFC_PIN_GROUP(hscif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) SH_PFC_PIN_GROUP(hscif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) SH_PFC_PIN_GROUP(hscif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) SH_PFC_PIN_GROUP(hscif1_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) SH_PFC_PIN_GROUP(hscif1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) SH_PFC_PIN_GROUP(hscif1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) SH_PFC_PIN_GROUP(hscif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) SH_PFC_PIN_GROUP(hspi0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) SH_PFC_PIN_GROUP(hspi0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) SH_PFC_PIN_GROUP(hspi1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) SH_PFC_PIN_GROUP(hspi1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) SH_PFC_PIN_GROUP(hspi2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) SH_PFC_PIN_GROUP(hspi2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) SH_PFC_PIN_GROUP(i2c1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) SH_PFC_PIN_GROUP(i2c2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) SH_PFC_PIN_GROUP(i2c2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) SH_PFC_PIN_GROUP(i2c3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) SH_PFC_PIN_GROUP(i2c3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) SH_PFC_PIN_GROUP(i2c3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) SH_PFC_PIN_GROUP(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) SH_PFC_PIN_GROUP(scif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) SH_PFC_PIN_GROUP(scif0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) SH_PFC_PIN_GROUP(scif0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) SH_PFC_PIN_GROUP(scif0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SH_PFC_PIN_GROUP(scif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) SH_PFC_PIN_GROUP(scif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SH_PFC_PIN_GROUP(scif1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SH_PFC_PIN_GROUP(scif1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) SH_PFC_PIN_GROUP(scif1_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) SH_PFC_PIN_GROUP(scif1_ctrl_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) SH_PFC_PIN_GROUP(scif1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) SH_PFC_PIN_GROUP(scif1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) SH_PFC_PIN_GROUP(scif2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) SH_PFC_PIN_GROUP(scif2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) SH_PFC_PIN_GROUP(scif2_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) SH_PFC_PIN_GROUP(scif2_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) SH_PFC_PIN_GROUP(scif2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) SH_PFC_PIN_GROUP(scif2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) SH_PFC_PIN_GROUP(scif2_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SH_PFC_PIN_GROUP(scif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) SH_PFC_PIN_GROUP(scif3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) SH_PFC_PIN_GROUP(scif3_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) SH_PFC_PIN_GROUP(scif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) SH_PFC_PIN_GROUP(scif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) SH_PFC_PIN_GROUP(scif5_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) SH_PFC_PIN_GROUP(scif5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) SH_PFC_PIN_GROUP(sdhi1_cd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) SH_PFC_PIN_GROUP(sdhi1_cd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) SH_PFC_PIN_GROUP(sdhi1_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) SH_PFC_PIN_GROUP(sdhi1_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SH_PFC_PIN_GROUP(sdhi1_data4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SH_PFC_PIN_GROUP(sdhi1_data4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) SH_PFC_PIN_GROUP(sdhi1_wp_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) SH_PFC_PIN_GROUP(sdhi1_wp_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) SH_PFC_PIN_GROUP(sdhi2_cd_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) SH_PFC_PIN_GROUP(sdhi2_cd_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) SH_PFC_PIN_GROUP(sdhi2_data1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) SH_PFC_PIN_GROUP(sdhi2_data1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) SH_PFC_PIN_GROUP(sdhi2_data4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) SH_PFC_PIN_GROUP(sdhi2_data4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) SH_PFC_PIN_GROUP(sdhi2_wp_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) SH_PFC_PIN_GROUP(sdhi2_wp_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) SH_PFC_PIN_GROUP(ssi012_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) SH_PFC_PIN_GROUP(ssi0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) SH_PFC_PIN_GROUP(ssi1_a_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) SH_PFC_PIN_GROUP(ssi1_b_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) SH_PFC_PIN_GROUP(ssi1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SH_PFC_PIN_GROUP(ssi2_a_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) SH_PFC_PIN_GROUP(ssi2_b_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SH_PFC_PIN_GROUP(ssi2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) SH_PFC_PIN_GROUP(ssi34_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) SH_PFC_PIN_GROUP(ssi3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) SH_PFC_PIN_GROUP(ssi4_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) SH_PFC_PIN_GROUP(ssi4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SH_PFC_PIN_GROUP(ssi5_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SH_PFC_PIN_GROUP(ssi5_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) SH_PFC_PIN_GROUP(ssi6_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) SH_PFC_PIN_GROUP(ssi6_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) SH_PFC_PIN_GROUP(ssi78_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) SH_PFC_PIN_GROUP(ssi7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) SH_PFC_PIN_GROUP(ssi8_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) SH_PFC_PIN_GROUP(usb0_ovc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) SH_PFC_PIN_GROUP(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) SH_PFC_PIN_GROUP(usb1_ovc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SH_PFC_PIN_GROUP(vin0_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) SH_PFC_PIN_GROUP(vin1_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static const char * const audio_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) "audio_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) "audio_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) "audio_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) "audio_clkout_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) "audio_clkout_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static const char * const can0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) "can0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) "can0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) "can_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) static const char * const can1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) "can1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) "can1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) "can_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) "can_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) "can_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) "can_clk_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static const char * const ether_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) "ether_rmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) "ether_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) "ether_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) static const char * const hscif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) "hscif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) "hscif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) "hscif0_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) "hscif0_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) "hscif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const char * const hscif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) "hscif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) "hscif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) "hscif1_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) "hscif1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) "hscif1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) "hscif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static const char * const hspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) "hspi0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) "hspi0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static const char * const hspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) "hspi1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "hspi1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const char * const hspi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "hspi2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) "hspi2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) "i2c1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) "i2c2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) "i2c2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) "i2c3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) "i2c3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) "i2c3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) "scif_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "scif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) "scif0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) "scif0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) "scif0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) "scif0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "scif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) "scif1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) "scif1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) "scif1_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) "scif1_ctrl_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) "scif1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "scif1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) "scif2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) "scif2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) "scif2_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "scif2_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) "scif2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) "scif2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) "scif2_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) "scif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) "scif3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) "scif3_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) "scif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) "scif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) "scif5_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) "scif5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) "sdhi1_cd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) "sdhi1_cd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) "sdhi1_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) "sdhi1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) "sdhi1_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) "sdhi1_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) "sdhi1_data4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) "sdhi1_data4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) "sdhi1_wp_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) "sdhi1_wp_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "sdhi2_cd_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) "sdhi2_cd_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) "sdhi2_ctrl_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) "sdhi2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "sdhi2_data1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) "sdhi2_data1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) "sdhi2_data4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) "sdhi2_data4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) "sdhi2_wp_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) "sdhi2_wp_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static const char * const ssi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) "ssi012_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) "ssi0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) "ssi1_a_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) "ssi1_b_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) "ssi1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) "ssi2_a_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) "ssi2_b_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) "ssi2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) "ssi34_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) "ssi3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) "ssi4_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) "ssi4_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) "ssi5_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) "ssi5_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) "ssi6_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) "ssi6_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) "ssi78_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) "ssi7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) "ssi8_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) "usb0_ovc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static const char * const usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) "usb1_ovc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) SH_PFC_FUNCTION(audio_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) SH_PFC_FUNCTION(can0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) SH_PFC_FUNCTION(can1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) SH_PFC_FUNCTION(ether),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) SH_PFC_FUNCTION(hscif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) SH_PFC_FUNCTION(hscif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) SH_PFC_FUNCTION(hspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) SH_PFC_FUNCTION(hspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) SH_PFC_FUNCTION(hspi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) SH_PFC_FUNCTION(ssi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) SH_PFC_FUNCTION(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) GP_0_31_FN, FN_IP1_14_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) GP_0_30_FN, FN_IP1_10_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) GP_0_29_FN, FN_IP1_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) GP_0_28_FN, FN_IP1_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) GP_0_27_FN, FN_IP1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) GP_0_26_FN, FN_IP1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) GP_0_25_FN, FN_IP0_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) GP_0_24_FN, FN_IP0_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) GP_0_23_FN, FN_IP0_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) GP_0_22_FN, FN_IP0_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) GP_0_21_FN, FN_IP0_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) GP_0_20_FN, FN_IP0_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) GP_0_19_FN, FN_IP0_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) GP_0_18_FN, FN_IP0_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) GP_0_17_FN, FN_IP0_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) GP_0_16_FN, FN_IP0_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) GP_0_15_FN, FN_IP0_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) GP_0_14_FN, FN_IP0_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) GP_0_13_FN, FN_IP0_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) GP_0_12_FN, FN_IP0_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) GP_0_11_FN, FN_IP0_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) GP_0_10_FN, FN_IP0_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) GP_0_9_FN, FN_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) GP_0_8_FN, FN_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) GP_0_7_FN, FN_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) GP_0_6_FN, FN_IP0_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) GP_0_5_FN, FN_IP0_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) GP_0_4_FN, FN_IP0_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) GP_0_3_FN, FN_IP0_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) GP_0_2_FN, FN_PENC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) GP_0_1_FN, FN_PENC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) GP_0_0_FN, FN_IP0_1_0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) GP_1_31_FN, FN_IP4_6_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) GP_1_30_FN, FN_IP4_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) GP_1_29_FN, FN_IP4_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) GP_1_28_FN, FN_IP3_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) GP_1_27_FN, FN_IP3_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) GP_1_26_FN, FN_IP3_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) GP_1_25_FN, FN_IP3_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) GP_1_24_FN, FN_IP3_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) GP_1_23_FN, FN_IP3_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) GP_1_22_FN, FN_IP3_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) GP_1_21_FN, FN_IP3_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) GP_1_20_FN, FN_IP3_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) GP_1_19_FN, FN_IP3_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) GP_1_18_FN, FN_IP3_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) GP_1_17_FN, FN_IP3_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) GP_1_16_FN, FN_IP3_7_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) GP_1_15_FN, FN_IP3_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) GP_1_14_FN, FN_IP3_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) GP_1_13_FN, FN_IP2_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) GP_1_12_FN, FN_IP2_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) GP_1_11_FN, FN_IP2_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) GP_1_10_FN, FN_IP2_16_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) GP_1_9_FN, FN_IP2_13_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) GP_1_8_FN, FN_IP2_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) GP_1_7_FN, FN_IP2_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) GP_1_6_FN, FN_IP2_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) GP_1_5_FN, FN_IP2_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) GP_1_4_FN, FN_IP1_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) GP_1_3_FN, FN_IP1_27_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) GP_1_2_FN, FN_IP1_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) GP_1_1_FN, FN_WE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) GP_1_0_FN, FN_IP1_23_21 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) GP_2_31_FN, FN_IP6_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) GP_2_30_FN, FN_IP6_6_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) GP_2_29_FN, FN_IP6_4_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) GP_2_28_FN, FN_IP6_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) GP_2_27_FN, FN_IP5_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) GP_2_26_FN, FN_IP5_28_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) GP_2_25_FN, FN_IP5_25_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) GP_2_24_FN, FN_IP5_22_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) GP_2_23_FN, FN_AUDIO_CLKB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) GP_2_22_FN, FN_AUDIO_CLKA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) GP_2_21_FN, FN_IP5_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) GP_2_20_FN, FN_IP5_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) GP_2_19_FN, FN_IP5_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) GP_2_18_FN, FN_IP5_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) GP_2_17_FN, FN_IP5_11_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) GP_2_16_FN, FN_IP5_9_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) GP_2_15_FN, FN_IP5_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) GP_2_14_FN, FN_IP5_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) GP_2_13_FN, FN_IP5_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) GP_2_12_FN, FN_IP5_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) GP_2_11_FN, FN_IP5_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) GP_2_10_FN, FN_IP4_30_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) GP_2_9_FN, FN_IP4_28_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) GP_2_8_FN, FN_IP4_26_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) GP_2_7_FN, FN_IP4_24_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) GP_2_6_FN, FN_IP4_20_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) GP_2_5_FN, FN_IP4_16_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) GP_2_4_FN, FN_IP4_14_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) GP_2_3_FN, FN_IP4_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) GP_2_2_FN, FN_IP4_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) GP_2_1_FN, FN_IP4_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) GP_2_0_FN, FN_IP4_7 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) GP_3_31_FN, FN_IP8_10_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) GP_3_30_FN, FN_IP8_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) GP_3_29_FN, FN_IP8_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) GP_3_28_FN, FN_IP8_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) GP_3_27_FN, FN_IP7_31_29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) GP_3_26_FN, FN_IP7_28_25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) GP_3_25_FN, FN_IP7_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) GP_3_24_FN, FN_IP7_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) GP_3_23_FN, FN_IP7_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) GP_3_22_FN, FN_IP7_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) GP_3_21_FN, FN_IP7_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) GP_3_20_FN, FN_IP7_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) GP_3_19_FN, FN_IP7_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) GP_3_18_FN, FN_IP7_5_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) GP_3_17_FN, FN_IP7_3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) GP_3_16_FN, FN_IP7_1_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) GP_3_15_FN, FN_IP6_31_30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) GP_3_14_FN, FN_IP6_29_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) GP_3_13_FN, FN_IP6_27_26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) GP_3_12_FN, FN_IP6_25_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) GP_3_11_FN, FN_IP6_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) GP_3_10_FN, FN_IP6_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) GP_3_9_FN, FN_IP6_20_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) GP_3_8_FN, FN_IP6_18_17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) GP_3_7_FN, FN_IP6_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) GP_3_6_FN, FN_IP6_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) GP_3_5_FN, FN_IP6_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) GP_3_4_FN, FN_IP6_12_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) GP_3_3_FN, FN_IP6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) GP_3_2_FN, FN_SSI_SCK34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) GP_3_1_FN, FN_IP6_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) GP_3_0_FN, FN_IP6_8 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) GP_4_26_FN, FN_AVS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) GP_4_25_FN, FN_AVS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) GP_4_24_FN, FN_IP10_24_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) GP_4_23_FN, FN_IP10_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) GP_4_22_FN, FN_IP10_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) GP_4_21_FN, FN_IP10_15_13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) GP_4_20_FN, FN_IP10_12_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) GP_4_19_FN, FN_IP10_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) GP_4_18_FN, FN_IP10_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) GP_4_17_FN, FN_IP10_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) GP_4_16_FN, FN_IP9_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) GP_4_15_FN, FN_IP9_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) GP_4_14_FN, FN_IP9_23_21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) GP_4_13_FN, FN_IP9_20_18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) GP_4_12_FN, FN_IP9_17_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) GP_4_11_FN, FN_IP9_14_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) GP_4_10_FN, FN_IP9_11_9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) GP_4_9_FN, FN_IP9_8_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) GP_4_8_FN, FN_IP9_5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) GP_4_7_FN, FN_IP9_2_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) GP_4_6_FN, FN_IP8_29_27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) GP_4_5_FN, FN_IP8_26_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) GP_4_4_FN, FN_IP8_23_22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) GP_4_3_FN, FN_IP8_21_19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) GP_4_2_FN, FN_IP8_18_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) GP_4_1_FN, FN_IP8_15_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) GP_4_0_FN, FN_IP8_13_11 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) 1, 1, 1, 1, 1, 3, 4, 3, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) /* IP0_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) /* IP0_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) FN_A19, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* IP0_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) FN_A18, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) /* IP0_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) FN_A17, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) /* IP0_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) FN_A16, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* IP0_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) FN_A15, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) /* IP0_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) FN_A14, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) /* IP0_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) FN_A13, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) /* IP0_23 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) FN_A12, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) /* IP0_22 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) FN_A11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) /* IP0_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) FN_A10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) /* IP0_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) FN_A9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) /* IP0_19 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) FN_A8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* IP0_18 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) FN_A7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* IP0_17 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) FN_A6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) /* IP0_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) FN_A5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) /* IP0_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) FN_A4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* IP0_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) FN_SD1_DAT3_A, FN_MMC_D3, 0, FN_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) FN_ATAG0_A, 0, FN_REMOCON_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) /* IP0_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) FN_SD1_DAT2_A, FN_MMC_D2, 0, FN_BS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) FN_ATADIR0_A, 0, FN_SDSELF_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) FN_PWM4_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /* IP0_7_5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) FN_AUDATA1, FN_ARM_TRACEDATA_1, FN_GPSIN_C, FN_USB_OVC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) FN_RX2_E, FN_SCL2_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) /* IP0_4_2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) FN_AUDATA0, FN_ARM_TRACEDATA_0, FN_GPSCLK_C, FN_USB_OVC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) FN_TX2_E, FN_SDA2_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) /* IP0_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) FN_PRESETOUT, 0, FN_PWM1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) GROUP(1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) 3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* IP1_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) /* IP1_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) /* IP1_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) FN_EX_CS1, FN_MMC_D4, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* IP1_27_25 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) FN_SSI_WS1_B, FN_EX_CS0, FN_SCL2_A, FN_TX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) FN_TS_SCK0_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) /* IP1_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) FN_WE1, FN_ATAWR0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) /* IP1_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) FN_MMC_D5, FN_ATADIR0_B, 0, FN_RD_WR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* IP1_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) FN_SSI_SCK1_B, FN_ATAG0_B, FN_CS1_A26, FN_SDA2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) FN_SCK2_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) /* IP1_17 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) FN_CS0, FN_HSPI_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* IP1_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) FN_CLKOUT, FN_HSPI_TX1_B, FN_PWM0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /* IP1_14_11 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) FN_SD1_WP_A, FN_MMC_D7, 0, FN_A25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) FN_DACK1_A, 0, FN_HCTS0_B, FN_RX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) FN_TS_SDAT0_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) /* IP1_10_8 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) FN_SD1_CD_A, FN_MMC_D6, 0, FN_A24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) FN_DREQ1_A, 0, FN_HRX0_B, FN_TS_SPSYNC0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* IP1_7_5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) FN_A23, FN_HTX0_B, FN_TX2_B, FN_DACK2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) FN_TS_SDEN0_A, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) /* IP1_4_2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) FN_A22, FN_HRTS0_B, FN_RX2_B, FN_DREQ2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) /* IP1_1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) FN_A21, FN_HSPI_CLK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /* IP1_0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) FN_A20, FN_HSPI_CS1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) 1, 1, 1, 3, 2, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* IP2_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) FN_MLB_CLK, FN_IRQ1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* IP2_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) FN_RD_WR_B, FN_IRQ0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) /* IP2_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) FN_D11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) /* IP2_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) FN_D10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) /* IP2_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) FN_D9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) /* IP2_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) FN_D8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) /* IP2_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) FN_D7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) /* IP2_24 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) FN_D6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /* IP2_23 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) FN_D5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) /* IP2_22 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) FN_D4, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) /* IP2_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) FN_D3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) /* IP2_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) FN_D2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* IP2_19 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) FN_D1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) /* IP2_18 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) FN_D0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /* IP2_17 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) FN_EX_WAIT0, FN_PWM0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) /* IP2_16_14 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) FN_DACK0, 0, 0, FN_TX3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) FN_DRACK0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* IP2_13_12 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) FN_DREQ0_A, 0, 0, FN_RX3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) /* IP2_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) FN_SD1_DAT1_A, FN_MMC_D1, 0, FN_ATAWR0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) FN_EX_CS5, FN_EX_WAIT2_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /* IP2_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) FN_SD1_DAT0_A, FN_MMC_D0, 0, FN_ATARD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) FN_EX_CS4, FN_EX_WAIT1_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) /* IP2_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) FN_SD1_CMD_A, FN_MMC_CMD, 0, FN_ATACS10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) FN_EX_CS3, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) /* IP2_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) FN_SD1_CLK_A, FN_MMC_CLK, 0, FN_ATACS00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) FN_EX_CS2, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) GROUP(1, 1, 1, 1, 1, 3, 3, 2, 3, 3, 3, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) 3, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) /* IP3_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) FN_DU0_DR6, FN_LCDOUT6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) /* IP3_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) FN_DU0_DR5, FN_LCDOUT5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) /* IP3_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) FN_DU0_DR4, FN_LCDOUT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) /* IP3_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) FN_DU0_DR3, FN_LCDOUT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) /* IP3_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) FN_DU0_DR2, FN_LCDOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /* IP3_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) FN_SSI_WS4, FN_DU0_DR1, FN_LCDOUT1, FN_AUDATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) FN_ARM_TRACEDATA_3, FN_SCL3_C, FN_ADICHS2, FN_TS_SPSYNC0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) /* IP3_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) FN_SSI_SCK4, FN_DU0_DR0, FN_LCDOUT0, FN_AUDATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) FN_ARM_TRACEDATA_2, FN_SDA3_C, FN_ADICHS1, FN_TS_SDEN0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) /* IP3_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) FN_SD1_DAT3_B, FN_HRTS0_A, FN_RTS0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* IP3_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) FN_SD1_DAT2_B, FN_HCTS0_A, FN_CTS0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) /* IP3_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) FN_SD1_DAT1_B, FN_HSCK0, FN_SCK0, FN_SCL3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) /* IP3_12_10 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) FN_SD1_DAT0_B, FN_HRX0_A, FN_RX0_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* IP3_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) FN_SD1_CLK_B, FN_HTX0_A, FN_TX0_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /* IP3_7_5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) FN_SD1_CMD_B, FN_SCIF_CLK, FN_AUDIO_CLKOUT_B, FN_CAN_CLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) FN_SDA3_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* IP3_4_2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) FN_MLB_DAT, FN_TX5_B, FN_SCL3_A, FN_IRQ3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) FN_SDSELF_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) /* IP3_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) FN_MLB_SIG, FN_RX5_B, FN_SDA3_A, FN_IRQ2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) GROUP(1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) 3, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) /* IP4_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) /* IP4_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) FN_VI0_R4_B, FN_DU0_DB4, FN_LCDOUT20, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) /* IP4_28_27 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) FN_VI0_R3_B, FN_DU0_DB3, FN_LCDOUT19, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) /* IP4_26_25 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) FN_VI0_R2_B, FN_DU0_DB2, FN_LCDOUT18, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) /* IP4_24_21 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) FN_AUDIO_CLKC, FN_VI0_R1_B, FN_DU0_DB1, FN_LCDOUT17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) FN_AUDATA7, FN_ARM_TRACEDATA_7, FN_GPSIN_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) FN_ADICS_SAMP, FN_TS_SCK0_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) /* IP4_20_17 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) FN_SSI_SCK2_B, FN_VI0_R0_B, FN_DU0_DB0, FN_LCDOUT16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) FN_AUDATA6, FN_ARM_TRACEDATA_6, FN_GPSCLK_A, FN_PWM0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) FN_ADICLK, FN_TS_SDAT0_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /* IP4_16_15 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) FN_DU0_DG7, FN_LCDOUT15, FN_TX4_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) /* IP4_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) FN_DU0_DG6, FN_LCDOUT14, FN_RX4_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) /* IP4_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) FN_DU0_DG5, FN_LCDOUT13, FN_TX0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) /* IP4_10_9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) FN_DU0_DG4, FN_LCDOUT12, FN_RX0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) /* IP4_8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) FN_DU0_DG3, FN_LCDOUT11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) /* IP4_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) FN_DU0_DG2, FN_LCDOUT10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) /* IP4_6_4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) FN_DU0_DG1, FN_LCDOUT9, FN_AUDATA5, FN_ARM_TRACEDATA_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) FN_RX1_D, FN_CAN0_RX_A, FN_ADIDATA, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) /* IP4_3_1 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) FN_DU0_DG0, FN_LCDOUT8, FN_AUDATA4, FN_ARM_TRACEDATA_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) FN_TX1_D, FN_CAN0_TX_A, FN_ADICHS0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) /* IP4_0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) FN_DU0_DR7, FN_LCDOUT7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) GROUP(1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) 1, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) /* IP5_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) /* IP5_30_29 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) FN_SSI_SDATA7, FN_HSPI_TX0_B, FN_RX2_A, FN_CAN0_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) /* IP5_28_26 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) FN_SSI_SDATA8, FN_SSI_SCK2_A, FN_HSPI_CS0_B, FN_TX2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) FN_CAN0_TX_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) /* IP5_25_23 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) FN_SD1_WP_B, FN_SSI_WS78, FN_HSPI_CLK0_B, FN_RX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) FN_CAN_CLK_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) /* IP5_22_21 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) FN_SD1_CD_B, FN_SSI_SCK78, FN_HSPI_RX0_B, FN_TX1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) /* IP5_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) FN_SSI_WS1_A, FN_DU0_CDE, FN_QPOLB, FN_AUDSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) FN_ARM_TRACECTL, FN_FMIN_D, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) /* IP5_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) FN_SSI_SCK1_A, FN_DU0_DISP, FN_QPOLA, FN_AUDCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) FN_ARM_TRACECLK, FN_BPFCLK_D, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /* IP5_14_13 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) FN_FMCLK_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) /* IP5_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /* IP5_11_10 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) FN_SSI_WS2_B, FN_DU0_EXHSYNC_DU0_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) FN_QSTH_QHS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) /* IP5_9_8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) FN_DU0_DOTCLKO_UT1, FN_QSTVB_QVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) FN_AUDIO_CLKOUT_A, FN_REMOCON_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) /* IP5_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) FN_DU0_DOTCLKO_UT0, FN_QCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /* IP5_6 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) FN_DU0_DOTCLKIN, FN_QSTVA_QVS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* IP5_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) FN_VI1_DATA11_B, FN_DU0_DB7, FN_LCDOUT23, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) /* IP5_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) FN_VI1_DATA10_B, FN_DU0_DB6, FN_LCDOUT22, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) /* IP5_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) FN_VI0_R5_B, FN_DU0_DB5, FN_LCDOUT21, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) GROUP(2, 2, 2, 2, 2, 1, 2, 2, 1, 2, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) 1, 1, 1, 1, 2, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) /* IP6_31_30 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) FN_SD0_DAT2, 0, FN_SUB_TDI, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) /* IP6_29_28 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) FN_SD0_DAT1, 0, FN_SUB_TCK, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) /* IP6_27_26 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) FN_SD0_DAT0, 0, FN_SUB_TMS, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) /* IP6_25_24 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) FN_SD0_CMD, 0, FN_SUB_TRST, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) /* IP6_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) FN_SD0_CLK, 0, FN_SUB_TDO, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) /* IP6_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) FN_SSI_SDATA0, FN_ARM_TRACEDATA_15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) /* IP6_20_19 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) FN_SSI_SDATA1, FN_ARM_TRACEDATA_14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) FN_SCL1_A, FN_SCK2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* IP6_18_17 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) FN_SSI_SDATA2, FN_HSPI_CS2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) FN_ARM_TRACEDATA_13, FN_SDA1_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) /* IP6_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) FN_SSI_WS012, FN_ARM_TRACEDATA_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) /* IP6_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) FN_SSI_SCK012, FN_ARM_TRACEDATA_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) FN_TX0_D, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) /* IP6_13 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) FN_SSI_SDATA3, FN_ARM_TRACEDATA_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) /* IP6_12_11 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) FN_SSI_SDATA4, FN_SSI_WS2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) FN_ARM_TRACEDATA_9, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) /* IP6_10 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) FN_SSI_WS34, FN_ARM_TRACEDATA_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* IP6_9 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) FN_SSI_SDATA5, FN_RX0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) /* IP6_8 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) FN_SSI_WS5, FN_TX4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) /* IP6_7 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) FN_SSI_SCK5, FN_RX4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* IP6_6_5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) FN_SSI_SDATA6, FN_HSPI_TX2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) FN_FMIN_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* IP6_4_2 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) FN_SSI_WS6, FN_HSPI_CLK2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) FN_BPFCLK_B, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) /* IP6_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) FN_SSI_SCK6, FN_HSPI_RX2_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) FN_FMCLK_B, FN_CAN1_TX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) GROUP(3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) /* IP7_31_29 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) FN_VI0_HSYNC, FN_SD2_CD_B, FN_VI1_DATA2, FN_DU1_DR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) 0, FN_HSPI_CS1_A, FN_RX3_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) /* IP7_28_25 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) FN_VI0_FIELD, FN_SD2_DAT3_B, FN_VI0_R3_C, FN_VI1_DATA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) FN_DU1_DG7, 0, FN_HSPI_CLK1_A, FN_TX4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /* IP7_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) FN_VI0_CLKENB, FN_SD2_DAT2_B, FN_VI1_DATA0, FN_DU1_DG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) 0, FN_HSPI_RX1_A, FN_RX4_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) /* IP7_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) FN_VI0_CLK, FN_CAN_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) /* IP7_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) FN_TCLK0, FN_HSCK1_A, FN_FMIN_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) FN_IRQ2_C, FN_CTS1_C, FN_SPEEDIN, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) /* IP7_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) FN_VI1_VSYNC, FN_HSPI_TX0, FN_HCTS1_A, FN_BPFCLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) 0, FN_TX1_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) /* IP7_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) FN_VI1_HSYNC, FN_HSPI_RX0_A, FN_HRTS1_A, FN_FMCLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) 0, FN_RX1_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) /* IP7_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) FN_VI1_FIELD, FN_HSPI_CS0_A, FN_HRX1_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) FN_SCK1_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) /* IP7_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) FN_VI1_CLKENB, FN_HSPI_CLK0_A, FN_HTX1_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) FN_RTS1_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* IP7_5_4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) FN_SD0_WP, 0, FN_RX5_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* IP7_3_2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) FN_SD0_CD, 0, FN_TX5_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) /* IP7_1_0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) FN_SD0_DAT3, 0, FN_IRQ1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) GROUP(1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) /* IP8_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) /* IP8_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) /* IP8_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) FN_VI0_G3, FN_SD2_CMD_B, FN_VI1_DATA5, FN_DU1_DR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) 0, FN_HRX1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) /* IP8_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) FN_VI0_G2, FN_SD2_CLK_B, FN_VI1_DATA4, FN_DU1_DR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) 0, FN_HTX1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) /* IP8_23_22 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) FN_VI0_DATA7_VI0_G1, FN_DU1_DB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) FN_RTS1_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) /* IP8_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) FN_VI0_DATA6_VI0_G0, FN_DU1_DB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) FN_CTS1_A, FN_PWM5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) /* IP8_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) FN_VI0_DATA5_VI0_B5, FN_DU1_DB3, FN_SCK1_A, FN_PWM4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) 0, FN_HSCK1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* IP8_15_14 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) FN_VI0_DATA4_VI0_B4, FN_DU1_DB2, FN_RX1_A, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) /* IP8_13_11 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) FN_VI0_DATA3_VI0_B3, FN_DU1_DG5, FN_TX1_A, FN_TX0_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) /* IP8_10_9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) FN_VI0_DATA2_VI0_B2, FN_DU1_DG4, FN_RX0_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* IP8_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) FN_VI0_DATA1_VI0_B1, FN_DU1_DG3, FN_IRQ3_B, FN_TX3_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) /* IP8_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) FN_VI0_DATA0_VI0_B0, FN_DU1_DG2, FN_IRQ2_B, FN_RX3_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) /* IP8_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) FN_VI0_VSYNC, FN_SD2_WP_B, FN_VI1_DATA3, FN_DU1_DR3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) 0, FN_HSPI_TX1_A, FN_TX3_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) GROUP(1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* IP9_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /* IP9_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) /* IP9_29_27 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) FN_VI1_DATA11_A, FN_DU1_EXHSYNC_DU1_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) FN_ETH_RXD1, FN_FMIN_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) 0, FN_RX2_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) FN_SCL2_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /* IP9_26_24 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) FN_VI1_DATA10_A, FN_DU1_DOTCLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) FN_ETH_RXD0, FN_BPFCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) 0, FN_TX2_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) FN_SDA2_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* IP9_23_21 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) FN_VI0_R5_A, 0, FN_ETH_RX_ER, FN_FMCLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) FN_IERX, FN_RX2_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* IP9_20_18 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) FN_VI0_R4_A, FN_ETH_TX_EN, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) FN_IETX, FN_TX2_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) /* IP9_17_15 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) FN_VI0_R3_A, FN_ETH_CRS_DV, 0, FN_IECLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) FN_SCK2_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /* IP9_14_12 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) FN_VI0_R2_A, FN_VI1_DATA9, FN_DU1_DB7, FN_ETH_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) 0, FN_PWM3, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) /* IP9_11_9 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) FN_VI0_R1_A, FN_VI1_DATA8, FN_DU1_DB6, FN_ETH_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) 0, FN_PWM2, FN_TCLK1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /* IP9_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) FN_VI0_R0_A, FN_VI1_CLK, FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /* IP9_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) FN_VI0_G5, FN_SD2_DAT1_B, FN_VI1_DATA7, FN_DU1_DR7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) 0, FN_HCTS1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) /* IP9_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) FN_VI0_G4, FN_SD2_DAT0_B, FN_VI1_DATA6, FN_DU1_DR6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) 0, FN_HRTS1_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) GROUP(1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) 3, 3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) /* IP10_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) /* IP10_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) /* IP10_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) /* IP10_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* IP10_27 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) /* IP10_26 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) /* IP10_25 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) /* IP10_24_22 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) FN_SD2_WP_A, FN_VI1_DATA15, FN_EX_WAIT2_B, FN_DACK0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) FN_HSPI_TX2_B, FN_CAN_CLK_C, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) /* IP10_21_19 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) FN_SD2_CD_A, FN_VI1_DATA14, FN_EX_WAIT1_B, FN_DREQ0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) FN_HSPI_RX2_B, FN_REMOCON_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) /* IP10_18_16 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) FN_SD2_DAT3_A, FN_VI1_DATA13, FN_DACK2_B, FN_ATAG1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) FN_HSPI_CS2_B, FN_GPSIN_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) /* IP10_15_13 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) FN_SD2_DAT2_A, FN_VI1_DATA12, FN_DREQ2_B, FN_ATADIR1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) FN_HSPI_CLK2_B, FN_GPSCLK_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) /* IP10_12_9 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) FN_SD2_DAT1_A, FN_DU1_CDE, FN_ATACS11, FN_DACK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) FN_ETH_MAGIC, FN_CAN1_TX_A, 0, FN_PWM6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) /* IP10_8_6 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) FN_SD2_DAT0_A, FN_DU1_DISP, FN_ATACS01, FN_DREQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) FN_ETH_LINK, FN_CAN1_RX_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) /* IP10_5_3 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) FN_SD2_CMD_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) FN_ATAWR1, FN_ETH_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) FN_SCL1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* IP10_2_0 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) FN_SD2_CLK_A, FN_DU1_EXVSYNC_DU1_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) FN_ATARD1, FN_ETH_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) FN_SDA1_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) GROUP(1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* SEL 31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) /* SEL_30 (SCIF5) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) /* SEL_29_28 (SCIF4) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) FN_SEL_SCIF4_A, FN_SEL_SCIF4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) FN_SEL_SCIF4_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) /* SEL_27_26 (SCIF3) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) FN_SEL_SCIF3_A, FN_SEL_SCIF3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* SEL_25_23 (SCIF2) [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) FN_SEL_SCIF2_A, FN_SEL_SCIF2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) FN_SEL_SCIF2_C, FN_SEL_SCIF2_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) FN_SEL_SCIF2_E, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) /* SEL_22_21 (SCIF1) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) FN_SEL_SCIF1_A, FN_SEL_SCIF1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) /* SEL_20_19 (SCIF0) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) FN_SEL_SCIF0_A, FN_SEL_SCIF0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) /* SEL_18 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) /* SEL_17 (SSI2) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) FN_SEL_SSI2_A, FN_SEL_SSI2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /* SEL_16 (SSI1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) FN_SEL_SSI1_A, FN_SEL_SSI1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* SEL_15 (VI1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) FN_SEL_VI1_A, FN_SEL_VI1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /* SEL_14_13 (VI0) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) FN_SEL_VI0_A, FN_SEL_VI0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) FN_SEL_VI0_C, FN_SEL_VI0_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* SEL_12 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) /* SEL_11 (SD2) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) FN_SEL_SD2_A, FN_SEL_SD2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) /* SEL_10 (SD1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) FN_SEL_SD1_A, FN_SEL_SD1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) /* SEL_9 (IRQ3) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) FN_SEL_IRQ3_A, FN_SEL_IRQ3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) /* SEL_8_7 (IRQ2) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) FN_SEL_IRQ2_A, FN_SEL_IRQ2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) FN_SEL_IRQ2_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* SEL_6 (IRQ1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) FN_SEL_IRQ1_A, FN_SEL_IRQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) /* SEL_5 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) /* SEL_4 (DREQ2) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) /* SEL_3 (DREQ1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) /* SEL_2 (DREQ0) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) /* SEL_1 (WAIT2) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) /* SEL_0 (WAIT1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) GROUP(1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) 1, 1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) /* SEL_31 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) /* SEL_30 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) /* SEL_29 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) /* SEL_28 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /* SEL_27 (CAN1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) FN_SEL_CAN1_A, FN_SEL_CAN1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) /* SEL_26 (CAN0) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) FN_SEL_CAN0_A, FN_SEL_CAN0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) /* SEL_25_24 (CANCLK) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) FN_SEL_CANCLK_A, FN_SEL_CANCLK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) FN_SEL_CANCLK_C, FN_SEL_CANCLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /* SEL_23 (HSCIF1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) FN_SEL_HSCIF1_A, FN_SEL_HSCIF1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) /* SEL_22 (HSCIF0) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) FN_SEL_HSCIF0_A, FN_SEL_HSCIF0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) /* SEL_21 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) /* SEL_20 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) /* SEL_19 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) /* SEL_18 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /* SEL_17 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) /* SEL_16 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) /* SEL_15 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) /* SEL_14_13 (REMOCON) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) FN_SEL_REMOCON_A, FN_SEL_REMOCON_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) FN_SEL_REMOCON_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) /* SEL_12_11 (FM) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) FN_SEL_FM_A, FN_SEL_FM_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) FN_SEL_FM_C, FN_SEL_FM_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) /* SEL_10_9 (GPS) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) FN_SEL_GPS_A, FN_SEL_GPS_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) FN_SEL_GPS_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) /* SEL_8 (TSIF0) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /* SEL_7 (HSPI2) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) /* SEL_6 (HSPI1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) /* SEL_5 (HSPI0) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /* SEL_4_3 (I2C3) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) FN_SEL_I2C3_A, FN_SEL_I2C3_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) FN_SEL_I2C3_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) /* SEL_2_1 (I2C2) [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) FN_SEL_I2C2_A, FN_SEL_I2C2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) FN_SEL_I2C2_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) /* SEL_0 (I2C1) [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) FN_SEL_I2C1_A, FN_SEL_I2C1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) static const struct pinmux_bias_reg pinmux_bias_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) { PINMUX_BIAS_REG("PUPR0", 0x100, "N/A", 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) [ 0] = RCAR_GP_PIN(0, 6), /* A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) [ 1] = RCAR_GP_PIN(0, 7), /* A1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) [ 2] = RCAR_GP_PIN(0, 8), /* A2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) [ 3] = RCAR_GP_PIN(0, 9), /* A3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) [ 4] = RCAR_GP_PIN(0, 10), /* A4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) [ 5] = RCAR_GP_PIN(0, 11), /* A5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) [ 6] = RCAR_GP_PIN(0, 12), /* A6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) [ 7] = RCAR_GP_PIN(0, 13), /* A7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) [ 8] = RCAR_GP_PIN(0, 14), /* A8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) [ 9] = RCAR_GP_PIN(0, 15), /* A9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) [10] = RCAR_GP_PIN(0, 16), /* A10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) [11] = RCAR_GP_PIN(0, 17), /* A11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) [12] = RCAR_GP_PIN(0, 18), /* A12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) [13] = RCAR_GP_PIN(0, 19), /* A13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) [14] = RCAR_GP_PIN(0, 20), /* A14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) [15] = RCAR_GP_PIN(0, 21), /* A15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) [16] = RCAR_GP_PIN(0, 22), /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) [17] = RCAR_GP_PIN(0, 23), /* A17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) [18] = RCAR_GP_PIN(0, 24), /* A18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) [19] = RCAR_GP_PIN(0, 25), /* A19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) [20] = RCAR_GP_PIN(0, 26), /* A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) [21] = RCAR_GP_PIN(0, 27), /* A21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) [22] = RCAR_GP_PIN(0, 28), /* A22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) [23] = RCAR_GP_PIN(0, 29), /* A23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) [24] = RCAR_GP_PIN(0, 30), /* A24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) [25] = RCAR_GP_PIN(0, 31), /* A25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) [26] = RCAR_GP_PIN(1, 3), /* /EX_CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) [27] = RCAR_GP_PIN(1, 4), /* /EX_CS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) [28] = RCAR_GP_PIN(1, 5), /* /EX_CS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) [29] = RCAR_GP_PIN(1, 6), /* /EX_CS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) [30] = RCAR_GP_PIN(1, 7), /* /EX_CS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) [31] = RCAR_GP_PIN(1, 8), /* /EX_CS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) { PINMUX_BIAS_REG("PUPR1", 0x104, "N/A", 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) [ 0] = RCAR_GP_PIN(0, 0), /* /PRESETOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) [ 1] = RCAR_GP_PIN(0, 5), /* /BS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) [ 2] = RCAR_GP_PIN(1, 0), /* RD//WR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) [ 3] = RCAR_GP_PIN(1, 1), /* /WE0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) [ 4] = RCAR_GP_PIN(1, 2), /* /WE1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) [ 5] = RCAR_GP_PIN(1, 11), /* EX_WAIT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) [ 6] = RCAR_GP_PIN(1, 9), /* DREQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) [ 7] = RCAR_GP_PIN(1, 10), /* DACK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) [ 8] = RCAR_GP_PIN(1, 12), /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) [ 9] = RCAR_GP_PIN(1, 13), /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) [10] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) [11] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) [12] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) [13] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) [14] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) [15] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) [16] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) [17] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) [18] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) [19] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) [20] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) [21] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) [22] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) [23] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) [24] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) [25] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) [26] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) [27] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) [28] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) [29] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) [30] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) [31] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) { PINMUX_BIAS_REG("PUPR2", 0x108, "N/A", 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) [ 0] = RCAR_GP_PIN(1, 22), /* DU0_DR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) [ 1] = RCAR_GP_PIN(1, 23), /* DU0_DR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) [ 2] = RCAR_GP_PIN(1, 24), /* DU0_DR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) [ 3] = RCAR_GP_PIN(1, 25), /* DU0_DR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) [ 4] = RCAR_GP_PIN(1, 26), /* DU0_DR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) [ 5] = RCAR_GP_PIN(1, 27), /* DU0_DR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) [ 6] = RCAR_GP_PIN(1, 28), /* DU0_DR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) [ 7] = RCAR_GP_PIN(1, 29), /* DU0_DR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) [ 8] = RCAR_GP_PIN(1, 30), /* DU0_DG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) [ 9] = RCAR_GP_PIN(1, 31), /* DU0_DG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) [10] = RCAR_GP_PIN(2, 0), /* DU0_DG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) [11] = RCAR_GP_PIN(2, 1), /* DU0_DG3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) [12] = RCAR_GP_PIN(2, 2), /* DU0_DG4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) [13] = RCAR_GP_PIN(2, 3), /* DU0_DG5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) [14] = RCAR_GP_PIN(2, 4), /* DU0_DG6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) [15] = RCAR_GP_PIN(2, 5), /* DU0_DG7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) [16] = RCAR_GP_PIN(2, 6), /* DU0_DB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) [17] = RCAR_GP_PIN(2, 7), /* DU0_DB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) [18] = RCAR_GP_PIN(2, 8), /* DU0_DB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) [19] = RCAR_GP_PIN(2, 9), /* DU0_DB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) [20] = RCAR_GP_PIN(2, 10), /* DU0_DB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) [21] = RCAR_GP_PIN(2, 11), /* DU0_DB5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) [22] = RCAR_GP_PIN(2, 12), /* DU0_DB6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) [23] = RCAR_GP_PIN(2, 13), /* DU0_DB7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) [24] = RCAR_GP_PIN(2, 14), /* DU0_DOTCLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) [25] = RCAR_GP_PIN(2, 15), /* DU0_DOTCLKOUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) [26] = RCAR_GP_PIN(2, 17), /* DU0_HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) [27] = RCAR_GP_PIN(2, 18), /* DU0_VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) [28] = RCAR_GP_PIN(2, 19), /* DU0_EXODDF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) [29] = RCAR_GP_PIN(2, 20), /* DU0_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) [30] = RCAR_GP_PIN(2, 21), /* DU0_CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) [31] = RCAR_GP_PIN(2, 16), /* DU0_DOTCLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) { PINMUX_BIAS_REG("PUPR3", 0x10c, "N/A", 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) [ 0] = RCAR_GP_PIN(3, 24), /* VI0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) [ 1] = RCAR_GP_PIN(3, 25), /* VI0_CLKENB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) [ 2] = RCAR_GP_PIN(3, 26), /* VI0_FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) [ 3] = RCAR_GP_PIN(3, 27), /* /VI0_HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) [ 4] = RCAR_GP_PIN(3, 28), /* /VI0_VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) [ 5] = RCAR_GP_PIN(3, 29), /* VI0_DATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) [ 6] = RCAR_GP_PIN(3, 30), /* VI0_DATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) [ 7] = RCAR_GP_PIN(3, 31), /* VI0_DATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) [ 8] = RCAR_GP_PIN(4, 0), /* VI0_DATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) [ 9] = RCAR_GP_PIN(4, 1), /* VI0_DATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) [10] = RCAR_GP_PIN(4, 2), /* VI0_DATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) [11] = RCAR_GP_PIN(4, 3), /* VI0_DATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) [12] = RCAR_GP_PIN(4, 4), /* VI0_DATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) [13] = RCAR_GP_PIN(4, 5), /* VI0_G2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) [14] = RCAR_GP_PIN(4, 6), /* VI0_G3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) [15] = RCAR_GP_PIN(4, 7), /* VI0_G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) [16] = RCAR_GP_PIN(4, 8), /* VI0_G5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) [17] = RCAR_GP_PIN(4, 21), /* VI1_DATA12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) [18] = RCAR_GP_PIN(4, 22), /* VI1_DATA13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) [19] = RCAR_GP_PIN(4, 23), /* VI1_DATA14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) [20] = RCAR_GP_PIN(4, 24), /* VI1_DATA15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) [21] = RCAR_GP_PIN(4, 9), /* ETH_REF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) [22] = RCAR_GP_PIN(4, 10), /* ETH_TXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) [23] = RCAR_GP_PIN(4, 11), /* ETH_TXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) [24] = RCAR_GP_PIN(4, 12), /* ETH_CRS_DV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) [25] = RCAR_GP_PIN(4, 13), /* ETH_TX_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) [26] = RCAR_GP_PIN(4, 14), /* ETH_RX_ER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) [27] = RCAR_GP_PIN(4, 15), /* ETH_RXD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) [28] = RCAR_GP_PIN(4, 16), /* ETH_RXD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) [29] = RCAR_GP_PIN(4, 17), /* ETH_MDC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) [30] = RCAR_GP_PIN(4, 18), /* ETH_MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) [31] = RCAR_GP_PIN(4, 19), /* ETH_LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) { PINMUX_BIAS_REG("PUPR4", 0x110, "N/A", 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) [ 0] = RCAR_GP_PIN(3, 6), /* SSI_SCK012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) [ 1] = RCAR_GP_PIN(3, 7), /* SSI_WS012 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) [ 2] = RCAR_GP_PIN(3, 10), /* SSI_SDATA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) [ 3] = RCAR_GP_PIN(3, 9), /* SSI_SDATA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) [ 4] = RCAR_GP_PIN(3, 8), /* SSI_SDATA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) [ 5] = RCAR_GP_PIN(3, 2), /* SSI_SCK34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) [ 6] = RCAR_GP_PIN(3, 3), /* SSI_WS34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) [ 7] = RCAR_GP_PIN(3, 5), /* SSI_SDATA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) [ 8] = RCAR_GP_PIN(3, 4), /* SSI_SDATA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) [ 9] = RCAR_GP_PIN(2, 31), /* SSI_SCK5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) [10] = RCAR_GP_PIN(3, 0), /* SSI_WS5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) [11] = RCAR_GP_PIN(3, 1), /* SSI_SDATA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) [12] = RCAR_GP_PIN(2, 28), /* SSI_SCK6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) [13] = RCAR_GP_PIN(2, 29), /* SSI_WS6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) [14] = RCAR_GP_PIN(2, 30), /* SSI_SDATA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) [15] = RCAR_GP_PIN(2, 24), /* SSI_SCK78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) [16] = RCAR_GP_PIN(2, 25), /* SSI_WS78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) [17] = RCAR_GP_PIN(2, 27), /* SSI_SDATA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) [18] = RCAR_GP_PIN(2, 26), /* SSI_SDATA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) [19] = RCAR_GP_PIN(3, 23), /* TCLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) [20] = RCAR_GP_PIN(3, 11), /* SD0_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) [21] = RCAR_GP_PIN(3, 12), /* SD0_CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) [22] = RCAR_GP_PIN(3, 13), /* SD0_DAT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) [23] = RCAR_GP_PIN(3, 14), /* SD0_DAT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) [24] = RCAR_GP_PIN(3, 15), /* SD0_DAT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) [25] = RCAR_GP_PIN(3, 16), /* SD0_DAT3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) [26] = RCAR_GP_PIN(3, 17), /* SD0_CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) [27] = RCAR_GP_PIN(3, 18), /* SD0_WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) [28] = RCAR_GP_PIN(2, 22), /* AUDIO_CLKA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) [29] = RCAR_GP_PIN(2, 23), /* AUDIO_CLKB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) [30] = RCAR_GP_PIN(1, 14), /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) [31] = RCAR_GP_PIN(1, 15), /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) { PINMUX_BIAS_REG("PUPR5", 0x114, "N/A", 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) [ 0] = RCAR_GP_PIN(0, 1), /* PENC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) [ 1] = RCAR_GP_PIN(0, 2), /* PENC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) [ 2] = RCAR_GP_PIN(0, 3), /* USB_OVC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) [ 3] = RCAR_GP_PIN(0, 4), /* USB_OVC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) [ 4] = RCAR_GP_PIN(1, 16), /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) [ 5] = RCAR_GP_PIN(1, 17), /* TX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) [ 6] = RCAR_GP_PIN(1, 18), /* RX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) [ 7] = RCAR_GP_PIN(1, 19), /* SCK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) [ 8] = RCAR_GP_PIN(1, 20), /* /CTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) [ 9] = RCAR_GP_PIN(1, 21), /* /RTS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) [10] = RCAR_GP_PIN(3, 19), /* HSPI_CLK0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) [11] = RCAR_GP_PIN(3, 20), /* /HSPI_CS0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) [12] = RCAR_GP_PIN(3, 21), /* HSPI_RX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) [13] = RCAR_GP_PIN(3, 22), /* HSPI_TX0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) [14] = RCAR_GP_PIN(4, 20), /* ETH_MAGIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) [15] = RCAR_GP_PIN(4, 25), /* AVS1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) [16] = RCAR_GP_PIN(4, 26), /* AVS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) [17] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) [18] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) [19] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) [20] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) [21] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) [22] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) [23] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) [24] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) [25] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) [26] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) [27] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) [28] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) [29] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) [30] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) [31] = SH_PFC_PIN_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) static unsigned int r8a7778_pinmux_get_bias(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) const struct pinmux_bias_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) addr = pfc->windows->virt + reg->puen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) if (ioread32(addr) & BIT(bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) return PIN_CONFIG_BIAS_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static void r8a7778_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) unsigned int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) const struct pinmux_bias_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) if (!reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) addr = pfc->windows->virt + reg->puen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) value = ioread32(addr) & ~BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if (bias == PIN_CONFIG_BIAS_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) value |= BIT(bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) iowrite32(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) static const struct sh_pfc_soc_operations r8a7778_pfc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) .get_bias = r8a7778_pinmux_get_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) .set_bias = r8a7778_pinmux_set_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) const struct sh_pfc_soc_info r8a7778_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) .name = "r8a7778_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) .ops = &r8a7778_pfc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) .unlock_reg = 0xfffc0000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .bias_regs = pinmux_bias_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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