^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A77470 processor support - PFC hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2018 Renesas Electronics Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPU_ALL_GP(fn, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PORT_GP_4(0, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PORT_GP_1(0, 4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PORT_GP_CFG_1(0, 5, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PORT_GP_CFG_1(0, 6, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_GP_CFG_1(0, 7, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_GP_CFG_1(0, 8, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_GP_CFG_1(0, 9, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_GP_CFG_1(0, 10, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_GP_1(0, 11, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_GP_1(0, 12, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_GP_CFG_1(0, 13, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PORT_GP_CFG_1(0, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_GP_CFG_1(0, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_GP_CFG_1(0, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_GP_CFG_1(0, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_GP_CFG_1(0, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PORT_GP_CFG_1(0, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PORT_GP_CFG_1(0, 20, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PORT_GP_CFG_1(0, 21, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PORT_GP_CFG_1(0, 22, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PORT_GP_23(1, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PORT_GP_32(2, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PORT_GP_17(3, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PORT_GP_1(3, 27, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PORT_GP_1(3, 28, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PORT_GP_1(3, 29, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PORT_GP_14(4, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PORT_GP_CFG_1(4, 14, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PORT_GP_CFG_1(4, 15, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PORT_GP_CFG_1(4, 16, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PORT_GP_CFG_1(4, 17, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PORT_GP_CFG_1(4, 18, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PORT_GP_CFG_1(4, 19, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PORT_GP_1(4, 20, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PORT_GP_1(4, 21, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PORT_GP_1(4, 22, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PORT_GP_1(4, 23, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PORT_GP_1(4, 24, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PORT_GP_1(4, 25, fn, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PORT_GP_32(5, fn, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) GP_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) GP_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, FN_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FN_IP0_3_0, FN_IP0_7_4, FN_IP0_11_8, FN_IP0_15_12, FN_IP0_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FN_IP0_23_20, FN_IP0_27_24, FN_IP0_31_28, FN_MMC0_CLK_SDHI1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FN_MMC0_CMD_SDHI1_CMD, FN_MMC0_D0_SDHI1_D0, FN_MMC0_D1_SDHI1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FN_MMC0_D2_SDHI1_D2, FN_MMC0_D3_SDHI1_D3, FN_IP1_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FN_IP1_7_4, FN_MMC0_D6, FN_MMC0_D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) FN_IP1_11_8, FN_IP1_15_12, FN_IP1_19_16, FN_IP1_23_20, FN_IP1_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FN_IP1_31_28, FN_IP2_3_0, FN_IP2_7_4, FN_IP2_11_8, FN_IP2_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FN_IP2_19_16, FN_IP2_23_20, FN_IP2_27_24, FN_IP2_31_28, FN_IP3_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FN_IP3_7_4, FN_IP3_11_8, FN_IP3_15_12, FN_IP3_19_16, FN_IP3_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FN_IP3_27_24, FN_IP3_31_28, FN_IP4_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FN_IP4_7_4, FN_IP4_11_8, FN_IP4_15_12, FN_IP4_19_16, FN_IP4_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_IP4_27_24, FN_IP4_31_28, FN_IP5_3_0, FN_IP5_7_4, FN_IP5_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FN_IP5_15_12, FN_IP5_19_16, FN_IP5_23_20, FN_IP5_27_24, FN_IP5_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FN_IP6_3_0, FN_IP6_7_4, FN_IP6_11_8, FN_IP6_15_12, FN_IP6_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_IP6_23_20, FN_IP6_27_24, FN_IP6_31_28, FN_IP7_3_0, FN_IP7_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FN_IP7_11_8, FN_IP7_15_12, FN_IP7_19_16, FN_IP7_23_20, FN_IP7_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) FN_IP7_31_28, FN_IP8_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FN_IP8_7_4, FN_IP8_11_8, FN_IP8_15_12, FN_IP8_19_16, FN_IP8_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_IP8_27_24, FN_IP8_31_28, FN_IP9_3_0, FN_IP9_7_4, FN_IP9_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_IP9_15_12, FN_IP9_19_16, FN_IP9_23_20, FN_IP9_27_24, FN_IP9_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FN_IP10_3_0, FN_IP10_7_4, FN_IP10_11_8, FN_IP10_15_12, FN_IP10_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* GPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FN_IP10_23_20, FN_IP10_27_24, FN_IP10_31_28, FN_IP11_3_0, FN_IP11_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_IP11_11_8, FN_IP11_15_12, FN_IP11_19_16, FN_IP11_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FN_IP11_27_24, FN_IP11_31_28, FN_IP12_3_0, FN_IP12_7_4, FN_IP12_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) FN_IP12_15_12, FN_IP12_19_16, FN_IP12_23_20, FN_IP12_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) FN_IP12_31_28, FN_IP13_3_0, FN_IP13_7_4, FN_IP13_11_8, FN_IP13_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_IP13_19_16, FN_IP13_23_20, FN_IP13_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* GPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) FN_IP13_31_28, FN_IP14_3_0, FN_IP14_7_4, FN_IP14_11_8, FN_IP14_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) FN_IP14_19_16, FN_IP14_23_20, FN_IP14_27_24, FN_IP14_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FN_IP15_3_0, FN_IP15_7_4, FN_IP15_11_8, FN_IP15_15_12, FN_IP15_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) FN_IP15_23_20, FN_IP15_27_24, FN_IP15_31_28, FN_IP16_3_0, FN_IP16_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) FN_IP16_11_8, FN_IP16_15_12, FN_IP16_19_16, FN_IP16_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FN_IP16_27_24, FN_IP16_31_28, FN_IP17_3_0, FN_IP17_7_4, FN_IP17_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_IP17_15_12, FN_IP17_19_16, FN_IP17_23_20, FN_IP17_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_SD0_CLK, FN_SSI_SCK1_C, FN_RX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_SD0_CMD, FN_SSI_WS1_C, FN_TX3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_SD0_DAT0, FN_SSI_SDATA1_C, FN_RX4_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FN_SD0_DAT1, FN_SSI_SCK0129_B, FN_TX4_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) FN_SD0_DAT2, FN_SSI_WS0129_B, FN_RX5_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) FN_SD0_DAT3, FN_SSI_SDATA0_B, FN_TX5_E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FN_SD0_CD, FN_CAN0_RX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FN_MMC0_D4, FN_SD1_CD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) FN_MMC0_D5, FN_SD1_WP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FN_D0, FN_SCL3_B, FN_RX5_B, FN_IRQ4, FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_D1, FN_SDA3_B, FN_TX5_B, FN_MSIOF2_TXD_C, FN_SSI_WS5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) FN_D2, FN_RX4_B, FN_SCL0_D, FN_PWM1_C, FN_MSIOF2_SCK_C, FN_SSI_SCK5_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FN_D3, FN_TX4_B, FN_SDA0_D, FN_PWM0_A, FN_MSIOF2_SYNC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_D4, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, FN_CAN_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) FN_D13, FN_MSIOF2_SYNC_A, FN_RX4_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) FN_D14, FN_MSIOF2_SS1, FN_TX4_C, FN_CAN1_RX_B, FN_AVB_AVTP_CAPTURE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, FN_CAN1_TX_B, FN_IRQ2, FN_AVB_AVTP_MATCH_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) FN_QSPI0_SPCLK, FN_WE0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) FN_QSPI0_IO2, FN_CS0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) FN_QSPI0_IO3, FN_RD_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) FN_QSPI0_SSL, FN_WE1_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FN_DU0_DR0, FN_RX5_C, FN_SCL2_D, FN_A0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) FN_DU0_DR1, FN_TX5_C, FN_SDA2_D, FN_A1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) FN_DU0_DR2, FN_RX0_D, FN_SCL0_E, FN_A2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) FN_DU0_DR3, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, FN_A3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FN_DU0_DR4, FN_RX1_D, FN_A4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FN_DU0_DR5, FN_TX1_D, FN_PWM1_B, FN_A5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FN_DU0_DR6, FN_RX2_C, FN_A6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) FN_DU0_DR7, FN_TX2_C, FN_PWM2_B, FN_A7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) FN_DU0_DG0, FN_RX3_B, FN_SCL3_D, FN_A8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) FN_DU0_DG1, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, FN_A9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FN_DU0_DG2, FN_RX4_D, FN_A10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FN_DU0_DG3, FN_TX4_D, FN_PWM4_B, FN_A11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FN_DU0_DG4, FN_HRX0_A, FN_A12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FN_DU0_DG5, FN_HTX0_A, FN_PWM5_B, FN_A13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FN_DU0_DG6, FN_HRX1_C, FN_A14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) FN_DU0_DG7, FN_HTX1_C, FN_PWM6_B, FN_A15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) FN_DU0_DB0, FN_SCL4_D, FN_CAN0_RX_C, FN_A16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FN_DU0_DB1, FN_SDA4_D, FN_CAN0_TX_C, FN_A17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) FN_DU0_DB2, FN_HCTS0_N, FN_A18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) FN_DU0_DB3, FN_HRTS0_N, FN_A19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FN_DU0_DB4, FN_HCTS1_N_C, FN_A20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FN_DU0_DB5, FN_HRTS1_N_C, FN_A21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FN_DU0_DB6, FN_A22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) FN_DU0_DB7, FN_A23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) FN_DU0_DOTCLKIN, FN_A24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) FN_DU0_DOTCLKOUT0, FN_A25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FN_DU0_DOTCLKOUT1, FN_MSIOF2_RXD_B, FN_CS1_N_A26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FN_DU0_EXHSYNC_DU0_HSYNC, FN_MSIOF2_TXD_B, FN_DREQ0_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FN_DU0_EXVSYNC_DU0_VSYNC, FN_MSIOF2_SYNC_B, FN_DACK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_MSIOF2_SCK_B, FN_DRACK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FN_DU0_DISP, FN_CAN1_RX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) FN_DU0_CDE, FN_CAN1_TX_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) FN_VI1_CLK, FN_AVB_RX_CLK, FN_ETH_REF_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FN_VI1_DATA0, FN_AVB_RX_DV, FN_ETH_CRS_DV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) FN_VI1_DATA1, FN_AVB_RXD0, FN_ETH_RXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) FN_VI1_DATA2, FN_AVB_RXD1, FN_ETH_RXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) FN_VI1_DATA3, FN_AVB_RXD2, FN_ETH_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) FN_VI1_DATA4, FN_AVB_RXD3, FN_ETH_RX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) FN_VI1_DATA5, FN_AVB_RXD4, FN_ETH_LINK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) FN_VI1_DATA6, FN_AVB_RXD5, FN_ETH_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) FN_VI1_DATA7, FN_AVB_RXD6, FN_ETH_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) FN_VI1_CLKENB, FN_SCL3_A, FN_AVB_RXD7, FN_ETH_MAGIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) FN_VI1_FIELD, FN_SDA3_A, FN_AVB_RX_ER, FN_ETH_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, FN_AVB_GTXREFCLK, FN_ETH_MDC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) FN_VI1_DATA8, FN_SCL2_B, FN_AVB_TX_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) FN_VI1_DATA9, FN_SDA2_B, FN_AVB_TXD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) FN_VI1_DATA10, FN_CAN0_RX_B, FN_AVB_TXD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) FN_VI1_DATA11, FN_CAN0_TX_B, FN_AVB_TXD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) FN_AVB_TXD3, FN_AUDIO_CLKA_B, FN_SSI_SCK1_D, FN_RX5_F, FN_MSIOF0_RXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) FN_AVB_TXD4, FN_AUDIO_CLKB_B, FN_SSI_WS1_D, FN_TX5_F, FN_MSIOF0_TXD_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, FN_SSI_SDATA1_D, FN_MSIOF0_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6, FN_CAN1_RX_D, FN_MSIOF0_SYNC_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK, FN_CAN1_TX_D, FN_DVC_MUTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, FN_SSI_SCK6_B, FN_VI0_G0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) FN_SDA1_A, FN_TX4_A, FN_DU1_DR1, FN_SSI_WS6_B, FN_VI0_G1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) FN_MSIOF0_SCK_A, FN_IRQ0, FN_DU1_DR4, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) FN_MSIOF0_SYNC_A, FN_PWM1_A, FN_DU1_DR5, FN_QSPI1_IO2, FN_SSI_SDATA7_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) FN_MSIOF0_SS1_A, FN_DU1_DR6, FN_QSPI1_IO3, FN_SSI_SDATA8_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) FN_MSIOF0_SS2_A, FN_DU1_DR7, FN_QSPI1_SSL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FN_HTX1_A, FN_SDA4_A, FN_DU1_DG1, FN_TX0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) FN_HCTS1_N_A, FN_PWM2_A, FN_DU1_DG2, FN_REMOCON_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) FN_HRTS1_N_A, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) FN_SD2_CLK, FN_HSCK1, FN_DU1_DG4, FN_SSI_SCK1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5, FN_SSI_SCK2_B, FN_PWM3_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6, FN_SSI_SDATA1_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) FN_SD2_DAT2, FN_RX2_A, FN_DU1_DB0, FN_SSI_SDATA2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) FN_SD2_DAT3, FN_TX2_A, FN_DU1_DB1, FN_SSI_WS9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) FN_SD2_CD, FN_SCIF2_SCK_A, FN_DU1_DB2, FN_SSI_SCK9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) FN_SD2_WP, FN_SCIF3_SCK, FN_DU1_DB3, FN_SSI_SDATA9_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4, FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) FN_SCL2_A, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C, FN_SSI_SCK4_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) FN_SDA2_A, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) FN_SSI_SCK5_A, FN_DU1_DOTCLKOUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) FN_SSI_WS5_A, FN_SCL3_C, FN_DU1_DOTCLKIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) FN_SSI_SDATA5_A, FN_SDA3_C, FN_DU1_DOTCLKOUT0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) FN_SSI_SCK6_A, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) FN_SSI_WS6_A, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) FN_SSI_SDATA6_A, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) FN_SSI_SCK78_A, FN_SDA4_E, FN_DU1_DISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) FN_SSI_WS78_A, FN_SCL4_E, FN_DU1_CDE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) FN_SSI_SDATA7_A, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_VI0_G5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, FN_VI0_G6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, FN_VI0_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, FN_VI0_R0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, FN_DACK1, FN_VI0_R1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, FN_CAN1_RX_A, FN_DREQ1_N, FN_VI0_R2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, FN_CAN1_TX_A, FN_DREQ2_N, FN_VI0_R3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) FN_SSI_SCK4_A, FN_AVB_MAGIC, FN_VI0_R4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) FN_SSI_WS4_A, FN_AVB_PHY_INT, FN_VI0_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) FN_SSI_SDATA4_A, FN_AVB_CRS, FN_VI0_R6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A, FN_DACK2, FN_VI0_CLK, FN_AVB_COL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FN_SSI_SDATA8_A, FN_RX1_B, FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FN_SSI_WS1_A, FN_TX1_B, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FN_SSI_SDATA1_A, FN_HRX1_B, FN_VI0_DATA1_VI0_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FN_SSI_SCK2_A, FN_HTX1_B, FN_AVB_TXD7, FN_VI0_DATA2_VI0_B2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FN_SSI_WS2_A, FN_HCTS1_N_B, FN_AVB_TX_ER, FN_VI0_DATA3_VI0_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) FN_SSI_SDATA2_A, FN_HRTS1_N_B, FN_VI0_DATA4_VI0_B4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* IPSR17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, FN_EX_WAIT1, FN_VI0_DATA5_VI0_B5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, FN_VI0_DATA6_VI0_B6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, FN_VI0_DATA7_VI0_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) FN_AUDIO_CLKA_A, FN_SCL0_B, FN_VI0_CLKENB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) FN_AUDIO_CLKB_A, FN_SDA0_B, FN_VI0_FIELD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) FN_AUDIO_CLKC_A, FN_SCL4_B, FN_VI0_HSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) FN_AUDIO_CLKOUT_A, FN_SDA4_B, FN_VI0_VSYNC_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* MOD_SEL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, FN_SEL_I2C04_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, FN_SEL_I2C03_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, FN_SEL_I2C00_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) FN_SEL_AVB_0, FN_SEL_AVB_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* MOD_SEL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, FN_SEL_SCIF5_4, FN_SEL_SCIF5_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, FN_SEL_SCIF4_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) FN_SEL_RCN_0, FN_SEL_RCN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) FN_SEL_TMU2_0, FN_SEL_TMU2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) FN_SEL_TMU1_0, FN_SEL_TMU1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* MOD_SEL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) FN_SEL_SSI9_0, FN_SEL_SSI9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) FN_SEL_SSI8_0, FN_SEL_SSI8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) FN_SEL_SSI7_0, FN_SEL_SSI7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) FN_SEL_SSI6_0, FN_SEL_SSI6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) FN_SEL_SSI5_0, FN_SEL_SSI5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) FN_SEL_SSI4_0, FN_SEL_SSI4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) FN_SEL_SSI2_0, FN_SEL_SSI2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) FN_SEL_SSI0_0, FN_SEL_SSI0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CLKOUT_MARK, MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK, MMC0_D6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MMC0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) SD0_CLK_MARK, SSI_SCK1_C_MARK, RX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) SD0_CMD_MARK, SSI_WS1_C_MARK, TX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SD0_DAT0_MARK, SSI_SDATA1_C_MARK, RX4_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SD0_DAT1_MARK, SSI_SCK0129_B_MARK, TX4_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SD0_DAT2_MARK, SSI_WS0129_B_MARK, RX5_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) SD0_DAT3_MARK, SSI_SDATA0_B_MARK, TX5_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) SD0_CD_MARK, CAN0_RX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SD0_WP_MARK, IRQ7_MARK, CAN0_TX_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MMC0_D4_MARK, SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MMC0_D5_MARK, SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) D0_MARK, SCL3_B_MARK, RX5_B_MARK, IRQ4_MARK, MSIOF2_RXD_C_MARK, SSI_SDATA5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) D1_MARK, SDA3_B_MARK, TX5_B_MARK, MSIOF2_TXD_C_MARK, SSI_WS5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) D2_MARK, RX4_B_MARK, SCL0_D_MARK, PWM1_C_MARK, MSIOF2_SCK_C_MARK, SSI_SCK5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) D3_MARK, TX4_B_MARK, SDA0_D_MARK, PWM0_A_MARK, MSIOF2_SYNC_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) D4_MARK, IRQ3_MARK, TCLK1_A_MARK, PWM6_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) D5_MARK, HRX2_MARK, SCL1_B_MARK, PWM2_C_MARK, TCLK2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) D6_MARK, HTX2_MARK, SDA1_B_MARK, PWM4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) D7_MARK, HSCK2_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) D8_MARK, HCTS2_N_MARK, RX1_C_MARK, SCL1_D_MARK, PWM3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) D9_MARK, HRTS2_N_MARK, TX1_C_MARK, SDA1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) D10_MARK, MSIOF2_RXD_A_MARK, HRX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) D11_MARK, MSIOF2_TXD_A_MARK, HTX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) D12_MARK, MSIOF2_SCK_A_MARK, HSCK0_MARK, CAN_CLK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) D13_MARK, MSIOF2_SYNC_A_MARK, RX4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) D14_MARK, MSIOF2_SS1_MARK, TX4_C_MARK, CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) D15_MARK, MSIOF2_SS2_MARK, PWM4_A_MARK, CAN1_TX_B_MARK, IRQ2_MARK, AVB_AVTP_MATCH_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) QSPI0_SPCLK_MARK, WE0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) QSPI0_MOSI_QSPI0_IO0_MARK, BS_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) QSPI0_MISO_QSPI0_IO1_MARK, RD_WR_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) QSPI0_IO2_MARK, CS0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) QSPI0_IO3_MARK, RD_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) QSPI0_SSL_MARK, WE1_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DU0_DR0_MARK, RX5_C_MARK, SCL2_D_MARK, A0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DU0_DR1_MARK, TX5_C_MARK, SDA2_D_MARK, A1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DU0_DR2_MARK, RX0_D_MARK, SCL0_E_MARK, A2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DU0_DR3_MARK, TX0_D_MARK, SDA0_E_MARK, PWM0_B_MARK, A3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DU0_DR4_MARK, RX1_D_MARK, A4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DU0_DR5_MARK, TX1_D_MARK, PWM1_B_MARK, A5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DU0_DR6_MARK, RX2_C_MARK, A6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DU0_DR7_MARK, TX2_C_MARK, PWM2_B_MARK, A7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DU0_DG0_MARK, RX3_B_MARK, SCL3_D_MARK, A8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DU0_DG1_MARK, TX3_B_MARK, SDA3_D_MARK, PWM3_B_MARK, A9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DU0_DG2_MARK, RX4_D_MARK, A10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DU0_DG3_MARK, TX4_D_MARK, PWM4_B_MARK, A11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DU0_DG4_MARK, HRX0_A_MARK, A12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DU0_DG5_MARK, HTX0_A_MARK, PWM5_B_MARK, A13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DU0_DG6_MARK, HRX1_C_MARK, A14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DU0_DG7_MARK, HTX1_C_MARK, PWM6_B_MARK, A15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DU0_DB0_MARK, SCL4_D_MARK, CAN0_RX_C_MARK, A16_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DU0_DB1_MARK, SDA4_D_MARK, CAN0_TX_C_MARK, A17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DU0_DB2_MARK, HCTS0_N_MARK, A18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DU0_DB3_MARK, HRTS0_N_MARK, A19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DU0_DB4_MARK, HCTS1_N_C_MARK, A20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DU0_DB5_MARK, HRTS1_N_C_MARK, A21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DU0_DB6_MARK, A22_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DU0_DB7_MARK, A23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DU0_DOTCLKIN_MARK, A24_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DU0_DOTCLKOUT0_MARK, A25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DU0_DOTCLKOUT1_MARK, MSIOF2_RXD_B_MARK, CS1_N_A26_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DU0_EXHSYNC_DU0_HSYNC_MARK, MSIOF2_TXD_B_MARK, DREQ0_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DU0_EXVSYNC_DU0_VSYNC_MARK, MSIOF2_SYNC_B_MARK, DACK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, MSIOF2_SCK_B_MARK, DRACK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DU0_DISP_MARK, CAN1_RX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DU0_CDE_MARK, CAN1_TX_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) VI1_CLK_MARK, AVB_RX_CLK_MARK, ETH_REF_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) VI1_DATA0_MARK, AVB_RX_DV_MARK, ETH_CRS_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) VI1_DATA1_MARK, AVB_RXD0_MARK, ETH_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) VI1_DATA2_MARK, AVB_RXD1_MARK, ETH_RXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) VI1_DATA3_MARK, AVB_RXD2_MARK, ETH_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) VI1_DATA4_MARK, AVB_RXD3_MARK, ETH_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) VI1_DATA5_MARK, AVB_RXD4_MARK, ETH_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) VI1_DATA6_MARK, AVB_RXD5_MARK, ETH_TXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) VI1_DATA7_MARK, AVB_RXD6_MARK, ETH_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) VI1_CLKENB_MARK, SCL3_A_MARK, AVB_RXD7_MARK, ETH_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) VI1_FIELD_MARK, SDA3_A_MARK, AVB_RX_ER_MARK, ETH_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) VI1_HSYNC_N_MARK, RX0_B_MARK, SCL0_C_MARK, AVB_GTXREFCLK_MARK, ETH_MDC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) VI1_VSYNC_N_MARK, TX0_B_MARK, SDA0_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) VI1_DATA8_MARK, SCL2_B_MARK, AVB_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) VI1_DATA9_MARK, SDA2_B_MARK, AVB_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) VI1_DATA10_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) VI1_DATA11_MARK, CAN0_TX_B_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) AVB_TXD3_MARK, AUDIO_CLKA_B_MARK, SSI_SCK1_D_MARK, RX5_F_MARK, MSIOF0_RXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) AVB_TXD4_MARK, AUDIO_CLKB_B_MARK, SSI_WS1_D_MARK, TX5_F_MARK, MSIOF0_TXD_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) AVB_TXD5_MARK, SCIF_CLK_B_MARK, AUDIO_CLKC_B_MARK, SSI_SDATA1_D_MARK, MSIOF0_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SCL0_A_MARK, RX0_C_MARK, PWM5_A_MARK, TCLK1_B_MARK, AVB_TXD6_MARK, CAN1_RX_D_MARK, MSIOF0_SYNC_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) SDA0_A_MARK, TX0_C_MARK, IRQ5_MARK, CAN_CLK_A_MARK, AVB_GTX_CLK_MARK, CAN1_TX_D_MARK, DVC_MUTE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) SCL1_A_MARK, RX4_A_MARK, PWM5_D_MARK, DU1_DR0_MARK, SSI_SCK6_B_MARK, VI0_G0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SDA1_A_MARK, TX4_A_MARK, DU1_DR1_MARK, SSI_WS6_B_MARK, VI0_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MSIOF0_RXD_A_MARK, RX5_A_MARK, SCL2_C_MARK, DU1_DR2_MARK, QSPI1_MOSI_QSPI1_IO0_MARK, SSI_SDATA6_B_MARK, VI0_G2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MSIOF0_TXD_A_MARK, TX5_A_MARK, SDA2_C_MARK, DU1_DR3_MARK, QSPI1_MISO_QSPI1_IO1_MARK, SSI_WS78_B_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MSIOF0_SCK_A_MARK, IRQ0_MARK, DU1_DR4_MARK, QSPI1_SPCLK_MARK, SSI_SCK78_B_MARK, VI0_G4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MSIOF0_SYNC_A_MARK, PWM1_A_MARK, DU1_DR5_MARK, QSPI1_IO2_MARK, SSI_SDATA7_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MSIOF0_SS1_A_MARK, DU1_DR6_MARK, QSPI1_IO3_MARK, SSI_SDATA8_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MSIOF0_SS2_A_MARK, DU1_DR7_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) HRX1_A_MARK, SCL4_A_MARK, PWM6_A_MARK, DU1_DG0_MARK, RX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) HTX1_A_MARK, SDA4_A_MARK, DU1_DG1_MARK, TX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) HCTS1_N_A_MARK, PWM2_A_MARK, DU1_DG2_MARK, REMOCON_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) HRTS1_N_A_MARK, DU1_DG3_MARK, SSI_WS1_B_MARK, IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) SD2_CLK_MARK, HSCK1_MARK, DU1_DG4_MARK, SSI_SCK1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) SD2_CMD_MARK, SCIF1_SCK_A_MARK, TCLK2_A_MARK, DU1_DG5_MARK, SSI_SCK2_B_MARK, PWM3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) SD2_DAT0_MARK, RX1_A_MARK, SCL1_E_MARK, DU1_DG6_MARK, SSI_SDATA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) SD2_DAT1_MARK, TX1_A_MARK, SDA1_E_MARK, DU1_DG7_MARK, SSI_WS2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) SD2_DAT2_MARK, RX2_A_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SD2_DAT3_MARK, TX2_A_MARK, DU1_DB1_MARK, SSI_WS9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SD2_CD_MARK, SCIF2_SCK_A_MARK, DU1_DB2_MARK, SSI_SCK9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) SD2_WP_MARK, SCIF3_SCK_MARK, DU1_DB3_MARK, SSI_SDATA9_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RX3_A_MARK, SCL1_C_MARK, MSIOF1_RXD_B_MARK, DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SDATA4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) TX3_A_MARK, SDA1_C_MARK, MSIOF1_TXD_B_MARK, DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SCL2_A_MARK, MSIOF1_SCK_B_MARK, DU1_DB6_MARK, AUDIO_CLKC_C_MARK, SSI_SCK4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SDA2_A_MARK, MSIOF1_SYNC_B_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SSI_SCK5_A_MARK, DU1_DOTCLKOUT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) SSI_WS5_A_MARK, SCL3_C_MARK, DU1_DOTCLKIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SSI_SDATA5_A_MARK, SDA3_C_MARK, DU1_DOTCLKOUT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SSI_SCK6_A_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) SSI_WS6_A_MARK, SCL4_C_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SSI_SDATA6_A_MARK, SDA4_C_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SSI_SCK78_A_MARK, SDA4_E_MARK, DU1_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) SSI_WS78_A_MARK, SCL4_E_MARK, DU1_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) SSI_SDATA7_A_MARK, IRQ8_MARK, AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) SSI_SCK0129_A_MARK, MSIOF1_RXD_A_MARK, RX5_D_MARK, VI0_G6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) SSI_WS0129_A_MARK, MSIOF1_TXD_A_MARK, TX5_D_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SSI_SDATA0_A_MARK, MSIOF1_SYNC_A_MARK, PWM0_C_MARK, VI0_R0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SSI_SCK34_MARK, MSIOF1_SCK_A_MARK, AVB_MDC_MARK, DACK1_MARK, VI0_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) SSI_WS34_MARK, MSIOF1_SS1_A_MARK, AVB_MDIO_MARK, CAN1_RX_A_MARK, DREQ1_N_MARK, VI0_R2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) SSI_SDATA3_MARK, MSIOF1_SS2_A_MARK, AVB_LINK_MARK, CAN1_TX_A_MARK, DREQ2_N_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SSI_SCK4_A_MARK, AVB_MAGIC_MARK, VI0_R4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SSI_WS4_A_MARK, AVB_PHY_INT_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) SSI_SDATA4_A_MARK, AVB_CRS_MARK, VI0_R6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) SSI_SCK1_A_MARK, SCIF1_SCK_B_MARK, PWM1_D_MARK, IRQ9_MARK, REMOCON_A_MARK, DACK2_MARK, VI0_CLK_MARK, AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) SSI_SDATA8_A_MARK, RX1_B_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_B_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SSI_WS1_A_MARK, TX1_B_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_B_MARK, VI0_DATA0_VI0_B0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SSI_SDATA1_A_MARK, HRX1_B_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SSI_SCK2_A_MARK, HTX1_B_MARK, AVB_TXD7_MARK, VI0_DATA2_VI0_B2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) SSI_WS2_A_MARK, HCTS1_N_B_MARK, AVB_TX_ER_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) SSI_SDATA2_A_MARK, HRTS1_N_B_MARK, VI0_DATA4_VI0_B4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* IPSR17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) SSI_SCK9_A_MARK, RX2_B_MARK, SCL3_E_MARK, EX_WAIT1_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) SSI_WS9_A_MARK, TX2_B_MARK, SDA3_E_MARK, VI0_DATA6_VI0_B6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) SSI_SDATA9_A_MARK, SCIF2_SCK_B_MARK, PWM2_D_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) AUDIO_CLKA_A_MARK, SCL0_B_MARK, VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) AUDIO_CLKB_A_MARK, SDA0_B_MARK, VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) AUDIO_CLKC_A_MARK, SCL4_B_MARK, VI0_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) AUDIO_CLKOUT_A_MARK, SDA4_B_MARK, VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINMUX_SINGLE(USB0_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINMUX_SINGLE(USB0_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINMUX_SINGLE(USB1_PWEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINMUX_SINGLE(USB1_OVC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINMUX_SINGLE(CLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_SINGLE(MMC0_CLK_SDHI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_SINGLE(MMC0_CMD_SDHI1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_SINGLE(MMC0_D0_SDHI1_D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_SINGLE(MMC0_D1_SDHI1_D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_SINGLE(MMC0_D2_SDHI1_D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINMUX_SINGLE(MMC0_D3_SDHI1_D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_SINGLE(MMC0_D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_SINGLE(MMC0_D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* IPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINMUX_IPSR_GPSR(IP0_3_0, SD0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_IPSR_MSEL(IP0_3_0, SSI_SCK1_C, SEL_SSI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINMUX_IPSR_MSEL(IP0_3_0, RX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINMUX_IPSR_GPSR(IP0_7_4, SD0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_IPSR_MSEL(IP0_7_4, SSI_WS1_C, SEL_SSI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINMUX_IPSR_MSEL(IP0_7_4, TX3_C, SEL_SCIF3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_IPSR_GPSR(IP0_11_8, SD0_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_IPSR_MSEL(IP0_11_8, SSI_SDATA1_C, SEL_SSI1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_IPSR_MSEL(IP0_11_8, RX4_E, SEL_SCIF4_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINMUX_IPSR_GPSR(IP0_15_12, SD0_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINMUX_IPSR_MSEL(IP0_15_12, SSI_SCK0129_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_MSEL(IP0_15_12, TX4_E, SEL_SCIF4_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_IPSR_GPSR(IP0_19_16, SD0_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINMUX_IPSR_MSEL(IP0_19_16, SSI_WS0129_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINMUX_IPSR_MSEL(IP0_19_16, RX5_E, SEL_SCIF5_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_IPSR_GPSR(IP0_23_20, SD0_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_IPSR_MSEL(IP0_23_20, SSI_SDATA0_B, SEL_SSI0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_MSEL(IP0_23_20, TX5_E, SEL_SCIF5_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINMUX_IPSR_GPSR(IP0_27_24, SD0_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINMUX_IPSR_MSEL(IP0_27_24, CAN0_RX_A, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_IPSR_GPSR(IP0_31_28, SD0_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_IPSR_GPSR(IP0_31_28, IRQ7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINMUX_IPSR_MSEL(IP0_31_28, CAN0_TX_A, SEL_CAN0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* IPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_IPSR_GPSR(IP1_3_0, MMC0_D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINMUX_IPSR_GPSR(IP1_3_0, SD1_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_IPSR_GPSR(IP1_7_4, MMC0_D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_GPSR(IP1_7_4, SD1_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_GPSR(IP1_11_8, D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINMUX_IPSR_MSEL(IP1_11_8, SCL3_B, SEL_I2C03_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_MSEL(IP1_11_8, RX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_IPSR_MSEL(IP1_11_8, MSIOF2_RXD_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_IPSR_MSEL(IP1_11_8, SSI_SDATA5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_IPSR_GPSR(IP1_15_12, D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_IPSR_MSEL(IP1_15_12, SDA3_B, SEL_I2C03_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_IPSR_MSEL(IP1_15_12, TX5_B, SEL_SCIF5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_IPSR_MSEL(IP1_15_12, MSIOF2_TXD_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_IPSR_MSEL(IP1_15_12, SSI_WS5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_IPSR_GPSR(IP1_19_16, D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_IPSR_MSEL(IP1_19_16, RX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_IPSR_MSEL(IP1_19_16, SCL0_D, SEL_I2C00_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_IPSR_GPSR(IP1_19_16, PWM1_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_IPSR_MSEL(IP1_19_16, MSIOF2_SCK_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_MSEL(IP1_19_16, SSI_SCK5_B, SEL_SSI5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_IPSR_GPSR(IP1_23_20, D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINMUX_IPSR_MSEL(IP1_23_20, TX4_B, SEL_SCIF4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_IPSR_MSEL(IP1_23_20, SDA0_D, SEL_I2C00_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_IPSR_GPSR(IP1_23_20, PWM0_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_IPSR_MSEL(IP1_23_20, MSIOF2_SYNC_C, SEL_MSIOF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_IPSR_GPSR(IP1_27_24, D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_IPSR_GPSR(IP1_27_24, IRQ3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_IPSR_MSEL(IP1_27_24, TCLK1_A, SEL_TMU1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_IPSR_GPSR(IP1_27_24, PWM6_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_IPSR_GPSR(IP1_31_28, D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_IPSR_GPSR(IP1_31_28, HRX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_IPSR_MSEL(IP1_31_28, SCL1_B, SEL_I2C01_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_IPSR_GPSR(IP1_31_28, PWM2_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_IPSR_MSEL(IP1_31_28, TCLK2_B, SEL_TMU2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* IPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_IPSR_GPSR(IP2_3_0, D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_IPSR_GPSR(IP2_3_0, HTX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_IPSR_MSEL(IP2_3_0, SDA1_B, SEL_I2C01_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_IPSR_GPSR(IP2_3_0, PWM4_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_IPSR_GPSR(IP2_7_4, D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_IPSR_GPSR(IP2_7_4, HSCK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_IPSR_MSEL(IP2_7_4, SCIF1_SCK_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_IPSR_GPSR(IP2_7_4, IRQ6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_IPSR_GPSR(IP2_7_4, PWM5_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_IPSR_GPSR(IP2_11_8, D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_IPSR_GPSR(IP2_11_8, HCTS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_IPSR_MSEL(IP2_11_8, RX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_IPSR_MSEL(IP2_11_8, SCL1_D, SEL_I2C01_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINMUX_IPSR_GPSR(IP2_11_8, PWM3_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_IPSR_GPSR(IP2_15_12, D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_IPSR_GPSR(IP2_15_12, HRTS2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_IPSR_MSEL(IP2_15_12, TX1_C, SEL_SCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINMUX_IPSR_MSEL(IP2_15_12, SDA1_D, SEL_I2C01_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_IPSR_GPSR(IP2_19_16, D10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_IPSR_MSEL(IP2_19_16, MSIOF2_RXD_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_IPSR_MSEL(IP2_19_16, HRX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_IPSR_GPSR(IP2_23_20, D11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_TXD_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINMUX_IPSR_MSEL(IP2_23_20, HTX0_B, SEL_HSCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_IPSR_GPSR(IP2_27_24, D12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SCK_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_IPSR_GPSR(IP2_27_24, HSCK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_IPSR_MSEL(IP2_27_24, CAN_CLK_C, SEL_CANCLK_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_IPSR_GPSR(IP2_31_28, D13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_IPSR_MSEL(IP2_31_28, RX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* IPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_IPSR_GPSR(IP3_3_0, D14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_IPSR_MSEL(IP3_3_0, TX4_C, SEL_SCIF4_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_MSEL(IP3_3_0, CAN1_RX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINMUX_IPSR_MSEL(IP3_3_0, AVB_AVTP_CAPTURE_A, SEL_AVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_GPSR(IP3_7_4, D15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_GPSR(IP3_11_8, QSPI0_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_IPSR_GPSR(IP3_11_8, WE0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_IPSR_GPSR(IP3_15_12, QSPI0_MOSI_QSPI0_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_IPSR_GPSR(IP3_15_12, BS_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_IPSR_GPSR(IP3_19_16, QSPI0_MISO_QSPI0_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_IPSR_GPSR(IP3_19_16, RD_WR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_IPSR_GPSR(IP3_23_20, QSPI0_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_IPSR_GPSR(IP3_23_20, CS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_IPSR_GPSR(IP3_27_24, QSPI0_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_IPSR_GPSR(IP3_27_24, RD_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_IPSR_GPSR(IP3_31_28, QSPI0_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_IPSR_GPSR(IP3_31_28, WE1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* IPSR4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_GPSR(IP4_3_0, EX_WAIT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_MSEL(IP4_3_0, CAN_CLK_B, SEL_CANCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_IPSR_MSEL(IP4_3_0, SCIF_CLK_A, SEL_SCIFCLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_GPSR(IP4_7_4, DU0_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_IPSR_MSEL(IP4_7_4, RX5_C, SEL_SCIF5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_IPSR_MSEL(IP4_7_4, SCL2_D, SEL_I2C02_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_IPSR_GPSR(IP4_7_4, A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) PINMUX_IPSR_GPSR(IP4_11_8, DU0_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_IPSR_MSEL(IP4_11_8, TX5_C, SEL_SCIF5_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_IPSR_MSEL(IP4_11_8, SDA2_D, SEL_I2C02_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_IPSR_GPSR(IP4_11_8, A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINMUX_IPSR_GPSR(IP4_15_12, DU0_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_IPSR_MSEL(IP4_15_12, RX0_D, SEL_SCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_IPSR_MSEL(IP4_15_12, SCL0_E, SEL_I2C00_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) PINMUX_IPSR_GPSR(IP4_15_12, A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) PINMUX_IPSR_GPSR(IP4_19_16, DU0_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_IPSR_MSEL(IP4_19_16, TX0_D, SEL_SCIF0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_IPSR_MSEL(IP4_19_16, SDA0_E, SEL_I2C00_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_IPSR_GPSR(IP4_19_16, PWM0_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_IPSR_GPSR(IP4_19_16, A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_IPSR_GPSR(IP4_23_20, DU0_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINMUX_IPSR_MSEL(IP4_23_20, RX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_IPSR_GPSR(IP4_23_20, A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_IPSR_GPSR(IP4_27_24, DU0_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_IPSR_MSEL(IP4_27_24, TX1_D, SEL_SCIF1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_IPSR_GPSR(IP4_27_24, PWM1_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_IPSR_GPSR(IP4_27_24, A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_IPSR_GPSR(IP4_31_28, DU0_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) PINMUX_IPSR_MSEL(IP4_31_28, RX2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_IPSR_GPSR(IP4_31_28, A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) /* IPSR5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_IPSR_GPSR(IP5_3_0, DU0_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_IPSR_MSEL(IP5_3_0, TX2_C, SEL_SCIF2_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_IPSR_GPSR(IP5_3_0, PWM2_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_IPSR_GPSR(IP5_3_0, A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_IPSR_GPSR(IP5_7_4, DU0_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_IPSR_MSEL(IP5_7_4, RX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_IPSR_MSEL(IP5_7_4, SCL3_D, SEL_I2C03_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_IPSR_GPSR(IP5_7_4, A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_IPSR_GPSR(IP5_11_8, DU0_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_IPSR_MSEL(IP5_11_8, TX3_B, SEL_SCIF3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_IPSR_MSEL(IP5_11_8, SDA3_D, SEL_I2C03_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_IPSR_GPSR(IP5_11_8, PWM3_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_IPSR_GPSR(IP5_11_8, A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_IPSR_GPSR(IP5_15_12, DU0_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_IPSR_MSEL(IP5_15_12, RX4_D, SEL_SCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_IPSR_GPSR(IP5_15_12, A10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_IPSR_GPSR(IP5_19_16, DU0_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_IPSR_MSEL(IP5_19_16, TX4_D, SEL_SCIF4_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_IPSR_GPSR(IP5_19_16, PWM4_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_IPSR_GPSR(IP5_19_16, A11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_IPSR_GPSR(IP5_23_20, DU0_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_IPSR_MSEL(IP5_23_20, HRX0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_IPSR_GPSR(IP5_23_20, A12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) PINMUX_IPSR_GPSR(IP5_27_24, DU0_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) PINMUX_IPSR_MSEL(IP5_27_24, HTX0_A, SEL_HSCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_IPSR_GPSR(IP5_27_24, PWM5_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_IPSR_GPSR(IP5_27_24, A13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_IPSR_GPSR(IP5_31_28, DU0_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_IPSR_MSEL(IP5_31_28, HRX1_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_IPSR_GPSR(IP5_31_28, A14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* IPSR6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_IPSR_GPSR(IP6_3_0, DU0_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_IPSR_MSEL(IP6_3_0, HTX1_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_IPSR_GPSR(IP6_3_0, PWM6_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_IPSR_GPSR(IP6_3_0, A15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_IPSR_GPSR(IP6_7_4, DU0_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_IPSR_MSEL(IP6_7_4, SCL4_D, SEL_I2C04_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_IPSR_MSEL(IP6_7_4, CAN0_RX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_IPSR_GPSR(IP6_7_4, A16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_IPSR_GPSR(IP6_11_8, DU0_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_IPSR_MSEL(IP6_11_8, SDA4_D, SEL_I2C04_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_IPSR_MSEL(IP6_11_8, CAN0_TX_C, SEL_CAN0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_IPSR_GPSR(IP6_11_8, A17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_IPSR_GPSR(IP6_15_12, DU0_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_IPSR_GPSR(IP6_15_12, HCTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_IPSR_GPSR(IP6_15_12, A18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_IPSR_GPSR(IP6_19_16, DU0_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_IPSR_GPSR(IP6_19_16, HRTS0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_IPSR_GPSR(IP6_19_16, A19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_IPSR_GPSR(IP6_23_20, DU0_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_IPSR_MSEL(IP6_23_20, HCTS1_N_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) PINMUX_IPSR_GPSR(IP6_23_20, A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_IPSR_GPSR(IP6_27_24, DU0_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_IPSR_MSEL(IP6_27_24, HRTS1_N_C, SEL_HSCIF1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_IPSR_GPSR(IP6_27_24, A21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_IPSR_GPSR(IP6_31_28, DU0_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) PINMUX_IPSR_GPSR(IP6_31_28, A22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* IPSR7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_IPSR_GPSR(IP7_3_0, DU0_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_IPSR_GPSR(IP7_3_0, A23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_IPSR_GPSR(IP7_7_4, DU0_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) PINMUX_IPSR_GPSR(IP7_7_4, A24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_IPSR_GPSR(IP7_11_8, DU0_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_IPSR_GPSR(IP7_11_8, A25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_IPSR_GPSR(IP7_15_12, DU0_DOTCLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_IPSR_MSEL(IP7_15_12, MSIOF2_RXD_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_IPSR_GPSR(IP7_15_12, CS1_N_A26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_IPSR_GPSR(IP7_19_16, DU0_EXHSYNC_DU0_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_IPSR_MSEL(IP7_19_16, MSIOF2_TXD_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_IPSR_GPSR(IP7_19_16, DREQ0_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_IPSR_GPSR(IP7_23_20, DU0_EXVSYNC_DU0_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_IPSR_MSEL(IP7_23_20, MSIOF2_SYNC_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_IPSR_GPSR(IP7_23_20, DACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_IPSR_GPSR(IP7_27_24, DU0_EXODDF_DU0_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_IPSR_MSEL(IP7_27_24, MSIOF2_SCK_B, SEL_MSIOF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_IPSR_GPSR(IP7_27_24, DRACK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_IPSR_GPSR(IP7_31_28, DU0_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) PINMUX_IPSR_MSEL(IP7_31_28, CAN1_RX_C, SEL_CAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* IPSR8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_IPSR_GPSR(IP8_3_0, DU0_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_IPSR_MSEL(IP8_3_0, CAN1_TX_C, SEL_CAN1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_IPSR_GPSR(IP8_7_4, VI1_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_IPSR_GPSR(IP8_7_4, AVB_RX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_IPSR_GPSR(IP8_7_4, ETH_REF_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_IPSR_GPSR(IP8_11_8, VI1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_IPSR_GPSR(IP8_11_8, AVB_RX_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_IPSR_GPSR(IP8_11_8, ETH_CRS_DV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_IPSR_GPSR(IP8_15_12, VI1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) PINMUX_IPSR_GPSR(IP8_15_12, AVB_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_IPSR_GPSR(IP8_15_12, ETH_RXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_IPSR_GPSR(IP8_19_16, VI1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_IPSR_GPSR(IP8_19_16, AVB_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_IPSR_GPSR(IP8_19_16, ETH_RXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) PINMUX_IPSR_GPSR(IP8_23_20, VI1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_IPSR_GPSR(IP8_23_20, AVB_RXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_IPSR_GPSR(IP8_23_20, ETH_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_IPSR_GPSR(IP8_27_24, VI1_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) PINMUX_IPSR_GPSR(IP8_27_24, AVB_RXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) PINMUX_IPSR_GPSR(IP8_27_24, ETH_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_IPSR_GPSR(IP8_31_28, VI1_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_IPSR_GPSR(IP8_31_28, AVB_RXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_IPSR_GPSR(IP8_31_28, ETH_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* IPSR9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_IPSR_GPSR(IP9_3_0, VI1_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_IPSR_GPSR(IP9_3_0, AVB_RXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_IPSR_GPSR(IP9_3_0, ETH_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_IPSR_GPSR(IP9_7_4, VI1_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_IPSR_GPSR(IP9_7_4, AVB_RXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) PINMUX_IPSR_GPSR(IP9_7_4, ETH_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_IPSR_GPSR(IP9_11_8, VI1_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_IPSR_MSEL(IP9_11_8, SCL3_A, SEL_I2C03_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_IPSR_GPSR(IP9_11_8, AVB_RXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_IPSR_GPSR(IP9_11_8, ETH_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) PINMUX_IPSR_GPSR(IP9_15_12, VI1_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) PINMUX_IPSR_MSEL(IP9_15_12, SDA3_A, SEL_I2C03_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_IPSR_GPSR(IP9_15_12, AVB_RX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_IPSR_GPSR(IP9_15_12, ETH_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_IPSR_GPSR(IP9_19_16, VI1_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) PINMUX_IPSR_MSEL(IP9_19_16, RX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) PINMUX_IPSR_MSEL(IP9_19_16, SCL0_C, SEL_I2C00_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_IPSR_GPSR(IP9_19_16, AVB_GTXREFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_IPSR_GPSR(IP9_19_16, ETH_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_IPSR_GPSR(IP9_23_20, VI1_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_IPSR_MSEL(IP9_23_20, TX0_B, SEL_SCIF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) PINMUX_IPSR_MSEL(IP9_23_20, SDA0_C, SEL_I2C00_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_IPSR_GPSR(IP9_23_20, AUDIO_CLKOUT_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_IPSR_GPSR(IP9_23_20, AVB_TX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_IPSR_GPSR(IP9_27_24, VI1_DATA8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_IPSR_MSEL(IP9_27_24, SCL2_B, SEL_I2C02_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) PINMUX_IPSR_GPSR(IP9_27_24, AVB_TX_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_IPSR_GPSR(IP9_31_28, VI1_DATA9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_IPSR_MSEL(IP9_31_28, SDA2_B, SEL_I2C02_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_IPSR_GPSR(IP9_31_28, AVB_TXD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* IPSR10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) PINMUX_IPSR_GPSR(IP10_3_0, VI1_DATA10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_IPSR_MSEL(IP10_3_0, CAN0_RX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_IPSR_GPSR(IP10_3_0, AVB_TXD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_IPSR_GPSR(IP10_7_4, VI1_DATA11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_IPSR_MSEL(IP10_7_4, CAN0_TX_B, SEL_CAN0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_IPSR_GPSR(IP10_7_4, AVB_TXD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_IPSR_GPSR(IP10_11_8, AVB_TXD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_IPSR_MSEL(IP10_11_8, AUDIO_CLKA_B, SEL_ADGA_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_IPSR_MSEL(IP10_11_8, SSI_SCK1_D, SEL_SSI1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_IPSR_MSEL(IP10_11_8, RX5_F, SEL_SCIF5_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_IPSR_MSEL(IP10_11_8, MSIOF0_RXD_B, SEL_MSIOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_IPSR_GPSR(IP10_15_12, AVB_TXD4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_IPSR_MSEL(IP10_15_12, AUDIO_CLKB_B, SEL_ADGB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_IPSR_MSEL(IP10_15_12, SSI_WS1_D, SEL_SSI1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_IPSR_MSEL(IP10_15_12, TX5_F, SEL_SCIF5_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_IPSR_MSEL(IP10_15_12, MSIOF0_TXD_B, SEL_MSIOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_IPSR_GPSR(IP10_19_16, AVB_TXD5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_IPSR_MSEL(IP10_19_16, SCIF_CLK_B, SEL_SCIFCLK_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_IPSR_MSEL(IP10_19_16, AUDIO_CLKC_B, SEL_ADGC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_IPSR_MSEL(IP10_19_16, SSI_SDATA1_D, SEL_SSI1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PINMUX_IPSR_MSEL(IP10_19_16, MSIOF0_SCK_B, SEL_MSIOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PINMUX_IPSR_MSEL(IP10_23_20, SCL0_A, SEL_I2C00_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_IPSR_MSEL(IP10_23_20, RX0_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_IPSR_GPSR(IP10_23_20, PWM5_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_IPSR_MSEL(IP10_23_20, TCLK1_B, SEL_TMU1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_IPSR_GPSR(IP10_23_20, AVB_TXD6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_D, SEL_CAN1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_IPSR_MSEL(IP10_23_20, MSIOF0_SYNC_B, SEL_MSIOF0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_IPSR_MSEL(IP10_27_24, SDA0_A, SEL_I2C00_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_IPSR_MSEL(IP10_27_24, TX0_C, SEL_SCIF0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_IPSR_GPSR(IP10_27_24, IRQ5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_IPSR_MSEL(IP10_27_24, CAN_CLK_A, SEL_CANCLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_IPSR_GPSR(IP10_27_24, AVB_GTX_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_D, SEL_CAN1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_IPSR_GPSR(IP10_27_24, DVC_MUTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_IPSR_MSEL(IP10_31_28, SCL1_A, SEL_I2C01_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_IPSR_MSEL(IP10_31_28, RX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_IPSR_GPSR(IP10_31_28, PWM5_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_IPSR_GPSR(IP10_31_28, DU1_DR0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_IPSR_MSEL(IP10_31_28, SSI_SCK6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_IPSR_GPSR(IP10_31_28, VI0_G0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* IPSR11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_IPSR_MSEL(IP11_3_0, SDA1_A, SEL_I2C01_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_IPSR_MSEL(IP11_3_0, TX4_A, SEL_SCIF4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_IPSR_GPSR(IP11_3_0, DU1_DR1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_IPSR_MSEL(IP11_3_0, SSI_WS6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_IPSR_GPSR(IP11_3_0, VI0_G1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_IPSR_MSEL(IP11_7_4, MSIOF0_RXD_A, SEL_MSIOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_IPSR_MSEL(IP11_7_4, RX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_IPSR_MSEL(IP11_7_4, SCL2_C, SEL_I2C02_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_IPSR_GPSR(IP11_7_4, DU1_DR2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) PINMUX_IPSR_GPSR(IP11_7_4, QSPI1_MOSI_QSPI1_IO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_IPSR_MSEL(IP11_7_4, SSI_SDATA6_B, SEL_SSI6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_IPSR_GPSR(IP11_7_4, VI0_G2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_IPSR_MSEL(IP11_11_8, MSIOF0_TXD_A, SEL_MSIOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_IPSR_MSEL(IP11_11_8, TX5_A, SEL_SCIF5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_IPSR_MSEL(IP11_11_8, SDA2_C, SEL_I2C02_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_IPSR_GPSR(IP11_11_8, DU1_DR3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_IPSR_GPSR(IP11_11_8, QSPI1_MISO_QSPI1_IO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_IPSR_MSEL(IP11_11_8, SSI_WS78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_IPSR_GPSR(IP11_11_8, VI0_G3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_IPSR_MSEL(IP11_15_12, MSIOF0_SCK_A, SEL_MSIOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) PINMUX_IPSR_GPSR(IP11_15_12, IRQ0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_IPSR_GPSR(IP11_15_12, DU1_DR4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_IPSR_GPSR(IP11_15_12, QSPI1_SPCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_IPSR_MSEL(IP11_15_12, SSI_SCK78_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_IPSR_GPSR(IP11_15_12, VI0_G4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_IPSR_MSEL(IP11_19_16, MSIOF0_SYNC_A, SEL_MSIOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_IPSR_GPSR(IP11_19_16, PWM1_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_IPSR_GPSR(IP11_19_16, DU1_DR5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_IPSR_GPSR(IP11_19_16, QSPI1_IO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_IPSR_MSEL(IP11_19_16, SSI_SDATA7_B, SEL_SSI7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_IPSR_MSEL(IP11_23_20, MSIOF0_SS1_A, SEL_MSIOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_IPSR_GPSR(IP11_23_20, DU1_DR6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_IPSR_GPSR(IP11_23_20, QSPI1_IO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_IPSR_MSEL(IP11_23_20, SSI_SDATA8_B, SEL_SSI8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_IPSR_MSEL(IP11_27_24, MSIOF0_SS2_A, SEL_MSIOF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_IPSR_GPSR(IP11_27_24, DU1_DR7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_IPSR_GPSR(IP11_27_24, QSPI1_SSL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_IPSR_MSEL(IP11_31_28, HRX1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINMUX_IPSR_MSEL(IP11_31_28, SCL4_A, SEL_I2C04_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_IPSR_GPSR(IP11_31_28, PWM6_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_IPSR_GPSR(IP11_31_28, DU1_DG0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_IPSR_MSEL(IP11_31_28, RX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* IPSR12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_IPSR_MSEL(IP12_3_0, HTX1_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_IPSR_MSEL(IP12_3_0, SDA4_A, SEL_I2C04_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINMUX_IPSR_GPSR(IP12_3_0, DU1_DG1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_IPSR_GPSR(IP12_7_4, PWM2_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_IPSR_GPSR(IP12_7_4, DU1_DG2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_IPSR_MSEL(IP12_7_4, REMOCON_B, SEL_RCN_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_A, SEL_HSCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_IPSR_GPSR(IP12_11_8, DU1_DG3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_IPSR_MSEL(IP12_11_8, SSI_WS1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINMUX_IPSR_GPSR(IP12_11_8, IRQ1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINMUX_IPSR_GPSR(IP12_15_12, SD2_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_IPSR_GPSR(IP12_15_12, HSCK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_IPSR_GPSR(IP12_15_12, DU1_DG4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_IPSR_MSEL(IP12_15_12, SSI_SCK1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_IPSR_GPSR(IP12_19_16, SD2_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_IPSR_MSEL(IP12_19_16, SCIF1_SCK_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_IPSR_MSEL(IP12_19_16, TCLK2_A, SEL_TMU2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINMUX_IPSR_GPSR(IP12_19_16, DU1_DG5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_IPSR_MSEL(IP12_19_16, SSI_SCK2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_IPSR_GPSR(IP12_19_16, PWM3_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_IPSR_GPSR(IP12_23_20, SD2_DAT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_IPSR_MSEL(IP12_23_20, RX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_IPSR_MSEL(IP12_23_20, SCL1_E, SEL_I2C01_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_IPSR_GPSR(IP12_23_20, DU1_DG6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINMUX_IPSR_MSEL(IP12_23_20, SSI_SDATA1_B, SEL_SSI1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_IPSR_GPSR(IP12_27_24, SD2_DAT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_IPSR_MSEL(IP12_27_24, TX1_A, SEL_SCIF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_IPSR_MSEL(IP12_27_24, SDA1_E, SEL_I2C01_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_IPSR_GPSR(IP12_27_24, DU1_DG7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_IPSR_GPSR(IP12_31_28, SD2_DAT2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_IPSR_MSEL(IP12_31_28, RX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_IPSR_GPSR(IP12_31_28, DU1_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_IPSR_MSEL(IP12_31_28, SSI_SDATA2_B, SEL_SSI2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* IPSR13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_IPSR_GPSR(IP13_3_0, SD2_DAT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINMUX_IPSR_GPSR(IP13_3_0, DU1_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_IPSR_MSEL(IP13_3_0, SSI_WS9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_IPSR_GPSR(IP13_7_4, SD2_CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_IPSR_MSEL(IP13_7_4, SCIF2_SCK_A, SEL_SCIF2_CLK_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_IPSR_GPSR(IP13_7_4, DU1_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_IPSR_MSEL(IP13_7_4, SSI_SCK9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_IPSR_GPSR(IP13_11_8, SD2_WP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_IPSR_GPSR(IP13_11_8, SCIF3_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_IPSR_GPSR(IP13_11_8, DU1_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA9_B, SEL_SSI9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_IPSR_MSEL(IP13_15_12, RX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_IPSR_MSEL(IP13_15_12, SCL1_C, SEL_I2C01_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_IPSR_GPSR(IP13_15_12, DU1_DB4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_IPSR_MSEL(IP13_15_12, AUDIO_CLKA_C, SEL_ADGA_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA4_B, SEL_SSI4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_IPSR_MSEL(IP13_19_16, TX3_A, SEL_SCIF3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_IPSR_MSEL(IP13_19_16, SDA1_C, SEL_I2C01_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_IPSR_GPSR(IP13_19_16, DU1_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_IPSR_MSEL(IP13_19_16, AUDIO_CLKB_C, SEL_ADGB_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_IPSR_MSEL(IP13_19_16, SSI_WS4_B, SEL_SSI4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_IPSR_MSEL(IP13_23_20, SCL2_A, SEL_I2C02_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SCK_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINMUX_IPSR_GPSR(IP13_23_20, DU1_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_IPSR_MSEL(IP13_23_20, AUDIO_CLKC_C, SEL_ADGC_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK4_B, SEL_SSI4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_IPSR_MSEL(IP13_27_24, SDA2_A, SEL_I2C02_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SYNC_B, SEL_MSIOF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINMUX_IPSR_GPSR(IP13_27_24, DU1_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_IPSR_MSEL(IP13_31_28, SSI_SCK5_A, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_IPSR_GPSR(IP13_31_28, DU1_DOTCLKOUT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* IPSR14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_IPSR_MSEL(IP14_3_0, SSI_WS5_A, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINMUX_IPSR_MSEL(IP14_3_0, SCL3_C, SEL_I2C03_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINMUX_IPSR_GPSR(IP14_3_0, DU1_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA5_A, SEL_SSI5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_IPSR_MSEL(IP14_7_4, SDA3_C, SEL_I2C03_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_IPSR_GPSR(IP14_7_4, DU1_DOTCLKOUT0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_IPSR_MSEL(IP14_11_8, SSI_SCK6_A, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_IPSR_GPSR(IP14_11_8, DU1_EXODDF_DU1_ODDF_DISP_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_IPSR_MSEL(IP14_15_12, SSI_WS6_A, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINMUX_IPSR_MSEL(IP14_15_12, SCL4_C, SEL_I2C04_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_IPSR_GPSR(IP14_15_12, DU1_EXHSYNC_DU1_HSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_IPSR_MSEL(IP14_19_16, SSI_SDATA6_A, SEL_SSI6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_IPSR_MSEL(IP14_19_16, SDA4_C, SEL_I2C04_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_IPSR_GPSR(IP14_19_16, DU1_EXVSYNC_DU1_VSYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_IPSR_MSEL(IP14_23_20, SSI_SCK78_A, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_IPSR_MSEL(IP14_23_20, SDA4_E, SEL_I2C04_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_IPSR_GPSR(IP14_23_20, DU1_DISP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_IPSR_MSEL(IP14_27_24, SSI_WS78_A, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_IPSR_MSEL(IP14_27_24, SCL4_E, SEL_I2C04_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_IPSR_GPSR(IP14_27_24, DU1_CDE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_IPSR_MSEL(IP14_31_28, SSI_SDATA7_A, SEL_SSI7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_IPSR_GPSR(IP14_31_28, IRQ8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_IPSR_MSEL(IP14_31_28, AUDIO_CLKA_D, SEL_ADGA_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_IPSR_MSEL(IP14_31_28, CAN_CLK_D, SEL_CANCLK_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_IPSR_GPSR(IP14_31_28, VI0_G5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* IPSR15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_IPSR_MSEL(IP15_3_0, SSI_SCK0129_A, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_IPSR_MSEL(IP15_3_0, MSIOF1_RXD_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_IPSR_MSEL(IP15_3_0, RX5_D, SEL_SCIF5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_IPSR_GPSR(IP15_3_0, VI0_G6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_IPSR_MSEL(IP15_7_4, SSI_WS0129_A, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_IPSR_MSEL(IP15_7_4, MSIOF1_TXD_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_IPSR_MSEL(IP15_7_4, TX5_D, SEL_SCIF5_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINMUX_IPSR_GPSR(IP15_7_4, VI0_G7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_IPSR_MSEL(IP15_11_8, SSI_SDATA0_A, SEL_SSI0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SYNC_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_IPSR_GPSR(IP15_11_8, PWM0_C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_IPSR_GPSR(IP15_11_8, VI0_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_IPSR_GPSR(IP15_15_12, AVB_MDC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_IPSR_GPSR(IP15_15_12, DACK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_IPSR_GPSR(IP15_15_12, VI0_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SS1_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_IPSR_GPSR(IP15_19_16, AVB_MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINMUX_IPSR_MSEL(IP15_19_16, CAN1_RX_A, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_IPSR_GPSR(IP15_19_16, DREQ1_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_IPSR_GPSR(IP15_19_16, VI0_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SS2_A, SEL_MSIOF1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_IPSR_GPSR(IP15_23_20, AVB_LINK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_IPSR_MSEL(IP15_23_20, CAN1_TX_A, SEL_CAN1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_IPSR_GPSR(IP15_23_20, DREQ2_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_IPSR_GPSR(IP15_23_20, VI0_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_IPSR_MSEL(IP15_27_24, SSI_SCK4_A, SEL_SSI4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_IPSR_GPSR(IP15_27_24, AVB_MAGIC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_IPSR_GPSR(IP15_27_24, VI0_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS4_A, SEL_SSI4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_IPSR_GPSR(IP15_31_28, AVB_PHY_INT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_IPSR_GPSR(IP15_31_28, VI0_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* IPSR16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_IPSR_MSEL(IP16_3_0, SSI_SDATA4_A, SEL_SSI4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_IPSR_GPSR(IP16_3_0, AVB_CRS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) PINMUX_IPSR_GPSR(IP16_3_0, VI0_R6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) PINMUX_IPSR_MSEL(IP16_7_4, SSI_SCK1_A, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_IPSR_MSEL(IP16_7_4, SCIF1_SCK_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_IPSR_GPSR(IP16_7_4, PWM1_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_IPSR_GPSR(IP16_7_4, IRQ9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_RCN_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_IPSR_GPSR(IP16_7_4, DACK2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_IPSR_GPSR(IP16_7_4, VI0_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_IPSR_GPSR(IP16_7_4, AVB_COL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_IPSR_MSEL(IP16_11_8, SSI_SDATA8_A, SEL_SSI8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_IPSR_MSEL(IP16_11_8, RX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_IPSR_MSEL(IP16_11_8, CAN0_RX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_IPSR_MSEL(IP16_11_8, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_IPSR_GPSR(IP16_11_8, VI0_R7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_IPSR_MSEL(IP16_15_12, SSI_WS1_A, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_IPSR_MSEL(IP16_15_12, TX1_B, SEL_SCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_IPSR_MSEL(IP16_15_12, CAN0_TX_D, SEL_CAN0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_IPSR_MSEL(IP16_15_12, AVB_AVTP_MATCH_B, SEL_AVB_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_IPSR_GPSR(IP16_15_12, VI0_DATA0_VI0_B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) PINMUX_IPSR_MSEL(IP16_19_16, SSI_SDATA1_A, SEL_SSI1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_IPSR_MSEL(IP16_19_16, HRX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_IPSR_GPSR(IP16_19_16, VI0_DATA1_VI0_B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_IPSR_MSEL(IP16_23_20, SSI_SCK2_A, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_IPSR_MSEL(IP16_23_20, HTX1_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_IPSR_GPSR(IP16_23_20, AVB_TXD7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_IPSR_GPSR(IP16_23_20, VI0_DATA2_VI0_B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_IPSR_MSEL(IP16_27_24, SSI_WS2_A, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_IPSR_MSEL(IP16_27_24, HCTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_IPSR_GPSR(IP16_27_24, AVB_TX_ER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) PINMUX_IPSR_GPSR(IP16_27_24, VI0_DATA3_VI0_B3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA2_A, SEL_SSI2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_IPSR_MSEL(IP16_31_28, HRTS1_N_B, SEL_HSCIF1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINMUX_IPSR_GPSR(IP16_31_28, VI0_DATA4_VI0_B4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* IPSR17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_A, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) PINMUX_IPSR_MSEL(IP17_3_0, RX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_IPSR_MSEL(IP17_3_0, SCL3_E, SEL_I2C03_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINMUX_IPSR_GPSR(IP17_3_0, EX_WAIT1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_IPSR_GPSR(IP17_3_0, VI0_DATA5_VI0_B5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_A, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_IPSR_MSEL(IP17_7_4, TX2_B, SEL_SCIF2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_IPSR_MSEL(IP17_7_4, SDA3_E, SEL_I2C03_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_IPSR_GPSR(IP17_7_4, VI0_DATA6_VI0_B6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) PINMUX_IPSR_MSEL(IP17_11_8, SSI_SDATA9_A, SEL_SSI9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_IPSR_GPSR(IP17_11_8, SCIF2_SCK_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_IPSR_GPSR(IP17_11_8, PWM2_D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_IPSR_GPSR(IP17_11_8, VI0_DATA7_VI0_B7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_IPSR_MSEL(IP17_15_12, AUDIO_CLKA_A, SEL_ADGA_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_IPSR_MSEL(IP17_15_12, SCL0_B, SEL_I2C00_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) PINMUX_IPSR_GPSR(IP17_15_12, VI0_CLKENB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) PINMUX_IPSR_MSEL(IP17_19_16, AUDIO_CLKB_A, SEL_ADGB_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_IPSR_MSEL(IP17_19_16, SDA0_B, SEL_I2C00_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_IPSR_GPSR(IP17_19_16, VI0_FIELD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_IPSR_MSEL(IP17_23_20, AUDIO_CLKC_A, SEL_ADGC_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_IPSR_MSEL(IP17_23_20, SCL4_B, SEL_I2C04_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_IPSR_GPSR(IP17_23_20, VI0_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) PINMUX_IPSR_MSEL(IP17_27_24, SDA4_B, SEL_I2C04_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_IPSR_GPSR(IP17_27_24, VI0_VSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_GPIO_GP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* - AVB -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const unsigned int avb_col_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const unsigned int avb_col_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) AVB_COL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static const unsigned int avb_crs_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) RCAR_GP_PIN(5, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const unsigned int avb_crs_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) AVB_CRS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static const unsigned int avb_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const unsigned int avb_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) AVB_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static const unsigned int avb_magic_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) RCAR_GP_PIN(5, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const unsigned int avb_magic_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) AVB_MAGIC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static const unsigned int avb_phy_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) static const unsigned int avb_phy_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) AVB_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const unsigned int avb_mdio_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static const unsigned int avb_mdio_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) AVB_MDC_MARK, AVB_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static const unsigned int avb_mii_tx_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static const unsigned int avb_mii_tx_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) AVB_TX_CLK_MARK, AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) AVB_TXD3_MARK, AVB_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) AVB_RXD3_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static const unsigned int avb_mii_tx_er_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static const unsigned int avb_mii_tx_er_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) AVB_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const unsigned int avb_gmii_tx_rx_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) RCAR_GP_PIN(4, 1), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(5, 22), RCAR_GP_PIN(3, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const unsigned int avb_gmii_tx_rx_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK, AVB_TX_CLK_MARK, AVB_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) AVB_TXD1_MARK, AVB_TXD2_MARK, AVB_TXD3_MARK, AVB_TXD4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) AVB_TXD5_MARK, AVB_TXD6_MARK, AVB_TXD7_MARK, AVB_TX_EN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) AVB_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) AVB_RX_CLK_MARK, AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK, AVB_RXD6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) AVB_RXD7_MARK, AVB_RX_DV_MARK, AVB_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static const unsigned int avb_avtp_match_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) RCAR_GP_PIN(1, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const unsigned int avb_avtp_match_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) AVB_AVTP_MATCH_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static const unsigned int avb_avtp_capture_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static const unsigned int avb_avtp_capture_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) AVB_AVTP_CAPTURE_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const unsigned int avb_avtp_match_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static const unsigned int avb_avtp_match_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) AVB_AVTP_MATCH_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static const unsigned int avb_avtp_capture_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static const unsigned int avb_avtp_capture_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) AVB_AVTP_CAPTURE_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) /* - DU --------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const unsigned int du0_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const unsigned int du0_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) DU0_DR3_MARK, DU0_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) DU0_DG3_MARK, DU0_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) DU0_DB3_MARK, DU0_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const unsigned int du0_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22), RCAR_GP_PIN(2, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static const unsigned int du0_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const unsigned int du0_clk0_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* DOTCLKOUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) RCAR_GP_PIN(2, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const unsigned int du0_clk0_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) DU0_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const unsigned int du0_clk1_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* DOTCLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) RCAR_GP_PIN(2, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const unsigned int du0_clk1_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) DU0_DOTCLKOUT1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static const unsigned int du0_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* CLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) RCAR_GP_PIN(2, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static const unsigned int du0_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) DU0_DOTCLKIN_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const unsigned int du0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const unsigned int du0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) DU0_EXVSYNC_DU0_VSYNC_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const unsigned int du0_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /* EXODDF/ODDF/DISP/CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) RCAR_GP_PIN(2, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static const unsigned int du0_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const unsigned int du0_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) RCAR_GP_PIN(2, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const unsigned int du0_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) DU0_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const unsigned int du0_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) RCAR_GP_PIN(2, 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const unsigned int du0_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) DU0_DISP_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static const unsigned int du1_rgb666_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* R[7:2], G[7:2], B[7:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static const unsigned int du1_rgb666_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) DU1_DR3_MARK, DU1_DR2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) DU1_DG3_MARK, DU1_DG2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) DU1_DB3_MARK, DU1_DB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static const unsigned int du1_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* R[7:0], G[7:0], B[7:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static const unsigned int du1_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static const unsigned int du1_clk0_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* DOTCLKOUT0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) static const unsigned int du1_clk0_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) DU1_DOTCLKOUT0_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static const unsigned int du1_clk1_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* DOTCLKOUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) RCAR_GP_PIN(5, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const unsigned int du1_clk1_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) DU1_DOTCLKOUT1_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static const unsigned int du1_clk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* DOTCLKIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) RCAR_GP_PIN(5, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const unsigned int du1_clk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) DU1_DOTCLKIN_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static const unsigned int du1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const unsigned int du1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static const unsigned int du1_oddf_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* EXODDF/ODDF/DISP/CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) RCAR_GP_PIN(5, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) static const unsigned int du1_oddf_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static const unsigned int du1_cde_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /* CDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) RCAR_GP_PIN(5, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static const unsigned int du1_cde_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) DU1_CDE_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static const unsigned int du1_disp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static const unsigned int du1_disp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) DU1_DISP_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* - I2C0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static const unsigned int i2c0_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static const unsigned int i2c0_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) SCL0_A_MARK, SDA0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const unsigned int i2c0_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) static const unsigned int i2c0_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) SCL0_B_MARK, SDA0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const unsigned int i2c0_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static const unsigned int i2c0_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SCL0_C_MARK, SDA0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const unsigned int i2c0_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static const unsigned int i2c0_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) SCL0_D_MARK, SDA0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static const unsigned int i2c0_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static const unsigned int i2c0_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) SCL0_E_MARK, SDA0_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* - I2C1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static const unsigned int i2c1_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static const unsigned int i2c1_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) SCL1_A_MARK, SDA1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static const unsigned int i2c1_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static const unsigned int i2c1_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) SCL1_B_MARK, SDA1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const unsigned int i2c1_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) static const unsigned int i2c1_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) SCL1_C_MARK, SDA1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const unsigned int i2c1_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static const unsigned int i2c1_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) SCL1_D_MARK, SDA1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const unsigned int i2c1_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const unsigned int i2c1_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) SCL1_E_MARK, SDA1_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* - I2C2 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const unsigned int i2c2_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const unsigned int i2c2_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) SCL2_A_MARK, SDA2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static const unsigned int i2c2_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static const unsigned int i2c2_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) SCL2_B_MARK, SDA2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static const unsigned int i2c2_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static const unsigned int i2c2_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SCL2_C_MARK, SDA2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static const unsigned int i2c2_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static const unsigned int i2c2_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) SCL2_D_MARK, SDA2_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) /* - I2C3 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static const unsigned int i2c3_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const unsigned int i2c3_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) SCL3_A_MARK, SDA3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static const unsigned int i2c3_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const unsigned int i2c3_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) SCL3_B_MARK, SDA3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const unsigned int i2c3_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static const unsigned int i2c3_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) SCL3_C_MARK, SDA3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static const unsigned int i2c3_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static const unsigned int i2c3_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) SCL3_D_MARK, SDA3_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static const unsigned int i2c3_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static const unsigned int i2c3_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) SCL3_E_MARK, SDA3_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* - I2C4 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const unsigned int i2c4_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static const unsigned int i2c4_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) SCL4_A_MARK, SDA4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static const unsigned int i2c4_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static const unsigned int i2c4_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SCL4_B_MARK, SDA4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static const unsigned int i2c4_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static const unsigned int i2c4_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) SCL4_C_MARK, SDA4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static const unsigned int i2c4_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) static const unsigned int i2c4_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) SCL4_D_MARK, SDA4_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) static const unsigned int i2c4_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static const unsigned int i2c4_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) SCL4_E_MARK, SDA4_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) /* - MMC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static const unsigned int mmc_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static const unsigned int mmc_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) MMC0_D0_SDHI1_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static const unsigned int mmc_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) static const unsigned int mmc_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static const unsigned int mmc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) static const unsigned int mmc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) MMC0_D4_MARK, MMC0_D5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) MMC0_D6_MARK, MMC0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static const unsigned int mmc_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) static const unsigned int mmc_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* - QSPI ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static const unsigned int qspi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static const unsigned int qspi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) QSPI0_SPCLK_MARK, QSPI0_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static const unsigned int qspi0_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static const unsigned int qspi0_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static const unsigned int qspi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) RCAR_GP_PIN(1, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static const unsigned int qspi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) QSPI0_MOSI_QSPI0_IO0_MARK, QSPI0_MISO_QSPI0_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) QSPI0_IO2_MARK, QSPI0_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const unsigned int qspi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* SPCLK, SSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static const unsigned int qspi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) QSPI1_SPCLK_MARK, QSPI1_SSL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static const unsigned int qspi1_data2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) /* MOSI_IO0, MISO_IO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static const unsigned int qspi1_data2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static const unsigned int qspi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) /* MOSI_IO0, MISO_IO1, IO2, IO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) RCAR_GP_PIN(4, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static const unsigned int qspi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) QSPI1_MOSI_QSPI1_IO0_MARK, QSPI1_MISO_QSPI1_IO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) QSPI1_IO2_MARK, QSPI1_IO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* - SCIF0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static const unsigned int scif0_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static const unsigned int scif0_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) RX0_A_MARK, TX0_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) static const unsigned int scif0_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static const unsigned int scif0_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) RX0_B_MARK, TX0_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static const unsigned int scif0_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static const unsigned int scif0_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) RX0_C_MARK, TX0_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static const unsigned int scif0_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static const unsigned int scif0_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) RX0_D_MARK, TX0_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* - SCIF1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static const unsigned int scif1_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static const unsigned int scif1_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) RX1_A_MARK, TX1_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const unsigned int scif1_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const unsigned int scif1_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) SCIF1_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static const unsigned int scif1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) static const unsigned int scif1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) RX1_B_MARK, TX1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static const unsigned int scif1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static const unsigned int scif1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) SCIF1_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) static const unsigned int scif1_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static const unsigned int scif1_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) RX1_C_MARK, TX1_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static const unsigned int scif1_clk_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) RCAR_GP_PIN(1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) static const unsigned int scif1_clk_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) SCIF1_SCK_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static const unsigned int scif1_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static const unsigned int scif1_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) RX1_D_MARK, TX1_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* - SCIF2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) static const unsigned int scif2_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) static const unsigned int scif2_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) RX2_A_MARK, TX2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static const unsigned int scif2_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) static const unsigned int scif2_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) SCIF2_SCK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) static const unsigned int scif2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static const unsigned int scif2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) RX2_B_MARK, TX2_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) static const unsigned int scif2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) static const unsigned int scif2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) SCIF2_SCK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const unsigned int scif2_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static const unsigned int scif2_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) RX2_C_MARK, TX2_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /* - SCIF3 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) static const unsigned int scif3_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static const unsigned int scif3_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) RX3_A_MARK, TX3_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static const unsigned int scif3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) static const unsigned int scif3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) SCIF3_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const unsigned int scif3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static const unsigned int scif3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) RX3_B_MARK, TX3_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const unsigned int scif3_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static const unsigned int scif3_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) RX3_C_MARK, TX3_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) /* - SCIF4 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) static const unsigned int scif4_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) static const unsigned int scif4_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) RX4_A_MARK, TX4_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static const unsigned int scif4_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) static const unsigned int scif4_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) RX4_B_MARK, TX4_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) static const unsigned int scif4_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) static const unsigned int scif4_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) RX4_C_MARK, TX4_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const unsigned int scif4_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static const unsigned int scif4_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) RX4_D_MARK, TX4_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static const unsigned int scif4_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const unsigned int scif4_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) RX4_E_MARK, TX4_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) /* - SCIF5 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static const unsigned int scif5_data_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static const unsigned int scif5_data_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) RX5_A_MARK, TX5_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static const unsigned int scif5_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static const unsigned int scif5_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) RX5_B_MARK, TX5_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) static const unsigned int scif5_data_c_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static const unsigned int scif5_data_c_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) RX5_C_MARK, TX5_C_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static const unsigned int scif5_data_d_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static const unsigned int scif5_data_d_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) RX5_D_MARK, TX5_D_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static const unsigned int scif5_data_e_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const unsigned int scif5_data_e_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) RX5_E_MARK, TX5_E_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static const unsigned int scif5_data_f_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const unsigned int scif5_data_f_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) RX5_F_MARK, TX5_F_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* - SCIF Clock ------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static const unsigned int scif_clk_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) RCAR_GP_PIN(1, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) static const unsigned int scif_clk_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) SCIF_CLK_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static const unsigned int scif_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) /* SCIF_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) RCAR_GP_PIN(3, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static const unsigned int scif_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) SCIF_CLK_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) RCAR_GP_PIN(0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) SD0_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) SD0_CLK_MARK, SD0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) RCAR_GP_PIN(0, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) SD0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) RCAR_GP_PIN(0, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) SD0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) RCAR_GP_PIN(0, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) MMC0_D0_SDHI1_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) RCAR_GP_PIN(0, 17), RCAR_GP_PIN(0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) MMC0_D0_SDHI1_D0_MARK, MMC0_D1_SDHI1_D1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) MMC0_D2_SDHI1_D2_MARK, MMC0_D3_SDHI1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) MMC0_CLK_SDHI1_CLK_MARK, MMC0_CMD_SDHI1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) RCAR_GP_PIN(0, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) SD1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) RCAR_GP_PIN(0, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) SD1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) RCAR_GP_PIN(4, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) SD2_DAT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) SD2_CLK_MARK, SD2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static const unsigned int sdhi2_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) RCAR_GP_PIN(4, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static const unsigned int sdhi2_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) SD2_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const unsigned int sdhi2_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) RCAR_GP_PIN(4, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) static const unsigned int sdhi2_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) SD2_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* - USB0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static const unsigned int usb0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) RCAR_GP_PIN(0, 0), /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) RCAR_GP_PIN(0, 1), /* OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) static const unsigned int usb0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) USB0_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) USB0_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* - USB1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static const unsigned int usb1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) RCAR_GP_PIN(0, 2), /* PWEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) RCAR_GP_PIN(0, 3), /* OVC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) static const unsigned int usb1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) USB1_PWEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) USB1_OVC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* - VIN0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) static const union vin_data vin0_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static const union vin_data vin0_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .data24 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) VI0_G0_MARK, VI0_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) VI0_R0_MARK, VI0_R1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static const unsigned int vin0_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) RCAR_GP_PIN(4, 6), RCAR_GP_PIN(5, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) static const unsigned int vin0_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) /* G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) VI0_G2_MARK, VI0_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) VI0_G4_MARK, VI0_G5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) VI0_G6_MARK, VI0_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /* R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) VI0_R2_MARK, VI0_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) VI0_R4_MARK, VI0_R5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) VI0_R6_MARK, VI0_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) static const unsigned int vin0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) RCAR_GP_PIN(5, 30), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) RCAR_GP_PIN(5, 31), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static const unsigned int vin0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) VI0_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) VI0_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) static const unsigned int vin0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) RCAR_GP_PIN(5, 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static const unsigned int vin0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) VI0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) static const unsigned int vin0_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) RCAR_GP_PIN(5, 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static const unsigned int vin0_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) VI0_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) static const unsigned int vin0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) RCAR_GP_PIN(5, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) static const unsigned int vin0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) VI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /* - VIN1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) static const union vin_data12 vin1_data_pins = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static const union vin_data12 vin1_data_mux = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) .data12 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) VI1_DATA0_MARK, VI1_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) VI1_DATA2_MARK, VI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) VI1_DATA4_MARK, VI1_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) VI1_DATA6_MARK, VI1_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) VI1_DATA8_MARK, VI1_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) VI1_DATA10_MARK, VI1_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) static const unsigned int vin1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) RCAR_GP_PIN(3, 11), /* HSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) RCAR_GP_PIN(3, 12), /* VSYNC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static const unsigned int vin1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) VI1_HSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) VI1_VSYNC_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static const unsigned int vin1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) RCAR_GP_PIN(3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static const unsigned int vin1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) VI1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) static const unsigned int vin1_clkenb_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) RCAR_GP_PIN(3, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static const unsigned int vin1_clkenb_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) VI1_CLKENB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static const unsigned int vin1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) RCAR_GP_PIN(3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static const unsigned int vin1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) VI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) SH_PFC_PIN_GROUP(avb_col),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) SH_PFC_PIN_GROUP(avb_crs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) SH_PFC_PIN_GROUP(avb_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) SH_PFC_PIN_GROUP(avb_magic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) SH_PFC_PIN_GROUP(avb_phy_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) SH_PFC_PIN_GROUP(avb_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) SH_PFC_PIN_GROUP(avb_mii_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) SH_PFC_PIN_GROUP(avb_mii_tx_er),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) SH_PFC_PIN_GROUP(avb_gmii_tx_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) SH_PFC_PIN_GROUP(avb_avtp_match_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) SH_PFC_PIN_GROUP(avb_avtp_capture_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) SH_PFC_PIN_GROUP(avb_avtp_match_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) SH_PFC_PIN_GROUP(avb_avtp_capture_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) SH_PFC_PIN_GROUP(du0_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) SH_PFC_PIN_GROUP(du0_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) SH_PFC_PIN_GROUP(du0_clk0_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) SH_PFC_PIN_GROUP(du0_clk1_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) SH_PFC_PIN_GROUP(du0_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) SH_PFC_PIN_GROUP(du0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) SH_PFC_PIN_GROUP(du0_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) SH_PFC_PIN_GROUP(du0_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) SH_PFC_PIN_GROUP(du0_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) SH_PFC_PIN_GROUP(du1_rgb666),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) SH_PFC_PIN_GROUP(du1_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) SH_PFC_PIN_GROUP(du1_clk0_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) SH_PFC_PIN_GROUP(du1_clk1_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) SH_PFC_PIN_GROUP(du1_clk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) SH_PFC_PIN_GROUP(du1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) SH_PFC_PIN_GROUP(du1_oddf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) SH_PFC_PIN_GROUP(du1_cde),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) SH_PFC_PIN_GROUP(du1_disp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) SH_PFC_PIN_GROUP(i2c0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) SH_PFC_PIN_GROUP(i2c0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) SH_PFC_PIN_GROUP(i2c0_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) SH_PFC_PIN_GROUP(i2c0_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) SH_PFC_PIN_GROUP(i2c0_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) SH_PFC_PIN_GROUP(i2c1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) SH_PFC_PIN_GROUP(i2c1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) SH_PFC_PIN_GROUP(i2c1_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) SH_PFC_PIN_GROUP(i2c1_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) SH_PFC_PIN_GROUP(i2c1_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) SH_PFC_PIN_GROUP(i2c2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) SH_PFC_PIN_GROUP(i2c2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) SH_PFC_PIN_GROUP(i2c2_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) SH_PFC_PIN_GROUP(i2c2_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) SH_PFC_PIN_GROUP(i2c3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) SH_PFC_PIN_GROUP(i2c3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) SH_PFC_PIN_GROUP(i2c3_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) SH_PFC_PIN_GROUP(i2c3_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) SH_PFC_PIN_GROUP(i2c3_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) SH_PFC_PIN_GROUP(i2c4_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) SH_PFC_PIN_GROUP(i2c4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) SH_PFC_PIN_GROUP(i2c4_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) SH_PFC_PIN_GROUP(i2c4_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) SH_PFC_PIN_GROUP(i2c4_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) SH_PFC_PIN_GROUP(mmc_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) SH_PFC_PIN_GROUP(mmc_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) SH_PFC_PIN_GROUP(mmc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) SH_PFC_PIN_GROUP(mmc_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) SH_PFC_PIN_GROUP(qspi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) SH_PFC_PIN_GROUP(qspi0_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) SH_PFC_PIN_GROUP(qspi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) SH_PFC_PIN_GROUP(qspi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) SH_PFC_PIN_GROUP(qspi1_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) SH_PFC_PIN_GROUP(qspi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) SH_PFC_PIN_GROUP(scif0_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) SH_PFC_PIN_GROUP(scif0_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) SH_PFC_PIN_GROUP(scif0_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) SH_PFC_PIN_GROUP(scif0_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) SH_PFC_PIN_GROUP(scif1_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) SH_PFC_PIN_GROUP(scif1_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) SH_PFC_PIN_GROUP(scif1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) SH_PFC_PIN_GROUP(scif1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) SH_PFC_PIN_GROUP(scif1_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) SH_PFC_PIN_GROUP(scif1_clk_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) SH_PFC_PIN_GROUP(scif1_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) SH_PFC_PIN_GROUP(scif2_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) SH_PFC_PIN_GROUP(scif2_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) SH_PFC_PIN_GROUP(scif2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) SH_PFC_PIN_GROUP(scif2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) SH_PFC_PIN_GROUP(scif2_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) SH_PFC_PIN_GROUP(scif3_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) SH_PFC_PIN_GROUP(scif3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) SH_PFC_PIN_GROUP(scif3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) SH_PFC_PIN_GROUP(scif3_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) SH_PFC_PIN_GROUP(scif4_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) SH_PFC_PIN_GROUP(scif4_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) SH_PFC_PIN_GROUP(scif4_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) SH_PFC_PIN_GROUP(scif4_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) SH_PFC_PIN_GROUP(scif4_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) SH_PFC_PIN_GROUP(scif5_data_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) SH_PFC_PIN_GROUP(scif5_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) SH_PFC_PIN_GROUP(scif5_data_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) SH_PFC_PIN_GROUP(scif5_data_d),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) SH_PFC_PIN_GROUP(scif5_data_e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) SH_PFC_PIN_GROUP(scif5_data_f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) SH_PFC_PIN_GROUP(scif_clk_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) SH_PFC_PIN_GROUP(scif_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) SH_PFC_PIN_GROUP(sdhi2_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) SH_PFC_PIN_GROUP(sdhi2_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) SH_PFC_PIN_GROUP(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) SH_PFC_PIN_GROUP(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) VIN_DATA_PIN_GROUP(vin0_data, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) VIN_DATA_PIN_GROUP(vin0_data, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) SH_PFC_PIN_GROUP(vin0_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) VIN_DATA_PIN_GROUP(vin0_data, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) VIN_DATA_PIN_GROUP(vin0_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) VIN_DATA_PIN_GROUP(vin0_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) VIN_DATA_PIN_GROUP(vin0_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) SH_PFC_PIN_GROUP(vin0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) SH_PFC_PIN_GROUP(vin0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) SH_PFC_PIN_GROUP(vin0_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) SH_PFC_PIN_GROUP(vin0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) VIN_DATA_PIN_GROUP(vin1_data, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) VIN_DATA_PIN_GROUP(vin1_data, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) VIN_DATA_PIN_GROUP(vin1_data, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) SH_PFC_PIN_GROUP(vin1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) SH_PFC_PIN_GROUP(vin1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) SH_PFC_PIN_GROUP(vin1_clkenb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) SH_PFC_PIN_GROUP(vin1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) static const char * const avb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) "avb_col",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) "avb_crs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) "avb_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) "avb_magic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) "avb_phy_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "avb_mdio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) "avb_mii_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) "avb_mii_tx_er",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) "avb_gmii_tx_rx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) "avb_avtp_match_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) "avb_avtp_capture_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) "avb_avtp_match_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) "avb_avtp_capture_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) static const char * const du0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) "du0_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) "du0_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) "du0_clk0_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) "du0_clk1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) "du0_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) "du0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) "du0_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) "du0_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) "du0_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) static const char * const du1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) "du1_rgb666",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) "du1_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) "du1_clk0_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) "du1_clk1_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) "du1_clk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) "du1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) "du1_oddf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) "du1_cde",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) "du1_disp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static const char * const i2c0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) "i2c0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) "i2c0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) "i2c0_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) "i2c0_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) "i2c0_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) static const char * const i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) "i2c1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) "i2c1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) "i2c1_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) "i2c1_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) "i2c1_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) static const char * const i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) "i2c2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) "i2c2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) "i2c2_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) "i2c2_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) static const char * const i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) "i2c3_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) "i2c3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) "i2c3_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) "i2c3_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) "i2c3_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) static const char * const i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) "i2c4_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) "i2c4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) "i2c4_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "i2c4_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) "i2c4_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) static const char * const mmc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) "mmc_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) "mmc_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) "mmc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) "mmc_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) static const char * const qspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) "qspi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) "qspi0_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) "qspi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) static const char * const qspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) "qspi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) "qspi1_data2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) "qspi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static const char * const scif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) "scif0_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) "scif0_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) "scif0_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) "scif0_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) static const char * const scif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) "scif1_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) "scif1_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) "scif1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "scif1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) "scif1_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) "scif1_clk_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) "scif1_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) static const char * const scif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) "scif2_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) "scif2_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) "scif2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) "scif2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) "scif2_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) static const char * const scif3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) "scif3_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) "scif3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) "scif3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) "scif3_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) static const char * const scif4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) "scif4_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) "scif4_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) "scif4_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) "scif4_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) "scif4_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static const char * const scif5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) "scif5_data_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) "scif5_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) "scif5_data_c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) "scif5_data_d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) "scif5_data_e",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) "scif5_data_f",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) static const char * const scif_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) "scif_clk_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) "scif_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) "sdhi2_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) "sdhi2_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) static const char * const usb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) "usb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) static const char * const usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) "usb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static const char * const vin0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) "vin0_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) "vin0_data20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) "vin0_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) "vin0_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) "vin0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) "vin0_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) "vin0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) "vin0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) "vin0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) "vin0_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) "vin0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) static const char * const vin1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) "vin1_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) "vin1_data10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) "vin1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) "vin1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) "vin1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) "vin1_clkenb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) "vin1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) SH_PFC_FUNCTION(avb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) SH_PFC_FUNCTION(du0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) SH_PFC_FUNCTION(du1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) SH_PFC_FUNCTION(i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) SH_PFC_FUNCTION(i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) SH_PFC_FUNCTION(i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) SH_PFC_FUNCTION(i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) SH_PFC_FUNCTION(i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) SH_PFC_FUNCTION(mmc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) SH_PFC_FUNCTION(qspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) SH_PFC_FUNCTION(qspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) SH_PFC_FUNCTION(scif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) SH_PFC_FUNCTION(scif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) SH_PFC_FUNCTION(scif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) SH_PFC_FUNCTION(scif3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) SH_PFC_FUNCTION(scif4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) SH_PFC_FUNCTION(scif5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) SH_PFC_FUNCTION(scif_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) SH_PFC_FUNCTION(usb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) SH_PFC_FUNCTION(usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) SH_PFC_FUNCTION(vin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) SH_PFC_FUNCTION(vin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) GP_0_22_FN, FN_MMC0_D7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) GP_0_21_FN, FN_MMC0_D6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) GP_0_20_FN, FN_IP1_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) GP_0_19_FN, FN_IP1_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) GP_0_18_FN, FN_MMC0_D3_SDHI1_D3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) GP_0_17_FN, FN_MMC0_D2_SDHI1_D2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) GP_0_16_FN, FN_MMC0_D1_SDHI1_D1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) GP_0_15_FN, FN_MMC0_D0_SDHI1_D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) GP_0_14_FN, FN_MMC0_CMD_SDHI1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) GP_0_13_FN, FN_MMC0_CLK_SDHI1_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) GP_0_12_FN, FN_IP0_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) GP_0_11_FN, FN_IP0_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) GP_0_10_FN, FN_IP0_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) GP_0_9_FN, FN_IP0_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) GP_0_8_FN, FN_IP0_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) GP_0_7_FN, FN_IP0_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) GP_0_6_FN, FN_IP0_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) GP_0_5_FN, FN_IP0_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) GP_0_4_FN, FN_CLKOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) GP_0_3_FN, FN_USB1_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) GP_0_2_FN, FN_USB1_PWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) GP_0_1_FN, FN_USB0_OVC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) GP_0_0_FN, FN_USB0_PWEN, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) GP_1_22_FN, FN_IP4_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) GP_1_21_FN, FN_IP3_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) GP_1_20_FN, FN_IP3_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) GP_1_19_FN, FN_IP3_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) GP_1_18_FN, FN_IP3_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) GP_1_17_FN, FN_IP3_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) GP_1_16_FN, FN_IP3_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) GP_1_15_FN, FN_IP3_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) GP_1_14_FN, FN_IP3_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) GP_1_13_FN, FN_IP2_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) GP_1_12_FN, FN_IP2_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) GP_1_11_FN, FN_IP2_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) GP_1_10_FN, FN_IP2_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) GP_1_9_FN, FN_IP2_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) GP_1_8_FN, FN_IP2_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) GP_1_7_FN, FN_IP2_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) GP_1_6_FN, FN_IP2_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) GP_1_5_FN, FN_IP1_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) GP_1_4_FN, FN_IP1_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) GP_1_3_FN, FN_IP1_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) GP_1_2_FN, FN_IP1_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) GP_1_1_FN, FN_IP1_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) GP_1_0_FN, FN_IP1_11_8, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) GP_2_31_FN, FN_IP8_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) GP_2_30_FN, FN_IP7_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) GP_2_29_FN, FN_IP7_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) GP_2_28_FN, FN_IP7_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) GP_2_27_FN, FN_IP7_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) GP_2_26_FN, FN_IP7_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) GP_2_25_FN, FN_IP7_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) GP_2_24_FN, FN_IP7_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) GP_2_23_FN, FN_IP7_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) GP_2_22_FN, FN_IP6_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) GP_2_21_FN, FN_IP6_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) GP_2_20_FN, FN_IP6_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) GP_2_19_FN, FN_IP6_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) GP_2_18_FN, FN_IP6_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) GP_2_17_FN, FN_IP6_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) GP_2_16_FN, FN_IP6_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) GP_2_15_FN, FN_IP6_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) GP_2_14_FN, FN_IP5_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) GP_2_13_FN, FN_IP5_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) GP_2_12_FN, FN_IP5_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) GP_2_11_FN, FN_IP5_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) GP_2_10_FN, FN_IP5_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) GP_2_9_FN, FN_IP5_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) GP_2_8_FN, FN_IP5_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) GP_2_7_FN, FN_IP5_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) GP_2_6_FN, FN_IP4_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) GP_2_5_FN, FN_IP4_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) GP_2_4_FN, FN_IP4_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) GP_2_3_FN, FN_IP4_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) GP_2_2_FN, FN_IP4_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) GP_2_1_FN, FN_IP4_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) GP_2_0_FN, FN_IP4_7_4, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) GP_3_29_FN, FN_IP10_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) GP_3_28_FN, FN_IP10_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) GP_3_27_FN, FN_IP10_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) GP_3_16_FN, FN_IP10_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) GP_3_15_FN, FN_IP10_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) GP_3_14_FN, FN_IP9_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) GP_3_13_FN, FN_IP9_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) GP_3_12_FN, FN_IP9_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) GP_3_11_FN, FN_IP9_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) GP_3_10_FN, FN_IP9_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) GP_3_9_FN, FN_IP9_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) GP_3_8_FN, FN_IP9_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) GP_3_7_FN, FN_IP9_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) GP_3_6_FN, FN_IP8_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) GP_3_5_FN, FN_IP8_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) GP_3_4_FN, FN_IP8_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) GP_3_3_FN, FN_IP8_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) GP_3_2_FN, FN_IP8_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) GP_3_1_FN, FN_IP8_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) GP_3_0_FN, FN_IP8_7_4, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) GP_4_25_FN, FN_IP13_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) GP_4_24_FN, FN_IP13_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) GP_4_23_FN, FN_IP13_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) GP_4_22_FN, FN_IP13_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) GP_4_21_FN, FN_IP13_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) GP_4_20_FN, FN_IP13_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) GP_4_19_FN, FN_IP13_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) GP_4_18_FN, FN_IP12_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) GP_4_17_FN, FN_IP12_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) GP_4_16_FN, FN_IP12_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) GP_4_15_FN, FN_IP12_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) GP_4_14_FN, FN_IP12_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) GP_4_13_FN, FN_IP12_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) GP_4_12_FN, FN_IP12_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) GP_4_11_FN, FN_IP12_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) GP_4_10_FN, FN_IP11_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) GP_4_9_FN, FN_IP11_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) GP_4_8_FN, FN_IP11_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) GP_4_7_FN, FN_IP11_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) GP_4_6_FN, FN_IP11_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) GP_4_5_FN, FN_IP11_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) GP_4_4_FN, FN_IP11_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) GP_4_3_FN, FN_IP11_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) GP_4_2_FN, FN_IP10_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) GP_4_1_FN, FN_IP10_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) GP_4_0_FN, FN_IP10_23_20, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) GP_5_31_FN, FN_IP17_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) GP_5_30_FN, FN_IP17_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) GP_5_29_FN, FN_IP17_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) GP_5_28_FN, FN_IP17_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) GP_5_27_FN, FN_IP17_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) GP_5_26_FN, FN_IP17_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) GP_5_25_FN, FN_IP17_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) GP_5_24_FN, FN_IP16_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) GP_5_23_FN, FN_IP16_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) GP_5_22_FN, FN_IP16_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) GP_5_21_FN, FN_IP16_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) GP_5_20_FN, FN_IP16_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) GP_5_19_FN, FN_IP16_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) GP_5_18_FN, FN_IP16_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) GP_5_17_FN, FN_IP16_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) GP_5_16_FN, FN_IP15_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) GP_5_15_FN, FN_IP15_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) GP_5_14_FN, FN_IP15_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) GP_5_13_FN, FN_IP15_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) GP_5_12_FN, FN_IP15_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) GP_5_11_FN, FN_IP15_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) GP_5_10_FN, FN_IP15_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) GP_5_9_FN, FN_IP15_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) GP_5_8_FN, FN_IP14_31_28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) GP_5_7_FN, FN_IP14_27_24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) GP_5_6_FN, FN_IP14_23_20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) GP_5_5_FN, FN_IP14_19_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) GP_5_4_FN, FN_IP14_15_12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) GP_5_3_FN, FN_IP14_11_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) GP_5_2_FN, FN_IP14_7_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) GP_5_1_FN, FN_IP14_3_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) GP_5_0_FN, FN_IP13_31_28, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060040, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) /* IP0_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) FN_SD0_WP, FN_IRQ7, FN_CAN0_TX_A, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) /* IP0_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) FN_SD0_CD, 0, FN_CAN0_RX_A, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) /* IP0_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) FN_SD0_DAT3, 0, 0, FN_SSI_SDATA0_B, FN_TX5_E, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) /* IP0_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) FN_SD0_DAT2, 0, 0, FN_SSI_WS0129_B, FN_RX5_E, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) /* IP0_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) FN_SD0_DAT1, 0, 0, FN_SSI_SCK0129_B, FN_TX4_E, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) /* IP0_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) FN_SD0_DAT0, 0, 0, FN_SSI_SDATA1_C, FN_RX4_E, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) /* IP0_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) FN_SD0_CMD, 0, 0, FN_SSI_WS1_C, FN_TX3_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) /* IP0_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) FN_SD0_CLK, 0, 0, FN_SSI_SCK1_C, FN_RX3_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060044, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) /* IP1_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) FN_D5, FN_HRX2, FN_SCL1_B, FN_PWM2_C, FN_TCLK2_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) /* IP1_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) FN_D4, 0, FN_IRQ3, FN_TCLK1_A, FN_PWM6_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) /* IP1_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) FN_D3, 0, FN_TX4_B, FN_SDA0_D, FN_PWM0_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) FN_MSIOF2_SYNC_C, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) /* IP1_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) FN_D2, 0, FN_RX4_B, FN_SCL0_D, FN_PWM1_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) FN_MSIOF2_SCK_C, FN_SSI_SCK5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) /* IP1_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) FN_D1, 0, FN_SDA3_B, FN_TX5_B, 0, FN_MSIOF2_TXD_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) FN_SSI_WS5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) /* IP1_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) FN_D0, 0, FN_SCL3_B, FN_RX5_B, FN_IRQ4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) FN_MSIOF2_RXD_C, FN_SSI_SDATA5_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) /* IP1_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) FN_MMC0_D5, FN_SD1_WP, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) /* IP1_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) FN_MMC0_D4, FN_SD1_CD, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060048, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) /* IP2_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) FN_D13, FN_MSIOF2_SYNC_A, 0, FN_RX4_C, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) /* IP2_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) FN_D12, FN_MSIOF2_SCK_A, FN_HSCK0, 0, FN_CAN_CLK_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) /* IP2_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) FN_D11, FN_MSIOF2_TXD_A, FN_HTX0_B, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) /* IP2_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) FN_D10, FN_MSIOF2_RXD_A, FN_HRX0_B, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) /* IP2_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) FN_D9, FN_HRTS2_N, FN_TX1_C, FN_SDA1_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) /* IP2_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) FN_D8, FN_HCTS2_N, FN_RX1_C, FN_SCL1_D, FN_PWM3_C, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) /* IP2_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) FN_D7, FN_HSCK2, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) /* IP2_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) FN_D6, FN_HTX2, FN_SDA1_B, FN_PWM4_C, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) { PINMUX_CFG_REG_VAR("IPSR3", 0xE606004C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) /* IP3_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) FN_QSPI0_SSL, FN_WE1_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) /* IP3_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) FN_QSPI0_IO3, FN_RD_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) /* IP3_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) FN_QSPI0_IO2, FN_CS0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) /* IP3_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) FN_QSPI0_MISO_QSPI0_IO1, FN_RD_WR_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) /* IP3_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) FN_QSPI0_MOSI_QSPI0_IO0, FN_BS_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) /* IP3_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) FN_QSPI0_SPCLK, FN_WE0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) /* IP3_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) FN_D15, FN_MSIOF2_SS2, FN_PWM4_A, 0, FN_CAN1_TX_B, FN_IRQ2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) FN_AVB_AVTP_MATCH_A, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /* IP3_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) FN_D14, FN_MSIOF2_SS1, 0, FN_TX4_C, FN_CAN1_RX_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) 0, FN_AVB_AVTP_CAPTURE_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060050, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) /* IP4_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) FN_DU0_DR6, 0, FN_RX2_C, 0, 0, 0, FN_A6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) /* IP4_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) FN_DU0_DR5, 0, FN_TX1_D, 0, FN_PWM1_B, 0, FN_A5, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) /* IP4_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) FN_DU0_DR4, 0, FN_RX1_D, 0, 0, 0, FN_A4, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) /* IP4_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) FN_DU0_DR3, 0, FN_TX0_D, FN_SDA0_E, FN_PWM0_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) FN_A3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) /* IP4_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) FN_DU0_DR2, 0, FN_RX0_D, FN_SCL0_E, 0, 0, FN_A2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) /* IP4_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) FN_DU0_DR1, 0, FN_TX5_C, FN_SDA2_D, 0, 0, FN_A1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* IP4_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) FN_DU0_DR0, 0, FN_RX5_C, FN_SCL2_D, 0, 0, FN_A0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) /* IP4_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK_A, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060054, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) /* IP5_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) FN_DU0_DG6, 0, FN_HRX1_C, 0, 0, 0, FN_A14, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) /* IP5_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) FN_DU0_DG5, 0, FN_HTX0_A, 0, FN_PWM5_B, 0, FN_A13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) /* IP5_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) FN_DU0_DG4, 0, FN_HRX0_A, 0, 0, 0, FN_A12, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) /* IP5_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) FN_DU0_DG3, 0, FN_TX4_D, 0, FN_PWM4_B, 0, FN_A11, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) /* IP5_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) FN_DU0_DG2, 0, FN_RX4_D, 0, 0, 0, FN_A10, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) /* IP5_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) FN_DU0_DG1, 0, FN_TX3_B, FN_SDA3_D, FN_PWM3_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) FN_A9, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) /* IP5_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) FN_DU0_DG0, 0, FN_RX3_B, FN_SCL3_D, 0, 0, FN_A8, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) /* IP5_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) FN_DU0_DR7, 0, FN_TX2_C, 0, FN_PWM2_B, 0, FN_A7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060058, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) /* IP6_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) FN_DU0_DB6, 0, 0, 0, 0, 0, FN_A22, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) /* IP6_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) FN_DU0_DB5, 0, FN_HRTS1_N_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) FN_A21, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) /* IP6_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) FN_DU0_DB4, 0, FN_HCTS1_N_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) FN_A20, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) /* IP6_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) FN_DU0_DB3, 0, FN_HRTS0_N, 0, 0, 0, FN_A19, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) /* IP6_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) FN_DU0_DB2, 0, FN_HCTS0_N, 0, 0, 0, FN_A18, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) /* IP6_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) FN_DU0_DB1, 0, 0, FN_SDA4_D, FN_CAN0_TX_C, 0, FN_A17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) /* IP6_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) FN_DU0_DB0, 0, 0, FN_SCL4_D, FN_CAN0_RX_C, 0, FN_A16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) /* IP6_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) FN_DU0_DG7, 0, FN_HTX1_C, 0, FN_PWM6_B, 0, FN_A15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) { PINMUX_CFG_REG_VAR("IPSR7", 0xE606005C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) /* IP7_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) FN_DU0_DISP, 0, 0, 0, FN_CAN1_RX_C, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) /* IP7_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, 0, FN_MSIOF2_SCK_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) 0, 0, 0, FN_DRACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) /* IP7_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_MSIOF2_SYNC_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) 0, 0, FN_DACK0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) /* IP7_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_MSIOF2_TXD_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) 0, 0, FN_DREQ0_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) /* IP7_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) FN_DU0_DOTCLKOUT1, 0, FN_MSIOF2_RXD_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) FN_CS1_N_A26, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) /* IP7_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) FN_DU0_DOTCLKOUT0, 0, 0, 0, 0, 0, FN_A25, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) /* IP7_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) FN_DU0_DOTCLKIN, 0, 0, 0, 0, 0, FN_A24, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) /* IP7_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) FN_DU0_DB7, 0, 0, 0, 0, 0, FN_A23, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060060, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) /* IP8_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) FN_VI1_DATA5, 0, 0, 0, FN_AVB_RXD4, FN_ETH_LINK, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) /* IP8_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) FN_VI1_DATA4, 0, 0, 0, FN_AVB_RXD3, FN_ETH_RX_ER, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) /* IP8_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) FN_VI1_DATA3, 0, 0, 0, FN_AVB_RXD2, FN_ETH_MDIO, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) /* IP8_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) FN_VI1_DATA2, 0, 0, 0, FN_AVB_RXD1, FN_ETH_RXD1, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) /* IP8_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) FN_VI1_DATA1, 0, 0, 0, FN_AVB_RXD0, FN_ETH_RXD0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) /* IP8_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) FN_VI1_DATA0, 0, 0, 0, FN_AVB_RX_DV, FN_ETH_CRS_DV, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) /* IP8_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) FN_VI1_CLK, 0, 0, 0, FN_AVB_RX_CLK, FN_ETH_REF_CLK, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) /* IP8_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) FN_DU0_CDE, 0, 0, 0, FN_CAN1_TX_C, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060064, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) /* IP9_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) FN_VI1_DATA9, 0, 0, FN_SDA2_B, FN_AVB_TXD0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) /* IP9_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) FN_VI1_DATA8, 0, 0, FN_SCL2_B, FN_AVB_TX_EN, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) /* IP9_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) FN_VI1_VSYNC_N, FN_TX0_B, FN_SDA0_C, FN_AUDIO_CLKOUT_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) FN_AVB_TX_CLK, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) /* IP9_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) FN_VI1_HSYNC_N, FN_RX0_B, FN_SCL0_C, 0, FN_AVB_GTXREFCLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) FN_ETH_MDC, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) /* IP9_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) FN_VI1_FIELD, FN_SDA3_A, 0, 0, FN_AVB_RX_ER, FN_ETH_TXD0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) /* IP9_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) FN_VI1_CLKENB, FN_SCL3_A, 0, 0, FN_AVB_RXD7, FN_ETH_MAGIC, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) /* IP9_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) FN_VI1_DATA7, 0, 0, 0, FN_AVB_RXD6, FN_ETH_TX_EN, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) /* IP9_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) FN_VI1_DATA6, 0, 0, 0, FN_AVB_RXD5, FN_ETH_TXD1, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060068, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) /* IP10_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) FN_SCL1_A, FN_RX4_A, FN_PWM5_D, FN_DU1_DR0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) FN_SSI_SCK6_B, FN_VI0_G0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) /* IP10_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) FN_SDA0_A, FN_TX0_C, FN_IRQ5, FN_CAN_CLK_A, FN_AVB_GTX_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) FN_CAN1_TX_D, FN_DVC_MUTE, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) /* IP10_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) FN_SCL0_A, FN_RX0_C, FN_PWM5_A, FN_TCLK1_B, FN_AVB_TXD6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) FN_CAN1_RX_D, FN_MSIOF0_SYNC_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) /* IP10_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) FN_AVB_TXD5, FN_SCIF_CLK_B, FN_AUDIO_CLKC_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) FN_SSI_SDATA1_D, 0, FN_MSIOF0_SCK_B, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) /* IP10_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) FN_AVB_TXD4, 0, FN_AUDIO_CLKB_B, 0, FN_SSI_WS1_D, FN_TX5_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) FN_MSIOF0_TXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) /* IP10_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) FN_AVB_TXD3, 0, FN_AUDIO_CLKA_B, 0, FN_SSI_SCK1_D, FN_RX5_F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) FN_MSIOF0_RXD_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /* IP10_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) FN_VI1_DATA11, 0, 0, FN_CAN0_TX_B, FN_AVB_TXD2, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) /* IP10_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) FN_VI1_DATA10, 0, 0, FN_CAN0_RX_B, FN_AVB_TXD1, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) { PINMUX_CFG_REG_VAR("IPSR11", 0xE606006C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) /* IP11_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) FN_HRX1_A, FN_SCL4_A, FN_PWM6_A, FN_DU1_DG0, FN_RX0_A, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) /* IP11_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) FN_MSIOF0_SS2_A, 0, 0, FN_DU1_DR7, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) FN_QSPI1_SSL, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) /* IP11_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) FN_MSIOF0_SS1_A, 0, 0, FN_DU1_DR6, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) FN_QSPI1_IO3, FN_SSI_SDATA8_B, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) /* IP11_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) FN_MSIOF0_SYNC_A, FN_PWM1_A, 0, FN_DU1_DR5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) 0, FN_QSPI1_IO2, FN_SSI_SDATA7_B, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) /* IP11_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) FN_MSIOF0_SCK_A, FN_IRQ0, 0, FN_DU1_DR4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) 0, FN_QSPI1_SPCLK, FN_SSI_SCK78_B, FN_VI0_G4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) /* IP11_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) FN_MSIOF0_TXD_A, FN_TX5_A, FN_SDA2_C, FN_DU1_DR3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) FN_QSPI1_MISO_QSPI1_IO1, FN_SSI_WS78_B, FN_VI0_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) /* IP11_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) FN_MSIOF0_RXD_A, FN_RX5_A, FN_SCL2_C, FN_DU1_DR2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) FN_QSPI1_MOSI_QSPI1_IO0, FN_SSI_SDATA6_B, FN_VI0_G2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) /* IP11_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) FN_SDA1_A, FN_TX4_A, 0, FN_DU1_DR1, 0, 0, FN_SSI_WS6_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) FN_VI0_G1, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060070, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) /* IP12_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) FN_SD2_DAT2, FN_RX2_A, 0, FN_DU1_DB0, FN_SSI_SDATA2_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) /* IP12_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) FN_SD2_DAT1, FN_TX1_A, FN_SDA1_E, FN_DU1_DG7, FN_SSI_WS2_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) /* IP12_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) FN_SD2_DAT0, FN_RX1_A, FN_SCL1_E, FN_DU1_DG6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) FN_SSI_SDATA1_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) /* IP12_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) FN_SD2_CMD, FN_SCIF1_SCK_A, FN_TCLK2_A, FN_DU1_DG5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) FN_SSI_SCK2_B, FN_PWM3_A, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) /* IP12_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) FN_SD2_CLK, FN_HSCK1, 0, FN_DU1_DG4, FN_SSI_SCK1_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) /* IP12_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) FN_HRTS1_N_A, 0, 0, FN_DU1_DG3, FN_SSI_WS1_B, FN_IRQ1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) /* IP12_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) FN_HCTS1_N_A, FN_PWM2_A, 0, FN_DU1_DG2, FN_REMOCON_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) /* IP12_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) FN_HTX1_A, FN_SDA4_A, 0, FN_DU1_DG1, FN_TX0_A, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060074, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) /* IP13_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) FN_SSI_SCK5_A, 0, 0, FN_DU1_DOTCLKOUT1, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) /* IP13_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) FN_SDA2_A, 0, FN_MSIOF1_SYNC_B, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) /* IP13_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) FN_SCL2_A, 0, FN_MSIOF1_SCK_B, FN_DU1_DB6, FN_AUDIO_CLKC_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) FN_SSI_SCK4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) /* IP13_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) FN_TX3_A, FN_SDA1_C, FN_MSIOF1_TXD_B, FN_DU1_DB5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) FN_AUDIO_CLKB_C, FN_SSI_WS4_B, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) /* IP13_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) FN_RX3_A, FN_SCL1_C, FN_MSIOF1_RXD_B, FN_DU1_DB4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) FN_AUDIO_CLKA_C, FN_SSI_SDATA4_B, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) /* IP13_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) FN_SD2_WP, FN_SCIF3_SCK, 0, FN_DU1_DB3, FN_SSI_SDATA9_B, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) /* IP13_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) FN_SD2_CD, FN_SCIF2_SCK_A, 0, FN_DU1_DB2, FN_SSI_SCK9_B, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) /* IP13_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) FN_SD2_DAT3, FN_TX2_A, 0, FN_DU1_DB1, FN_SSI_WS9_B, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060078, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) /* IP14_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) FN_SSI_SDATA7_A, 0, 0, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) FN_VI0_G5, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) /* IP14_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) FN_SSI_WS78_A, 0, FN_SCL4_E, FN_DU1_CDE, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) /* IP14_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) FN_SSI_SCK78_A, 0, FN_SDA4_E, FN_DU1_DISP, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) /* IP14_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) FN_SSI_SDATA6_A, 0, FN_SDA4_C, FN_DU1_EXVSYNC_DU1_VSYNC, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /* IP14_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) FN_SSI_WS6_A, 0, FN_SCL4_C, FN_DU1_EXHSYNC_DU1_HSYNC, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) /* IP14_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) FN_SSI_SCK6_A, 0, 0, FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) /* IP14_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) FN_SSI_SDATA5_A, 0, FN_SDA3_C, FN_DU1_DOTCLKOUT0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) /* IP14_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) FN_SSI_WS5_A, 0, FN_SCL3_C, FN_DU1_DOTCLKIN, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) { PINMUX_CFG_REG_VAR("IPSR15", 0xE606007C, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) /* IP15_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) FN_SSI_WS4_A, 0, FN_AVB_PHY_INT, 0, 0, 0, FN_VI0_R5, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) /* IP15_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) FN_SSI_SCK4_A, 0, FN_AVB_MAGIC, 0, 0, 0, FN_VI0_R4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) /* IP15_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) FN_SSI_SDATA3, FN_MSIOF1_SS2_A, FN_AVB_LINK, 0, FN_CAN1_TX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) FN_DREQ2_N, FN_VI0_R3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) /* IP15_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) FN_SSI_WS34, FN_MSIOF1_SS1_A, FN_AVB_MDIO, 0, FN_CAN1_RX_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) FN_DREQ1_N, FN_VI0_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) /* IP15_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) FN_SSI_SCK34, FN_MSIOF1_SCK_A, FN_AVB_MDC, 0, 0, FN_DACK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) FN_VI0_R1, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) /* IP15_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) FN_SSI_SDATA0_A, FN_MSIOF1_SYNC_A, FN_PWM0_C, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) FN_VI0_R0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) /* IP15_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) FN_SSI_WS0129_A, FN_MSIOF1_TXD_A, FN_TX5_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) FN_VI0_G7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) /* IP15_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) FN_SSI_SCK0129_A, FN_MSIOF1_RXD_A, FN_RX5_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) FN_VI0_G6, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060080, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) /* IP16_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) FN_SSI_SDATA2_A, FN_HRTS1_N_B, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) FN_VI0_DATA4_VI0_B4, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) /* IP16_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) FN_SSI_WS2_A, FN_HCTS1_N_B, 0, 0, 0, FN_AVB_TX_ER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) FN_VI0_DATA3_VI0_B3, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) /* IP16_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) FN_SSI_SCK2_A, FN_HTX1_B, 0, 0, 0, FN_AVB_TXD7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) FN_VI0_DATA2_VI0_B2, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) /* IP16_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) FN_SSI_SDATA1_A, FN_HRX1_B, 0, 0, 0, 0, FN_VI0_DATA1_VI0_B1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) /* IP16_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) FN_SSI_WS1_A, FN_TX1_B, 0, 0, FN_CAN0_TX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) FN_AVB_AVTP_MATCH_B, FN_VI0_DATA0_VI0_B0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) /* IP16_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) FN_SSI_SDATA8_A, FN_RX1_B, 0, 0, FN_CAN0_RX_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) FN_AVB_AVTP_CAPTURE_B, FN_VI0_R7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) /* IP16_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) FN_SSI_SCK1_A, FN_SCIF1_SCK_B, FN_PWM1_D, FN_IRQ9, FN_REMOCON_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) FN_DACK2, FN_VI0_CLK, FN_AVB_COL, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) /* IP16_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) FN_SSI_SDATA4_A, 0, FN_AVB_CRS, 0, 0, 0, FN_VI0_R6, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) { PINMUX_CFG_REG_VAR("IPSR17", 0xE6060084, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) GROUP(4, 4, 4, 4, 4, 4, 4, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) /* IP17_31_28 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) /* IP17_27_24 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) FN_AUDIO_CLKOUT_A, FN_SDA4_B, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) FN_VI0_VSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) /* IP17_23_20 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) FN_AUDIO_CLKC_A, FN_SCL4_B, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) FN_VI0_HSYNC_N, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) /* IP17_19_16 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) FN_AUDIO_CLKB_A, FN_SDA0_B, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) FN_VI0_FIELD, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) /* IP17_15_12 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) FN_AUDIO_CLKA_A, FN_SCL0_B, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) FN_VI0_CLKENB, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) /* IP17_11_8 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) FN_SSI_SDATA9_A, FN_SCIF2_SCK_B, FN_PWM2_D, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) FN_VI0_DATA7_VI0_B7, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) /* IP17_7_4 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) FN_SSI_WS9_A, FN_TX2_B, FN_SDA3_E, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) FN_VI0_DATA6_VI0_B6, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) /* IP17_3_0 [4] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) FN_SSI_SCK9_A, FN_RX2_B, FN_SCL3_E, 0, 0, FN_EX_WAIT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) FN_VI0_DATA5_VI0_B5, 0, 0, 0, 0, 0, 0, 0, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xE60600C0, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) GROUP(1, 1, 1, 1, 1, 2, 1, 1, 2, 2, 2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) 3, 3, 1, 2, 3, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) /* SEL_ADGA [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) FN_SEL_ADGA_0, FN_SEL_ADGA_1, FN_SEL_ADGA_2, FN_SEL_ADGA_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) /* SEL_CANCLK [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) FN_SEL_CANCLK_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) /* SEL_CAN1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) /* SEL_CAN0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) /* SEL_I2C04 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) FN_SEL_I2C04_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) /* SEL_I2C03 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) FN_SEL_I2C03_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) /* SEL_I2C02 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) /* SEL_I2C01 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) FN_SEL_I2C01_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) /* SEL_I2C00 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) FN_SEL_I2C00_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) /* SEL_AVB [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) FN_SEL_AVB_0, FN_SEL_AVB_1, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xE60600C4, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) GROUP(1, 3, 3, 2, 2, 1, 2, 2, 2, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) 1, 1, 2, 1, 1, 2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) /* SEL_SCIFCLK [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) /* SEL_SCIF5 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) FN_SEL_SCIF5_4, FN_SEL_SCIF5_5, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) /* SEL_SCIF4 [3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) FN_SEL_SCIF4_4, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) /* SEL_SCIF3 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) /* SEL_SCIF2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) /* SEL_SCIF2_CLK [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) FN_SEL_SCIF2_CLK_0, FN_SEL_SCIF2_CLK_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) /* SEL_SCIF1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /* SEL_SCIF0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) /* SEL_MSIOF2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) FN_SEL_MSIOF2_0, FN_SEL_MSIOF2_1, FN_SEL_MSIOF2_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) /* SEL_MSIOF1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) FN_SEL_MSIOF1_0, FN_SEL_MSIOF1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) /* SEL_MSIOF0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) FN_SEL_MSIOF0_0, FN_SEL_MSIOF0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) /* SEL_RCN [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) FN_SEL_RCN_0, FN_SEL_RCN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) /* SEL_TMU2 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) FN_SEL_TMU2_0, FN_SEL_TMU2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) /* SEL_TMU1 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) FN_SEL_TMU1_0, FN_SEL_TMU1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) /* RESERVED [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) /* SEL_HSCIF1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) /* SEL_HSCIF0 [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE60600C8, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) 2, 2, 2, 2, 2, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) /* RESERVED [1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) /* SEL_ADGB [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) FN_SEL_ADGB_0, FN_SEL_ADGB_1, FN_SEL_ADGB_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) /* SEL_ADGC [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) FN_SEL_ADGC_0, FN_SEL_ADGC_1, FN_SEL_ADGC_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) /* SEL_SSI9 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) FN_SEL_SSI9_0, FN_SEL_SSI9_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) /* SEL_SSI8 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) FN_SEL_SSI8_0, FN_SEL_SSI8_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) /* SEL_SSI7 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) FN_SEL_SSI7_0, FN_SEL_SSI7_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) /* SEL_SSI6 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) FN_SEL_SSI6_0, FN_SEL_SSI6_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) /* SEL_SSI5 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) FN_SEL_SSI5_0, FN_SEL_SSI5_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) /* SEL_SSI4 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) FN_SEL_SSI4_0, FN_SEL_SSI4_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) /* SEL_SSI2 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) FN_SEL_SSI2_0, FN_SEL_SSI2_1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) /* SEL_SSI1 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI1_2, FN_SEL_SSI1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) /* SEL_SSI0 [2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) FN_SEL_SSI0_0, FN_SEL_SSI0_1, 0, 0, ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) static int r8a77470_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) u32 *pocctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) int bit = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) *pocctrl = 0xe60600b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) if (pin >= RCAR_GP_PIN(0, 5) && pin <= RCAR_GP_PIN(0, 10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) if (pin >= RCAR_GP_PIN(0, 13) && pin <= RCAR_GP_PIN(0, 22))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) bit = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) if (pin >= RCAR_GP_PIN(4, 14) && pin <= RCAR_GP_PIN(4, 19))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) return bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) static const struct sh_pfc_soc_operations r8a77470_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) .pin_to_pocctrl = r8a77470_pin_to_pocctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) #ifdef CONFIG_PINCTRL_PFC_R8A77470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) const struct sh_pfc_soc_info r8a77470_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) .name = "r8a77470_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) .ops = &r8a77470_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) .unlock_reg = 0xe6060000, /* PMMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags