^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * R8A7740 processor support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2011 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CPU_ALL_PORT(fn, pfx, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PORT_10(200, fn, pfx##20, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IRQC_PIN_MUX(irq, pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const unsigned int intc_irq##irq##_pins[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static const unsigned int intc_irq##irq##_mux[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) IRQ##irq##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IRQC_PINS_MUX(irq, idx, pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) IRQ##irq##_PORT##pin##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* PORT0_DATA -> PORT211_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PORT_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* PORT0_IN -> PORT211_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINMUX_INPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PORT_ALL(IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINMUX_INPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* PORT0_OUT -> PORT211_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINMUX_OUTPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PORT_ALL(OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINMUX_OUTPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MSEL1CR_31_0, MSEL1CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MSEL1CR_30_0, MSEL1CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MSEL1CR_29_0, MSEL1CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MSEL1CR_28_0, MSEL1CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MSEL1CR_27_0, MSEL1CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MSEL1CR_26_0, MSEL1CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MSEL1CR_16_0, MSEL1CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MSEL1CR_15_0, MSEL1CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MSEL1CR_14_0, MSEL1CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MSEL1CR_13_0, MSEL1CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MSEL1CR_12_0, MSEL1CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MSEL1CR_9_0, MSEL1CR_9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MSEL1CR_7_0, MSEL1CR_7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MSEL1CR_6_0, MSEL1CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MSEL1CR_5_0, MSEL1CR_5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MSEL1CR_4_0, MSEL1CR_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MSEL1CR_3_0, MSEL1CR_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MSEL1CR_2_0, MSEL1CR_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MSEL1CR_0_0, MSEL1CR_0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MSEL3CR_6_0, MSEL3CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MSEL4CR_19_0, MSEL4CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MSEL4CR_18_0, MSEL4CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MSEL4CR_15_0, MSEL4CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MSEL4CR_10_0, MSEL4CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MSEL4CR_6_0, MSEL4CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MSEL4CR_4_0, MSEL4CR_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MSEL4CR_1_0, MSEL4CR_1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MSEL5CR_30_0, MSEL5CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSEL5CR_29_0, MSEL5CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) MSEL5CR_27_0, MSEL5CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) MSEL5CR_25_0, MSEL5CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MSEL5CR_23_0, MSEL5CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MSEL5CR_21_0, MSEL5CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) MSEL5CR_19_0, MSEL5CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) MSEL5CR_17_0, MSEL5CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) MSEL5CR_15_0, MSEL5CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) MSEL5CR_14_0, MSEL5CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MSEL5CR_13_0, MSEL5CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MSEL5CR_12_0, MSEL5CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MSEL5CR_11_0, MSEL5CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) MSEL5CR_10_0, MSEL5CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MSEL5CR_8_0, MSEL5CR_8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) MSEL5CR_7_0, MSEL5CR_7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) MSEL5CR_6_0, MSEL5CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MSEL5CR_5_0, MSEL5CR_5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MSEL5CR_4_0, MSEL5CR_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MSEL5CR_3_0, MSEL5CR_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MSEL5CR_2_0, MSEL5CR_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MSEL5CR_0_0, MSEL5CR_0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) IRQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) IRQ8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) IRQ10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) IRQ11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) IRQ17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) IRQ18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) IRQ19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) IRQ20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) IRQ21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) IRQ22_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) IRQ23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) IRQ24_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) IRQ25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* DBGT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DBGMD21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* FSI-A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) FSIAISLD_PORT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) FSIASPDIF_PORT18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* FSI-B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) FSIBCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* FMSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) FMSISLD_PORT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* SCIFA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* SCIFA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* SCIFA2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) SCIFA2_SCK_PORT199_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* SCIFA3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) SCIFA3_SCK_PORT116_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SCIFA3_CTS_PORT117_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) SCIFA3_RXD_PORT174_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) SCIFA3_TXD_PORT175_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) SCIFA3_SCK_PORT158_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) SCIFA3_CTS_PORT162_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) SCIFA3_RXD_PORT159_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) SCIFA3_TXD_PORT160_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* SCIFA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) SCIFA4_TXD_PORT13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) SCIFA4_TXD_PORT203_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) SCIFA4_TXD_PORT93_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) SCIFA4_SCK_PORT205_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* SCIFA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) SCIFA5_RXD_PORT10_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) SCIFA5_TXD_PORT208_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) SCIFA5_RXD_PORT92_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) SCIFA5_SCK_PORT206_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* SCIFA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* SCIFA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* SCIFB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SCIFB_RXD_PORT191_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SCIFB_TXD_PORT192_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) SCIFB_RTS_PORT186_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) SCIFB_CTS_PORT187_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) SCIFB_RXD_PORT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) SCIFB_TXD_PORT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) SCIFB_RTS_PORT172_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) SCIFB_CTS_PORT173_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* LCD0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) LCD0_D16_MARK, LCD0_D17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) LCD0_LCLK_PORT165_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) LCD0_LCLK_PORT102_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* LCD1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) LCD1_DON_MARK, LCD1_VCPWC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* RSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) RSPI_MISO_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* VIO CKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) VIO_CKO1_MARK, /* needs fixup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) VIO_CKO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) VIO_CKO_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) VIO_CKO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* VIO0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) VIO0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) VIO0_D14_PORT25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) VIO0_D15_PORT24_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) VIO0_D14_PORT95_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) VIO0_D15_PORT96_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* VIO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* TPU0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) TPU0TO2_PORT202_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* SSP1 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* SSP1 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) STP1_IPSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) STP1_IPEN_PORT187_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) STP1_IPEN_PORT193_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* SIM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SIM_RST_MARK, SIM_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) SIM_D_PORT199_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* SDHI0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* SDHI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* SDHI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) SDHI2_CLK_MARK, SDHI2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SDHI2_WP_PORT25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) SDHI2_CD_PORT202_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* MSIOF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MSIOF2_RSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* KEYSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) KEYIN1_PORT44_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) KEYIN2_PORT45_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) KEYIN3_PORT46_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) KEYIN1_PORT57_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) KEYIN2_PORT56_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) KEYIN3_PORT55_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* VOU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* MEMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MEMC_CS1_MARK, /* MSEL4CR_6_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MEMC_ADV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MEMC_WAIT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) MEMC_BUSCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MEMC_A1_MARK, /* MSEL4CR_6_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MEMC_DREQ0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MEMC_DREQ1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MEMC_A0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* MMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* MSIOF0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MSIOF0_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* MSIOF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MSIOF1_TSYNC_PORT120_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MSIOF1_RXD_PORT75_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* USB0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* USB1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) USB1_OCI_MARK, USB1_PPON_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* BBIF1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* BBIF2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) BBIF2_RXD2_PORT60_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) BBIF2_TSYNC2_PORT6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) BBIF2_TSCK2_PORT59_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) BBIF2_TXD2_PORT183_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) BBIF2_TSCK2_PORT89_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) BBIF2_TSYNC2_PORT184_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* BSC / FLCTL / PCMCIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CS0_MARK, CS2_MARK, CS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CS5B_MARK, CS6A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) CS5A_PORT19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) IOIS16_MARK, /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) A0_MARK, A1_MARK, A2_MARK, A3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) A4_FOE_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) A5_FCDE_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) A6_MARK, A7_MARK, A8_MARK, A9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) A10_MARK, A11_MARK, A12_MARK, A13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) A14_MARK, A15_MARK, A16_MARK, A17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) A18_MARK, A19_MARK, A20_MARK, A21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) A22_MARK, A23_MARK, A24_MARK, A25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) A26_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) D15_NAF15_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) D16_MARK, D17_MARK, D18_MARK, D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) D20_MARK, D21_MARK, D22_MARK, D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) D24_MARK, D25_MARK, D26_MARK, D27_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) D28_MARK, D29_MARK, D30_MARK, D31_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) WE0_FWE_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) WE1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) WE2_ICIORD_MARK, /* share with PCMCIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) WE3_ICIOWR_MARK, /* share with PCMCIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) CKO_MARK, BS_MARK, RDWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) RD_FSC_MARK, /* share with FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) WAIT_PORT177_MARK, /* WAIT Port 90/177 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) WAIT_PORT90_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* IRDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* ATAPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* RMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) RMII_REF50CK_MARK, /* for RMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) RMII_REF125CK_MARK, /* for GMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* GEther */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ET_ETXD2_MARK, ET_ETXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* DMA0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) DREQ0_MARK, DACK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* DMA1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) DREQ1_MARK, DACK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* SYSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* IRREM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) IROUT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* SDENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) HDMI_HPD_MARK, HDMI_CEC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) EDEBGREQ_PULLUP_MARK, /* for JTAG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) EDEBGREQ_PULLDOWN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) TRACEAUD_FROM_LCDC0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) TRACEAUD_FROM_MEMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_DATA_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Port0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Port1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Port2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Port3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Port4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Port5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Port6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Port7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* Port8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* Port9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Port10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Port11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Port12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Port13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* Port14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Port15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Port16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Port17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Port18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Port19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Port20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Port21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Port22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Port23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* Port24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Port25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Port26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Port27 - Port39 Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Port38 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Port40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Port41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* Port42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /* Port43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Port44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Port45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* Port46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Port47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Port48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Port49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* Port50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Port51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Port52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Port53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Port54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Port55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Port56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* Port57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Port58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Port59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* Port60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /* Port61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Port62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /* Port63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Port64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* Port65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* Port66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Port67 - Port73 Function1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Port67 - Port73 Function2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Port67 - Port73 Function4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Port67 - Port73 Function6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Port67 - Port71 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Port74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Port75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Port76 - Port80 Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Port81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Port82 - Port88 Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* Port89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* Port90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_DATA(DACK0_MARK, PORT90_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Port91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* Port92 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Port93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* Port94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Port95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) /* Port96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /* Port97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) /* Port98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* Port99 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) /* Port100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Port101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_DATA(FCE0_MARK, PORT101_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Port102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_DATA(FRB_MARK, PORT102_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Port103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_DATA(CS5B_MARK, PORT103_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_DATA(FCE1_MARK, PORT103_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) /* Port104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_DATA(CS6A_MARK, PORT104_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Port105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Port106 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) /* Port107 - Port115 Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_DATA(CS0_MARK, PORT109_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_DATA(CS2_MARK, PORT110_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) PINMUX_DATA(CS4_MARK, PORT111_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) PINMUX_DATA(WE1_MARK, PORT112_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_DATA(RDWR_MARK, PORT114_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* Port116 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) PINMUX_DATA(A25_MARK, PORT116_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) PINMUX_DATA(GPO1_MARK, PORT116_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) /* Port117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PINMUX_DATA(A24_MARK, PORT117_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_DATA(GPO0_MARK, PORT117_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* Port118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) PINMUX_DATA(A23_MARK, PORT118_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_DATA(GPI1_MARK, PORT118_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Port119 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_DATA(A22_MARK, PORT119_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_DATA(GPI0_MARK, PORT119_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Port120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_DATA(A21_MARK, PORT120_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Port121 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_DATA(A20_MARK, PORT121_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /* Port122 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_DATA(A19_MARK, PORT122_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Port123 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_DATA(A18_MARK, PORT123_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Port124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_DATA(A17_MARK, PORT124_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* Port125 - Port141 Function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_DATA(A16_MARK, PORT125_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_DATA(A15_MARK, PORT126_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINMUX_DATA(A14_MARK, PORT127_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINMUX_DATA(A13_MARK, PORT128_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_DATA(A12_MARK, PORT129_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_DATA(A11_MARK, PORT130_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINMUX_DATA(A10_MARK, PORT131_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINMUX_DATA(A9_MARK, PORT132_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_DATA(A8_MARK, PORT133_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_DATA(A7_MARK, PORT134_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINMUX_DATA(A6_MARK, PORT135_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINMUX_DATA(A3_MARK, PORT138_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINMUX_DATA(A2_MARK, PORT139_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINMUX_DATA(A1_MARK, PORT140_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_DATA(CKO_MARK, PORT141_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* Port142 - Port157 Function1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Port142 - Port149 Function3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* Port158 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_DATA(D31_MARK, PORT158_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Port159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_DATA(D30_MARK, PORT159_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Port160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_DATA(D29_MARK, PORT160_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /* Port161 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINMUX_DATA(D28_MARK, PORT161_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* Port162 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_DATA(D27_MARK, PORT162_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* Port163 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_DATA(D26_MARK, PORT163_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINMUX_DATA(IROUT_MARK, PORT163_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Port164 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_DATA(D25_MARK, PORT164_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* Port165 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_DATA(D24_MARK, PORT165_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* Port166 - Port171 Function1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_DATA(D21_MARK, PORT166_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINMUX_DATA(D20_MARK, PORT167_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINMUX_DATA(D19_MARK, PORT168_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINMUX_DATA(D18_MARK, PORT169_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINMUX_DATA(D17_MARK, PORT170_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINMUX_DATA(D16_MARK, PORT171_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Port166 - Port171 Function3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* Port166 - Port171 Function6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* Port167 - Port171 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /* Port172 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) PINMUX_DATA(D23_MARK, PORT172_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* Port173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINMUX_DATA(D22_MARK, PORT173_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* Port174 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINMUX_DATA(A26_MARK, PORT174_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) /* Port175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINMUX_DATA(A0_MARK, PORT175_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINMUX_DATA(BS_MARK, PORT175_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) /* Port176 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Port177 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Port178 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Port179 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) /* Port180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* Port181 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* Port182 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* Port183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* Port184 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINMUX_DATA(DACK1_MARK, PORT184_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) /* Port185 - Port192 Function1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* Port185 - Port192 Function3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /* Port185 - Port192 Function6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* Port193 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* Port194 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) /* Port195 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Port196 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) /* Port197 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /* Port198 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* Port199 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) /* Port200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* Port201 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Port202 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) /* Port203 - Port208 Function1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* Port203 - Port208 Function3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) /* Port203 - Port208 Function6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* Port203 - Port208 Function7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) /* Port209 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PINMUX_DATA(VBUS_MARK, PORT209_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Port210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) /* Port211 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /* SDENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) /* SYSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define __I (SH_PFC_PIN_CFG_INPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define __O (SH_PFC_PIN_CFG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define __PU (SH_PFC_PIN_CFG_PULL_UP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) /* Table 56-1 (I/O and Pull U/D) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) /* - BSC -------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static const unsigned int bsc_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) 157, 156, 155, 154, 153, 152, 151, 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static const unsigned int bsc_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static const unsigned int bsc_data16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) 157, 156, 155, 154, 153, 152, 151, 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) 149, 148, 147, 146, 145, 144, 143, 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static const unsigned int bsc_data16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static const unsigned int bsc_data32_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /* D[0:31] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) 157, 156, 155, 154, 153, 152, 151, 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) 149, 148, 147, 146, 145, 144, 143, 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) 171, 170, 169, 168, 167, 166, 173, 172,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) 165, 164, 163, 162, 161, 160, 159, 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static const unsigned int bsc_data32_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) D16_MARK, D17_MARK, D18_MARK, D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) D20_MARK, D21_MARK, D22_MARK, D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) D24_MARK, D25_MARK, D26_MARK, D27_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) D28_MARK, D29_MARK, D30_MARK, D31_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static const unsigned int bsc_cs0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) 109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static const unsigned int bsc_cs0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) CS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) static const unsigned int bsc_cs2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) 110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) static const unsigned int bsc_cs2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) CS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static const unsigned int bsc_cs4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static const unsigned int bsc_cs4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) CS4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) static const unsigned int bsc_cs5a_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) 105,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) static const unsigned int bsc_cs5a_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) CS5A_PORT105_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static const unsigned int bsc_cs5a_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) static const unsigned int bsc_cs5a_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) CS5A_PORT19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static const unsigned int bsc_cs5b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) static const unsigned int bsc_cs5b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) CS5B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static const unsigned int bsc_cs6a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) /* CS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) 104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) static const unsigned int bsc_cs6a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) CS6A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) static const unsigned int bsc_rd_we8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /* RD, WE[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) 115, 113,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) static const unsigned int bsc_rd_we8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) RD_FSC_MARK, WE0_FWE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) static const unsigned int bsc_rd_we16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) /* RD, WE[0:1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) 115, 113, 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static const unsigned int bsc_rd_we16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) static const unsigned int bsc_rd_we32_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* RD, WE[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) 115, 113, 112, 108, 107,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static const unsigned int bsc_rd_we32_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static const unsigned int bsc_bs_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) /* BS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) 175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) static const unsigned int bsc_bs_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) BS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const unsigned int bsc_rdwr_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) /* RDWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) static const unsigned int bsc_rdwr_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) RDWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) /* - CEU0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) static const unsigned int ceu0_data_0_7_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) 34, 33, 32, 31, 30, 29, 28, 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) static const unsigned int ceu0_data_0_7_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static const unsigned int ceu0_data_8_15_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) /* D[8:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) 182, 181, 180, 179, 178, 26, 25, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static const unsigned int ceu0_data_8_15_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) VIO0_D15_PORT24_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static const unsigned int ceu0_data_8_15_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* D[8:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) 182, 181, 180, 179, 178, 22, 95, 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const unsigned int ceu0_data_8_15_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) VIO0_D15_PORT96_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) static const unsigned int ceu0_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* CKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static const unsigned int ceu0_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) VIO_CKO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static const unsigned int ceu0_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* CKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const unsigned int ceu0_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) VIO_CKO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const unsigned int ceu0_clk_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) /* CKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static const unsigned int ceu0_clk_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) VIO_CKO2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static const unsigned int ceu0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) /* CLK, VD, HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) 35, 39, 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static const unsigned int ceu0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) static const unsigned int ceu0_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) /* FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) 38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) static const unsigned int ceu0_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) VIO0_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) /* - CEU1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) static const unsigned int ceu1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) 182, 181, 180, 179, 178, 26, 25, 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const unsigned int ceu1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static const unsigned int ceu1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* CKO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static const unsigned int ceu1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) VIO_CKO_1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const unsigned int ceu1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /* CLK, VD, HD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) 197, 198, 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) static const unsigned int ceu1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static const unsigned int ceu1_field_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* FIELD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) static const unsigned int ceu1_field_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) VIO1_FIELD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* - FSIA ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static const unsigned int fsia_mclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static const unsigned int fsia_mclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) FSIACK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static const unsigned int fsia_mclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* OMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) static const unsigned int fsia_mclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) FSIAOMC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static const unsigned int fsia_sclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) /* ILR, IBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) 12, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static const unsigned int fsia_sclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) FSIAILR_MARK, FSIAIBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const unsigned int fsia_sclk_out_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* OLR, OBT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) 7, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) static const unsigned int fsia_sclk_out_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) FSIAOLR_MARK, FSIAOBT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) static const unsigned int fsia_data_in_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) /* ISLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static const unsigned int fsia_data_in_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) FSIAISLD_PORT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static const unsigned int fsia_data_in_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /* ISLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static const unsigned int fsia_data_in_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) FSIAISLD_PORT5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static const unsigned int fsia_data_out_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) /* OSLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) static const unsigned int fsia_data_out_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) FSIAOSLD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static const unsigned int fsia_data_out_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* OSLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static const unsigned int fsia_data_out_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) FSIAOSLD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) static const unsigned int fsia_data_out_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) /* OSLD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) static const unsigned int fsia_data_out_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) FSIAOSLD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) static const unsigned int fsia_spdif_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) static const unsigned int fsia_spdif_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) FSIASPDIF_PORT9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) static const unsigned int fsia_spdif_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) /* SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) static const unsigned int fsia_spdif_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) FSIASPDIF_PORT18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) /* - FSIB ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) static const unsigned int fsib_mclk_in_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) /* CK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static const unsigned int fsib_mclk_in_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) FSIBCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) /* - GETHER ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) static const unsigned int gether_rmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) static const unsigned int gether_rmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) RMII_MDC_MARK, RMII_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) static const unsigned int gether_mii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* RXD[0:3], RX_CLK, RX_DV, RX_ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * TXD[0:3], TX_CLK, TX_EN, TX_ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * CRS, COL, MDC, MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) 185, 186, 187, 188, 174, 161, 204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) 171, 170, 169, 168, 184, 183, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) 205, 163, 206, 207,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) static const unsigned int gether_mii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) static const unsigned int gether_gmii_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) /* RXD[0:7], RX_CLK, RX_DV, RX_ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * CRS, COL, MDC, MDIO, REF125CK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) 205, 163, 206, 207, 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) static const unsigned int gether_gmii_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) RMII_REF125CK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static const unsigned int gether_int_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /* PHY_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) 164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) static const unsigned int gether_int_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ET_PHY_INT_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static const unsigned int gether_link_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) /* LINK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) 177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static const unsigned int gether_link_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ET_LINK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) static const unsigned int gether_wol_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* WOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) 175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static const unsigned int gether_wol_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ET_WOL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* - HDMI ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) static const unsigned int hdmi_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) /* HPD, CEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) 210, 211,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static const unsigned int hdmi_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) HDMI_HPD_MARK, HDMI_CEC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* - INTC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) IRQC_PINS_MUX(0, 0, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) IRQC_PINS_MUX(0, 1, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) IRQC_PIN_MUX(1, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) IRQC_PINS_MUX(2, 0, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) IRQC_PINS_MUX(2, 1, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) IRQC_PINS_MUX(3, 0, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) IRQC_PINS_MUX(3, 1, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) IRQC_PINS_MUX(4, 0, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) IRQC_PINS_MUX(4, 1, 172);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) IRQC_PINS_MUX(5, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) IRQC_PINS_MUX(5, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) IRQC_PINS_MUX(6, 0, 121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) IRQC_PINS_MUX(6, 1, 173);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) IRQC_PINS_MUX(7, 0, 120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) IRQC_PINS_MUX(7, 1, 209);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) IRQC_PIN_MUX(8, 119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) IRQC_PINS_MUX(9, 0, 118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) IRQC_PINS_MUX(9, 1, 210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) IRQC_PIN_MUX(10, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) IRQC_PIN_MUX(11, 104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) IRQC_PINS_MUX(12, 0, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) IRQC_PINS_MUX(12, 1, 97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) IRQC_PINS_MUX(13, 0, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) IRQC_PINS_MUX(13, 1, 98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) IRQC_PINS_MUX(14, 0, 63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) IRQC_PINS_MUX(14, 1, 99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) IRQC_PINS_MUX(15, 0, 62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) IRQC_PINS_MUX(15, 1, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) IRQC_PINS_MUX(16, 0, 68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) IRQC_PINS_MUX(16, 1, 211);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) IRQC_PIN_MUX(17, 69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) IRQC_PIN_MUX(18, 70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) IRQC_PIN_MUX(19, 71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) IRQC_PIN_MUX(20, 67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) IRQC_PIN_MUX(21, 202);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) IRQC_PIN_MUX(22, 95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) IRQC_PIN_MUX(23, 96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) IRQC_PIN_MUX(24, 180);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) IRQC_PIN_MUX(25, 38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) IRQC_PINS_MUX(26, 0, 58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) IRQC_PINS_MUX(26, 1, 81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) IRQC_PINS_MUX(27, 0, 57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) IRQC_PINS_MUX(27, 1, 168);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) IRQC_PINS_MUX(28, 0, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) IRQC_PINS_MUX(28, 1, 169);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) IRQC_PINS_MUX(29, 0, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) IRQC_PINS_MUX(29, 1, 170);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) IRQC_PINS_MUX(30, 0, 49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) IRQC_PINS_MUX(30, 1, 171);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) IRQC_PINS_MUX(31, 0, 41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) IRQC_PINS_MUX(31, 1, 167);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* - LCD0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static const unsigned int lcd0_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) static const unsigned int lcd0_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) static const unsigned int lcd0_data9_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /* D[0:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) static const unsigned int lcd0_data9_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) LCD0_D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static const unsigned int lcd0_data12_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /* D[0:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) 50, 49, 48, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static const unsigned int lcd0_data12_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) static const unsigned int lcd0_data16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) /* D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) 50, 49, 48, 47, 46, 45, 44, 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) static const unsigned int lcd0_data16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) static const unsigned int lcd0_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) /* D[0:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) 50, 49, 48, 47, 46, 45, 44, 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) 42, 41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static const unsigned int lcd0_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) LCD0_D16_MARK, LCD0_D17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static const unsigned int lcd0_data24_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) /* D[0:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) 50, 49, 48, 47, 46, 45, 44, 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) 42, 41, 40, 4, 3, 2, 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) static const unsigned int lcd0_data24_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) LCD0_D23_PORT1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static const unsigned int lcd0_data24_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) /* D[0:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) 58, 57, 56, 55, 54, 53, 52, 51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) 50, 49, 48, 47, 46, 45, 44, 43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) 42, 41, 163, 162, 161, 158, 160, 159,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) static const unsigned int lcd0_data24_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) static const unsigned int lcd0_display_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) /* DON, VCPWC, VEPWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) 61, 59, 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static const unsigned int lcd0_display_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) static const unsigned int lcd0_lclk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) /* LCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static const unsigned int lcd0_lclk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) LCD0_LCLK_PORT102_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) static const unsigned int lcd0_lclk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* LCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) 165,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) static const unsigned int lcd0_lclk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) LCD0_LCLK_PORT165_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) static const unsigned int lcd0_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) /* VSYN, HSYN, DCK, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) 63, 64, 62, 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) static const unsigned int lcd0_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) static const unsigned int lcd0_sys_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) /* CS, WR, RD, RS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) 64, 62, 164, 65,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) static const unsigned int lcd0_sys_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) /* - LCD1 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static const unsigned int lcd1_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) 4, 3, 2, 1, 0, 91, 92, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) static const unsigned int lcd1_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static const unsigned int lcd1_data9_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) /* D[0:8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) 4, 3, 2, 1, 0, 91, 92, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static const unsigned int lcd1_data9_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) LCD1_D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static const unsigned int lcd1_data12_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) /* D[0:11] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) 4, 3, 2, 1, 0, 91, 92, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) 93, 94, 21, 201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static const unsigned int lcd1_data12_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static const unsigned int lcd1_data16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) /* D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) 4, 3, 2, 1, 0, 91, 92, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) 93, 94, 21, 201, 200, 199, 196, 195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) static const unsigned int lcd1_data16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static const unsigned int lcd1_data18_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) /* D[0:17] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) 4, 3, 2, 1, 0, 91, 92, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) 93, 94, 21, 201, 200, 199, 196, 195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) 194, 193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static const unsigned int lcd1_data18_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) LCD1_D16_MARK, LCD1_D17_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) static const unsigned int lcd1_data24_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) /* D[0:23] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) 4, 3, 2, 1, 0, 91, 92, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) 93, 94, 21, 201, 200, 199, 196, 195,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) 194, 193, 198, 197, 75, 74, 15, 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) static const unsigned int lcd1_data24_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static const unsigned int lcd1_display_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* DON, VCPWC, VEPWC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) 100, 5, 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) static const unsigned int lcd1_display_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) static const unsigned int lcd1_lclk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) /* LCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static const unsigned int lcd1_lclk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) LCD1_LCLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) static const unsigned int lcd1_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) /* VSYN, HSYN, DCK, DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) 98, 97, 99, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static const unsigned int lcd1_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) static const unsigned int lcd1_sys_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /* CS, WR, RD, RS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) 97, 99, 13, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) static const unsigned int lcd1_sys_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) /* - MMCIF ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) static const unsigned int mmc0_data1_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) static const unsigned int mmc0_data1_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) MMC0_D0_PORT68_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) static const unsigned int mmc0_data4_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) 68, 69, 70, 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static const unsigned int mmc0_data4_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static const unsigned int mmc0_data8_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) 68, 69, 70, 71, 72, 73, 74, 75,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) static const unsigned int mmc0_data8_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) static const unsigned int mmc0_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) 67, 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) static const unsigned int mmc0_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) static const unsigned int mmc0_data1_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) 149,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) static const unsigned int mmc0_data1_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) MMC1_D0_PORT149_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) static const unsigned int mmc0_data4_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) 149, 148, 147, 146,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static const unsigned int mmc0_data4_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static const unsigned int mmc0_data8_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) 149, 148, 147, 146, 145, 144, 143, 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static const unsigned int mmc0_data8_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static const unsigned int mmc0_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) 104, 103,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) static const unsigned int mmc0_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* - SCIFA0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) static const unsigned int scifa0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) 197, 198,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) static const unsigned int scifa0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) static const unsigned int scifa0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) 188,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) static const unsigned int scifa0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) SCIFA0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) static const unsigned int scifa0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) 194, 193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) static const unsigned int scifa0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) /* - SCIFA1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) static const unsigned int scifa1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) 195, 196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) static const unsigned int scifa1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static const unsigned int scifa1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) 185,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) static const unsigned int scifa1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) SCIFA1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static const unsigned int scifa1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) 23, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) static const unsigned int scifa1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* - SCIFA2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static const unsigned int scifa2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) 200, 201,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) static const unsigned int scifa2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) static const unsigned int scifa2_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) static const unsigned int scifa2_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) SCIFA2_SCK_PORT22_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) static const unsigned int scifa2_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) static const unsigned int scifa2_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) SCIFA2_SCK_PORT199_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static const unsigned int scifa2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) 96, 95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static const unsigned int scifa2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) /* - SCIFA3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) static const unsigned int scifa3_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) 174, 175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static const unsigned int scifa3_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static const unsigned int scifa3_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) static const unsigned int scifa3_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) SCIFA3_SCK_PORT116_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static const unsigned int scifa3_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) 105, 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static const unsigned int scifa3_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) static const unsigned int scifa3_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) 159, 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) static const unsigned int scifa3_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) static const unsigned int scifa3_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) static const unsigned int scifa3_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) SCIFA3_SCK_PORT158_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static const unsigned int scifa3_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) 161, 162,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) static const unsigned int scifa3_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* - SCIFA4 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static const unsigned int scifa4_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) 12, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) static const unsigned int scifa4_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static const unsigned int scifa4_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) 204, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) static const unsigned int scifa4_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) static const unsigned int scifa4_data_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) 94, 93,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) static const unsigned int scifa4_data_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) static const unsigned int scifa4_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) static const unsigned int scifa4_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) SCIFA4_SCK_PORT21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const unsigned int scifa4_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) 205,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static const unsigned int scifa4_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) SCIFA4_SCK_PORT205_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) /* - SCIFA5 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) static const unsigned int scifa5_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) 10, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static const unsigned int scifa5_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) static const unsigned int scifa5_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) 207, 208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) static const unsigned int scifa5_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) static const unsigned int scifa5_data_2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) 92, 91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) static const unsigned int scifa5_data_2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static const unsigned int scifa5_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) static const unsigned int scifa5_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) SCIFA5_SCK_PORT23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) static const unsigned int scifa5_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) 206,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) static const unsigned int scifa5_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) SCIFA5_SCK_PORT206_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* - SCIFA6 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) static const unsigned int scifa6_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) 25, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) static const unsigned int scifa6_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) static const unsigned int scifa6_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static const unsigned int scifa6_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) SCIFA6_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /* - SCIFA7 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) static const unsigned int scifa7_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) 0, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) static const unsigned int scifa7_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* - SCIFB ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) static const unsigned int scifb_data_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) 191, 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) static const unsigned int scifb_data_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) static const unsigned int scifb_clk_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) 190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static const unsigned int scifb_clk_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) SCIFB_SCK_PORT190_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) static const unsigned int scifb_ctrl_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) 186, 187,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) static const unsigned int scifb_ctrl_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static const unsigned int scifb_data_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) /* RXD, TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) 3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) static const unsigned int scifb_data_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) static const unsigned int scifb_clk_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) /* SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) static const unsigned int scifb_clk_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) SCIFB_SCK_PORT2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) static const unsigned int scifb_ctrl_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) /* RTS, CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) 172, 173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) static const unsigned int scifb_ctrl_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) 77,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) SDHI0_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) 76, 82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) SDHI0_CMD_MARK, SDHI0_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) 81,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) SDHI0_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) 83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) SDHI0_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) SDHI1_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) 68, 69, 70, 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) 67, 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) SDHI1_CMD_MARK, SDHI1_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) static const unsigned int sdhi1_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) 72,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) static const unsigned int sdhi1_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) SDHI1_CD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) static const unsigned int sdhi1_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) 73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) static const unsigned int sdhi1_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) SDHI1_WP_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) 205,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) SDHI2_D0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) 205, 206, 207, 208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) 204, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) SDHI2_CMD_MARK, SDHI2_CLK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) static const unsigned int sdhi2_cd_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) 202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static const unsigned int sdhi2_cd_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) SDHI2_CD_PORT202_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) static const unsigned int sdhi2_wp_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) 177,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) static const unsigned int sdhi2_wp_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) SDHI2_WP_PORT177_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static const unsigned int sdhi2_cd_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) static const unsigned int sdhi2_cd_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) SDHI2_CD_PORT24_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) static const unsigned int sdhi2_wp_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) static const unsigned int sdhi2_wp_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) SDHI2_WP_PORT25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) /* - TPU0 ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static const unsigned int tpu0_to0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) static const unsigned int tpu0_to0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) TPU0TO0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static const unsigned int tpu0_to1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) static const unsigned int tpu0_to1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) TPU0TO1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) static const unsigned int tpu0_to2_0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) static const unsigned int tpu0_to2_0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) TPU0TO2_PORT66_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) static const unsigned int tpu0_to2_1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) 202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) static const unsigned int tpu0_to2_1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) TPU0TO2_PORT202_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) static const unsigned int tpu0_to3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) /* TO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) 180,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) static const unsigned int tpu0_to3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) TPU0TO3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) SH_PFC_PIN_GROUP(bsc_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) SH_PFC_PIN_GROUP(bsc_data16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) SH_PFC_PIN_GROUP(bsc_data32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) SH_PFC_PIN_GROUP(bsc_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) SH_PFC_PIN_GROUP(bsc_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) SH_PFC_PIN_GROUP(bsc_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) SH_PFC_PIN_GROUP(bsc_cs5a_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) SH_PFC_PIN_GROUP(bsc_cs5a_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) SH_PFC_PIN_GROUP(bsc_cs5b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) SH_PFC_PIN_GROUP(bsc_cs6a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) SH_PFC_PIN_GROUP(bsc_rd_we8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) SH_PFC_PIN_GROUP(bsc_rd_we16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) SH_PFC_PIN_GROUP(bsc_rd_we32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) SH_PFC_PIN_GROUP(bsc_bs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) SH_PFC_PIN_GROUP(bsc_rdwr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) SH_PFC_PIN_GROUP(ceu0_data_0_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) SH_PFC_PIN_GROUP(ceu0_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) SH_PFC_PIN_GROUP(ceu0_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) SH_PFC_PIN_GROUP(ceu0_clk_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) SH_PFC_PIN_GROUP(ceu0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) SH_PFC_PIN_GROUP(ceu0_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) SH_PFC_PIN_GROUP(ceu1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) SH_PFC_PIN_GROUP(ceu1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) SH_PFC_PIN_GROUP(ceu1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) SH_PFC_PIN_GROUP(ceu1_field),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) SH_PFC_PIN_GROUP(fsia_mclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) SH_PFC_PIN_GROUP(fsia_mclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) SH_PFC_PIN_GROUP(fsia_sclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) SH_PFC_PIN_GROUP(fsia_sclk_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) SH_PFC_PIN_GROUP(fsia_data_in_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) SH_PFC_PIN_GROUP(fsia_data_in_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) SH_PFC_PIN_GROUP(fsia_data_out_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) SH_PFC_PIN_GROUP(fsia_data_out_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) SH_PFC_PIN_GROUP(fsia_data_out_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) SH_PFC_PIN_GROUP(fsia_spdif_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) SH_PFC_PIN_GROUP(fsia_spdif_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) SH_PFC_PIN_GROUP(fsib_mclk_in),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) SH_PFC_PIN_GROUP(gether_rmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) SH_PFC_PIN_GROUP(gether_mii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) SH_PFC_PIN_GROUP(gether_gmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) SH_PFC_PIN_GROUP(gether_int),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) SH_PFC_PIN_GROUP(gether_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) SH_PFC_PIN_GROUP(gether_wol),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) SH_PFC_PIN_GROUP(hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) SH_PFC_PIN_GROUP(intc_irq0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) SH_PFC_PIN_GROUP(intc_irq0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) SH_PFC_PIN_GROUP(intc_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) SH_PFC_PIN_GROUP(intc_irq2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) SH_PFC_PIN_GROUP(intc_irq2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) SH_PFC_PIN_GROUP(intc_irq3_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) SH_PFC_PIN_GROUP(intc_irq3_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) SH_PFC_PIN_GROUP(intc_irq4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) SH_PFC_PIN_GROUP(intc_irq4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) SH_PFC_PIN_GROUP(intc_irq5_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) SH_PFC_PIN_GROUP(intc_irq5_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) SH_PFC_PIN_GROUP(intc_irq6_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) SH_PFC_PIN_GROUP(intc_irq6_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) SH_PFC_PIN_GROUP(intc_irq7_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) SH_PFC_PIN_GROUP(intc_irq7_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) SH_PFC_PIN_GROUP(intc_irq8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) SH_PFC_PIN_GROUP(intc_irq9_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) SH_PFC_PIN_GROUP(intc_irq9_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) SH_PFC_PIN_GROUP(intc_irq10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) SH_PFC_PIN_GROUP(intc_irq11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) SH_PFC_PIN_GROUP(intc_irq12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) SH_PFC_PIN_GROUP(intc_irq12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) SH_PFC_PIN_GROUP(intc_irq13_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) SH_PFC_PIN_GROUP(intc_irq13_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) SH_PFC_PIN_GROUP(intc_irq14_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) SH_PFC_PIN_GROUP(intc_irq14_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) SH_PFC_PIN_GROUP(intc_irq15_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) SH_PFC_PIN_GROUP(intc_irq15_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) SH_PFC_PIN_GROUP(intc_irq16_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) SH_PFC_PIN_GROUP(intc_irq16_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) SH_PFC_PIN_GROUP(intc_irq17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) SH_PFC_PIN_GROUP(intc_irq18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) SH_PFC_PIN_GROUP(intc_irq19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) SH_PFC_PIN_GROUP(intc_irq20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) SH_PFC_PIN_GROUP(intc_irq21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) SH_PFC_PIN_GROUP(intc_irq22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) SH_PFC_PIN_GROUP(intc_irq23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) SH_PFC_PIN_GROUP(intc_irq24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) SH_PFC_PIN_GROUP(intc_irq25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) SH_PFC_PIN_GROUP(intc_irq26_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) SH_PFC_PIN_GROUP(intc_irq26_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) SH_PFC_PIN_GROUP(intc_irq27_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) SH_PFC_PIN_GROUP(intc_irq27_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) SH_PFC_PIN_GROUP(intc_irq28_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) SH_PFC_PIN_GROUP(intc_irq28_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) SH_PFC_PIN_GROUP(intc_irq29_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) SH_PFC_PIN_GROUP(intc_irq29_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) SH_PFC_PIN_GROUP(intc_irq30_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) SH_PFC_PIN_GROUP(intc_irq30_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) SH_PFC_PIN_GROUP(intc_irq31_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) SH_PFC_PIN_GROUP(intc_irq31_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) SH_PFC_PIN_GROUP(lcd0_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) SH_PFC_PIN_GROUP(lcd0_data9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) SH_PFC_PIN_GROUP(lcd0_data12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) SH_PFC_PIN_GROUP(lcd0_data16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) SH_PFC_PIN_GROUP(lcd0_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) SH_PFC_PIN_GROUP(lcd0_data24_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) SH_PFC_PIN_GROUP(lcd0_data24_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) SH_PFC_PIN_GROUP(lcd0_display),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) SH_PFC_PIN_GROUP(lcd0_lclk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) SH_PFC_PIN_GROUP(lcd0_lclk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) SH_PFC_PIN_GROUP(lcd0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) SH_PFC_PIN_GROUP(lcd0_sys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) SH_PFC_PIN_GROUP(lcd1_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) SH_PFC_PIN_GROUP(lcd1_data9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) SH_PFC_PIN_GROUP(lcd1_data12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) SH_PFC_PIN_GROUP(lcd1_data16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) SH_PFC_PIN_GROUP(lcd1_data18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) SH_PFC_PIN_GROUP(lcd1_data24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) SH_PFC_PIN_GROUP(lcd1_display),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) SH_PFC_PIN_GROUP(lcd1_lclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) SH_PFC_PIN_GROUP(lcd1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) SH_PFC_PIN_GROUP(lcd1_sys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) SH_PFC_PIN_GROUP(mmc0_data1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) SH_PFC_PIN_GROUP(mmc0_data4_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) SH_PFC_PIN_GROUP(mmc0_data8_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) SH_PFC_PIN_GROUP(mmc0_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) SH_PFC_PIN_GROUP(mmc0_data1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) SH_PFC_PIN_GROUP(mmc0_data4_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) SH_PFC_PIN_GROUP(mmc0_data8_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) SH_PFC_PIN_GROUP(mmc0_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) SH_PFC_PIN_GROUP(scifa0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) SH_PFC_PIN_GROUP(scifa0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) SH_PFC_PIN_GROUP(scifa0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) SH_PFC_PIN_GROUP(scifa1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) SH_PFC_PIN_GROUP(scifa1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) SH_PFC_PIN_GROUP(scifa1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) SH_PFC_PIN_GROUP(scifa2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) SH_PFC_PIN_GROUP(scifa2_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) SH_PFC_PIN_GROUP(scifa2_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) SH_PFC_PIN_GROUP(scifa2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) SH_PFC_PIN_GROUP(scifa3_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) SH_PFC_PIN_GROUP(scifa3_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) SH_PFC_PIN_GROUP(scifa3_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) SH_PFC_PIN_GROUP(scifa3_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) SH_PFC_PIN_GROUP(scifa3_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) SH_PFC_PIN_GROUP(scifa3_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) SH_PFC_PIN_GROUP(scifa4_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) SH_PFC_PIN_GROUP(scifa4_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) SH_PFC_PIN_GROUP(scifa4_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) SH_PFC_PIN_GROUP(scifa4_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) SH_PFC_PIN_GROUP(scifa4_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) SH_PFC_PIN_GROUP(scifa5_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) SH_PFC_PIN_GROUP(scifa5_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) SH_PFC_PIN_GROUP(scifa5_data_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) SH_PFC_PIN_GROUP(scifa5_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) SH_PFC_PIN_GROUP(scifa5_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) SH_PFC_PIN_GROUP(scifa6_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) SH_PFC_PIN_GROUP(scifa6_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) SH_PFC_PIN_GROUP(scifa7_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) SH_PFC_PIN_GROUP(scifb_data_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) SH_PFC_PIN_GROUP(scifb_clk_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) SH_PFC_PIN_GROUP(scifb_ctrl_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) SH_PFC_PIN_GROUP(scifb_data_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) SH_PFC_PIN_GROUP(scifb_clk_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) SH_PFC_PIN_GROUP(scifb_ctrl_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) SH_PFC_PIN_GROUP(sdhi1_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) SH_PFC_PIN_GROUP(sdhi1_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) SH_PFC_PIN_GROUP(sdhi2_cd_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) SH_PFC_PIN_GROUP(sdhi2_wp_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) SH_PFC_PIN_GROUP(sdhi2_cd_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) SH_PFC_PIN_GROUP(sdhi2_wp_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) SH_PFC_PIN_GROUP(tpu0_to0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) SH_PFC_PIN_GROUP(tpu0_to1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) SH_PFC_PIN_GROUP(tpu0_to2_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) SH_PFC_PIN_GROUP(tpu0_to2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) SH_PFC_PIN_GROUP(tpu0_to3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) static const char * const bsc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) "bsc_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) "bsc_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) "bsc_data32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) "bsc_cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) "bsc_cs2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) "bsc_cs4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) "bsc_cs5a_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) "bsc_cs5a_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) "bsc_cs5b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) "bsc_cs6a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) "bsc_rd_we8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) "bsc_rd_we16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) "bsc_rd_we32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) "bsc_bs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) "bsc_rdwr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) static const char * const ceu0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) "ceu0_data_0_7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) "ceu0_data_8_15_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) "ceu0_data_8_15_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) "ceu0_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) "ceu0_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) "ceu0_clk_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) "ceu0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) "ceu0_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) static const char * const ceu1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) "ceu1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) "ceu1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) "ceu1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) "ceu1_field",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) static const char * const fsia_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) "fsia_mclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) "fsia_mclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) "fsia_sclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) "fsia_sclk_out",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) "fsia_data_in_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) "fsia_data_in_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) "fsia_data_out_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) "fsia_data_out_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) "fsia_data_out_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) "fsia_spdif_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) "fsia_spdif_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) static const char * const fsib_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) "fsib_mclk_in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static const char * const gether_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) "gether_rmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) "gether_mii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) "gether_gmii",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) "gether_int",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) "gether_link",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) "gether_wol",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) static const char * const hdmi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) "hdmi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) static const char * const intc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) "intc_irq0_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) "intc_irq0_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) "intc_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) "intc_irq2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) "intc_irq2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) "intc_irq3_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) "intc_irq3_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) "intc_irq4_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) "intc_irq4_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) "intc_irq5_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) "intc_irq5_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) "intc_irq6_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) "intc_irq6_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) "intc_irq7_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) "intc_irq7_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) "intc_irq8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) "intc_irq9_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) "intc_irq9_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) "intc_irq10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) "intc_irq11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) "intc_irq12_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) "intc_irq12_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) "intc_irq13_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) "intc_irq13_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) "intc_irq14_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) "intc_irq14_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) "intc_irq15_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) "intc_irq15_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) "intc_irq16_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) "intc_irq16_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) "intc_irq17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) "intc_irq18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) "intc_irq19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) "intc_irq20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) "intc_irq21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) "intc_irq22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) "intc_irq23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) "intc_irq24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) "intc_irq25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) "intc_irq26_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) "intc_irq26_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) "intc_irq27_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) "intc_irq27_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) "intc_irq28_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) "intc_irq28_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) "intc_irq29_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) "intc_irq29_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) "intc_irq30_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) "intc_irq30_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) "intc_irq31_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) "intc_irq31_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) static const char * const lcd0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) "lcd0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) "lcd0_data9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) "lcd0_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) "lcd0_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) "lcd0_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) "lcd0_data24_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) "lcd0_data24_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) "lcd0_display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) "lcd0_lclk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) "lcd0_lclk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) "lcd0_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) "lcd0_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) static const char * const lcd1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) "lcd1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) "lcd1_data9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) "lcd1_data12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) "lcd1_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) "lcd1_data18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) "lcd1_data24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) "lcd1_display",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) "lcd1_lclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) "lcd1_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) "lcd1_sys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) static const char * const mmc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) "mmc0_data1_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) "mmc0_data4_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) "mmc0_data8_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) "mmc0_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) "mmc0_data1_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) "mmc0_data4_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) "mmc0_data8_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) "mmc0_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) static const char * const scifa0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) "scifa0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) "scifa0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) "scifa0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) static const char * const scifa1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) "scifa1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) "scifa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) "scifa1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) static const char * const scifa2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) "scifa2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) "scifa2_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) "scifa2_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) "scifa2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) static const char * const scifa3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) "scifa3_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) "scifa3_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) "scifa3_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) "scifa3_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) "scifa3_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) "scifa3_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) static const char * const scifa4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) "scifa4_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) "scifa4_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) "scifa4_data_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) "scifa4_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) "scifa4_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) static const char * const scifa5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) "scifa5_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) "scifa5_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) "scifa5_data_2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) "scifa5_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) "scifa5_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) static const char * const scifa6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) "scifa6_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) "scifa6_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) static const char * const scifa7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) "scifa7_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) static const char * const scifb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) "scifb_data_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) "scifb_clk_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) "scifb_ctrl_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) "scifb_data_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) "scifb_clk_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) "scifb_ctrl_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) "sdhi1_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) "sdhi1_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) "sdhi2_cd_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) "sdhi2_wp_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) "sdhi2_cd_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) "sdhi2_wp_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) static const char * const tpu0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) "tpu0_to0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) "tpu0_to1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) "tpu0_to2_0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) "tpu0_to2_1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) "tpu0_to3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) SH_PFC_FUNCTION(bsc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) SH_PFC_FUNCTION(ceu0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) SH_PFC_FUNCTION(ceu1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) SH_PFC_FUNCTION(fsia),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) SH_PFC_FUNCTION(fsib),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) SH_PFC_FUNCTION(gether),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) SH_PFC_FUNCTION(hdmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) SH_PFC_FUNCTION(intc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) SH_PFC_FUNCTION(lcd0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) SH_PFC_FUNCTION(lcd1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) SH_PFC_FUNCTION(mmc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) SH_PFC_FUNCTION(scifa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) SH_PFC_FUNCTION(scifa1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) SH_PFC_FUNCTION(scifa2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) SH_PFC_FUNCTION(scifa3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) SH_PFC_FUNCTION(scifa4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) SH_PFC_FUNCTION(scifa5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) SH_PFC_FUNCTION(scifa6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) SH_PFC_FUNCTION(scifa7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) SH_PFC_FUNCTION(scifb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) SH_PFC_FUNCTION(tpu0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) PORTCR(0, 0xe6050000), /* PORT0CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) PORTCR(1, 0xe6050001), /* PORT1CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) PORTCR(2, 0xe6050002), /* PORT2CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) PORTCR(3, 0xe6050003), /* PORT3CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) PORTCR(4, 0xe6050004), /* PORT4CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) PORTCR(5, 0xe6050005), /* PORT5CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) PORTCR(6, 0xe6050006), /* PORT6CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) PORTCR(7, 0xe6050007), /* PORT7CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) PORTCR(8, 0xe6050008), /* PORT8CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) PORTCR(9, 0xe6050009), /* PORT9CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) PORTCR(10, 0xe605000a), /* PORT10CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) PORTCR(11, 0xe605000b), /* PORT11CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) PORTCR(12, 0xe605000c), /* PORT12CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) PORTCR(13, 0xe605000d), /* PORT13CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) PORTCR(14, 0xe605000e), /* PORT14CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) PORTCR(15, 0xe605000f), /* PORT15CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) PORTCR(16, 0xe6050010), /* PORT16CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) PORTCR(17, 0xe6050011), /* PORT17CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) PORTCR(18, 0xe6050012), /* PORT18CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) PORTCR(19, 0xe6050013), /* PORT19CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) PORTCR(20, 0xe6050014), /* PORT20CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) PORTCR(21, 0xe6050015), /* PORT21CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) PORTCR(22, 0xe6050016), /* PORT22CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) PORTCR(23, 0xe6050017), /* PORT23CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) PORTCR(24, 0xe6050018), /* PORT24CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) PORTCR(25, 0xe6050019), /* PORT25CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) PORTCR(26, 0xe605001a), /* PORT26CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) PORTCR(27, 0xe605001b), /* PORT27CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) PORTCR(28, 0xe605001c), /* PORT28CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) PORTCR(29, 0xe605001d), /* PORT29CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) PORTCR(30, 0xe605001e), /* PORT30CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) PORTCR(31, 0xe605001f), /* PORT31CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) PORTCR(32, 0xe6050020), /* PORT32CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) PORTCR(33, 0xe6050021), /* PORT33CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) PORTCR(34, 0xe6050022), /* PORT34CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) PORTCR(35, 0xe6050023), /* PORT35CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) PORTCR(36, 0xe6050024), /* PORT36CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) PORTCR(37, 0xe6050025), /* PORT37CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) PORTCR(38, 0xe6050026), /* PORT38CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) PORTCR(39, 0xe6050027), /* PORT39CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) PORTCR(40, 0xe6050028), /* PORT40CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) PORTCR(41, 0xe6050029), /* PORT41CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) PORTCR(42, 0xe605002a), /* PORT42CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) PORTCR(43, 0xe605002b), /* PORT43CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) PORTCR(44, 0xe605002c), /* PORT44CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) PORTCR(45, 0xe605002d), /* PORT45CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) PORTCR(46, 0xe605002e), /* PORT46CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) PORTCR(47, 0xe605002f), /* PORT47CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) PORTCR(48, 0xe6050030), /* PORT48CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) PORTCR(49, 0xe6050031), /* PORT49CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) PORTCR(50, 0xe6050032), /* PORT50CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) PORTCR(51, 0xe6050033), /* PORT51CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) PORTCR(52, 0xe6050034), /* PORT52CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) PORTCR(53, 0xe6050035), /* PORT53CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) PORTCR(54, 0xe6050036), /* PORT54CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) PORTCR(55, 0xe6050037), /* PORT55CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) PORTCR(56, 0xe6050038), /* PORT56CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) PORTCR(57, 0xe6050039), /* PORT57CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) PORTCR(58, 0xe605003a), /* PORT58CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) PORTCR(59, 0xe605003b), /* PORT59CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) PORTCR(60, 0xe605003c), /* PORT60CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) PORTCR(61, 0xe605003d), /* PORT61CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) PORTCR(62, 0xe605003e), /* PORT62CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) PORTCR(63, 0xe605003f), /* PORT63CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) PORTCR(64, 0xe6050040), /* PORT64CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) PORTCR(65, 0xe6050041), /* PORT65CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) PORTCR(66, 0xe6050042), /* PORT66CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) PORTCR(67, 0xe6050043), /* PORT67CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) PORTCR(68, 0xe6050044), /* PORT68CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) PORTCR(69, 0xe6050045), /* PORT69CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) PORTCR(70, 0xe6050046), /* PORT70CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) PORTCR(71, 0xe6050047), /* PORT71CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) PORTCR(72, 0xe6050048), /* PORT72CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) PORTCR(73, 0xe6050049), /* PORT73CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) PORTCR(74, 0xe605004a), /* PORT74CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) PORTCR(75, 0xe605004b), /* PORT75CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) PORTCR(76, 0xe605004c), /* PORT76CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) PORTCR(77, 0xe605004d), /* PORT77CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) PORTCR(78, 0xe605004e), /* PORT78CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) PORTCR(79, 0xe605004f), /* PORT79CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) PORTCR(80, 0xe6050050), /* PORT80CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) PORTCR(81, 0xe6050051), /* PORT81CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) PORTCR(82, 0xe6050052), /* PORT82CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) PORTCR(83, 0xe6050053), /* PORT83CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) PORTCR(84, 0xe6051054), /* PORT84CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) PORTCR(85, 0xe6051055), /* PORT85CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) PORTCR(86, 0xe6051056), /* PORT86CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) PORTCR(87, 0xe6051057), /* PORT87CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) PORTCR(88, 0xe6051058), /* PORT88CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) PORTCR(89, 0xe6051059), /* PORT89CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) PORTCR(90, 0xe605105a), /* PORT90CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) PORTCR(91, 0xe605105b), /* PORT91CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) PORTCR(92, 0xe605105c), /* PORT92CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) PORTCR(93, 0xe605105d), /* PORT93CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) PORTCR(94, 0xe605105e), /* PORT94CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) PORTCR(95, 0xe605105f), /* PORT95CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) PORTCR(96, 0xe6051060), /* PORT96CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) PORTCR(97, 0xe6051061), /* PORT97CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) PORTCR(98, 0xe6051062), /* PORT98CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) PORTCR(99, 0xe6051063), /* PORT99CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) PORTCR(100, 0xe6051064), /* PORT100CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) PORTCR(101, 0xe6051065), /* PORT101CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) PORTCR(102, 0xe6051066), /* PORT102CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) PORTCR(103, 0xe6051067), /* PORT103CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) PORTCR(104, 0xe6051068), /* PORT104CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) PORTCR(105, 0xe6051069), /* PORT105CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) PORTCR(106, 0xe605106a), /* PORT106CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) PORTCR(107, 0xe605106b), /* PORT107CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) PORTCR(108, 0xe605106c), /* PORT108CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) PORTCR(109, 0xe605106d), /* PORT109CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) PORTCR(110, 0xe605106e), /* PORT110CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) PORTCR(111, 0xe605106f), /* PORT111CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) PORTCR(112, 0xe6051070), /* PORT112CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) PORTCR(113, 0xe6051071), /* PORT113CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) PORTCR(114, 0xe6051072), /* PORT114CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) PORTCR(115, 0xe6052073), /* PORT115CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) PORTCR(116, 0xe6052074), /* PORT116CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) PORTCR(117, 0xe6052075), /* PORT117CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) PORTCR(118, 0xe6052076), /* PORT118CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) PORTCR(119, 0xe6052077), /* PORT119CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) PORTCR(120, 0xe6052078), /* PORT120CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) PORTCR(121, 0xe6052079), /* PORT121CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) PORTCR(122, 0xe605207a), /* PORT122CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) PORTCR(123, 0xe605207b), /* PORT123CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) PORTCR(124, 0xe605207c), /* PORT124CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) PORTCR(125, 0xe605207d), /* PORT125CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) PORTCR(126, 0xe605207e), /* PORT126CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) PORTCR(127, 0xe605207f), /* PORT127CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) PORTCR(128, 0xe6052080), /* PORT128CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) PORTCR(129, 0xe6052081), /* PORT129CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) PORTCR(130, 0xe6052082), /* PORT130CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) PORTCR(131, 0xe6052083), /* PORT131CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) PORTCR(132, 0xe6052084), /* PORT132CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) PORTCR(133, 0xe6052085), /* PORT133CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) PORTCR(134, 0xe6052086), /* PORT134CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) PORTCR(135, 0xe6052087), /* PORT135CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) PORTCR(136, 0xe6052088), /* PORT136CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) PORTCR(137, 0xe6052089), /* PORT137CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) PORTCR(138, 0xe605208a), /* PORT138CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) PORTCR(139, 0xe605208b), /* PORT139CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) PORTCR(140, 0xe605208c), /* PORT140CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) PORTCR(141, 0xe605208d), /* PORT141CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) PORTCR(142, 0xe605208e), /* PORT142CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) PORTCR(143, 0xe605208f), /* PORT143CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) PORTCR(144, 0xe6052090), /* PORT144CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) PORTCR(145, 0xe6052091), /* PORT145CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) PORTCR(146, 0xe6052092), /* PORT146CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) PORTCR(147, 0xe6052093), /* PORT147CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) PORTCR(148, 0xe6052094), /* PORT148CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) PORTCR(149, 0xe6052095), /* PORT149CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) PORTCR(150, 0xe6052096), /* PORT150CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) PORTCR(151, 0xe6052097), /* PORT151CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) PORTCR(152, 0xe6052098), /* PORT152CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) PORTCR(153, 0xe6052099), /* PORT153CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) PORTCR(154, 0xe605209a), /* PORT154CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) PORTCR(155, 0xe605209b), /* PORT155CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) PORTCR(156, 0xe605209c), /* PORT156CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) PORTCR(157, 0xe605209d), /* PORT157CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) PORTCR(158, 0xe605209e), /* PORT158CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) PORTCR(159, 0xe605209f), /* PORT159CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) PORTCR(160, 0xe60520a0), /* PORT160CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) PORTCR(161, 0xe60520a1), /* PORT161CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) PORTCR(162, 0xe60520a2), /* PORT162CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) PORTCR(163, 0xe60520a3), /* PORT163CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) PORTCR(164, 0xe60520a4), /* PORT164CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) PORTCR(165, 0xe60520a5), /* PORT165CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) PORTCR(166, 0xe60520a6), /* PORT166CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) PORTCR(167, 0xe60520a7), /* PORT167CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) PORTCR(168, 0xe60520a8), /* PORT168CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) PORTCR(169, 0xe60520a9), /* PORT169CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) PORTCR(170, 0xe60520aa), /* PORT170CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) PORTCR(171, 0xe60520ab), /* PORT171CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) PORTCR(172, 0xe60520ac), /* PORT172CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) PORTCR(173, 0xe60520ad), /* PORT173CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) PORTCR(174, 0xe60520ae), /* PORT174CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) PORTCR(175, 0xe60520af), /* PORT175CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) PORTCR(176, 0xe60520b0), /* PORT176CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) PORTCR(177, 0xe60520b1), /* PORT177CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) PORTCR(178, 0xe60520b2), /* PORT178CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) PORTCR(179, 0xe60520b3), /* PORT179CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) PORTCR(180, 0xe60520b4), /* PORT180CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) PORTCR(181, 0xe60520b5), /* PORT181CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) PORTCR(182, 0xe60520b6), /* PORT182CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) PORTCR(183, 0xe60520b7), /* PORT183CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) PORTCR(184, 0xe60520b8), /* PORT184CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) PORTCR(185, 0xe60520b9), /* PORT185CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) PORTCR(186, 0xe60520ba), /* PORT186CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) PORTCR(187, 0xe60520bb), /* PORT187CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) PORTCR(188, 0xe60520bc), /* PORT188CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) PORTCR(189, 0xe60520bd), /* PORT189CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) PORTCR(190, 0xe60520be), /* PORT190CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) PORTCR(191, 0xe60520bf), /* PORT191CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) PORTCR(192, 0xe60520c0), /* PORT192CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) PORTCR(193, 0xe60520c1), /* PORT193CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) PORTCR(194, 0xe60520c2), /* PORT194CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) PORTCR(195, 0xe60520c3), /* PORT195CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) PORTCR(196, 0xe60520c4), /* PORT196CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) PORTCR(197, 0xe60520c5), /* PORT197CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) PORTCR(198, 0xe60520c6), /* PORT198CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) PORTCR(199, 0xe60520c7), /* PORT199CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) PORTCR(200, 0xe60520c8), /* PORT200CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) PORTCR(201, 0xe60520c9), /* PORT201CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) PORTCR(202, 0xe60520ca), /* PORT202CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) PORTCR(203, 0xe60520cb), /* PORT203CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) PORTCR(204, 0xe60520cc), /* PORT204CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) PORTCR(205, 0xe60520cd), /* PORT205CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) PORTCR(206, 0xe60520ce), /* PORT206CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) PORTCR(207, 0xe60520cf), /* PORT207CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) PORTCR(208, 0xe60520d0), /* PORT208CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) PORTCR(209, 0xe60520d1), /* PORT209CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) PORTCR(210, 0xe60530d2), /* PORT210CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) PORTCR(211, 0xe60530d3), /* PORT211CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) MSEL1CR_31_0, MSEL1CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) MSEL1CR_30_0, MSEL1CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) MSEL1CR_29_0, MSEL1CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) MSEL1CR_28_0, MSEL1CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) MSEL1CR_27_0, MSEL1CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) MSEL1CR_26_0, MSEL1CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) MSEL1CR_16_0, MSEL1CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) MSEL1CR_15_0, MSEL1CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) MSEL1CR_14_0, MSEL1CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) MSEL1CR_13_0, MSEL1CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) MSEL1CR_12_0, MSEL1CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) MSEL1CR_9_0, MSEL1CR_9_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) MSEL1CR_7_0, MSEL1CR_7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) MSEL1CR_6_0, MSEL1CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) MSEL1CR_5_0, MSEL1CR_5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) MSEL1CR_4_0, MSEL1CR_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) MSEL1CR_3_0, MSEL1CR_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) MSEL1CR_2_0, MSEL1CR_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) MSEL1CR_0_0, MSEL1CR_0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) MSEL3CR_15_0, MSEL3CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) MSEL3CR_6_0, MSEL3CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) MSEL4CR_19_0, MSEL4CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) MSEL4CR_18_0, MSEL4CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) MSEL4CR_15_0, MSEL4CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) MSEL4CR_10_0, MSEL4CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) MSEL4CR_6_0, MSEL4CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) MSEL4CR_4_0, MSEL4CR_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) MSEL4CR_1_0, MSEL4CR_1_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) MSEL5CR_31_0, MSEL5CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) MSEL5CR_30_0, MSEL5CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) MSEL5CR_29_0, MSEL5CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) MSEL5CR_27_0, MSEL5CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) MSEL5CR_25_0, MSEL5CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) MSEL5CR_23_0, MSEL5CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) MSEL5CR_21_0, MSEL5CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) MSEL5CR_19_0, MSEL5CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) MSEL5CR_17_0, MSEL5CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) MSEL5CR_15_0, MSEL5CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) MSEL5CR_14_0, MSEL5CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) MSEL5CR_13_0, MSEL5CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) MSEL5CR_12_0, MSEL5CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) MSEL5CR_11_0, MSEL5CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) MSEL5CR_10_0, MSEL5CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) MSEL5CR_8_0, MSEL5CR_8_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) MSEL5CR_7_0, MSEL5CR_7_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) MSEL5CR_6_0, MSEL5CR_6_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) MSEL5CR_5_0, MSEL5CR_5_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) MSEL5CR_4_0, MSEL5CR_4_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) MSEL5CR_3_0, MSEL5CR_3_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) MSEL5CR_2_0, MSEL5CR_2_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) MSEL5CR_0_0, MSEL5CR_0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) static const struct pinmux_data_reg pinmux_data_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) PORT115_DATA, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) 0, 0, PORT209_DATA, PORT208_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) PORT211_DATA, PORT210_DATA, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) 0, 0, 0, 0 ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) static const struct pinmux_irq pinmux_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) PINMUX_IRQ(2, 13), /* IRQ0A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) PINMUX_IRQ(20), /* IRQ1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) PINMUX_IRQ(11, 12), /* IRQ2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) PINMUX_IRQ(10, 14), /* IRQ3A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) PINMUX_IRQ(15, 172), /* IRQ4A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) PINMUX_IRQ(0, 1), /* IRQ5A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) PINMUX_IRQ(121, 173), /* IRQ6A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) PINMUX_IRQ(120, 209), /* IRQ7A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) PINMUX_IRQ(119), /* IRQ8A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) PINMUX_IRQ(118, 210), /* IRQ9A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) PINMUX_IRQ(19), /* IRQ10A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) PINMUX_IRQ(104), /* IRQ11A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) PINMUX_IRQ(42, 97), /* IRQ12A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) PINMUX_IRQ(64, 98), /* IRQ13A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) PINMUX_IRQ(63, 99), /* IRQ14A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) PINMUX_IRQ(62, 100), /* IRQ15A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) PINMUX_IRQ(68, 211), /* IRQ16A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) PINMUX_IRQ(69), /* IRQ17A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) PINMUX_IRQ(70), /* IRQ18A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) PINMUX_IRQ(71), /* IRQ19A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) PINMUX_IRQ(67), /* IRQ20A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) PINMUX_IRQ(202), /* IRQ21A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) PINMUX_IRQ(95), /* IRQ22A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) PINMUX_IRQ(96), /* IRQ23A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) PINMUX_IRQ(180), /* IRQ24A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) PINMUX_IRQ(38), /* IRQ25A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) PINMUX_IRQ(58, 81), /* IRQ26A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) PINMUX_IRQ(57, 168), /* IRQ27A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) PINMUX_IRQ(56, 169), /* IRQ28A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) PINMUX_IRQ(50, 170), /* IRQ29A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) PINMUX_IRQ(49, 171), /* IRQ30A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) PINMUX_IRQ(41, 167), /* IRQ31A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) #define PORTnCR_PULMD_OFF (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) #define PORTnCR_PULMD_DOWN (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) #define PORTnCR_PULMD_UP (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) #define PORTnCR_PULMD_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) struct r8a7740_portcr_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) unsigned int end_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) const struct r8a7740_portcr_group *group =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) &r8a7740_portcr_offsets[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) if (pin <= group->end_pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) return pfc->windows->virt + group->offset + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) switch (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) case PORTnCR_PULMD_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) return PIN_CONFIG_BIAS_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) case PORTnCR_PULMD_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) return PIN_CONFIG_BIAS_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) case PORTnCR_PULMD_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) unsigned int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) switch (bias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) value |= PORTnCR_PULMD_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) value |= PORTnCR_PULMD_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) iowrite8(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) .get_bias = r8a7740_pinmux_get_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) .set_bias = r8a7740_pinmux_set_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) const struct sh_pfc_soc_info r8a7740_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) .name = "r8a7740_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) .ops = &r8a7740_pfc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) .input = { PINMUX_INPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) PINMUX_INPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) .output = { PINMUX_OUTPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) PINMUX_OUTPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) .function = { PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) .data_regs = pinmux_data_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) .gpio_irq = pinmux_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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