^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2012-2013 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CPU_ALL_PORT(fn, pfx, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* Port0 - Port30 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PORT_10(0, fn, pfx, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PORT_10(10, fn, pfx##1, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PORT_10(20, fn, pfx##2, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_1(30, fn, pfx##30, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Port32 - Port40 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PORT_1(40, fn, pfx##40, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Port64 - Port85 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PORT_10(70, fn, pfx##7, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Port96 - Port126 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PORT_10(100, fn, pfx##10, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PORT_10(110, fn, pfx##11, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PORT_1(126, fn, pfx##126, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* Port128 - Port134 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PORT_1(134, fn, pfx##134, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Port160 - Port178 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PORT_10(160, fn, pfx##16, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PORT_1(178, fn, pfx##178, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Port192 - Port222 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PORT_10(200, fn, pfx##20, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PORT_10(210, fn, pfx##21, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PORT_1(222, fn, pfx##222, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* Port224 - Port250 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PORT_10(230, fn, pfx##23, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PORT_10(240, fn, pfx##24, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PORT_1(250, fn, pfx##250, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Port256 - Port283 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PORT_10(260, fn, pfx##26, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PORT_10(270, fn, pfx##27, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Port288 - Port308 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PORT_10(290, fn, pfx##29, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PORT_1(308, fn, pfx##308, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Port320 - Port329 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PORT_10(320, fn, pfx##32, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* PORT0_DATA -> PORT329_DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PORT_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* PORT0_IN -> PORT329_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINMUX_INPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PORT_ALL(IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINMUX_INPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* PORT0_OUT -> PORT329_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINMUX_OUTPUT_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PORT_ALL(OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINMUX_OUTPUT_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MSEL1CR_31_0, MSEL1CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MSEL1CR_27_0, MSEL1CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MSEL1CR_25_0, MSEL1CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MSEL1CR_24_0, MSEL1CR_24_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MSEL1CR_22_0, MSEL1CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MSEL1CR_21_0, MSEL1CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MSEL1CR_20_0, MSEL1CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MSEL1CR_19_0, MSEL1CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MSEL1CR_18_0, MSEL1CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MSEL1CR_17_0, MSEL1CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MSEL1CR_16_0, MSEL1CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MSEL1CR_15_0, MSEL1CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MSEL1CR_14_0, MSEL1CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MSEL1CR_13_0, MSEL1CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MSEL1CR_12_0, MSEL1CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MSEL1CR_11_0, MSEL1CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MSEL1CR_10_0, MSEL1CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MSEL1CR_09_0, MSEL1CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MSEL1CR_08_0, MSEL1CR_08_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MSEL1CR_07_0, MSEL1CR_07_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MSEL1CR_06_0, MSEL1CR_06_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MSEL1CR_05_0, MSEL1CR_05_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MSEL1CR_04_0, MSEL1CR_04_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MSEL1CR_03_0, MSEL1CR_03_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MSEL1CR_02_0, MSEL1CR_02_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MSEL1CR_01_0, MSEL1CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MSEL1CR_00_0, MSEL1CR_00_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MSEL3CR_31_0, MSEL3CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MSEL3CR_28_0, MSEL3CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MSEL3CR_27_0, MSEL3CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MSEL3CR_26_0, MSEL3CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MSEL3CR_23_0, MSEL3CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MSEL3CR_22_0, MSEL3CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MSEL3CR_21_0, MSEL3CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MSEL3CR_20_0, MSEL3CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MSEL3CR_19_0, MSEL3CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MSEL3CR_18_0, MSEL3CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MSEL3CR_17_0, MSEL3CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MSEL3CR_16_0, MSEL3CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MSEL3CR_15_0, MSEL3CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MSEL3CR_12_0, MSEL3CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MSEL3CR_11_0, MSEL3CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MSEL3CR_10_0, MSEL3CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MSEL3CR_09_0, MSEL3CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MSEL3CR_06_0, MSEL3CR_06_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MSEL3CR_03_0, MSEL3CR_03_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MSEL3CR_01_0, MSEL3CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MSEL3CR_00_0, MSEL3CR_00_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MSEL4CR_30_0, MSEL4CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MSEL4CR_29_0, MSEL4CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MSEL4CR_28_0, MSEL4CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) MSEL4CR_27_0, MSEL4CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MSEL4CR_26_0, MSEL4CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) MSEL4CR_25_0, MSEL4CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) MSEL4CR_24_0, MSEL4CR_24_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MSEL4CR_23_0, MSEL4CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MSEL4CR_22_0, MSEL4CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) MSEL4CR_21_0, MSEL4CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) MSEL4CR_20_0, MSEL4CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) MSEL4CR_19_0, MSEL4CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) MSEL4CR_18_0, MSEL4CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MSEL4CR_17_0, MSEL4CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) MSEL4CR_16_0, MSEL4CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MSEL4CR_15_0, MSEL4CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MSEL4CR_14_0, MSEL4CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MSEL4CR_13_0, MSEL4CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) MSEL4CR_12_0, MSEL4CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MSEL4CR_11_0, MSEL4CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) MSEL4CR_10_0, MSEL4CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) MSEL4CR_09_0, MSEL4CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MSEL4CR_07_0, MSEL4CR_07_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MSEL4CR_04_0, MSEL4CR_04_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MSEL4CR_01_0, MSEL4CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MSEL5CR_31_0, MSEL5CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MSEL5CR_30_0, MSEL5CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) MSEL5CR_29_0, MSEL5CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) MSEL5CR_28_0, MSEL5CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MSEL5CR_27_0, MSEL5CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) MSEL5CR_26_0, MSEL5CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MSEL5CR_25_0, MSEL5CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MSEL5CR_24_0, MSEL5CR_24_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MSEL5CR_23_0, MSEL5CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MSEL5CR_22_0, MSEL5CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MSEL5CR_21_0, MSEL5CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MSEL5CR_20_0, MSEL5CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MSEL5CR_19_0, MSEL5CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MSEL5CR_18_0, MSEL5CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) MSEL5CR_17_0, MSEL5CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) MSEL5CR_16_0, MSEL5CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) MSEL5CR_15_0, MSEL5CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MSEL5CR_14_0, MSEL5CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MSEL5CR_13_0, MSEL5CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MSEL5CR_12_0, MSEL5CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MSEL5CR_11_0, MSEL5CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MSEL5CR_10_0, MSEL5CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MSEL5CR_09_0, MSEL5CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) MSEL5CR_08_0, MSEL5CR_08_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) MSEL5CR_07_0, MSEL5CR_07_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) MSEL5CR_06_0, MSEL5CR_06_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MSEL8CR_16_0, MSEL8CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) MSEL8CR_01_0, MSEL8CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MSEL8CR_00_0, MSEL8CR_00_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define F1(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define F2(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define F3(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define F4(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define F5(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define F6(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define F7(a) a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IRQ(a) IRQ##a##_MARK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) F1(SCIFA1_RTS), F7(CSCIF1_RTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) F1(SCIFA1_CTS), F7(CSCIF1_CTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) F1(SCIFA1_SCK), F7(CSCIF1_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) F7(CHSCIF0_HSCK), /* Port40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) F1(PDM0_DATA), /* Port64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) F1(PDM1_DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) IRQ(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) F7(CHSCIF1_HRTS), /* Port70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) F7(CHSCIF1_HCTS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) F1(KEYIN0), /* Port96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) F2(KEYOUT7), F5(RFANAEN), IRQ(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) F5(SIM0_VOLTSEL1), /* Port130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) IRQ(20), /* Port160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) IRQ(21), IRQ(22), IRQ(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) IRQ(24), IRQ(25), IRQ(26), IRQ(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) F1(A9), F2(MMCD1_6), IRQ(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) F1(A8), F2(MMCD1_5), IRQ(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) F1(A7), F2(MMCD1_4), IRQ(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) F1(A6), F2(MMCD1_3), IRQ(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) F1(A5), F2(MMCD1_2), IRQ(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) F1(A4), F2(MMCD1_1), IRQ(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) F1(A3), F2(MMCD1_0), IRQ(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) F1(A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) F1(A0), F2(BS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) F1(CKO), F2(MMCCLK1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) F1(CS0_N), F5(SIM0_GPO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) F1(CS2_N), F5(SIM0_GPO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) F1(D15), F5(GIO_OUT15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) F1(D14), F5(GIO_OUT14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) F1(D13), F5(GIO_OUT13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) F1(D12), F5(GIO_OUT12), /* Port210 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) F1(D11), F5(WGM_TXP2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) F1(D9), F2(VIO_D9), F5(GIO_OUT9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) F1(D8), F2(VIO_D8), F5(GIO_OUT8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) F1(D7), F2(VIO_D7), F5(GIO_OUT7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) F1(D6), F2(VIO_D6), F5(GIO_OUT6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) F1(WE0_N), F2(RDWR_227),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) F1(WE1_N), F5(SIM0_GPO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) F1(PWMO), F2(VIO_CKO1_229),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) F2(VIO_CKO3_233), F4(SF_PORT_1_233),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) F1(FSIAISLD), F2(PDM3_DATA_235),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) F1(FSIBISLD), /* Port240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) F1(FSIBCK), F3(ISP_SHUTTER0_245),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) F4(MSIOF6_SS1), /* Port300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) IRQ(55), IRQ(56), IRQ(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* specify valid pin states for each pin in GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINMUX_DATA_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* Port0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Port1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Port2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Port3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Port4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Port5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* Port6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* Port7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Port8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Port9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Port10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Port11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Port12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Port13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Port14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Port15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Port16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* Port17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Port18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Port19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Port20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Port21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Port22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Port23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* Port24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Port25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Port26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Port27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Port28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Port29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Port30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Port32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Port33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* Port34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* Port35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Port36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Port37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Port38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* Port39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* Port40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Port64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /* Port65 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Port66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* Port67 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Port68 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* Port69 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Port70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) /* Port71 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Port72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /* Port73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /* Port74 - Port85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) PINMUX_DATA(TXP_MARK, PORT80_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) PINMUX_DATA(TXP2_MARK, PORT81_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Port96 - Port101 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Port102 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Port103 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /* Port104 - Port108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) /* Port109 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Port110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* Port111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /* Port112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* Port113 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /* Port114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Port115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* Port116 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Port117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* Port118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) /* Port119 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Port120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Port121 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* Port122 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /* Port123 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) /* Port124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* Port125 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* Port126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Port128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Port129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /* Port130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Port131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* Port132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* Port133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /* Port134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Port160 - Port178 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Port192 - Port200 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) PINMUX_DATA(A10_MARK, PORT192_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) PINMUX_DATA(A9_MARK, PORT193_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) PINMUX_DATA(A8_MARK, PORT194_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) PINMUX_DATA(A7_MARK, PORT195_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) PINMUX_DATA(A6_MARK, PORT196_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) PINMUX_DATA(A5_MARK, PORT197_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) PINMUX_DATA(A4_MARK, PORT198_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) PINMUX_DATA(A3_MARK, PORT199_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) PINMUX_DATA(A2_MARK, PORT200_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* Port192 - Port200 FN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Port192 - Port200 IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Port201 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINMUX_DATA(A1_MARK, PORT201_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Port202 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINMUX_DATA(A0_MARK, PORT202_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINMUX_DATA(BS_MARK, PORT202_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Port203 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINMUX_DATA(CKO_MARK, PORT203_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* Port204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Port205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* Port206 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Port207 - Port212 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINMUX_DATA(D15_MARK, PORT207_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINMUX_DATA(D14_MARK, PORT208_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINMUX_DATA(D13_MARK, PORT209_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINMUX_DATA(D12_MARK, PORT210_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINMUX_DATA(D11_MARK, PORT211_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINMUX_DATA(D10_MARK, PORT212_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Port207 - Port212 FN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Port213 - Port222 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINMUX_DATA(D9_MARK, PORT213_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINMUX_DATA(D8_MARK, PORT214_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINMUX_DATA(D7_MARK, PORT215_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINMUX_DATA(D6_MARK, PORT216_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINMUX_DATA(D5_MARK, PORT217_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINMUX_DATA(D4_MARK, PORT218_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINMUX_DATA(D3_MARK, PORT219_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINMUX_DATA(D2_MARK, PORT220_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINMUX_DATA(D1_MARK, PORT221_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINMUX_DATA(D0_MARK, PORT222_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Port213 - Port222 FN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /* Port213 - Port222 FN5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Port224 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Port225 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINMUX_DATA(RD_N_MARK, PORT225_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Port226 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Port227 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* Port228 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Port229 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINMUX_DATA(PWMO_MARK, PORT229_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* Port230 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Port231 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /* Port232 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Port233 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Port234 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Port235 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* Port236 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Port237 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Port238 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* Port239 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) /* Port240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* Port241 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Port242 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Port243 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Port244 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* Port245 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Port246 - Port250 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Port256 - Port258 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) /* Port259 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Port260 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) /* Port261 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* Port262 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Port263 - Port266 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Port263 - Port266 FN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Port267 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Port268 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Port269 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Port270 - Port273 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* Port270 - Port273 FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) /* Port274 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Port275 - Port280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) /* Port281 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Port282 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* Port283 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Port289 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /* Port290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) /* Port291 - Port294 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) /* Port291 - Port294 FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* Port295 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Port296 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /* Port297 - Port300 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* Port297 - Port300 FN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Port297 - Port300 FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Port297 - Port300 FN4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Port301 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Port302 - Port306 FN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /* Port302 - Port306 FN3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* Port307 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) /* Port308 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Port320 - Port329 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define __O (SH_PFC_PIN_CFG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define __PUD (SH_PFC_PIN_CFG_PULL_UP_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) R8A73A4_PIN_IO_PU_PD(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) R8A73A4_PIN_IO_PU_PD(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) R8A73A4_PIN_IO_PU_PD(126),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) R8A73A4_PIN_IO_PU_PD(134),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) R8A73A4_PIN_IO_PU_PD(178),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) R8A73A4_PIN_IO_PU_PD(222),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) R8A73A4_PIN_IO_PU_PD(250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) R8A73A4_PIN_IO_PU_PD(308),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* - IRQC ------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define IRQC_PINS_MUX(pin, irq_mark) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const unsigned int irqc_irq##irq_mark##_pins[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) pin, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) static const unsigned int irqc_irq##irq_mark##_mux[] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) IRQ##irq_mark##_MARK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) IRQC_PINS_MUX(0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) IRQC_PINS_MUX(1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) IRQC_PINS_MUX(2, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) IRQC_PINS_MUX(3, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) IRQC_PINS_MUX(4, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) IRQC_PINS_MUX(5, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) IRQC_PINS_MUX(6, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) IRQC_PINS_MUX(7, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) IRQC_PINS_MUX(8, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) IRQC_PINS_MUX(9, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) IRQC_PINS_MUX(10, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) IRQC_PINS_MUX(11, 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) IRQC_PINS_MUX(12, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) IRQC_PINS_MUX(13, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) IRQC_PINS_MUX(14, 14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) IRQC_PINS_MUX(15, 15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) IRQC_PINS_MUX(66, 40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) IRQC_PINS_MUX(84, 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) IRQC_PINS_MUX(85, 18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) IRQC_PINS_MUX(102, 41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) IRQC_PINS_MUX(103, 42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) IRQC_PINS_MUX(109, 43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) IRQC_PINS_MUX(110, 44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) IRQC_PINS_MUX(111, 45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) IRQC_PINS_MUX(112, 46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) IRQC_PINS_MUX(113, 47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) IRQC_PINS_MUX(114, 48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) IRQC_PINS_MUX(115, 49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) IRQC_PINS_MUX(160, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) IRQC_PINS_MUX(161, 21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) IRQC_PINS_MUX(162, 22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) IRQC_PINS_MUX(163, 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) IRQC_PINS_MUX(175, 24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) IRQC_PINS_MUX(176, 25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) IRQC_PINS_MUX(177, 26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) IRQC_PINS_MUX(178, 27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) IRQC_PINS_MUX(192, 31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) IRQC_PINS_MUX(193, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) IRQC_PINS_MUX(194, 33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) IRQC_PINS_MUX(195, 34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) IRQC_PINS_MUX(196, 35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) IRQC_PINS_MUX(197, 36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) IRQC_PINS_MUX(198, 37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) IRQC_PINS_MUX(199, 38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) IRQC_PINS_MUX(200, 39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) IRQC_PINS_MUX(290, 51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) IRQC_PINS_MUX(296, 52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) IRQC_PINS_MUX(301, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) IRQC_PINS_MUX(320, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) IRQC_PINS_MUX(321, 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) IRQC_PINS_MUX(322, 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) IRQC_PINS_MUX(323, 29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) IRQC_PINS_MUX(324, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) IRQC_PINS_MUX(325, 53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) IRQC_PINS_MUX(326, 54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) IRQC_PINS_MUX(327, 55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) IRQC_PINS_MUX(328, 56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) IRQC_PINS_MUX(329, 57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /* - MMCIF0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static const unsigned int mmc0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) 164,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static const unsigned int mmc0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) MMCD0_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) static const unsigned int mmc0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) 164, 165, 166, 167,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static const unsigned int mmc0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const unsigned int mmc0_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) 164, 165, 166, 167, 168, 169, 170, 171,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const unsigned int mmc0_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static const unsigned int mmc0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) 172, 173,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static const unsigned int mmc0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) MMCCMD0_MARK, MMCCLK0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* - MMCIF1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) static const unsigned int mmc1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) /* D[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) 199,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static const unsigned int mmc1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) MMCD1_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static const unsigned int mmc1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) 199, 198, 197, 196,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) static const unsigned int mmc1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static const unsigned int mmc1_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) /* D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) 199, 198, 197, 196, 195, 194, 193, 192,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static const unsigned int mmc1_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) static const unsigned int mmc1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) /* CMD, CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) 200, 203,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const unsigned int mmc1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) MMCCMD1_MARK, MMCCLK1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* - SCIFA0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static const unsigned int scifa0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* SCIFA0_RXD, SCIFA0_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) 117, 116,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static const unsigned int scifa0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static const unsigned int scifa0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* SCIFA0_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) 34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static const unsigned int scifa0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SCIFA0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const unsigned int scifa0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) /* SCIFA0_RTS, SCIFA0_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) 32, 33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const unsigned int scifa0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* - SCIFA1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static const unsigned int scifa1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* SCIFA1_RXD, SCIFA1_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) 119, 118,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static const unsigned int scifa1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static const unsigned int scifa1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* SCIFA1_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) 37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static const unsigned int scifa1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SCIFA1_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static const unsigned int scifa1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) /* SCIFA1_RTS, SCIFA1_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) 35, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static const unsigned int scifa1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) /* - SCIFB0 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static const unsigned int scifb0_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) /* SCIFB0_RXD, SCIFB0_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) 123, 122,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) static const unsigned int scifb0_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static const unsigned int scifb0_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* SCIFB0_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static const unsigned int scifb0_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) SCIFB0_SCK_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static const unsigned int scifb0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) /* SCIFB0_RTS, SCIFB0_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) 38, 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static const unsigned int scifb0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) /* - SCIFB1 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static const unsigned int scifb1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* SCIFB1_RXD, SCIFB1_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) 27, 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) static const unsigned int scifb1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static const unsigned int scifb1_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* SCIFB1_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static const unsigned int scifb1_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) SCIFB1_SCK_28_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) static const unsigned int scifb1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* SCIFB1_RTS, SCIFB1_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) 24, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static const unsigned int scifb1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) static const unsigned int scifb1_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* SCIFB1_RXD, SCIFB1_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) 72, 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static const unsigned int scifb1_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const unsigned int scifb1_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* SCIFB1_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) 261,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static const unsigned int scifb1_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) SCIFB1_SCK_261_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static const unsigned int scifb1_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* SCIFB1_RTS, SCIFB1_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) 70, 71,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) static const unsigned int scifb1_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* - SCIFB2 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) static const unsigned int scifb2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* SCIFB2_RXD, SCIFB2_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) 69, 68,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static const unsigned int scifb2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static const unsigned int scifb2_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) /* SCIFB2_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) 262,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static const unsigned int scifb2_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SCIFB2_SCK_262_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) static const unsigned int scifb2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* SCIFB2_RTS, SCIFB2_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) 73, 66,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const unsigned int scifb2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) static const unsigned int scifb2_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) /* SCIFB2_RXD, SCIFB2_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) 297, 295,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static const unsigned int scifb2_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static const unsigned int scifb2_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* SCIFB2_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) 299,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static const unsigned int scifb2_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) SCIFB2_SCK_299_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static const unsigned int scifb2_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /* SCIFB2_RTS, SCIFB2_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) 300, 298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static const unsigned int scifb2_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) /* - SCIFB3 ----------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) static const unsigned int scifb3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* SCIFB3_RXD, SCIFB3_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) 22, 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static const unsigned int scifb3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) static const unsigned int scifb3_clk_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) /* SCIFB3_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static const unsigned int scifb3_clk_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) SCIFB3_SCK_23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static const unsigned int scifb3_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* SCIFB3_RTS, SCIFB3_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) 19, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) static const unsigned int scifb3_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static const unsigned int scifb3_data_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) /* SCIFB3_RXD, SCIFB3_TXD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) 120, 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) static const unsigned int scifb3_data_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) static const unsigned int scifb3_clk_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* SCIFB3_SCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) static const unsigned int scifb3_clk_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) SCIFB3_SCK_40_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const unsigned int scifb3_ctrl_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* SCIFB3_RTS, SCIFB3_CTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) 38, 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static const unsigned int scifb3_ctrl_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* - SDHI0 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) static const unsigned int sdhi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) 302,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static const unsigned int sdhi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) SDHID0_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) static const unsigned int sdhi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) 302, 303, 304, 305,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static const unsigned int sdhi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const unsigned int sdhi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) 308, 306,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) static const unsigned int sdhi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) SDHICLK0_MARK, SDHICMD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) static const unsigned int sdhi0_cd_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) /* CD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) 301,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static const unsigned int sdhi0_cd_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) SDHICD0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) static const unsigned int sdhi0_wp_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* WP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) 307,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static const unsigned int sdhi0_wp_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) SDHIWP0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* - SDHI1 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static const unsigned int sdhi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) 289,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static const unsigned int sdhi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) SDHID1_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) static const unsigned int sdhi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) 289, 290, 291, 292,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const unsigned int sdhi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static const unsigned int sdhi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) 293, 294,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static const unsigned int sdhi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SDHICLK1_MARK, SDHICMD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /* - SDHI2 ------------------------------------------------------------------ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static const unsigned int sdhi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) 295,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) static const unsigned int sdhi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) SDHID2_0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static const unsigned int sdhi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* D[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) 295, 296, 297, 298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static const unsigned int sdhi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) static const unsigned int sdhi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) /* CLK, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) 299, 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static const unsigned int sdhi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) SDHICLK2_MARK, SDHICMD2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) SH_PFC_PIN_GROUP(irqc_irq0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) SH_PFC_PIN_GROUP(irqc_irq1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) SH_PFC_PIN_GROUP(irqc_irq2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) SH_PFC_PIN_GROUP(irqc_irq3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) SH_PFC_PIN_GROUP(irqc_irq4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) SH_PFC_PIN_GROUP(irqc_irq5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SH_PFC_PIN_GROUP(irqc_irq6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) SH_PFC_PIN_GROUP(irqc_irq7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) SH_PFC_PIN_GROUP(irqc_irq8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SH_PFC_PIN_GROUP(irqc_irq9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SH_PFC_PIN_GROUP(irqc_irq10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) SH_PFC_PIN_GROUP(irqc_irq11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) SH_PFC_PIN_GROUP(irqc_irq12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) SH_PFC_PIN_GROUP(irqc_irq13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) SH_PFC_PIN_GROUP(irqc_irq14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) SH_PFC_PIN_GROUP(irqc_irq15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) SH_PFC_PIN_GROUP(irqc_irq16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) SH_PFC_PIN_GROUP(irqc_irq17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) SH_PFC_PIN_GROUP(irqc_irq18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) SH_PFC_PIN_GROUP(irqc_irq19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) SH_PFC_PIN_GROUP(irqc_irq20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) SH_PFC_PIN_GROUP(irqc_irq21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) SH_PFC_PIN_GROUP(irqc_irq22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) SH_PFC_PIN_GROUP(irqc_irq23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) SH_PFC_PIN_GROUP(irqc_irq24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) SH_PFC_PIN_GROUP(irqc_irq25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) SH_PFC_PIN_GROUP(irqc_irq26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) SH_PFC_PIN_GROUP(irqc_irq27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) SH_PFC_PIN_GROUP(irqc_irq28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) SH_PFC_PIN_GROUP(irqc_irq29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) SH_PFC_PIN_GROUP(irqc_irq30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) SH_PFC_PIN_GROUP(irqc_irq31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) SH_PFC_PIN_GROUP(irqc_irq32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) SH_PFC_PIN_GROUP(irqc_irq33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) SH_PFC_PIN_GROUP(irqc_irq34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SH_PFC_PIN_GROUP(irqc_irq35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SH_PFC_PIN_GROUP(irqc_irq36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) SH_PFC_PIN_GROUP(irqc_irq37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) SH_PFC_PIN_GROUP(irqc_irq38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) SH_PFC_PIN_GROUP(irqc_irq39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) SH_PFC_PIN_GROUP(irqc_irq40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) SH_PFC_PIN_GROUP(irqc_irq41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) SH_PFC_PIN_GROUP(irqc_irq42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) SH_PFC_PIN_GROUP(irqc_irq43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) SH_PFC_PIN_GROUP(irqc_irq44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) SH_PFC_PIN_GROUP(irqc_irq45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SH_PFC_PIN_GROUP(irqc_irq46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SH_PFC_PIN_GROUP(irqc_irq47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) SH_PFC_PIN_GROUP(irqc_irq48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) SH_PFC_PIN_GROUP(irqc_irq49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SH_PFC_PIN_GROUP(irqc_irq50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) SH_PFC_PIN_GROUP(irqc_irq51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) SH_PFC_PIN_GROUP(irqc_irq52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) SH_PFC_PIN_GROUP(irqc_irq53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) SH_PFC_PIN_GROUP(irqc_irq54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SH_PFC_PIN_GROUP(irqc_irq55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) SH_PFC_PIN_GROUP(irqc_irq56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) SH_PFC_PIN_GROUP(irqc_irq57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) SH_PFC_PIN_GROUP(mmc0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SH_PFC_PIN_GROUP(mmc0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SH_PFC_PIN_GROUP(mmc0_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) SH_PFC_PIN_GROUP(mmc0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) SH_PFC_PIN_GROUP(mmc1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) SH_PFC_PIN_GROUP(mmc1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) SH_PFC_PIN_GROUP(mmc1_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) SH_PFC_PIN_GROUP(mmc1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) SH_PFC_PIN_GROUP(scifa0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) SH_PFC_PIN_GROUP(scifa0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) SH_PFC_PIN_GROUP(scifa0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) SH_PFC_PIN_GROUP(scifa1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) SH_PFC_PIN_GROUP(scifa1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) SH_PFC_PIN_GROUP(scifa1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) SH_PFC_PIN_GROUP(scifb0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) SH_PFC_PIN_GROUP(scifb0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) SH_PFC_PIN_GROUP(scifb0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) SH_PFC_PIN_GROUP(scifb1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) SH_PFC_PIN_GROUP(scifb1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) SH_PFC_PIN_GROUP(scifb1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) SH_PFC_PIN_GROUP(scifb1_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) SH_PFC_PIN_GROUP(scifb1_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) SH_PFC_PIN_GROUP(scifb1_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) SH_PFC_PIN_GROUP(scifb2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) SH_PFC_PIN_GROUP(scifb2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) SH_PFC_PIN_GROUP(scifb2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) SH_PFC_PIN_GROUP(scifb2_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) SH_PFC_PIN_GROUP(scifb2_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) SH_PFC_PIN_GROUP(scifb2_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) SH_PFC_PIN_GROUP(scifb3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) SH_PFC_PIN_GROUP(scifb3_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) SH_PFC_PIN_GROUP(scifb3_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) SH_PFC_PIN_GROUP(scifb3_data_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) SH_PFC_PIN_GROUP(scifb3_clk_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) SH_PFC_PIN_GROUP(scifb3_ctrl_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) SH_PFC_PIN_GROUP(sdhi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) SH_PFC_PIN_GROUP(sdhi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) SH_PFC_PIN_GROUP(sdhi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) SH_PFC_PIN_GROUP(sdhi0_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) SH_PFC_PIN_GROUP(sdhi0_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) SH_PFC_PIN_GROUP(sdhi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) SH_PFC_PIN_GROUP(sdhi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) SH_PFC_PIN_GROUP(sdhi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) SH_PFC_PIN_GROUP(sdhi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) SH_PFC_PIN_GROUP(sdhi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) SH_PFC_PIN_GROUP(sdhi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static const char * const irqc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) "irqc_irq0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) "irqc_irq1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) "irqc_irq2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) "irqc_irq3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) "irqc_irq4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) "irqc_irq5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) "irqc_irq6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "irqc_irq7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) "irqc_irq8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) "irqc_irq9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) "irqc_irq10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) "irqc_irq11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) "irqc_irq12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) "irqc_irq13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) "irqc_irq14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) "irqc_irq15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) "irqc_irq16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) "irqc_irq17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) "irqc_irq18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) "irqc_irq19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) "irqc_irq20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) "irqc_irq21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) "irqc_irq22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) "irqc_irq23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) "irqc_irq24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) "irqc_irq25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) "irqc_irq26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) "irqc_irq27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) "irqc_irq28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) "irqc_irq29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) "irqc_irq30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) "irqc_irq31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) "irqc_irq32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) "irqc_irq33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) "irqc_irq34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) "irqc_irq35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) "irqc_irq36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) "irqc_irq37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) "irqc_irq38",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) "irqc_irq39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) "irqc_irq40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) "irqc_irq41",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) "irqc_irq42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) "irqc_irq43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) "irqc_irq44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) "irqc_irq45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) "irqc_irq46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) "irqc_irq47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) "irqc_irq48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) "irqc_irq49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) "irqc_irq50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) "irqc_irq51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) "irqc_irq52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) "irqc_irq53",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) "irqc_irq54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) "irqc_irq55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) "irqc_irq56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) "irqc_irq57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) static const char * const mmc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) "mmc0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) "mmc0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) "mmc0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) "mmc0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) static const char * const mmc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) "mmc1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) "mmc1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) "mmc1_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) "mmc1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) static const char * const scifa0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) "scifa0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) "scifa0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) "scifa0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) static const char * const scifa1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) "scifa1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) "scifa1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) "scifa1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static const char * const scifb0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) "scifb0_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) "scifb0_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) "scifb0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static const char * const scifb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) "scifb1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) "scifb1_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) "scifb1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) "scifb1_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) "scifb1_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) "scifb1_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) static const char * const scifb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) "scifb2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) "scifb2_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) "scifb2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) "scifb2_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) "scifb2_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) "scifb2_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static const char * const scifb3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "scifb3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) "scifb3_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) "scifb3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) "scifb3_data_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) "scifb3_clk_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) "scifb3_ctrl_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) static const char * const sdhi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) "sdhi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) "sdhi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) "sdhi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) "sdhi0_cd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) "sdhi0_wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static const char * const sdhi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) "sdhi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) "sdhi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) "sdhi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) static const char * const sdhi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) "sdhi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) "sdhi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) "sdhi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) SH_PFC_FUNCTION(irqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) SH_PFC_FUNCTION(mmc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) SH_PFC_FUNCTION(mmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) SH_PFC_FUNCTION(scifa0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) SH_PFC_FUNCTION(scifa1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) SH_PFC_FUNCTION(scifb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) SH_PFC_FUNCTION(scifb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) SH_PFC_FUNCTION(scifb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) SH_PFC_FUNCTION(scifb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) SH_PFC_FUNCTION(sdhi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) SH_PFC_FUNCTION(sdhi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) SH_PFC_FUNCTION(sdhi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) PORTCR(0, 0xe6050000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) PORTCR(1, 0xe6050001),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) PORTCR(2, 0xe6050002),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) PORTCR(3, 0xe6050003),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) PORTCR(4, 0xe6050004),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) PORTCR(5, 0xe6050005),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) PORTCR(6, 0xe6050006),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) PORTCR(7, 0xe6050007),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) PORTCR(8, 0xe6050008),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) PORTCR(9, 0xe6050009),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) PORTCR(10, 0xe605000A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) PORTCR(11, 0xe605000B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) PORTCR(12, 0xe605000C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) PORTCR(13, 0xe605000D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) PORTCR(14, 0xe605000E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) PORTCR(15, 0xe605000F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) PORTCR(16, 0xe6050010),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) PORTCR(17, 0xe6050011),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) PORTCR(18, 0xe6050012),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) PORTCR(19, 0xe6050013),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) PORTCR(20, 0xe6050014),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) PORTCR(21, 0xe6050015),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) PORTCR(22, 0xe6050016),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) PORTCR(23, 0xe6050017),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) PORTCR(24, 0xe6050018),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) PORTCR(25, 0xe6050019),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) PORTCR(26, 0xe605001A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) PORTCR(27, 0xe605001B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) PORTCR(28, 0xe605001C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) PORTCR(29, 0xe605001D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) PORTCR(30, 0xe605001E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) PORTCR(32, 0xe6051020),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) PORTCR(33, 0xe6051021),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) PORTCR(34, 0xe6051022),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) PORTCR(35, 0xe6051023),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) PORTCR(36, 0xe6051024),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) PORTCR(37, 0xe6051025),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) PORTCR(38, 0xe6051026),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) PORTCR(39, 0xe6051027),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) PORTCR(40, 0xe6051028),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) PORTCR(64, 0xe6050040),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) PORTCR(65, 0xe6050041),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) PORTCR(66, 0xe6050042),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) PORTCR(67, 0xe6050043),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) PORTCR(68, 0xe6050044),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) PORTCR(69, 0xe6050045),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) PORTCR(70, 0xe6050046),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) PORTCR(71, 0xe6050047),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) PORTCR(72, 0xe6050048),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) PORTCR(73, 0xe6050049),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) PORTCR(74, 0xe605004A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) PORTCR(75, 0xe605004B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) PORTCR(76, 0xe605004C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) PORTCR(77, 0xe605004D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) PORTCR(78, 0xe605004E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) PORTCR(79, 0xe605004F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) PORTCR(80, 0xe6050050),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) PORTCR(81, 0xe6050051),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) PORTCR(82, 0xe6050052),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) PORTCR(83, 0xe6050053),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) PORTCR(84, 0xe6050054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) PORTCR(85, 0xe6050055),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) PORTCR(96, 0xe6051060),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) PORTCR(97, 0xe6051061),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) PORTCR(98, 0xe6051062),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) PORTCR(99, 0xe6051063),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) PORTCR(100, 0xe6051064),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) PORTCR(101, 0xe6051065),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) PORTCR(102, 0xe6051066),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) PORTCR(103, 0xe6051067),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) PORTCR(104, 0xe6051068),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) PORTCR(105, 0xe6051069),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) PORTCR(106, 0xe605106A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) PORTCR(107, 0xe605106B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) PORTCR(108, 0xe605106C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) PORTCR(109, 0xe605106D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) PORTCR(110, 0xe605106E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) PORTCR(111, 0xe605106F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) PORTCR(112, 0xe6051070),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) PORTCR(113, 0xe6051071),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) PORTCR(114, 0xe6051072),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) PORTCR(115, 0xe6051073),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) PORTCR(116, 0xe6051074),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) PORTCR(117, 0xe6051075),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) PORTCR(118, 0xe6051076),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) PORTCR(119, 0xe6051077),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) PORTCR(120, 0xe6051078),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) PORTCR(121, 0xe6051079),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) PORTCR(122, 0xe605107A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) PORTCR(123, 0xe605107B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) PORTCR(124, 0xe605107C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) PORTCR(125, 0xe605107D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) PORTCR(126, 0xe605107E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) PORTCR(128, 0xe6051080),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) PORTCR(129, 0xe6051081),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) PORTCR(130, 0xe6051082),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) PORTCR(131, 0xe6051083),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) PORTCR(132, 0xe6051084),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) PORTCR(133, 0xe6051085),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) PORTCR(134, 0xe6051086),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) PORTCR(160, 0xe60520A0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) PORTCR(161, 0xe60520A1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) PORTCR(162, 0xe60520A2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) PORTCR(163, 0xe60520A3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) PORTCR(164, 0xe60520A4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) PORTCR(165, 0xe60520A5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) PORTCR(166, 0xe60520A6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) PORTCR(167, 0xe60520A7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) PORTCR(168, 0xe60520A8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) PORTCR(169, 0xe60520A9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) PORTCR(170, 0xe60520AA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) PORTCR(171, 0xe60520AB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) PORTCR(172, 0xe60520AC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) PORTCR(173, 0xe60520AD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) PORTCR(174, 0xe60520AE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) PORTCR(175, 0xe60520AF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) PORTCR(176, 0xe60520B0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) PORTCR(177, 0xe60520B1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) PORTCR(178, 0xe60520B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) PORTCR(192, 0xe60520C0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) PORTCR(193, 0xe60520C1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) PORTCR(194, 0xe60520C2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) PORTCR(195, 0xe60520C3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) PORTCR(196, 0xe60520C4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) PORTCR(197, 0xe60520C5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) PORTCR(198, 0xe60520C6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) PORTCR(199, 0xe60520C7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) PORTCR(200, 0xe60520C8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) PORTCR(201, 0xe60520C9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) PORTCR(202, 0xe60520CA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) PORTCR(203, 0xe60520CB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) PORTCR(204, 0xe60520CC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) PORTCR(205, 0xe60520CD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) PORTCR(206, 0xe60520CE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) PORTCR(207, 0xe60520CF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) PORTCR(208, 0xe60520D0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) PORTCR(209, 0xe60520D1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) PORTCR(210, 0xe60520D2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) PORTCR(211, 0xe60520D3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) PORTCR(212, 0xe60520D4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) PORTCR(213, 0xe60520D5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) PORTCR(214, 0xe60520D6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) PORTCR(215, 0xe60520D7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) PORTCR(216, 0xe60520D8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) PORTCR(217, 0xe60520D9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) PORTCR(218, 0xe60520DA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) PORTCR(219, 0xe60520DB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) PORTCR(220, 0xe60520DC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) PORTCR(221, 0xe60520DD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) PORTCR(222, 0xe60520DE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) PORTCR(224, 0xe60520E0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) PORTCR(225, 0xe60520E1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) PORTCR(226, 0xe60520E2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) PORTCR(227, 0xe60520E3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) PORTCR(228, 0xe60520E4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) PORTCR(229, 0xe60520E5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) PORTCR(230, 0xe60520e6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) PORTCR(231, 0xe60520E7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) PORTCR(232, 0xe60520E8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) PORTCR(233, 0xe60520E9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) PORTCR(234, 0xe60520EA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) PORTCR(235, 0xe60520EB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) PORTCR(236, 0xe60520EC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) PORTCR(237, 0xe60520ED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) PORTCR(238, 0xe60520EE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) PORTCR(239, 0xe60520EF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) PORTCR(240, 0xe60520F0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) PORTCR(241, 0xe60520F1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) PORTCR(242, 0xe60520F2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) PORTCR(243, 0xe60520F3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) PORTCR(244, 0xe60520F4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) PORTCR(245, 0xe60520F5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) PORTCR(246, 0xe60520F6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) PORTCR(247, 0xe60520F7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) PORTCR(248, 0xe60520F8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) PORTCR(249, 0xe60520F9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) PORTCR(250, 0xe60520FA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) PORTCR(256, 0xe6052100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) PORTCR(257, 0xe6052101),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) PORTCR(258, 0xe6052102),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) PORTCR(259, 0xe6052103),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) PORTCR(260, 0xe6052104),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) PORTCR(261, 0xe6052105),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) PORTCR(262, 0xe6052106),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) PORTCR(263, 0xe6052107),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) PORTCR(264, 0xe6052108),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) PORTCR(265, 0xe6052109),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) PORTCR(266, 0xe605210A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) PORTCR(267, 0xe605210B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) PORTCR(268, 0xe605210C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) PORTCR(269, 0xe605210D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) PORTCR(270, 0xe605210E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) PORTCR(271, 0xe605210F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) PORTCR(272, 0xe6052110),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) PORTCR(273, 0xe6052111),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) PORTCR(274, 0xe6052112),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) PORTCR(275, 0xe6052113),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) PORTCR(276, 0xe6052114),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) PORTCR(277, 0xe6052115),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) PORTCR(278, 0xe6052116),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) PORTCR(279, 0xe6052117),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) PORTCR(280, 0xe6052118),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) PORTCR(281, 0xe6052119),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) PORTCR(282, 0xe605211A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) PORTCR(283, 0xe605211B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) PORTCR(288, 0xe6053120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) PORTCR(289, 0xe6053121),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) PORTCR(290, 0xe6053122),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) PORTCR(291, 0xe6053123),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) PORTCR(292, 0xe6053124),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) PORTCR(293, 0xe6053125),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) PORTCR(294, 0xe6053126),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) PORTCR(295, 0xe6053127),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) PORTCR(296, 0xe6053128),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) PORTCR(297, 0xe6053129),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) PORTCR(298, 0xe605312A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) PORTCR(299, 0xe605312B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) PORTCR(300, 0xe605312C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) PORTCR(301, 0xe605312D),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) PORTCR(302, 0xe605312E),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) PORTCR(303, 0xe605312F),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) PORTCR(304, 0xe6053130),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) PORTCR(305, 0xe6053131),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) PORTCR(306, 0xe6053132),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) PORTCR(307, 0xe6053133),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) PORTCR(308, 0xe6053134),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) PORTCR(320, 0xe6053140),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) PORTCR(321, 0xe6053141),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) PORTCR(322, 0xe6053142),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) PORTCR(323, 0xe6053143),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) PORTCR(324, 0xe6053144),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) PORTCR(325, 0xe6053145),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) PORTCR(326, 0xe6053146),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) PORTCR(327, 0xe6053147),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) PORTCR(328, 0xe6053148),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) PORTCR(329, 0xe6053149),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) MSEL1CR_31_0, MSEL1CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) MSEL1CR_27_0, MSEL1CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) MSEL1CR_25_0, MSEL1CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) MSEL1CR_24_0, MSEL1CR_24_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) MSEL1CR_22_0, MSEL1CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) MSEL1CR_21_0, MSEL1CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) MSEL1CR_20_0, MSEL1CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) MSEL1CR_19_0, MSEL1CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) MSEL1CR_18_0, MSEL1CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) MSEL1CR_17_0, MSEL1CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) MSEL1CR_16_0, MSEL1CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) MSEL1CR_15_0, MSEL1CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) MSEL1CR_14_0, MSEL1CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) MSEL1CR_13_0, MSEL1CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) MSEL1CR_12_0, MSEL1CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) MSEL1CR_11_0, MSEL1CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) MSEL1CR_10_0, MSEL1CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) MSEL1CR_09_0, MSEL1CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) MSEL1CR_08_0, MSEL1CR_08_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) MSEL1CR_07_0, MSEL1CR_07_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) MSEL1CR_06_0, MSEL1CR_06_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) MSEL1CR_05_0, MSEL1CR_05_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) MSEL1CR_04_0, MSEL1CR_04_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) MSEL1CR_03_0, MSEL1CR_03_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) MSEL1CR_02_0, MSEL1CR_02_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) MSEL1CR_01_0, MSEL1CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) MSEL1CR_00_0, MSEL1CR_00_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) MSEL3CR_31_0, MSEL3CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) MSEL3CR_28_0, MSEL3CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) MSEL3CR_27_0, MSEL3CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) MSEL3CR_26_0, MSEL3CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) MSEL3CR_23_0, MSEL3CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) MSEL3CR_22_0, MSEL3CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) MSEL3CR_21_0, MSEL3CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) MSEL3CR_20_0, MSEL3CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) MSEL3CR_19_0, MSEL3CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) MSEL3CR_18_0, MSEL3CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) MSEL3CR_17_0, MSEL3CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) MSEL3CR_16_0, MSEL3CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) MSEL3CR_15_0, MSEL3CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) MSEL3CR_12_0, MSEL3CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) MSEL3CR_11_0, MSEL3CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) MSEL3CR_10_0, MSEL3CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) MSEL3CR_09_0, MSEL3CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) MSEL3CR_06_0, MSEL3CR_06_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) MSEL3CR_03_0, MSEL3CR_03_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) MSEL3CR_01_0, MSEL3CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) MSEL3CR_00_0, MSEL3CR_00_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) MSEL4CR_30_0, MSEL4CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) MSEL4CR_29_0, MSEL4CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) MSEL4CR_28_0, MSEL4CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) MSEL4CR_27_0, MSEL4CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) MSEL4CR_26_0, MSEL4CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) MSEL4CR_25_0, MSEL4CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) MSEL4CR_24_0, MSEL4CR_24_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) MSEL4CR_23_0, MSEL4CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) MSEL4CR_22_0, MSEL4CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) MSEL4CR_21_0, MSEL4CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) MSEL4CR_20_0, MSEL4CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) MSEL4CR_19_0, MSEL4CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) MSEL4CR_18_0, MSEL4CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) MSEL4CR_17_0, MSEL4CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) MSEL4CR_16_0, MSEL4CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) MSEL4CR_15_0, MSEL4CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) MSEL4CR_14_0, MSEL4CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) MSEL4CR_13_0, MSEL4CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) MSEL4CR_12_0, MSEL4CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) MSEL4CR_11_0, MSEL4CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) MSEL4CR_10_0, MSEL4CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) MSEL4CR_09_0, MSEL4CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) MSEL4CR_07_0, MSEL4CR_07_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) MSEL4CR_04_0, MSEL4CR_04_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) MSEL4CR_01_0, MSEL4CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) MSEL5CR_31_0, MSEL5CR_31_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) MSEL5CR_30_0, MSEL5CR_30_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) MSEL5CR_29_0, MSEL5CR_29_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) MSEL5CR_28_0, MSEL5CR_28_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) MSEL5CR_27_0, MSEL5CR_27_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) MSEL5CR_26_0, MSEL5CR_26_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) MSEL5CR_25_0, MSEL5CR_25_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) MSEL5CR_24_0, MSEL5CR_24_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) MSEL5CR_23_0, MSEL5CR_23_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) MSEL5CR_22_0, MSEL5CR_22_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) MSEL5CR_21_0, MSEL5CR_21_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) MSEL5CR_20_0, MSEL5CR_20_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) MSEL5CR_19_0, MSEL5CR_19_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) MSEL5CR_18_0, MSEL5CR_18_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) MSEL5CR_17_0, MSEL5CR_17_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) MSEL5CR_16_0, MSEL5CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) MSEL5CR_15_0, MSEL5CR_15_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) MSEL5CR_14_0, MSEL5CR_14_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) MSEL5CR_13_0, MSEL5CR_13_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) MSEL5CR_12_0, MSEL5CR_12_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) MSEL5CR_11_0, MSEL5CR_11_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) MSEL5CR_10_0, MSEL5CR_10_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) MSEL5CR_09_0, MSEL5CR_09_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) MSEL5CR_08_0, MSEL5CR_08_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) MSEL5CR_07_0, MSEL5CR_07_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) MSEL5CR_06_0, MSEL5CR_06_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) MSEL8CR_16_0, MSEL8CR_16_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) MSEL8CR_01_0, MSEL8CR_01_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) MSEL8CR_00_0, MSEL8CR_00_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) static const struct pinmux_data_reg pinmux_data_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) 0, 0, 0, PORT40_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) 0, 0, PORT85_DATA, PORT84_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) 0, 0, 0, PORT308_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) 0, 0, PORT329_DATA, PORT328_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) static const struct pinmux_irq pinmux_irqs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) PINMUX_IRQ(0), /* IRQ0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) PINMUX_IRQ(1), /* IRQ1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) PINMUX_IRQ(2), /* IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) PINMUX_IRQ(3), /* IRQ3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) PINMUX_IRQ(4), /* IRQ4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) PINMUX_IRQ(5), /* IRQ5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) PINMUX_IRQ(6), /* IRQ6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) PINMUX_IRQ(7), /* IRQ7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) PINMUX_IRQ(8), /* IRQ8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) PINMUX_IRQ(9), /* IRQ9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) PINMUX_IRQ(10), /* IRQ10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) PINMUX_IRQ(11), /* IRQ11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) PINMUX_IRQ(12), /* IRQ12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) PINMUX_IRQ(13), /* IRQ13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) PINMUX_IRQ(14), /* IRQ14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) PINMUX_IRQ(15), /* IRQ15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) PINMUX_IRQ(320), /* IRQ16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) PINMUX_IRQ(321), /* IRQ17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) PINMUX_IRQ(85), /* IRQ18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) PINMUX_IRQ(84), /* IRQ19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) PINMUX_IRQ(160), /* IRQ20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) PINMUX_IRQ(161), /* IRQ21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) PINMUX_IRQ(162), /* IRQ22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) PINMUX_IRQ(163), /* IRQ23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) PINMUX_IRQ(175), /* IRQ24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) PINMUX_IRQ(176), /* IRQ25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) PINMUX_IRQ(177), /* IRQ26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) PINMUX_IRQ(178), /* IRQ27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) PINMUX_IRQ(322), /* IRQ28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) PINMUX_IRQ(323), /* IRQ29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) PINMUX_IRQ(324), /* IRQ30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) PINMUX_IRQ(192), /* IRQ31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) PINMUX_IRQ(193), /* IRQ32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) PINMUX_IRQ(194), /* IRQ33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) PINMUX_IRQ(195), /* IRQ34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) PINMUX_IRQ(196), /* IRQ35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) PINMUX_IRQ(197), /* IRQ36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) PINMUX_IRQ(198), /* IRQ37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) PINMUX_IRQ(199), /* IRQ38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) PINMUX_IRQ(200), /* IRQ39 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) PINMUX_IRQ(66), /* IRQ40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) PINMUX_IRQ(102), /* IRQ41 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) PINMUX_IRQ(103), /* IRQ42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) PINMUX_IRQ(109), /* IRQ43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) PINMUX_IRQ(110), /* IRQ44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) PINMUX_IRQ(111), /* IRQ45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) PINMUX_IRQ(112), /* IRQ46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) PINMUX_IRQ(113), /* IRQ47 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) PINMUX_IRQ(114), /* IRQ48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) PINMUX_IRQ(115), /* IRQ49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) PINMUX_IRQ(301), /* IRQ50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) PINMUX_IRQ(290), /* IRQ51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) PINMUX_IRQ(296), /* IRQ52 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) PINMUX_IRQ(325), /* IRQ53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) PINMUX_IRQ(326), /* IRQ54 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) PINMUX_IRQ(327), /* IRQ55 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) PINMUX_IRQ(328), /* IRQ56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) PINMUX_IRQ(329), /* IRQ57 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define PORTCR_PULMD_OFF (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define PORTCR_PULMD_DOWN (2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) #define PORTCR_PULMD_UP (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) #define PORTCR_PULMD_MASK (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static const unsigned int r8a73a4_portcr_offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) 0x00000000, 0x00001000, 0x00000000, 0x00001000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) 0x00001000, 0x00002000, 0x00002000, 0x00002000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) 0x00002000, 0x00003000, 0x00003000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) switch (ioread8(addr) & PORTCR_PULMD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) case PORTCR_PULMD_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return PIN_CONFIG_BIAS_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) case PORTCR_PULMD_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return PIN_CONFIG_BIAS_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) case PORTCR_PULMD_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) return PIN_CONFIG_BIAS_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) unsigned int bias)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) void __iomem *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) value = ioread8(addr) & ~PORTCR_PULMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) switch (bias) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) value |= PORTCR_PULMD_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) value |= PORTCR_PULMD_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) iowrite8(value, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .get_bias = r8a73a4_pinmux_get_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .set_bias = r8a73a4_pinmux_set_bias,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .name = "r8a73a4_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .ops = &r8a73a4_pfc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .data_regs = pinmux_data_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .gpio_irq = pinmux_irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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