^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Pin Function Controller Support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Niklas Söderlund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "sh_pfc.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CPU_ALL_PORT(fn, pfx, sfx) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PORT_10(100, fn, pfx##10, sfx), PORT_10(110, fn, pfx##11, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PORT_10(120, fn, pfx##12, sfx), PORT_10(130, fn, pfx##13, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PORT_10(140, fn, pfx##14, sfx), PORT_1(150, fn, pfx##150, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PORT_1(151, fn, pfx##151, sfx), PORT_1(152, fn, pfx##152, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PORT_1(153, fn, pfx##153, sfx), PORT_1(154, fn, pfx##154, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PORT_1(155, fn, pfx##155, sfx), PORT_1(156, fn, pfx##156, sfx), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PORT_1(157, fn, pfx##157, sfx), PORT_1(158, fn, pfx##158, sfx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CPU_ALL_NOGP(fn) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PIN_NOGP(LCD3_B2, "B15", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PIN_NOGP(LCD3_B3, "C15", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PIN_NOGP(LCD3_B4, "D15", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PIN_NOGP(LCD3_B5, "B14", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PIN_NOGP(LCD3_B6, "C14", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PIN_NOGP(LCD3_B7, "D14", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PIN_NOGP(LCD3_G2, "B17", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PIN_NOGP(LCD3_G3, "C17", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PIN_NOGP(LCD3_G4, "D17", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PIN_NOGP(LCD3_G5, "B16", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PIN_NOGP(LCD3_G6, "C16", fn), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PIN_NOGP(LCD3_G7, "D16", fn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINMUX_RESERVED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINMUX_DATA_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PORT_ALL(DATA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINMUX_DATA_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINMUX_FUNCTION_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PORT_ALL(FN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) FN_LCD3_1_0_PORT18, FN_LCD3_1_0_PORT20, FN_LCD3_1_0_PORT21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) FN_LCD3_1_0_PORT22, FN_LCD3_1_0_PORT23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) FN_JT_SEL, FN_ERR_RST_REQB, FN_REF_CLKO, FN_EXT_CLKI, FN_LCD3_PXCLKB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) FN_LCD3_9_8_PORT38, FN_LCD3_9_8_PORT39, FN_LCD3_11_10_PORT40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) FN_LCD3_11_10_PORT41, FN_LCD3_11_10_PORT42, FN_LCD3_11_10_PORT43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) FN_IIC_1_0_PORT46, FN_IIC_1_0_PORT47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) FN_LCD3_R0, FN_LCD3_R1, FN_LCD3_R2, FN_LCD3_R3, FN_LCD3_R4, FN_LCD3_R5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) FN_IIC0_SCL, FN_IIC0_SDA, FN_SD_CKI, FN_SDI0_CKO, FN_SDI0_CKI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) FN_SDI0_CMD, FN_SDI0_DATA0, FN_SDI0_DATA1, FN_SDI0_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) FN_SDI0_DATA3, FN_SDI0_DATA4, FN_SDI0_DATA5, FN_SDI0_DATA6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) FN_SDI0_DATA7, FN_SDI1_CKO, FN_SDI1_CKI, FN_SDI1_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) FN_AB_1_0_PORT71, FN_AB_1_0_PORT72, FN_AB_1_0_PORT73,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) FN_AB_1_0_PORT74, FN_AB_1_0_PORT75, FN_AB_1_0_PORT76,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) FN_AB_1_0_PORT77, FN_AB_1_0_PORT78, FN_AB_1_0_PORT79,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) FN_AB_1_0_PORT80, FN_AB_1_0_PORT81, FN_AB_1_0_PORT82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) FN_AB_1_0_PORT83, FN_AB_1_0_PORT84, FN_AB_3_2_PORT85,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) FN_AB_3_2_PORT86, FN_AB_3_2_PORT87, FN_AB_3_2_PORT88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) FN_AB_5_4_PORT89, FN_AB_5_4_PORT90, FN_AB_7_6_PORT91,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) FN_AB_7_6_PORT92, FN_AB_1_0_PORT93, FN_AB_1_0_PORT94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) FN_AB_1_0_PORT95,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) FN_SDI1_DATA0, FN_SDI1_DATA1, FN_SDI1_DATA2, FN_SDI1_DATA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) FN_AB_CLK, FN_AB_CSB0, FN_AB_CSB1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) FN_AB_13_12_PORT104, FN_AB_13_12_PORT103, FN_AB_11_10_PORT102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) FN_AB_11_10_PORT101, FN_AB_11_10_PORT100, FN_AB_9_8_PORT99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) FN_AB_9_8_PORT98, FN_AB_9_8_PORT97,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) FN_USI_1_0_PORT109, FN_USI_1_0_PORT110, FN_USI_1_0_PORT111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) FN_USI_1_0_PORT112, FN_USI_3_2_PORT113, FN_USI_3_2_PORT114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) FN_USI_5_4_PORT115, FN_USI_5_4_PORT116, FN_USI_5_4_PORT117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) FN_USI_5_4_PORT118, FN_USI_7_6_PORT119, FN_USI_9_8_PORT120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) FN_USI_9_8_PORT121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) FN_AB_A20, FN_USI0_CS1, FN_USI0_CS2, FN_USI1_DI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) FN_USI1_DO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) FN_NTSC_CLK, FN_NTSC_DATA0, FN_NTSC_DATA1, FN_NTSC_DATA2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) FN_NTSC_DATA3, FN_NTSC_DATA4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* GPRS4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) FN_HSI_1_0_PORT143, FN_HSI_1_0_PORT144, FN_HSI_1_0_PORT145,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) FN_HSI_1_0_PORT146, FN_HSI_1_0_PORT147, FN_HSI_1_0_PORT148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) FN_HSI_1_0_PORT149, FN_HSI_1_0_PORT150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) FN_UART_1_0_PORT157, FN_UART_1_0_PORT158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) FN_NTSC_DATA5, FN_NTSC_DATA6, FN_NTSC_DATA7, FN_CAM_CLKO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) FN_CAM_CLKI, FN_CAM_VS, FN_CAM_HS, FN_CAM_YUV0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) FN_CAM_YUV1, FN_CAM_YUV2, FN_CAM_YUV3, FN_CAM_YUV4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) FN_CAM_YUV5, FN_CAM_YUV6, FN_CAM_YUV7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) FN_JT_TDO, FN_JT_TDOEN, FN_LOWPWR, FN_USB_VBUS, FN_UART1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) FN_UART1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* CHG_PINSEL_LCD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) FN_SEL_LCD3_9_8_00, FN_SEL_LCD3_9_8_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01, FN_SEL_LCD3_11_10_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* CHG_PINSEL_IIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* CHG_PINSEL_AB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) FN_SEL_AB_1_0_00, FN_SEL_AB_1_0_10, FN_SEL_AB_3_2_00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) FN_SEL_AB_3_2_01, FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01, FN_SEL_AB_5_4_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) FN_SEL_AB_5_4_11, FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) FN_SEL_AB_7_6_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) FN_SEL_AB_11_10_00, FN_SEL_AB_11_10_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) FN_SEL_AB_13_12_00, FN_SEL_AB_13_12_10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* CHG_PINSEL_USI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* CHG_PINSEL_HSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* CHG_PINSEL_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINMUX_FUNCTION_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINMUX_MARK_BEGIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) JT_SEL_MARK, ERR_RST_REQB_MARK, REF_CLKO_MARK, EXT_CLKI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) LCD3_PXCLKB_MARK, SD_CKI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK, LCD3_R4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) LCD3_R5_MARK, IIC0_SCL_MARK, IIC0_SDA_MARK, SDI0_CKO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) SDI0_CKI_MARK, SDI0_CMD_MARK, SDI0_DATA0_MARK, SDI0_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) SDI0_DATA2_MARK, SDI0_DATA3_MARK, SDI0_DATA4_MARK, SDI0_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) SDI0_DATA6_MARK, SDI0_DATA7_MARK, SDI1_CKO_MARK, SDI1_CKI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) SDI1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) AB_CLK_MARK, AB_CSB0_MARK, AB_CSB1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) AB_A20_MARK, USI0_CS1_MARK, USI0_CS2_MARK, USI1_DI_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) USI1_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) NTSC_CLK_MARK, NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) NTSC_DATA3_MARK, NTSC_DATA4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK, CAM_CLKO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK, CAM_YUV0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK, CAM_YUV4_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) JT_TDO_MARK, JT_TDOEN_MARK, USB_VBUS_MARK, LOWPWR_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) UART1_RX_MARK, UART1_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* CHG_PINSEL_LCD3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) LCD3_PXCLK_MARK, LCD3_CLK_I_MARK, LCD3_HS_MARK, LCD3_VS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) LCD3_DE_MARK, LCD3_R6_MARK, LCD3_R7_MARK, LCD3_G0_MARK, LCD3_G1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) LCD3_G2_MARK, LCD3_G3_MARK, LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) LCD3_G7_MARK, LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) YUV3_CLK_O_MARK, YUV3_CLK_I_MARK, YUV3_HS_MARK, YUV3_VS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) YUV3_DE_MARK, YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK, YUV3_D8_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK, YUV3_D12_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TP33_CLK_MARK, TP33_CTRL_MARK, TP33_DATA0_MARK, TP33_DATA1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) TP33_DATA2_MARK, TP33_DATA3_MARK, TP33_DATA4_MARK, TP33_DATA5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) TP33_DATA6_MARK, TP33_DATA7_MARK, TP33_DATA8_MARK, TP33_DATA9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) TP33_DATA10_MARK, TP33_DATA11_MARK, TP33_DATA12_MARK, TP33_DATA13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TP33_DATA14_MARK, TP33_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* CHG_PINSEL_IIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IIC1_SCL_MARK, IIC1_SDA_MARK, UART3_RX_MARK, UART3_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* CHG_PINSEL_AB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) AB_CSB2_MARK, AB_CSB3_MARK, AB_RDB_MARK, AB_WRB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) AB_WAIT_MARK, AB_ADV_MARK, AB_AD0_MARK, AB_AD1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) AB_AD2_MARK, AB_AD3_MARK, AB_AD4_MARK, AB_AD5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) AB_AD6_MARK, AB_AD7_MARK, AB_AD8_MARK, AB_AD9_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) AB_AD10_MARK, AB_AD11_MARK, AB_AD12_MARK, AB_AD13_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) AB_AD14_MARK, AB_AD15_MARK, AB_A17_MARK, AB_A18_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) AB_A19_MARK, AB_A21_MARK, AB_A22_MARK, AB_A23_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) AB_A24_MARK, AB_A25_MARK, AB_A26_MARK, AB_A27_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) AB_A28_MARK, AB_BEN0_MARK, AB_BEN1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DTV_DATA_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) SDI2_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CF_IOWRB_MARK, CF_IORDY_MARK, CF_RESET_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) CF_A00_MARK, CF_A01_MARK, CF_A02_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK, CF_CDB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) USI5_CS0_A_MARK, USI5_CS1_A_MARK, USI5_CS2_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* CHG_PINSEL_USI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) USI0_CS3_MARK, USI0_CS4_MARK, USI0_CS5_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) USI0_CS6_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) USI2_CS0_MARK, USI2_CS1_MARK, USI2_CS2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) USI3_CS0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) USI4_CS0_MARK, USI4_CS1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PWM0_MARK, PWM1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DTV_DATA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* CHG_PINSEL_HSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) USI5_CLK_B_MARK, USI5_DO_B_MARK, USI5_CS0_B_MARK, USI5_CS1_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) USI5_CS2_B_MARK, USI5_CS3_B_MARK, USI5_CS4_B_MARK, USI5_DI_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* CHG_PINSEL_UART */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) UART1_CTSB_MARK, UART1_RTSB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) UART2_RX_MARK, UART2_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINMUX_MARK_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Pins not associated with a GPIO port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PORT_ASSIGN_LAST(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* Expand to a list of sh_pfc_pin entries (named PORT#).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * NOTE: No config are recorded since the driver do not handle pinconf. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define __PIN_CFG(pn, pfx, sfx) SH_PFC_PIN_CFG(pfx, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PINMUX_EMEV_GPIO_ALL() CPU_ALL_PORT(__PIN_CFG, , unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct sh_pfc_pin pinmux_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINMUX_EMEV_GPIO_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINMUX_NOGP_ALL(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Expand to a list of name_DATA, name_FN marks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define __PORT_DATA(pn, pfx, sfx) PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define PINMUX_EMEV_DATA_ALL() CPU_ALL_PORT(__PORT_DATA, , unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const u16 pinmux_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINMUX_EMEV_DATA_ALL(), /* PINMUX_DATA(PORTN_DATA, PORTN_FN), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* GPSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* V9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINMUX_SINGLE(JT_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* U9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINMUX_SINGLE(ERR_RST_REQB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* V8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINMUX_SINGLE(REF_CLKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* U8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINMUX_SINGLE(EXT_CLKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* B22*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, LCD3_PXCLK, SEL_LCD3_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINMUX_IPSR_NOFN(LCD3_1_0_PORT18, YUV3_CLK_O, SEL_LCD3_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* C21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINMUX_SINGLE(LCD3_PXCLKB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* A21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, LCD3_CLK_I, SEL_LCD3_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINMUX_IPSR_NOFN(LCD3_1_0_PORT20, YUV3_CLK_I, SEL_LCD3_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* B21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, LCD3_HS, SEL_LCD3_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINMUX_IPSR_NOFN(LCD3_1_0_PORT21, YUV3_HS, SEL_LCD3_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* C20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, LCD3_VS, SEL_LCD3_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINMUX_IPSR_NOFN(LCD3_1_0_PORT22, YUV3_VS, SEL_LCD3_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* D19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, LCD3_DE, SEL_LCD3_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINMUX_IPSR_NOFN(LCD3_1_0_PORT23, YUV3_DE, SEL_LCD3_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* GPSR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINMUX_SINGLE(LCD3_R0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* B20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINMUX_SINGLE(LCD3_R1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* A19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINMUX_SINGLE(LCD3_R2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* B19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINMUX_SINGLE(LCD3_R3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* C19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINMUX_SINGLE(LCD3_R4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* B18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINMUX_SINGLE(LCD3_R5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* C18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, LCD3_R6, SEL_LCD3_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINMUX_IPSR_NOFN(LCD3_9_8_PORT38, TP33_CLK, SEL_LCD3_9_8_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* D18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, LCD3_R7, SEL_LCD3_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINMUX_IPSR_NOFN(LCD3_9_8_PORT39, TP33_CTRL, SEL_LCD3_9_8_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* A18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, LCD3_G0, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, YUV3_D0, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINMUX_IPSR_NOFN(LCD3_11_10_PORT40, TP33_DATA0, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* A17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, LCD3_G1, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, YUV3_D1, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINMUX_IPSR_NOFN(LCD3_11_10_PORT41, TP33_DATA1, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* B17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINMUX_DATA(LCD3_G2_MARK, FN_SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINMUX_DATA(YUV3_D2_MARK, FN_SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINMUX_DATA(TP33_DATA2_MARK, FN_SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* C17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINMUX_DATA(LCD3_G3_MARK, FN_SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINMUX_DATA(YUV3_D3_MARK, FN_SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINMUX_DATA(TP33_DATA3_MARK, FN_SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* D17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINMUX_DATA(LCD3_G4_MARK, FN_SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINMUX_DATA(YUV3_D4_MARK, FN_SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINMUX_DATA(TP33_DATA4_MARK, FN_SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* B16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINMUX_DATA(LCD3_G5_MARK, FN_SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINMUX_DATA(YUV3_D5_MARK, FN_SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINMUX_DATA(TP33_DATA5_MARK, FN_SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* C16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINMUX_DATA(LCD3_G6_MARK, FN_SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINMUX_DATA(YUV3_D6_MARK, FN_SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINMUX_DATA(TP33_DATA6_MARK, FN_SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* D16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINMUX_DATA(LCD3_G7_MARK, FN_SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINMUX_DATA(YUV3_D7_MARK, FN_SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINMUX_DATA(TP33_DATA7_MARK, FN_SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, LCD3_B0, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, YUV3_D8, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINMUX_IPSR_NOFN(LCD3_11_10_PORT42, TP33_DATA8, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* A15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B1, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D9, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA9, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* B15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B2, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D10, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA10, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* C15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B3, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D11, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA11, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* D15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B4, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D12, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA12, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* B14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B5, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D13, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA13, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* C14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B6, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D14, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA14, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* D14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, LCD3_B7, SEL_LCD3_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, YUV3_D15, SEL_LCD3_11_10_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINMUX_IPSR_NOFN(LCD3_11_10_PORT43, TP33_DATA15, SEL_LCD3_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* AA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINMUX_SINGLE(IIC0_SCL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* AA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINMUX_SINGLE(IIC0_SDA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Y9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINMUX_IPSR_NOFN(IIC_1_0_PORT46, IIC1_SCL, SEL_IIC_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINMUX_IPSR_NOFN(IIC_1_0_PORT46, UART3_RX, SEL_IIC_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Y8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINMUX_IPSR_NOFN(IIC_1_0_PORT47, IIC1_SDA, SEL_IIC_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINMUX_IPSR_NOFN(IIC_1_0_PORT47, UART3_TX, SEL_IIC_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* AC19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINMUX_SINGLE(SD_CKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* AB18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINMUX_SINGLE(SDI0_CKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* AC18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINMUX_SINGLE(SDI0_CKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Y12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINMUX_SINGLE(SDI0_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* AA13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINMUX_SINGLE(SDI0_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Y13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINMUX_SINGLE(SDI0_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* AA14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINMUX_SINGLE(SDI0_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Y14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINMUX_SINGLE(SDI0_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* AA15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINMUX_SINGLE(SDI0_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Y15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINMUX_SINGLE(SDI0_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* AA16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINMUX_SINGLE(SDI0_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Y16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINMUX_SINGLE(SDI0_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* AB22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINMUX_SINGLE(SDI1_CKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* AA23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINMUX_SINGLE(SDI1_CKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* AC21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINMUX_SINGLE(SDI1_CMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* GPSR2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* AB21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINMUX_SINGLE(SDI1_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* AB20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINMUX_SINGLE(SDI1_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* AB19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINMUX_SINGLE(SDI1_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* AA19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINMUX_SINGLE(SDI1_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* J23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINMUX_SINGLE(AB_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* D21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINMUX_SINGLE(AB_CSB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* E21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINMUX_SINGLE(AB_CSB1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* F20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINMUX_IPSR_NOFN(AB_1_0_PORT71, AB_CSB2, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINMUX_IPSR_NOFN(AB_1_0_PORT71, CF_CSB0, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* G20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINMUX_IPSR_NOFN(AB_1_0_PORT72, AB_CSB3, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINMUX_IPSR_NOFN(AB_1_0_PORT72, CF_CSB1, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* J20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINMUX_IPSR_NOFN(AB_1_0_PORT73, AB_RDB, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINMUX_IPSR_NOFN(AB_1_0_PORT73, CF_IORDB, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /* H20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINMUX_IPSR_NOFN(AB_1_0_PORT74, AB_WRB, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINMUX_IPSR_NOFN(AB_1_0_PORT74, CF_IOWRB, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* L20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINMUX_IPSR_NOFN(AB_1_0_PORT75, AB_WAIT, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINMUX_IPSR_NOFN(AB_1_0_PORT75, CF_IORDY, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* K20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINMUX_IPSR_NOFN(AB_1_0_PORT76, AB_ADV, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINMUX_IPSR_NOFN(AB_1_0_PORT76, CF_RESET, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* C23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINMUX_IPSR_NOFN(AB_1_0_PORT77, AB_AD0, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINMUX_IPSR_NOFN(AB_1_0_PORT77, CF_D00, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* C22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINMUX_IPSR_NOFN(AB_1_0_PORT78, AB_AD1, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINMUX_IPSR_NOFN(AB_1_0_PORT78, CF_D01, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* D23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINMUX_IPSR_NOFN(AB_1_0_PORT79, AB_AD2, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINMUX_IPSR_NOFN(AB_1_0_PORT79, CF_D02, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* D22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINMUX_IPSR_NOFN(AB_1_0_PORT80, AB_AD3, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINMUX_IPSR_NOFN(AB_1_0_PORT80, CF_D03, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* E23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINMUX_IPSR_NOFN(AB_1_0_PORT81, AB_AD4, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINMUX_IPSR_NOFN(AB_1_0_PORT81, CF_D04, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* E22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINMUX_IPSR_NOFN(AB_1_0_PORT82, AB_AD5, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINMUX_IPSR_NOFN(AB_1_0_PORT82, CF_D05, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* F23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINMUX_IPSR_NOFN(AB_1_0_PORT83, AB_AD6, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINMUX_IPSR_NOFN(AB_1_0_PORT83, CF_D06, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* F22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINMUX_IPSR_NOFN(AB_1_0_PORT84, AB_AD7, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINMUX_IPSR_NOFN(AB_1_0_PORT84, CF_D07, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* F21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINMUX_IPSR_NOFN(AB_3_2_PORT85, AB_AD8, SEL_AB_3_2_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINMUX_IPSR_NOFN(AB_3_2_PORT85, DTV_BCLK_A, SEL_AB_3_2_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINMUX_IPSR_NOFN(AB_3_2_PORT85, CF_D08, SEL_AB_3_2_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINMUX_IPSR_NOFN(AB_3_2_PORT85, USI5_CLK_A, SEL_AB_3_2_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* G23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINMUX_IPSR_NOFN(AB_3_2_PORT86, AB_AD9, SEL_AB_3_2_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINMUX_IPSR_NOFN(AB_3_2_PORT86, DTV_PSYNC_A, SEL_AB_3_2_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINMUX_IPSR_NOFN(AB_3_2_PORT86, CF_D09, SEL_AB_3_2_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINMUX_IPSR_NOFN(AB_3_2_PORT86, USI5_DI_A, SEL_AB_3_2_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* G22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINMUX_IPSR_NOFN(AB_3_2_PORT87, AB_AD10, SEL_AB_3_2_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINMUX_IPSR_NOFN(AB_3_2_PORT87, DTV_VALID_A, SEL_AB_3_2_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINMUX_IPSR_NOFN(AB_3_2_PORT87, CF_D10, SEL_AB_3_2_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINMUX_IPSR_NOFN(AB_3_2_PORT87, USI5_DO_A, SEL_AB_3_2_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* G21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINMUX_IPSR_NOFN(AB_3_2_PORT88, AB_AD11, SEL_AB_3_2_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINMUX_IPSR_NOFN(AB_3_2_PORT88, DTV_DATA_A, SEL_AB_3_2_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINMUX_IPSR_NOFN(AB_3_2_PORT88, CF_D11, SEL_AB_3_2_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINMUX_IPSR_NOFN(AB_3_2_PORT88, USI5_CS0_A, SEL_AB_3_2_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* H23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINMUX_IPSR_NOFN(AB_5_4_PORT89, AB_AD12, SEL_AB_5_4_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINMUX_IPSR_NOFN(AB_5_4_PORT89, SDI2_DATA0, SEL_AB_5_4_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINMUX_IPSR_NOFN(AB_5_4_PORT89, CF_D12, SEL_AB_5_4_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINMUX_IPSR_NOFN(AB_5_4_PORT89, USI5_CS1_A, SEL_AB_5_4_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* H22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINMUX_IPSR_NOFN(AB_5_4_PORT90, AB_AD13, SEL_AB_5_4_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINMUX_IPSR_NOFN(AB_5_4_PORT90, SDI2_DATA1, SEL_AB_5_4_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINMUX_IPSR_NOFN(AB_5_4_PORT90, CF_D13, SEL_AB_5_4_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINMUX_IPSR_NOFN(AB_5_4_PORT90, USI5_CS2_A, SEL_AB_5_4_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* H21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINMUX_IPSR_NOFN(AB_7_6_PORT91, AB_AD14, SEL_AB_7_6_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINMUX_IPSR_NOFN(AB_7_6_PORT91, SDI2_DATA2, SEL_AB_7_6_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINMUX_IPSR_NOFN(AB_7_6_PORT91, CF_D14, SEL_AB_7_6_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* J22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINMUX_IPSR_NOFN(AB_7_6_PORT92, AB_AD15, SEL_AB_7_6_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINMUX_IPSR_NOFN(AB_7_6_PORT92, SDI2_DATA3, SEL_AB_7_6_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINMUX_IPSR_NOFN(AB_7_6_PORT92, CF_D15, SEL_AB_7_6_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* J21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINMUX_IPSR_NOFN(AB_1_0_PORT93, AB_A17, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINMUX_IPSR_NOFN(AB_1_0_PORT93, CF_A00, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* K21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINMUX_IPSR_NOFN(AB_1_0_PORT94, AB_A18, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINMUX_IPSR_NOFN(AB_1_0_PORT94, CF_A01, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* L21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINMUX_IPSR_NOFN(AB_1_0_PORT95, AB_A19, SEL_AB_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINMUX_IPSR_NOFN(AB_1_0_PORT95, CF_A02, SEL_AB_1_0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* GPSR3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* M21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINMUX_SINGLE(AB_A20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* N21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINMUX_IPSR_NOFN(AB_9_8_PORT97, AB_A21, SEL_AB_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINMUX_IPSR_NOFN(AB_9_8_PORT97, SDI2_CKO, SEL_AB_9_8_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINMUX_IPSR_NOFN(AB_9_8_PORT97, CF_INTRQ, SEL_AB_9_8_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* M20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINMUX_IPSR_NOFN(AB_9_8_PORT98, AB_A22, SEL_AB_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINMUX_IPSR_NOFN(AB_9_8_PORT98, SDI2_CKI, SEL_AB_9_8_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* N20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINMUX_IPSR_NOFN(AB_9_8_PORT99, AB_A23, SEL_AB_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINMUX_IPSR_NOFN(AB_9_8_PORT99, SDI2_CMD, SEL_AB_9_8_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /* L18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINMUX_IPSR_NOFN(AB_11_10_PORT100, AB_A24, SEL_AB_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINMUX_IPSR_NOFN(AB_11_10_PORT100, CF_INPACKB, SEL_AB_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* M18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINMUX_IPSR_NOFN(AB_11_10_PORT101, AB_A25, SEL_AB_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINMUX_IPSR_NOFN(AB_11_10_PORT101, CF_CDB1, SEL_AB_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* N18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINMUX_IPSR_NOFN(AB_11_10_PORT102, AB_A26, SEL_AB_11_10_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINMUX_IPSR_NOFN(AB_11_10_PORT102, CF_CDB2, SEL_AB_11_10_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* L17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_A27, SEL_AB_13_12_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINMUX_IPSR_NOFN(AB_13_12_PORT103, AB_BEN0, SEL_AB_13_12_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* M17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_A28, SEL_AB_13_12_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINMUX_IPSR_NOFN(AB_13_12_PORT104, AB_BEN1, SEL_AB_13_12_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) /* B8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINMUX_SINGLE(USI0_CS1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* B9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINMUX_SINGLE(USI0_CS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* C10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINMUX_SINGLE(USI1_DI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINMUX_SINGLE(USI1_DO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* AB5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINMUX_IPSR_NOFN(USI_1_0_PORT109, USI2_CLK, SEL_USI_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINMUX_IPSR_NOFN(USI_1_0_PORT109, DTV_BCLK_B, SEL_USI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* AA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINMUX_IPSR_NOFN(USI_1_0_PORT110, USI2_DI, SEL_USI_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINMUX_IPSR_NOFN(USI_1_0_PORT110, DTV_PSYNC_B, SEL_USI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* AA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINMUX_IPSR_NOFN(USI_1_0_PORT111, USI2_DO, SEL_USI_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINMUX_IPSR_NOFN(USI_1_0_PORT111, DTV_VALID_B, SEL_USI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Y7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINMUX_IPSR_NOFN(USI_1_0_PORT112, USI2_CS0, SEL_USI_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINMUX_IPSR_NOFN(USI_1_0_PORT112, DTV_DATA_B, SEL_USI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* AA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI2_CS1, SEL_USI_3_2_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINMUX_IPSR_NOFN(USI_3_2_PORT113, USI4_CS0, SEL_USI_3_2_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Y6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI2_CS2, SEL_USI_3_2_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINMUX_IPSR_NOFN(USI_3_2_PORT114, USI4_CS1, SEL_USI_3_2_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) /* AC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI3_CLK, SEL_USI_5_4_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINMUX_IPSR_NOFN(USI_5_4_PORT115, USI0_CS3, SEL_USI_5_4_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* AC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI3_DI, SEL_USI_5_4_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINMUX_IPSR_NOFN(USI_5_4_PORT116, USI0_CS4, SEL_USI_5_4_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI3_DO, SEL_USI_5_4_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINMUX_IPSR_NOFN(USI_5_4_PORT117, USI0_CS5, SEL_USI_5_4_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* AB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI3_CS0, SEL_USI_5_4_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINMUX_IPSR_NOFN(USI_5_4_PORT118, USI0_CS6, SEL_USI_5_4_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* AB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINMUX_IPSR_NOFN(USI_7_6_PORT119, USI4_CLK, SEL_USI_7_6_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* AA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINMUX_IPSR_NOFN(USI_9_8_PORT120, PWM0, SEL_USI_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINMUX_IPSR_NOFN(USI_9_8_PORT120, USI4_DI, SEL_USI_9_8_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Y5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINMUX_IPSR_NOFN(USI_9_8_PORT121, PWM1, SEL_USI_9_8_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINMUX_IPSR_NOFN(USI_9_8_PORT121, USI4_DO, SEL_USI_9_8_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* V20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINMUX_SINGLE(NTSC_CLK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* P20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINMUX_SINGLE(NTSC_DATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* P18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINMUX_SINGLE(NTSC_DATA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* R20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINMUX_SINGLE(NTSC_DATA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* R18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINMUX_SINGLE(NTSC_DATA3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* T20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINMUX_SINGLE(NTSC_DATA4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* GPRS3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* T18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINMUX_SINGLE(NTSC_DATA5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* U20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINMUX_SINGLE(NTSC_DATA6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* U18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINMUX_SINGLE(NTSC_DATA7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* W23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINMUX_SINGLE(CAM_CLKO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Y23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINMUX_SINGLE(CAM_CLKI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* W22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINMUX_SINGLE(CAM_VS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* V21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINMUX_SINGLE(CAM_HS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* T21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINMUX_SINGLE(CAM_YUV0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* T22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINMUX_SINGLE(CAM_YUV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* T23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINMUX_SINGLE(CAM_YUV2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* U21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINMUX_SINGLE(CAM_YUV3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* U22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINMUX_SINGLE(CAM_YUV4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /* U23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINMUX_SINGLE(CAM_YUV5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* V22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINMUX_SINGLE(CAM_YUV6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* V23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINMUX_SINGLE(CAM_YUV7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* K22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINMUX_IPSR_NOFN(HSI_1_0_PORT143, USI5_CLK_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* K23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINMUX_IPSR_NOFN(HSI_1_0_PORT144, USI5_DO_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* L23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINMUX_IPSR_NOFN(HSI_1_0_PORT145, USI5_CS0_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* L22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINMUX_IPSR_NOFN(HSI_1_0_PORT146, USI5_CS1_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* N22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINMUX_IPSR_NOFN(HSI_1_0_PORT147, USI5_CS2_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* N23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINMUX_IPSR_NOFN(HSI_1_0_PORT148, USI5_CS3_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* M23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINMUX_IPSR_NOFN(HSI_1_0_PORT149, USI5_CS4_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* M22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINMUX_IPSR_NOFN(HSI_1_0_PORT150, USI5_DI_B, SEL_HSI_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINMUX_SINGLE(JT_TDO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* F13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINMUX_SINGLE(JT_TDOEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* AA12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINMUX_SINGLE(USB_VBUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /* A12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINMUX_SINGLE(LOWPWR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* Y11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) PINMUX_SINGLE(UART1_RX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Y10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) PINMUX_SINGLE(UART1_TX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* AA10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART1_CTSB, SEL_UART_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PINMUX_IPSR_NOFN(UART_1_0_PORT157, UART2_RX, SEL_UART_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* AB10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART1_RTSB, SEL_UART_1_0_00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) PINMUX_IPSR_NOFN(UART_1_0_PORT158, UART2_TX, SEL_UART_1_0_01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define EMEV_MUX_PIN(name, pin, mark) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const unsigned int name##_pins[] = { pin }; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const unsigned int name##_mux[] = { mark##_MARK }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* = [ System ] =========== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) EMEV_MUX_PIN(err_rst_reqb, 3, ERR_RST_REQB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) EMEV_MUX_PIN(ref_clko, 4, REF_CLKO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) EMEV_MUX_PIN(ext_clki, 5, EXT_CLKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) EMEV_MUX_PIN(lowpwr, 154, LOWPWR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* = [ External Memory] === */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const unsigned int ab_main_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* AB_RDB, AB_WRB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 73, 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* AB_AD[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 81, 82, 83, 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 85, 86, 87, 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 89, 90, 91, 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const unsigned int ab_main_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) AB_RDB_MARK, AB_WRB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) AB_AD0_MARK, AB_AD1_MARK, AB_AD2_MARK, AB_AD3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) AB_AD4_MARK, AB_AD5_MARK, AB_AD6_MARK, AB_AD7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) AB_AD8_MARK, AB_AD9_MARK, AB_AD10_MARK, AB_AD11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) AB_AD12_MARK, AB_AD13_MARK, AB_AD14_MARK, AB_AD15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) EMEV_MUX_PIN(ab_clk, 68, AB_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) EMEV_MUX_PIN(ab_csb0, 69, AB_CSB0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) EMEV_MUX_PIN(ab_csb1, 70, AB_CSB1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) EMEV_MUX_PIN(ab_csb2, 71, AB_CSB2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) EMEV_MUX_PIN(ab_csb3, 72, AB_CSB3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) EMEV_MUX_PIN(ab_wait, 75, AB_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) EMEV_MUX_PIN(ab_adv, 76, AB_ADV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) EMEV_MUX_PIN(ab_a17, 93, AB_A17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) EMEV_MUX_PIN(ab_a18, 94, AB_A18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) EMEV_MUX_PIN(ab_a19, 95, AB_A19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) EMEV_MUX_PIN(ab_a20, 96, AB_A20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) EMEV_MUX_PIN(ab_a21, 97, AB_A21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) EMEV_MUX_PIN(ab_a22, 98, AB_A22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) EMEV_MUX_PIN(ab_a23, 99, AB_A23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) EMEV_MUX_PIN(ab_a24, 100, AB_A24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) EMEV_MUX_PIN(ab_a25, 101, AB_A25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) EMEV_MUX_PIN(ab_a26, 102, AB_A26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) EMEV_MUX_PIN(ab_a27, 103, AB_A27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) EMEV_MUX_PIN(ab_a28, 104, AB_A28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) EMEV_MUX_PIN(ab_ben0, 103, AB_BEN0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) EMEV_MUX_PIN(ab_ben1, 104, AB_BEN1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* = [ CAM ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) EMEV_MUX_PIN(cam_clko, 131, CAM_CLKO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const unsigned int cam_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* CLKI, VS, HS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 132, 133, 134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* CAM_YUV[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 135, 136, 137, 138,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 139, 140, 141, 142,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const unsigned int cam_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) CAM_CLKI_MARK, CAM_VS_MARK, CAM_HS_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) CAM_YUV0_MARK, CAM_YUV1_MARK, CAM_YUV2_MARK, CAM_YUV3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) CAM_YUV4_MARK, CAM_YUV5_MARK, CAM_YUV6_MARK, CAM_YUV7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) /* = [ CF ] -============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const unsigned int cf_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* CSB0, CSB1, IORDB, IOWRB, IORDY, RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * A00, A01, A02, INTRQ, INPACKB, CDB1, CDB2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 71, 72, 73, 74,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 75, 76, 93, 94,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 95, 97, 100, 101,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const unsigned int cf_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) CF_CSB0_MARK, CF_CSB1_MARK, CF_IORDB_MARK, CF_IOWRB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) CF_IORDY_MARK, CF_RESET_MARK, CF_A00_MARK, CF_A01_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) CF_A02_MARK, CF_INTRQ_MARK, CF_INPACKB_MARK, CF_CDB1_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) CF_CDB2_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const unsigned int cf_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* CF_D[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 81, 82, 83, 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const unsigned int cf_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const unsigned int cf_data16_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* CF_D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) 77, 78, 79, 80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 81, 82, 83, 84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) 85, 86, 87, 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 89, 90, 91, 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const unsigned int cf_data16_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) CF_D00_MARK, CF_D01_MARK, CF_D02_MARK, CF_D03_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) CF_D04_MARK, CF_D05_MARK, CF_D06_MARK, CF_D07_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) CF_D08_MARK, CF_D09_MARK, CF_D10_MARK, CF_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) CF_D12_MARK, CF_D13_MARK, CF_D14_MARK, CF_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* = [ DTV ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const unsigned int dtv_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* BCLK, PSYNC, VALID, DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 85, 86, 87, 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const unsigned int dtv_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DTV_BCLK_A_MARK, DTV_PSYNC_A_MARK, DTV_VALID_A_MARK, DTV_DATA_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const unsigned int dtv_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* BCLK, PSYNC, VALID, DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 109, 110, 111, 112,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const unsigned int dtv_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DTV_BCLK_B_MARK, DTV_PSYNC_B_MARK, DTV_VALID_B_MARK, DTV_DATA_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* = [ IIC0 ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const unsigned int iic0_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) 44, 45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const unsigned int iic0_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) IIC0_SCL_MARK, IIC0_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* = [ IIC1 ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const unsigned int iic1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /* SCL, SDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) 46, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const unsigned int iic1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) IIC1_SCL_MARK, IIC1_SDA_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* = [ JTAG ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const unsigned int jtag_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* SEL, TDO, TDOEN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) 2, 151, 152,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const unsigned int jtag_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) JT_SEL_MARK, JT_TDO_MARK, JT_TDOEN_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) /* = [ LCD/YUV ] ========== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) EMEV_MUX_PIN(lcd3_pxclk, 18, LCD3_PXCLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) EMEV_MUX_PIN(lcd3_pxclkb, 19, LCD3_PXCLKB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) EMEV_MUX_PIN(lcd3_clk_i, 20, LCD3_CLK_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const unsigned int lcd3_sync_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* HS, VS, DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) 21, 22, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const unsigned int lcd3_sync_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) LCD3_HS_MARK, LCD3_VS_MARK, LCD3_DE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const unsigned int lcd3_rgb888_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* R[0:7], G[0:7], B[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) 32, 33, 34, 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) 36, 37, 38, 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) 40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) 42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const unsigned int lcd3_rgb888_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) LCD3_R0_MARK, LCD3_R1_MARK, LCD3_R2_MARK, LCD3_R3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) LCD3_R4_MARK, LCD3_R5_MARK, LCD3_R6_MARK, LCD3_R7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) LCD3_G0_MARK, LCD3_G1_MARK, LCD3_G2_MARK, LCD3_G3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) LCD3_G4_MARK, LCD3_G5_MARK, LCD3_G6_MARK, LCD3_G7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) LCD3_B0_MARK, LCD3_B1_MARK, LCD3_B2_MARK, LCD3_B3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) LCD3_B4_MARK, LCD3_B5_MARK, LCD3_B6_MARK, LCD3_B7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) EMEV_MUX_PIN(yuv3_clk_i, 20, YUV3_CLK_I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const unsigned int yuv3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* CLK_O, HS, VS, DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) 18, 21, 22, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /* YUV3_D[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) 40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) 42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const unsigned int yuv3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) YUV3_CLK_O_MARK, YUV3_HS_MARK, YUV3_VS_MARK, YUV3_DE_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) YUV3_D0_MARK, YUV3_D1_MARK, YUV3_D2_MARK, YUV3_D3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) YUV3_D4_MARK, YUV3_D5_MARK, YUV3_D6_MARK, YUV3_D7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) YUV3_D8_MARK, YUV3_D9_MARK, YUV3_D10_MARK, YUV3_D11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) YUV3_D12_MARK, YUV3_D13_MARK, YUV3_D14_MARK, YUV3_D15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* = [ NTSC ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) EMEV_MUX_PIN(ntsc_clk, 122, NTSC_CLK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const unsigned int ntsc_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* NTSC_DATA[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) 123, 124, 125, 126,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) 127, 128, 129, 130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const unsigned int ntsc_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) NTSC_DATA0_MARK, NTSC_DATA1_MARK, NTSC_DATA2_MARK, NTSC_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) NTSC_DATA4_MARK, NTSC_DATA5_MARK, NTSC_DATA6_MARK, NTSC_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* = [ PWM0 ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) EMEV_MUX_PIN(pwm0, 120, PWM0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) /* = [ PWM1 ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) EMEV_MUX_PIN(pwm1, 121, PWM1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* = [ SD ] =============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) EMEV_MUX_PIN(sd_cki, 48, SD_CKI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* = [ SDIO0 ] ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const unsigned int sdi0_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) /* CKO, CKI, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) 50, 51, 52,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const unsigned int sdi0_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) SDI0_CKO_MARK, SDI0_CKI_MARK, SDI0_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const unsigned int sdi0_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* SDI0_DATA[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) 53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const unsigned int sdi0_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) SDI0_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const unsigned int sdi0_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* SDI0_DATA[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) 53, 54, 55, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const unsigned int sdi0_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const unsigned int sdi0_data8_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* SDI0_DATA[0:7] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) 53, 54, 55, 56,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) 57, 58, 59, 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const unsigned int sdi0_data8_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) SDI0_DATA0_MARK, SDI0_DATA1_MARK, SDI0_DATA2_MARK, SDI0_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) SDI0_DATA4_MARK, SDI0_DATA5_MARK, SDI0_DATA6_MARK, SDI0_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* = [ SDIO1 ] ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const unsigned int sdi1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* CKO, CKI, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) 61, 62, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const unsigned int sdi1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) SDI1_CKO_MARK, SDI1_CKI_MARK, SDI1_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const unsigned int sdi1_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* SDI1_DATA[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const unsigned int sdi1_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) SDI1_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const unsigned int sdi1_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /* SDI1_DATA[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) 64, 65, 66, 67,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const unsigned int sdi1_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) SDI1_DATA0_MARK, SDI1_DATA1_MARK, SDI1_DATA2_MARK, SDI1_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) /* = [ SDIO2 ] ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const unsigned int sdi2_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* CKO, CKI, CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) 97, 98, 99,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const unsigned int sdi2_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) SDI2_CKO_MARK, SDI2_CKI_MARK, SDI2_CMD_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const unsigned int sdi2_data1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* SDI2_DATA[0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) 89,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const unsigned int sdi2_data1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) SDI2_DATA0_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned int sdi2_data4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* SDI2_DATA[0:3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) 89, 90, 91, 92,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const unsigned int sdi2_data4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) SDI2_DATA0_MARK, SDI2_DATA1_MARK, SDI2_DATA2_MARK, SDI2_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) /* = [ TP33 ] ============= */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const unsigned int tp33_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* CLK, CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) 38, 39,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* TP33_DATA[0:15] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) 40, 41, PIN_LCD3_G2, PIN_LCD3_G3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PIN_LCD3_G4, PIN_LCD3_G5, PIN_LCD3_G6, PIN_LCD3_G7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) 42, 43, PIN_LCD3_B2, PIN_LCD3_B3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PIN_LCD3_B4, PIN_LCD3_B5, PIN_LCD3_B6, PIN_LCD3_B7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const unsigned int tp33_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) TP33_CLK_MARK, TP33_CTRL_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) TP33_DATA0_MARK, TP33_DATA1_MARK, TP33_DATA2_MARK, TP33_DATA3_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) TP33_DATA4_MARK, TP33_DATA5_MARK, TP33_DATA6_MARK, TP33_DATA7_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) TP33_DATA8_MARK, TP33_DATA9_MARK, TP33_DATA10_MARK, TP33_DATA11_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) TP33_DATA12_MARK, TP33_DATA13_MARK, TP33_DATA14_MARK, TP33_DATA15_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* = [ UART1 ] ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const unsigned int uart1_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) 155, 156,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const unsigned int uart1_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) UART1_RX_MARK, UART1_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const unsigned int uart1_ctrl_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* CTSB, RTSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 157, 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const unsigned int uart1_ctrl_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) UART1_CTSB_MARK, UART1_RTSB_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) /* = [ UART2 ] ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const unsigned int uart2_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) 157, 158,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const unsigned int uart2_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) UART2_RX_MARK, UART2_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* = [ UART3 ] ============ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static const unsigned int uart3_data_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* RX, TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) 46, 47,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const unsigned int uart3_data_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) UART3_RX_MARK, UART3_TX_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* = [ USB ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) EMEV_MUX_PIN(usb_vbus, 153, USB_VBUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* = [ USI0 ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) EMEV_MUX_PIN(usi0_cs1, 105, USI0_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) EMEV_MUX_PIN(usi0_cs2, 106, USI0_CS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) EMEV_MUX_PIN(usi0_cs3, 115, USI0_CS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) EMEV_MUX_PIN(usi0_cs4, 116, USI0_CS4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) EMEV_MUX_PIN(usi0_cs5, 117, USI0_CS5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) EMEV_MUX_PIN(usi0_cs6, 118, USI0_CS6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* = [ USI1 ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static const unsigned int usi1_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* DI, DO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) 107, 108,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const unsigned int usi1_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) USI1_DI_MARK, USI1_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* = [ USI2 ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const unsigned int usi2_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) /* CLK, DI, DO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) 109, 110, 111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const unsigned int usi2_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) USI2_CLK_MARK, USI2_DI_MARK, USI2_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) EMEV_MUX_PIN(usi2_cs0, 112, USI2_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) EMEV_MUX_PIN(usi2_cs1, 113, USI2_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) EMEV_MUX_PIN(usi2_cs2, 114, USI2_CS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /* = [ USI3 ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const unsigned int usi3_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* CLK, DI, DO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) 115, 116, 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static const unsigned int usi3_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) USI3_CLK_MARK, USI3_DI_MARK, USI3_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) EMEV_MUX_PIN(usi3_cs0, 118, USI3_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* = [ USI4 ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static const unsigned int usi4_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* CLK, DI, DO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) 119, 120, 121,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const unsigned int usi4_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) USI4_CLK_MARK, USI4_DI_MARK, USI4_DO_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) EMEV_MUX_PIN(usi4_cs0, 113, USI4_CS0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) EMEV_MUX_PIN(usi4_cs1, 114, USI4_CS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* = [ USI5 ] ============== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const unsigned int usi5_a_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* CLK, DI, DO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) 85, 86, 87,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const unsigned int usi5_a_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) USI5_CLK_A_MARK, USI5_DI_A_MARK, USI5_DO_A_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) EMEV_MUX_PIN(usi5_cs0_a, 88, USI5_CS0_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) EMEV_MUX_PIN(usi5_cs1_a, 89, USI5_CS1_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) EMEV_MUX_PIN(usi5_cs2_a, 90, USI5_CS2_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const unsigned int usi5_b_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* CLK, DI, DO*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) 143, 144, 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const unsigned int usi5_b_mux[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) USI5_CLK_B_MARK, USI5_DI_B_MARK, USI5_DO_B_MARK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) EMEV_MUX_PIN(usi5_cs0_b, 145, USI5_CS0_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) EMEV_MUX_PIN(usi5_cs1_b, 146, USI5_CS1_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) EMEV_MUX_PIN(usi5_cs2_b, 147, USI5_CS2_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) EMEV_MUX_PIN(usi5_cs3_b, 148, USI5_CS3_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) EMEV_MUX_PIN(usi5_cs4_b, 149, USI5_CS4_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const struct sh_pfc_pin_group pinmux_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) SH_PFC_PIN_GROUP(err_rst_reqb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) SH_PFC_PIN_GROUP(ref_clko),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SH_PFC_PIN_GROUP(ext_clki),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) SH_PFC_PIN_GROUP(lowpwr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SH_PFC_PIN_GROUP(ab_main),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) SH_PFC_PIN_GROUP(ab_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SH_PFC_PIN_GROUP(ab_csb0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) SH_PFC_PIN_GROUP(ab_csb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SH_PFC_PIN_GROUP(ab_csb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SH_PFC_PIN_GROUP(ab_csb3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SH_PFC_PIN_GROUP(ab_wait),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) SH_PFC_PIN_GROUP(ab_adv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) SH_PFC_PIN_GROUP(ab_a17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) SH_PFC_PIN_GROUP(ab_a18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) SH_PFC_PIN_GROUP(ab_a19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) SH_PFC_PIN_GROUP(ab_a20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) SH_PFC_PIN_GROUP(ab_a21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) SH_PFC_PIN_GROUP(ab_a22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) SH_PFC_PIN_GROUP(ab_a23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) SH_PFC_PIN_GROUP(ab_a24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SH_PFC_PIN_GROUP(ab_a25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) SH_PFC_PIN_GROUP(ab_a26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) SH_PFC_PIN_GROUP(ab_a27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) SH_PFC_PIN_GROUP(ab_a28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) SH_PFC_PIN_GROUP(ab_ben0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) SH_PFC_PIN_GROUP(ab_ben1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SH_PFC_PIN_GROUP(cam_clko),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SH_PFC_PIN_GROUP(cam),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) SH_PFC_PIN_GROUP(cf_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) SH_PFC_PIN_GROUP(cf_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) SH_PFC_PIN_GROUP(cf_data16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) SH_PFC_PIN_GROUP(dtv_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) SH_PFC_PIN_GROUP(dtv_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) SH_PFC_PIN_GROUP(iic0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SH_PFC_PIN_GROUP(iic1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SH_PFC_PIN_GROUP(jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SH_PFC_PIN_GROUP(lcd3_pxclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SH_PFC_PIN_GROUP(lcd3_pxclkb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SH_PFC_PIN_GROUP(lcd3_clk_i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SH_PFC_PIN_GROUP(lcd3_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SH_PFC_PIN_GROUP(lcd3_rgb888),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SH_PFC_PIN_GROUP(yuv3_clk_i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SH_PFC_PIN_GROUP(yuv3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) SH_PFC_PIN_GROUP(ntsc_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) SH_PFC_PIN_GROUP(ntsc_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) SH_PFC_PIN_GROUP(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) SH_PFC_PIN_GROUP(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) SH_PFC_PIN_GROUP(sd_cki),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SH_PFC_PIN_GROUP(sdi0_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SH_PFC_PIN_GROUP(sdi0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) SH_PFC_PIN_GROUP(sdi0_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) SH_PFC_PIN_GROUP(sdi0_data8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SH_PFC_PIN_GROUP(sdi1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SH_PFC_PIN_GROUP(sdi1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SH_PFC_PIN_GROUP(sdi1_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) SH_PFC_PIN_GROUP(sdi2_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SH_PFC_PIN_GROUP(sdi2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) SH_PFC_PIN_GROUP(sdi2_data4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SH_PFC_PIN_GROUP(tp33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) SH_PFC_PIN_GROUP(uart1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SH_PFC_PIN_GROUP(uart1_ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SH_PFC_PIN_GROUP(uart2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SH_PFC_PIN_GROUP(uart3_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SH_PFC_PIN_GROUP(usb_vbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) SH_PFC_PIN_GROUP(usi0_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SH_PFC_PIN_GROUP(usi0_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) SH_PFC_PIN_GROUP(usi0_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SH_PFC_PIN_GROUP(usi0_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SH_PFC_PIN_GROUP(usi0_cs5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SH_PFC_PIN_GROUP(usi0_cs6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) SH_PFC_PIN_GROUP(usi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) SH_PFC_PIN_GROUP(usi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) SH_PFC_PIN_GROUP(usi2_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SH_PFC_PIN_GROUP(usi2_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SH_PFC_PIN_GROUP(usi2_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) SH_PFC_PIN_GROUP(usi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) SH_PFC_PIN_GROUP(usi3_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) SH_PFC_PIN_GROUP(usi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) SH_PFC_PIN_GROUP(usi4_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SH_PFC_PIN_GROUP(usi4_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) SH_PFC_PIN_GROUP(usi5_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) SH_PFC_PIN_GROUP(usi5_cs0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SH_PFC_PIN_GROUP(usi5_cs1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) SH_PFC_PIN_GROUP(usi5_cs2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SH_PFC_PIN_GROUP(usi5_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SH_PFC_PIN_GROUP(usi5_cs0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) SH_PFC_PIN_GROUP(usi5_cs1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) SH_PFC_PIN_GROUP(usi5_cs2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) SH_PFC_PIN_GROUP(usi5_cs3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) SH_PFC_PIN_GROUP(usi5_cs4_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const char * const ab_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) "ab_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "ab_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "ab_csb0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) "ab_csb1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) "ab_csb2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) "ab_csb3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) "ab_wait",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) "ab_adv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) "ab_a17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) "ab_a18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) "ab_a19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) "ab_a20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "ab_a21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) "ab_a22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "ab_a23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "ab_a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) "ab_a25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) "ab_a26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "ab_a27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) "ab_a28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) "ab_ben0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) "ab_ben1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) static const char * const cam_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) "cam_clko",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) "cam",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const char * const cf_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "cf_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) "cf_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) "cf_data16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static const char * const dtv_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) "dtv_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) "dtv_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static const char * const err_rst_reqb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) "err_rst_reqb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const char * const ext_clki_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) "ext_clki",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static const char * const iic0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) "iic0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static const char * const iic1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "iic1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) static const char * const jtag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) "jtag",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const char * const lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) "lcd3_pxclk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) "lcd3_pxclkb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) "lcd3_clk_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) "lcd3_sync",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) "lcd3_rgb888",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) "yuv3_clk_i",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "yuv3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static const char * const lowpwr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "lowpwr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) static const char * const ntsc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) "ntsc_clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "ntsc_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static const char * const pwm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) "pwm0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static const char * const pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "pwm1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static const char * const ref_clko_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) "ref_clko",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const char * const sd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) "sd_cki",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const char * const sdi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) "sdi0_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "sdi0_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) "sdi0_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) "sdi0_data8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static const char * const sdi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "sdi1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) "sdi1_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) "sdi1_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static const char * const sdi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) "sdi2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) "sdi2_data1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) "sdi2_data4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static const char * const tp33_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) "tp33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static const char * const uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) "uart1_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) "uart1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const char * const uart2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) "uart2_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static const char * const uart3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) "uart3_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const char * const usb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) "usb_vbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static const char * const usi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) "usi0_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) "usi0_cs2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) "usi0_cs3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) "usi0_cs4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) "usi0_cs5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) "usi0_cs6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static const char * const usi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) "usi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static const char * const usi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) "usi2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) "usi2_cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) "usi2_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) "usi2_cs2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static const char * const usi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) "usi3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) "usi3_cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) static const char * const usi4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) "usi4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) "usi4_cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) "usi4_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static const char * const usi5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) "usi5_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) "usi5_cs0_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) "usi5_cs1_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) "usi5_cs2_a",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) "usi5_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) "usi5_cs0_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) "usi5_cs1_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) "usi5_cs2_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) "usi5_cs3_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) "usi5_cs4_b",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static const struct sh_pfc_function pinmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) SH_PFC_FUNCTION(ab),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) SH_PFC_FUNCTION(cam),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) SH_PFC_FUNCTION(cf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) SH_PFC_FUNCTION(dtv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) SH_PFC_FUNCTION(err_rst_reqb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) SH_PFC_FUNCTION(ext_clki),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SH_PFC_FUNCTION(iic0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) SH_PFC_FUNCTION(iic1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) SH_PFC_FUNCTION(jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) SH_PFC_FUNCTION(lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) SH_PFC_FUNCTION(lowpwr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) SH_PFC_FUNCTION(ntsc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) SH_PFC_FUNCTION(pwm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) SH_PFC_FUNCTION(pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) SH_PFC_FUNCTION(ref_clko),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) SH_PFC_FUNCTION(sd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) SH_PFC_FUNCTION(sdi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) SH_PFC_FUNCTION(sdi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) SH_PFC_FUNCTION(sdi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) SH_PFC_FUNCTION(tp33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) SH_PFC_FUNCTION(uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) SH_PFC_FUNCTION(uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) SH_PFC_FUNCTION(uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) SH_PFC_FUNCTION(usb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SH_PFC_FUNCTION(usi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) SH_PFC_FUNCTION(usi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SH_PFC_FUNCTION(usi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) SH_PFC_FUNCTION(usi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) SH_PFC_FUNCTION(usi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) SH_PFC_FUNCTION(usi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static const struct pinmux_cfg_reg pinmux_config_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) { PINMUX_CFG_REG("GPSR0", 0xe0140200, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) 0, PORT31_FN, /* PIN: J18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) 0, PORT30_FN, /* PIN: H18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) 0, PORT29_FN, /* PIN: G18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) 0, PORT28_FN, /* PIN: F18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) 0, PORT27_FN, /* PIN: F17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) 0, PORT26_FN, /* PIN: F16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) 0, PORT25_FN, /* PIN: E20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) 0, PORT24_FN, /* PIN: D20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) FN_LCD3_1_0_PORT23, PORT23_FN, /* PIN: D19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) FN_LCD3_1_0_PORT22, PORT22_FN, /* PIN: C20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) FN_LCD3_1_0_PORT21, PORT21_FN, /* PIN: B21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) FN_LCD3_1_0_PORT20, PORT20_FN, /* PIN: A21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) FN_LCD3_PXCLKB, PORT19_FN, /* PIN: C21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) FN_LCD3_1_0_PORT18, PORT18_FN, /* PIN: B22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) 0, PORT17_FN, /* PIN: W20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) 0, PORT16_FN, /* PIN: W21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) 0, PORT15_FN, /* PIN: Y19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) 0, PORT14_FN, /* PIN: Y20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) 0, PORT13_FN, /* PIN: Y21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) 0, PORT12_FN, /* PIN: AA20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) 0, PORT11_FN, /* PIN: AA21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) 0, PORT10_FN, /* PIN: AA22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) 0, PORT9_FN, /* PIN: V15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) 0, PORT8_FN, /* PIN: V16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) 0, PORT7_FN, /* PIN: V17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) 0, PORT6_FN, /* PIN: V18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) FN_EXT_CLKI, PORT5_FN, /* PIN: U8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) FN_REF_CLKO, PORT4_FN, /* PIN: V8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) FN_ERR_RST_REQB, PORT3_FN, /* PIN: U9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) FN_JT_SEL, PORT2_FN, /* PIN: V9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) 0, PORT1_FN, /* PIN: U10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) 0, PORT0_FN, /* PIN: V10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) { PINMUX_CFG_REG("GPSR1", 0xe0140204, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) FN_SDI1_CMD, PORT63_FN, /* PIN: AC21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) FN_SDI1_CKI, PORT62_FN, /* PIN: AA23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) FN_SDI1_CKO, PORT61_FN, /* PIN: AB22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) FN_SDI0_DATA7, PORT60_FN, /* PIN: Y16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) FN_SDI0_DATA6, PORT59_FN, /* PIN: AA16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) FN_SDI0_DATA5, PORT58_FN, /* PIN: Y15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) FN_SDI0_DATA4, PORT57_FN, /* PIN: AA15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) FN_SDI0_DATA3, PORT56_FN, /* PIN: Y14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) FN_SDI0_DATA2, PORT55_FN, /* PIN: AA14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) FN_SDI0_DATA1, PORT54_FN, /* PIN: Y13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) FN_SDI0_DATA0, PORT53_FN, /* PIN: AA13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) FN_SDI0_CMD, PORT52_FN, /* PIN: Y12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) FN_SDI0_CKI, PORT51_FN, /* PIN: AC18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) FN_SDI0_CKO, PORT50_FN, /* PIN: AB18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) 0, PORT49_FN, /* PIN: AB16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) FN_SD_CKI, PORT48_FN, /* PIN: AC19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) FN_IIC_1_0_PORT47, PORT47_FN, /* PIN: Y8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) FN_IIC_1_0_PORT46, PORT46_FN, /* PIN: Y9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) FN_IIC0_SDA, PORT45_FN, /* PIN: AA8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) FN_IIC0_SCL, PORT44_FN, /* PIN: AA9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) FN_LCD3_11_10_PORT43, PORT43_FN, /* PIN: A15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) FN_LCD3_11_10_PORT42, PORT42_FN, /* PIN: A16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) FN_LCD3_11_10_PORT41, PORT41_FN, /* PIN: A17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) FN_LCD3_11_10_PORT40, PORT40_FN, /* PIN: A18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) FN_LCD3_9_8_PORT39, PORT39_FN, /* PIN: D18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) FN_LCD3_9_8_PORT38, PORT38_FN, /* PIN: C18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) FN_LCD3_R5, PORT37_FN, /* PIN: B18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) FN_LCD3_R4, PORT36_FN, /* PIN: C19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) FN_LCD3_R3, PORT35_FN, /* PIN: B19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) FN_LCD3_R2, PORT34_FN, /* PIN: A19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) FN_LCD3_R1, PORT33_FN, /* PIN: B20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) FN_LCD3_R0, PORT32_FN, /* PIN: A20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) { PINMUX_CFG_REG("GPSR2", 0xe0140208, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) FN_AB_1_0_PORT95, PORT95_FN, /* PIN: L21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) FN_AB_1_0_PORT94, PORT94_FN, /* PIN: K21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) FN_AB_1_0_PORT93, PORT93_FN, /* PIN: J21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) FN_AB_7_6_PORT92, PORT92_FN, /* PIN: J22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) FN_AB_7_6_PORT91, PORT91_FN, /* PIN: H21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) FN_AB_5_4_PORT90, PORT90_FN, /* PIN: H22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) FN_AB_5_4_PORT89, PORT89_FN, /* PIN: H23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) FN_AB_3_2_PORT88, PORT88_FN, /* PIN: G21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) FN_AB_3_2_PORT87, PORT87_FN, /* PIN: G22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) FN_AB_3_2_PORT86, PORT86_FN, /* PIN: G23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) FN_AB_3_2_PORT85, PORT85_FN, /* PIN: F21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) FN_AB_1_0_PORT84, PORT84_FN, /* PIN: F22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) FN_AB_1_0_PORT83, PORT83_FN, /* PIN: F23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) FN_AB_1_0_PORT82, PORT82_FN, /* PIN: E22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) FN_AB_1_0_PORT81, PORT81_FN, /* PIN: E23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) FN_AB_1_0_PORT80, PORT80_FN, /* PIN: D22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) FN_AB_1_0_PORT79, PORT79_FN, /* PIN: D23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) FN_AB_1_0_PORT78, PORT78_FN, /* PIN: C22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) FN_AB_1_0_PORT77, PORT77_FN, /* PIN: C23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) FN_AB_1_0_PORT76, PORT76_FN, /* PIN: K20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) FN_AB_1_0_PORT75, PORT75_FN, /* PIN: L20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) FN_AB_1_0_PORT74, PORT74_FN, /* PIN: H20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) FN_AB_1_0_PORT73, PORT73_FN, /* PIN: J20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) FN_AB_1_0_PORT72, PORT72_FN, /* PIN: G20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) FN_AB_1_0_PORT71, PORT71_FN, /* PIN: F20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) FN_AB_CSB1, PORT70_FN, /* PIN: E21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) FN_AB_CSB0, PORT69_FN, /* PIN: D21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) FN_AB_CLK, PORT68_FN, /* PIN: J23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) FN_SDI1_DATA3, PORT67_FN, /* PIN: AA19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) FN_SDI1_DATA2, PORT66_FN, /* PIN: AB19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) FN_SDI1_DATA1, PORT65_FN, /* PIN: AB20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) FN_SDI1_DATA0, PORT64_FN, /* PIN: AB21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { PINMUX_CFG_REG("GPSR3", 0xe014020c, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) FN_NTSC_DATA4, PORT127_FN, /* PIN: T20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) FN_NTSC_DATA3, PORT126_FN, /* PIN: R18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) FN_NTSC_DATA2, PORT125_FN, /* PIN: R20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) FN_NTSC_DATA1, PORT124_FN, /* PIN: P18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) FN_NTSC_DATA0, PORT123_FN, /* PIN: P20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) FN_NTSC_CLK, PORT122_FN, /* PIN: V20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) FN_USI_9_8_PORT121, PORT121_FN, /* PIN: Y5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) FN_USI_9_8_PORT120, PORT120_FN, /* PIN: AA4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) FN_USI_7_6_PORT119, PORT119_FN, /* PIN: AB3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) FN_USI_5_4_PORT118, PORT118_FN, /* PIN: AB4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) FN_USI_5_4_PORT117, PORT117_FN, /* PIN: AC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) FN_USI_5_4_PORT116, PORT116_FN, /* PIN: AC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) FN_USI_5_4_PORT115, PORT115_FN, /* PIN: AC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) FN_USI_3_2_PORT114, PORT114_FN, /* PIN: Y6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) FN_USI_3_2_PORT113, PORT113_FN, /* PIN: AA7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) FN_USI_1_0_PORT112, PORT112_FN, /* PIN: Y7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) FN_USI_1_0_PORT111, PORT111_FN, /* PIN: AA5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) FN_USI_1_0_PORT110, PORT110_FN, /* PIN: AA6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) FN_USI_1_0_PORT109, PORT109_FN, /* PIN: AB5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) FN_USI1_DO, PORT108_FN, /* PIN: D10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) FN_USI1_DI, PORT107_FN, /* PIN: C10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) FN_USI0_CS2, PORT106_FN, /* PIN: B9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) FN_USI0_CS1, PORT105_FN, /* PIN: B8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) FN_AB_13_12_PORT104, PORT104_FN, /* PIN: M17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) FN_AB_13_12_PORT103, PORT103_FN, /* PIN: L17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) FN_AB_11_10_PORT102, PORT102_FN, /* PIN: N18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) FN_AB_11_10_PORT101, PORT101_FN, /* PIN: M18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) FN_AB_11_10_PORT100, PORT100_FN, /* PIN: L18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) FN_AB_9_8_PORT99, PORT99_FN, /* PIN: N20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) FN_AB_9_8_PORT98, PORT98_FN, /* PIN: M20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) FN_AB_9_8_PORT97, PORT97_FN, /* PIN: N21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) FN_AB_A20, PORT96_FN, /* PIN: M21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) { PINMUX_CFG_REG("GPSR4", 0xe0140210, 32, 1, GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) FN_UART_1_0_PORT158, PORT158_FN, /* PIN: AB10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) FN_UART_1_0_PORT157, PORT157_FN, /* PIN: AA10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) FN_UART1_TX, PORT156_FN, /* PIN: Y10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) FN_UART1_RX, PORT155_FN, /* PIN: Y11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) FN_LOWPWR, PORT154_FN, /* PIN: A12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) FN_USB_VBUS, PORT153_FN, /* PIN: AA12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) FN_JT_TDOEN, PORT152_FN, /* PIN: F13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) FN_JT_TDO, PORT151_FN, /* PIN: D13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) FN_HSI_1_0_PORT150, PORT150_FN, /* PIN: M22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) FN_HSI_1_0_PORT149, PORT149_FN, /* PIN: M23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) FN_HSI_1_0_PORT148, PORT148_FN, /* PIN: N23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) FN_HSI_1_0_PORT147, PORT147_FN, /* PIN: N22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) FN_HSI_1_0_PORT146, PORT146_FN, /* PIN: L22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) FN_HSI_1_0_PORT145, PORT145_FN, /* PIN: L23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) FN_HSI_1_0_PORT144, PORT144_FN, /* PIN: K23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) FN_HSI_1_0_PORT143, PORT143_FN, /* PIN: K22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) FN_CAM_YUV7, PORT142_FN, /* PIN: V23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) FN_CAM_YUV6, PORT141_FN, /* PIN: V22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) FN_CAM_YUV5, PORT140_FN, /* PIN: U23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) FN_CAM_YUV4, PORT139_FN, /* PIN: U22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) FN_CAM_YUV3, PORT138_FN, /* PIN: U21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) FN_CAM_YUV2, PORT137_FN, /* PIN: T23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) FN_CAM_YUV1, PORT136_FN, /* PIN: T22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) FN_CAM_YUV0, PORT135_FN, /* PIN: T21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) FN_CAM_HS, PORT134_FN, /* PIN: V21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) FN_CAM_VS, PORT133_FN, /* PIN: W22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) FN_CAM_CLKI, PORT132_FN, /* PIN: Y23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) FN_CAM_CLKO, PORT131_FN, /* PIN: W23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) FN_NTSC_DATA7, PORT130_FN, /* PIN: U18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) FN_NTSC_DATA6, PORT129_FN, /* PIN: U20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) FN_NTSC_DATA5, PORT128_FN, /* PIN: T18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) { PINMUX_CFG_REG_VAR("CHG_PINSEL_LCD3", 0xe0140284, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* 31 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* 11 - 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) FN_SEL_LCD3_11_10_00, FN_SEL_LCD3_11_10_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) FN_SEL_LCD3_11_10_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /* 9 - 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) FN_SEL_LCD3_9_8_00, 0, FN_SEL_LCD3_9_8_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* 7 - 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) /* 1 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) FN_SEL_LCD3_1_0_00, FN_SEL_LCD3_1_0_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) { PINMUX_CFG_REG_VAR("CHG_PINSEL_UART", 0xe0140288, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) 1, 1, 1, 1, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) /* 31 - 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) /* 1 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) FN_SEL_UART_1_0_00, FN_SEL_UART_1_0_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) { PINMUX_CFG_REG_VAR("CHG_PINSEL_IIC", 0xe014028c, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) 1, 1, 1, 1, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* 31 - 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) /* 1 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) FN_SEL_IIC_1_0_00, FN_SEL_IIC_1_0_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) { PINMUX_CFG_REG_VAR("CHG_PINSEL_AB", 0xe0140294, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) /* 31 - 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* 13 - 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) FN_SEL_AB_13_12_00, 0, FN_SEL_AB_13_12_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) /* 11 - 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) FN_SEL_AB_11_10_00, 0, FN_SEL_AB_11_10_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* 9 - 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) FN_SEL_AB_9_8_00, FN_SEL_AB_9_8_01, FN_SEL_AB_9_8_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* 7 - 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) FN_SEL_AB_7_6_00, FN_SEL_AB_7_6_01, FN_SEL_AB_7_6_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* 5 - 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) FN_SEL_AB_5_4_00, FN_SEL_AB_5_4_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) FN_SEL_AB_5_4_10, FN_SEL_AB_5_4_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) /* 3 - 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) FN_SEL_AB_3_2_00, FN_SEL_AB_3_2_01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) FN_SEL_AB_3_2_10, FN_SEL_AB_3_2_11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* 1 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) FN_SEL_AB_1_0_00, 0, FN_SEL_AB_1_0_10, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) { PINMUX_CFG_REG_VAR("CHG_PINSEL_USI", 0xe0140298, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) 2, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) /* 31 - 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /* 9 - 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) FN_SEL_USI_9_8_00, FN_SEL_USI_9_8_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* 7 - 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) FN_SEL_USI_7_6_00, FN_SEL_USI_7_6_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) /* 5 - 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) FN_SEL_USI_5_4_00, FN_SEL_USI_5_4_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* 3 - 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) FN_SEL_USI_3_2_00, FN_SEL_USI_3_2_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) /* 1 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) FN_SEL_USI_1_0_00, FN_SEL_USI_1_0_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) { PINMUX_CFG_REG_VAR("CHG_PINSEL_HSI", 0xe01402a8, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) GROUP(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) 1, 1, 1, 1, 1, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) GROUP(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) /* 31 - 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* 1 - 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) FN_SEL_HSI_1_0_00, FN_SEL_HSI_1_0_01, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) const struct sh_pfc_soc_info emev2_pinmux_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .name = "emev2_pfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .pins = pinmux_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .nr_pins = ARRAY_SIZE(pinmux_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) .groups = pinmux_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .nr_groups = ARRAY_SIZE(pinmux_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .functions = pinmux_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) .nr_functions = ARRAY_SIZE(pinmux_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) .cfg_regs = pinmux_config_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .pinmux_data = pinmux_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .pinmux_data_size = ARRAY_SIZE(pinmux_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags