Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * SuperH Pin Function Controller GPIO driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright (C) 2009 - 2012 Paul Mundt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) struct sh_pfc_gpio_data_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	const struct pinmux_data_reg *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	u32 shadow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) struct sh_pfc_gpio_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	u8 dbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u8 dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct sh_pfc_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct sh_pfc			*pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	struct gpio_chip		gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	struct sh_pfc_window		*mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct sh_pfc_gpio_data_reg	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct sh_pfc_gpio_pin		*pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct sh_pfc_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	return chip->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 			      struct sh_pfc_gpio_data_reg **reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 			      unsigned int *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int idx = sh_pfc_get_pin_index(chip->pfc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	*reg = &chip->regs[gpio_pin->dreg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	*bit = gpio_pin->dbit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static u32 gpio_read_data_reg(struct sh_pfc_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 			      const struct pinmux_data_reg *dreg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	phys_addr_t address = dreg->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	return sh_pfc_read_raw_reg(mem, dreg->reg_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static void gpio_write_data_reg(struct sh_pfc_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 				const struct pinmux_data_reg *dreg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	phys_addr_t address = dreg->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	void __iomem *mem = address - chip->mem->phys + chip->mem->virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct sh_pfc *pfc = chip->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	const struct pinmux_data_reg *dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		for (bit = 0; bit < dreg->reg_width; bit++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			if (dreg->enum_ids[bit] == pin->enum_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				gpio_pin->dreg = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				gpio_pin->dbit = bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	struct sh_pfc *pfc = chip->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	const struct pinmux_data_reg *dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* Count the number of data registers, allocate memory and initialize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	 * them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	chip->regs = devm_kcalloc(pfc->dev, i, sizeof(*chip->regs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (chip->regs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		chip->regs[i].info = dreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	for (i = 0; i < pfc->info->nr_pins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		if (pfc->info->pins[i].enum_id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		gpio_setup_data_reg(chip, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * Pin GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	struct sh_pfc *pfc = gpio_to_pfc(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	int idx = sh_pfc_get_pin_index(pfc, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return pinctrl_gpio_request(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return pinctrl_gpio_free(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			       int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct sh_pfc_gpio_data_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	unsigned int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	gpio_get_data_reg(chip, offset, &reg, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	pos = reg->info->reg_width - (bit + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		reg->shadow |= BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		reg->shadow &= ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	gpio_write_data_reg(chip, reg->info, reg->shadow);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	return pinctrl_gpio_direction_input(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 				    int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return pinctrl_gpio_direction_output(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct sh_pfc_chip *chip = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	struct sh_pfc_gpio_data_reg *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	gpio_get_data_reg(chip, offset, &reg, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	pos = reg->info->reg_width - (bit + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	gpio_pin_set_value(gpiochip_get_data(gc), offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct sh_pfc *pfc = gpio_to_pfc(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	unsigned int i, k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	for (i = 0; i < pfc->info->gpio_irq_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		const short *gpios = pfc->info->gpio_irq[i].gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		for (k = 0; gpios[k] >= 0; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			if (gpios[k] == offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				return pfc->irqs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int gpio_pin_setup(struct sh_pfc_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct sh_pfc *pfc = chip->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct gpio_chip *gc = &chip->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	chip->pins = devm_kcalloc(pfc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 				  pfc->info->nr_pins, sizeof(*chip->pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (chip->pins == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	ret = gpio_setup_data_regs(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	gc->request = gpio_pin_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	gc->free = gpio_pin_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	gc->direction_input = gpio_pin_direction_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	gc->get = gpio_pin_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	gc->direction_output = gpio_pin_direction_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	gc->set = gpio_pin_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	gc->to_irq = gpio_pin_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	gc->label = pfc->info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	gc->parent = pfc->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	gc->base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	gc->ngpio = pfc->nr_gpio_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)  * Function GPIOs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	struct sh_pfc *pfc = gpio_to_pfc(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	unsigned int mark = pfc->info->func_gpios[offset].enum_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	dev_notice_once(pfc->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			"Use of GPIO API for function requests is deprecated, convert to pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	if (mark == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	spin_lock_irqsave(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	spin_unlock_irqrestore(&pfc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int gpio_function_setup(struct sh_pfc_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct sh_pfc *pfc = chip->pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct gpio_chip *gc = &chip->gpio_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	gc->request = gpio_function_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	gc->label = pfc->info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	gc->base = pfc->nr_gpio_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	gc->ngpio = pfc->info->nr_func_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* -----------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * Register/unregister
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct sh_pfc_chip *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		    struct sh_pfc_window *mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct sh_pfc_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (unlikely(!chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	chip->mem = mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	chip->pfc = pfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	ret = setup(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ret = devm_gpiochip_add_data(pfc->dev, &chip->gpio_chip, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	if (unlikely(ret < 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		return ERR_PTR(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		 chip->gpio_chip.label, chip->gpio_chip.base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	return chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct sh_pfc_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	phys_addr_t address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (pfc->info->data_regs == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	/* Find the memory window that contain the GPIO registers. Boards that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	 * register a separate GPIO device will not supply a memory resource
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	 * that covers the data registers. In that case don't try to handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	 * GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	address = pfc->info->data_regs[0].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	for (i = 0; i < pfc->num_windows; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		struct sh_pfc_window *window = &pfc->windows[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		if (address >= window->phys &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		    address < window->phys + window->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (i == pfc->num_windows)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	/* If we have IRQ resources make sure their number is correct. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (pfc->num_irqs != pfc->info->gpio_irq_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		dev_err(pfc->dev, "invalid number of IRQ resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	/* Register the real GPIOs chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if (IS_ERR(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		return PTR_ERR(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	pfc->gpio = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (IS_ENABLED(CONFIG_OF) && pfc->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #ifdef CONFIG_PINCTRL_SH_FUNC_GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	 * Register the GPIO to pin mappings. As pins with GPIO ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	 * must come first in the ranges, skip the pins without GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	 * ports by stopping at the first range that contains such a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	 * pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	for (i = 0; i < pfc->nr_ranges; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		const struct sh_pfc_pin_range *range = &pfc->ranges[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		if (range->start >= pfc->nr_gpio_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		ret = gpiochip_add_pin_range(&chip->gpio_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			dev_name(pfc->dev), range->start, range->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			range->end - range->start + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	/* Register the function GPIOs chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (pfc->info->nr_func_gpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		if (IS_ERR(chip))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			return PTR_ERR(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #endif /* CONFIG_PINCTRL_SH_FUNC_GPIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }