^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PMIC_GPIO_ADDRESS_RANGE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* type and subtype registers base address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PMIC_GPIO_REG_TYPE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PMIC_GPIO_REG_SUBTYPE 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* GPIO peripheral type and subtype out_values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PMIC_GPIO_TYPE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PMIC_MPP_REG_RT_STS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* control register base address offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PMIC_GPIO_REG_MODE_CTL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PMIC_GPIO_REG_DIG_IN_CTL 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PMIC_GPIO_REG_EN_CTL 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* PMIC_GPIO_REG_MODE_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PMIC_GPIO_MODE_DIGITAL_INPUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PMIC_GPIO_REG_DIG_VIN_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PMIC_GPIO_REG_VIN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PMIC_GPIO_REG_VIN_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* PMIC_GPIO_REG_DIG_PULL_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PMIC_GPIO_REG_PULL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PMIC_GPIO_REG_PULL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PMIC_GPIO_PULL_DOWN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PMIC_GPIO_PULL_DISABLE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* PMIC_GPIO_REG_DIG_IN_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* PMIC_GPIO_REG_DIG_OUT_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * Output type - indicates pin should be configured as push-pull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * open drain or open source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PMIC_GPIO_OUT_BUF_CMOS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* PMIC_GPIO_REG_EN_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define PMIC_GPIO_PHYSICAL_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Qualcomm specific pin configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* The index of each function in pmic_gpio_functions[] array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum pmic_gpio_func_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PMIC_GPIO_FUNC_INDEX_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PMIC_GPIO_FUNC_INDEX_PAIRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PMIC_GPIO_FUNC_INDEX_FUNC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PMIC_GPIO_FUNC_INDEX_FUNC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PMIC_GPIO_FUNC_INDEX_FUNC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PMIC_GPIO_FUNC_INDEX_FUNC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PMIC_GPIO_FUNC_INDEX_DTEST1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PMIC_GPIO_FUNC_INDEX_DTEST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PMIC_GPIO_FUNC_INDEX_DTEST3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PMIC_GPIO_FUNC_INDEX_DTEST4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * struct pmic_gpio_pad - keep current GPIO settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @base: Address base in SPMI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @is_enabled: Set to false when GPIO should be put in high Z state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @out_value: Cached pin output value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @have_buffer: Set to true if GPIO output could be configured in push-pull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * open-drain or open-source mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @output_enabled: Set to true if GPIO output logic is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @input_enabled: Set to true if GPIO input buffer logic is enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @num_sources: Number of power-sources supported by this GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @power_source: Current power-source used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @buffer_type: Push-pull, open-drain or open-source.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @pullup: Constant current which flow trough GPIO output buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @strength: No, Low, Medium, High
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @function: See pmic_gpio_functions[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @atest: the ATEST selection for GPIO analog-pass-through mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @dtest_buffer: the DTEST buffer selection for digital input mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pmic_gpio_pad {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) bool is_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool out_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) bool have_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool output_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool input_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool analog_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool lv_mv_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int num_sources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int power_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int buffer_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) unsigned int pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int atest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned int dtest_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pmic_gpio_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct regmap *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct pinctrl_dev *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct irq_chip irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct pinconf_generic_params pmic_gpio_bindings[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const char *const pmic_gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const char *const pmic_gpio_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int pmic_gpio_read(struct pmic_gpio_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct pmic_gpio_pad *pad, unsigned int addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ret = regmap_read(state->map, pad->base + addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_err(state->dev, "read 0x%x failed\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int pmic_gpio_write(struct pmic_gpio_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct pmic_gpio_pad *pad, unsigned int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ret = regmap_write(state->map, pad->base + addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) dev_err(state->dev, "write 0x%x failed\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Every PIN is a group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return pctldev->desc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return pctldev->desc->pins[pin].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const unsigned **pins, unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *pins = &pctldev->desc->pins[pin].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .get_groups_count = pmic_gpio_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .get_group_name = pmic_gpio_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .get_group_pins = pmic_gpio_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return ARRAY_SIZE(pmic_gpio_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return pmic_gpio_functions[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const char *const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) unsigned *const num_qgroups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *groups = pmic_gpio_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *num_qgroups = pctldev->desc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct pmic_gpio_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) pr_err("function: %d is not defined\n", function);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) pad = pctldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Non-LV/MV subtypes only support 2 special functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * offsetting the dtestx function values by 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!pad->lv_mv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) pr_err("LV/MV subtype doesn't have func3/func4\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PMIC_GPIO_FUNC_INDEX_FUNC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) pad->function = function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (pad->analog_pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else if (pad->output_enabled && pad->input_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else if (pad->output_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val = PMIC_GPIO_MODE_DIGITAL_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (pad->lv_mv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = pmic_gpio_write(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PMIC_GPIO_REG_MODE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) val = pad->atest - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = pmic_gpio_write(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) val = pad->out_value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) val |= pad->function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = pmic_gpio_write(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct pinmux_ops pmic_gpio_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .get_functions_count = pmic_gpio_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .get_function_name = pmic_gpio_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .get_function_groups = pmic_gpio_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .set_mux = pmic_gpio_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int pin, unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) unsigned param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct pmic_gpio_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pad = pctldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) case PIN_CONFIG_DRIVE_OPEN_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pad->pullup != PMIC_GPIO_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (pad->pullup != PMIC_GPIO_PULL_UP_30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (pad->is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case PIN_CONFIG_POWER_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) arg = pad->power_source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!pad->input_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) arg = pad->out_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case PMIC_GPIO_CONF_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) arg = pad->pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case PMIC_GPIO_CONF_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) arg = pad->strength;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case PMIC_GPIO_CONF_ATEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) arg = pad->atest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case PMIC_GPIO_CONF_ANALOG_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) arg = pad->analog_pass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case PMIC_GPIO_CONF_DTEST_BUFFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) arg = pad->dtest_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned long *configs, unsigned nconfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct pmic_gpio_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned param, arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pad = pctldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pad->is_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) for (i = 0; i < nconfs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case PIN_CONFIG_DRIVE_PUSH_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!pad->have_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) case PIN_CONFIG_DRIVE_OPEN_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (!pad->have_buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) pad->pullup = PMIC_GPIO_PULL_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) pad->pullup = PMIC_GPIO_PULL_UP_30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pad->pullup = PMIC_GPIO_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pad->pullup = PMIC_GPIO_PULL_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pad->is_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case PIN_CONFIG_POWER_SOURCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (arg >= pad->num_sources)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pad->power_source = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pad->input_enabled = arg ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pad->output_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) pad->out_value = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case PMIC_GPIO_CONF_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (arg > PMIC_GPIO_PULL_UP_1P5_30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) pad->pullup = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case PMIC_GPIO_CONF_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (arg > PMIC_GPIO_STRENGTH_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) pad->strength = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) case PMIC_GPIO_CONF_ATEST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!pad->lv_mv_type || arg > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) pad->atest = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case PMIC_GPIO_CONF_ANALOG_PASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (!pad->lv_mv_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) pad->analog_pass = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case PMIC_GPIO_CONF_DTEST_BUFFER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (arg > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pad->dtest_buffer = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (pad->dtest_buffer == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if (pad->lv_mv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val = pad->dtest_buffer - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val = BIT(pad->dtest_buffer - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (pad->analog_pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else if (pad->output_enabled && pad->input_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) else if (pad->output_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) val = PMIC_GPIO_MODE_DIGITAL_INPUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (pad->lv_mv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ret = pmic_gpio_write(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PMIC_GPIO_REG_MODE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val = pad->atest - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = pmic_gpio_write(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val = pad->out_value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) val |= pad->function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = pmic_gpio_write(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct seq_file *s, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct pmic_gpio_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int ret, val, function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char *const biases[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char *const buffer_types[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "push-pull", "open-drain", "open-source"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char *const strengths[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "no", "high", "medium", "low"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pad = pctldev->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) seq_puts(s, " ---");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (pad->input_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pad->out_value = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * For the non-LV/MV subtypes only 2 special functions are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * available, offsetting the dtest function values by 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) function = pad->function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!pad->lv_mv_type &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) PMIC_GPIO_FUNC_INDEX_FUNC3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (pad->analog_pass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) seq_puts(s, " analog-pass");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) seq_printf(s, " %-4s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pad->output_enabled ? "out" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) seq_printf(s, " %-7s", pmic_gpio_functions[function]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) seq_printf(s, " vin-%d", pad->power_source);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) seq_printf(s, " %-27s", biases[pad->pullup]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) seq_printf(s, " %-7s", strengths[pad->strength]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) seq_printf(s, " atest-%d", pad->atest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) seq_printf(s, " dtest-%d", pad->dtest_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const struct pinconf_ops pmic_gpio_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .pin_config_group_get = pmic_gpio_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .pin_config_group_set = pmic_gpio_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .pin_config_group_dbg_show = pmic_gpio_config_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct pmic_gpio_state *state = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static int pmic_gpio_direction_output(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned pin, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct pmic_gpio_state *state = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct pmic_gpio_state *state = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct pmic_gpio_pad *pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) pad = state->ctrl->desc->pins[pin].drv_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (!pad->is_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (pad->input_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return !!pad->out_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct pmic_gpio_state *state = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) pmic_gpio_config_set(state->ctrl, pin, &config, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static int pmic_gpio_of_xlate(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) const struct of_phandle_args *gpio_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) u32 *flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (chip->of_gpio_n_cells < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *flags = gpio_desc->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct pmic_gpio_state *state = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) for (i = 0; i < chip->ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pmic_gpio_config_dbg_show(state->ctrl, s, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const struct gpio_chip pmic_gpio_gpio_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .direction_input = pmic_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .direction_output = pmic_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .get = pmic_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .set = pmic_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .of_xlate = pmic_gpio_of_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .dbg_show = pmic_gpio_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int pmic_gpio_populate(struct pmic_gpio_state *state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct pmic_gpio_pad *pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) int type, subtype, val, dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (type != PMIC_GPIO_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) type, pad->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (subtype < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return subtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) switch (subtype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) case PMIC_GPIO_SUBTYPE_GPIO_4CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pad->have_buffer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) pad->num_sources = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) case PMIC_GPIO_SUBTYPE_GPIO_8CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pad->have_buffer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pad->num_sources = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case PMIC_GPIO_SUBTYPE_GPIO_LV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pad->num_sources = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pad->have_buffer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) pad->lv_mv_type = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case PMIC_GPIO_SUBTYPE_GPIO_MV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) pad->num_sources = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pad->have_buffer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) pad->lv_mv_type = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (pad->lv_mv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) val = pmic_gpio_read(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) switch (dir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case PMIC_GPIO_MODE_DIGITAL_INPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pad->input_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pad->output_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pad->input_enabled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pad->output_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pad->input_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) pad->output_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!pad->lv_mv_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) pad->analog_pass = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dev_err(state->dev, "unknown GPIO direction\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) pad->dtest_buffer =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) else if (!pad->lv_mv_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pad->dtest_buffer = ffs(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pad->dtest_buffer = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (pad->lv_mv_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) val = pmic_gpio_read(state, pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pad->is_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int pmic_gpio_domain_translate(struct irq_domain *domain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) struct irq_fwspec *fwspec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned long *hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) unsigned int *type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct pmic_gpio_state *state = container_of(domain->host_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct pmic_gpio_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (fwspec->param_count != 2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) *hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) *type = fwspec->param[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return offset + PMIC_GPIO_PHYSICAL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) unsigned int child_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) unsigned int child_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) unsigned int *parent_hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unsigned int *parent_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *parent_hwirq = child_hwirq + 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *parent_type = child_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int pmic_gpio_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct irq_domain *parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct device_node *parent_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct pinctrl_pin_desc *pindesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct pinctrl_desc *pctrldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct pmic_gpio_pad *pad, *pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct pmic_gpio_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) int ret, npins, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ret = of_property_read_u32(dev->of_node, "reg", ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(dev, "missing base address");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) npins = (uintptr_t) device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) platform_set_drvdata(pdev, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) state->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) state->map = dev_get_regmap(dev->parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!pindesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!pads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!pctrldesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) pctrldesc->confops = &pmic_gpio_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) pctrldesc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) pctrldesc->name = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) pctrldesc->pins = pindesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pctrldesc->npins = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pctrldesc->custom_params = pmic_gpio_bindings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) pctrldesc->custom_conf_items = pmic_conf_items;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) for (i = 0; i < npins; i++, pindesc++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) pad = &pads[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) pindesc->drv_data = pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pindesc->number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pindesc->name = pmic_gpio_groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = pmic_gpio_populate(state, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) state->chip = pmic_gpio_gpio_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) state->chip.parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) state->chip.base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) state->chip.ngpio = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) state->chip.label = dev_name(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) state->chip.of_gpio_n_cells = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) state->chip.can_sleep = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (IS_ERR(state->ctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return PTR_ERR(state->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) parent_node = of_irq_find_parent(state->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (!parent_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) parent_domain = irq_find_host(parent_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) of_node_put(parent_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) state->irq.name = "spmi-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) state->irq.irq_ack = irq_chip_ack_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) state->irq.irq_mask = irq_chip_mask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) state->irq.irq_unmask = irq_chip_unmask_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) state->irq.irq_set_type = irq_chip_set_type_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) state->irq.irq_set_wake = irq_chip_set_wake_parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) state->irq.flags = IRQCHIP_MASK_ON_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) girq = &state->chip.irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) girq->chip = &state->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) girq->handler = handle_level_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) girq->fwnode = of_node_to_fwnode(state->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) girq->parent_domain = parent_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = gpiochip_add_data(&state->chip, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) dev_err(state->dev, "can't add gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * For DeviceTree-supported systems, the gpio core checks the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * pinctrl's device node for the "gpio-ranges" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * If it is present, it takes care of adding the pin ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * for the driver. In this case the driver can skip ahead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * In order to remain compatible with older, existing DeviceTree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * files which don't set the "gpio-ranges" property or systems that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * utilize ACPI the driver has to call gpiochip_add_pin_range().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(dev, "failed to add pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) goto err_range;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) err_range:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) gpiochip_remove(&state->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int pmic_gpio_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct pmic_gpio_state *state = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) gpiochip_remove(&state->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static const struct of_device_id pmic_gpio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) { .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) { .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) { .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* pm8950 has 8 GPIOs with holes on 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) { .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) { .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) { .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) { .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) { .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) { .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) { .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) { .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) { .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) { .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) { .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* pm8150b has 12 GPIOs with holes on 3, r and 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) { .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* pm8150l has 12 GPIOs with holes on 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) { .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) { .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) { .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static struct platform_driver pmic_gpio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .name = "qcom-spmi-gpio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .of_match_table = pmic_gpio_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .probe = pmic_gpio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .remove = pmic_gpio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) module_platform_driver(pmic_gpio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MODULE_ALIAS("platform:qcom-spmi-gpio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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