^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const char * const sm8250_tiles[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "west",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "south",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "north",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) WEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) SOUTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) NORTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [msm_mux_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define REG_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) msm_mux_gpio, /* gpio mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) msm_mux_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) msm_mux_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) msm_mux_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) msm_mux_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) msm_mux_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) msm_mux_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) msm_mux_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) msm_mux_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) msm_mux_##f9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .nfuncs = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .ctl_reg = REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .io_reg = REG_SIZE * id + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .intr_cfg_reg = REG_SIZE * id + 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .intr_status_reg = REG_SIZE * id + 0xc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .intr_target_reg = REG_SIZE * id + 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .tile = _tile, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .intr_target_kpss_val = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .tile = NORTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define UFS_RESET(pg_name, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .ctl_reg = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .io_reg = offset + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .tile = SOUTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .pull_bit = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .drv_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .out_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct pinctrl_pin_desc sm8250_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(114, "GPIO_114"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(115, "GPIO_115"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(116, "GPIO_116"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(117, "GPIO_117"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(118, "GPIO_118"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(119, "GPIO_119"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(120, "GPIO_120"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(121, "GPIO_121"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(122, "GPIO_122"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(123, "GPIO_123"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(124, "GPIO_124"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(125, "GPIO_125"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(126, "GPIO_126"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(127, "GPIO_127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(128, "GPIO_128"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(129, "GPIO_129"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(130, "GPIO_130"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(131, "GPIO_131"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(132, "GPIO_132"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(133, "GPIO_133"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(134, "GPIO_134"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(135, "GPIO_135"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(136, "GPIO_136"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(137, "GPIO_137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(138, "GPIO_138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(139, "GPIO_139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(140, "GPIO_140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(141, "GPIO_141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(142, "GPIO_142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(143, "GPIO_143"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(144, "GPIO_144"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(145, "GPIO_145"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(146, "GPIO_146"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(147, "GPIO_147"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(148, "GPIO_148"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(149, "GPIO_149"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(150, "GPIO_150"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(151, "GPIO_151"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(152, "GPIO_152"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(153, "GPIO_153"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(154, "GPIO_154"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(155, "GPIO_155"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(156, "GPIO_156"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(157, "GPIO_157"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(158, "GPIO_158"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(159, "GPIO_159"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(160, "GPIO_160"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(161, "GPIO_161"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(162, "GPIO_162"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(163, "GPIO_163"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(164, "GPIO_164"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(165, "GPIO_165"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(166, "GPIO_166"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(167, "GPIO_167"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(168, "GPIO_168"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(169, "GPIO_169"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(170, "GPIO_170"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(171, "GPIO_171"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(172, "GPIO_172"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(173, "GPIO_173"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(174, "GPIO_174"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(175, "GPIO_175"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(176, "GPIO_176"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(177, "GPIO_177"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(178, "GPIO_178"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(179, "GPIO_179"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(180, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(181, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(182, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(183, "UFS_RESET"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define DECLARE_MSM_GPIO_PINS(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DECLARE_MSM_GPIO_PINS(114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DECLARE_MSM_GPIO_PINS(115);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DECLARE_MSM_GPIO_PINS(116);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DECLARE_MSM_GPIO_PINS(117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DECLARE_MSM_GPIO_PINS(118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DECLARE_MSM_GPIO_PINS(119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DECLARE_MSM_GPIO_PINS(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DECLARE_MSM_GPIO_PINS(121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DECLARE_MSM_GPIO_PINS(122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DECLARE_MSM_GPIO_PINS(123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DECLARE_MSM_GPIO_PINS(124);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DECLARE_MSM_GPIO_PINS(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DECLARE_MSM_GPIO_PINS(126);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DECLARE_MSM_GPIO_PINS(127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DECLARE_MSM_GPIO_PINS(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DECLARE_MSM_GPIO_PINS(129);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DECLARE_MSM_GPIO_PINS(130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DECLARE_MSM_GPIO_PINS(131);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DECLARE_MSM_GPIO_PINS(132);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DECLARE_MSM_GPIO_PINS(133);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DECLARE_MSM_GPIO_PINS(134);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DECLARE_MSM_GPIO_PINS(135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DECLARE_MSM_GPIO_PINS(136);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DECLARE_MSM_GPIO_PINS(137);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DECLARE_MSM_GPIO_PINS(138);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DECLARE_MSM_GPIO_PINS(139);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DECLARE_MSM_GPIO_PINS(140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DECLARE_MSM_GPIO_PINS(141);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DECLARE_MSM_GPIO_PINS(142);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DECLARE_MSM_GPIO_PINS(143);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DECLARE_MSM_GPIO_PINS(144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DECLARE_MSM_GPIO_PINS(145);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DECLARE_MSM_GPIO_PINS(146);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DECLARE_MSM_GPIO_PINS(147);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DECLARE_MSM_GPIO_PINS(148);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DECLARE_MSM_GPIO_PINS(149);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DECLARE_MSM_GPIO_PINS(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DECLARE_MSM_GPIO_PINS(151);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DECLARE_MSM_GPIO_PINS(152);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DECLARE_MSM_GPIO_PINS(153);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DECLARE_MSM_GPIO_PINS(154);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DECLARE_MSM_GPIO_PINS(155);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DECLARE_MSM_GPIO_PINS(156);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DECLARE_MSM_GPIO_PINS(157);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DECLARE_MSM_GPIO_PINS(158);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DECLARE_MSM_GPIO_PINS(159);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DECLARE_MSM_GPIO_PINS(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DECLARE_MSM_GPIO_PINS(161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DECLARE_MSM_GPIO_PINS(162);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DECLARE_MSM_GPIO_PINS(163);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DECLARE_MSM_GPIO_PINS(164);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DECLARE_MSM_GPIO_PINS(165);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DECLARE_MSM_GPIO_PINS(166);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DECLARE_MSM_GPIO_PINS(167);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DECLARE_MSM_GPIO_PINS(168);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DECLARE_MSM_GPIO_PINS(169);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DECLARE_MSM_GPIO_PINS(170);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DECLARE_MSM_GPIO_PINS(171);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DECLARE_MSM_GPIO_PINS(172);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DECLARE_MSM_GPIO_PINS(173);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DECLARE_MSM_GPIO_PINS(174);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DECLARE_MSM_GPIO_PINS(175);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DECLARE_MSM_GPIO_PINS(176);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DECLARE_MSM_GPIO_PINS(177);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DECLARE_MSM_GPIO_PINS(178);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DECLARE_MSM_GPIO_PINS(179);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const unsigned int ufs_reset_pins[] = { 180 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const unsigned int sdc2_clk_pins[] = { 181 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const unsigned int sdc2_cmd_pins[] = { 182 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const unsigned int sdc2_data_pins[] = { 183 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum sm8250_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msm_mux_aoss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msm_mux_atest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msm_mux_audio_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msm_mux_cam_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msm_mux_cci_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msm_mux_cci_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) msm_mux_cci_timer0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msm_mux_cci_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msm_mux_cci_timer2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_mux_cci_timer3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msm_mux_cci_timer4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msm_mux_cri_trng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msm_mux_cri_trng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msm_mux_cri_trng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msm_mux_dbg_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) msm_mux_ddr_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msm_mux_ddr_pxi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msm_mux_ddr_pxi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msm_mux_ddr_pxi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msm_mux_ddr_pxi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msm_mux_dp_hot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) msm_mux_dp_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msm_mux_gcc_gp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) msm_mux_gcc_gp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msm_mux_gcc_gp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msm_mux_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msm_mux_ibi_i3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msm_mux_jitter_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msm_mux_lpass_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msm_mux_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msm_mux_mdp_vsync0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msm_mux_mdp_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msm_mux_mdp_vsync2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) msm_mux_mdp_vsync3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) msm_mux_mi2s0_data0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msm_mux_mi2s0_data1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msm_mux_mi2s0_sck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) msm_mux_mi2s0_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) msm_mux_mi2s1_data0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) msm_mux_mi2s1_data1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) msm_mux_mi2s1_sck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msm_mux_mi2s1_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msm_mux_mi2s2_data0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msm_mux_mi2s2_data1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) msm_mux_mi2s2_sck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msm_mux_mi2s2_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) msm_mux_pci_e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msm_mux_pci_e1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msm_mux_pci_e2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msm_mux_phase_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msm_mux_pll_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) msm_mux_pll_bypassnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) msm_mux_pll_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) msm_mux_pll_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msm_mux_pri_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msm_mux_prng_rosc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msm_mux_qdss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msm_mux_qdss_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) msm_mux_qspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) msm_mux_qspi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) msm_mux_qspi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) msm_mux_qspi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) msm_mux_qspi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msm_mux_qspi_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) msm_mux_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) msm_mux_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) msm_mux_qup10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msm_mux_qup11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) msm_mux_qup12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) msm_mux_qup13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) msm_mux_qup14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msm_mux_qup15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) msm_mux_qup16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) msm_mux_qup17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) msm_mux_qup18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) msm_mux_qup19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msm_mux_qup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) msm_mux_qup3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) msm_mux_qup4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) msm_mux_qup5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) msm_mux_qup6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) msm_mux_qup7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) msm_mux_qup8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) msm_mux_qup9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) msm_mux_qup_l4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) msm_mux_qup_l5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) msm_mux_qup_l6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) msm_mux_sd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) msm_mux_sdc40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) msm_mux_sdc41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msm_mux_sdc42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) msm_mux_sdc43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) msm_mux_sdc4_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msm_mux_sdc4_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) msm_mux_sec_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msm_mux_sp_cmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msm_mux_tgu_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) msm_mux_tgu_ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) msm_mux_tgu_ch2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) msm_mux_tgu_ch3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) msm_mux_tsense_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) msm_mux_tsense_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) msm_mux_tsif0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) msm_mux_tsif0_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) msm_mux_tsif0_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) msm_mux_tsif0_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) msm_mux_tsif0_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) msm_mux_tsif1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) msm_mux_tsif1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) msm_mux_tsif1_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) msm_mux_tsif1_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) msm_mux_tsif1_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) msm_mux_usb2phy_ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) msm_mux_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) msm_mux_vsense_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) msm_mux__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const char * const tsif1_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "gpio75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const char * const sdc41_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "gpio75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const char * const tsif1_sync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const char * const sdc40_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const char * const aoss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const phase_flag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50", "gpio51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "gpio69", "gpio70", "gpio71", "gpio72", "gpio73", "gpio74", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "gpio103", "gpio104", "gpio115", "gpio116", "gpio117", "gpio118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "gpio119", "gpio120", "gpio122", "gpio124", "gpio125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const char * const sd_write_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const pci_e0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "gpio79", "gpio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const char * const pci_e1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "gpio82", "gpio83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const char * const pci_e2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "gpio85", "gpio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const char * const tgu_ch0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "gpio85",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const char * const atest_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "gpio24", "gpio25", "gpio26", "gpio27", "gpio32", "gpio33", "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "gpio35", "gpio36", "gpio37", "gpio85", "gpio86", "gpio87", "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const char * const tgu_ch3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "gpio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const char * const tsif1_error_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const char * const tgu_ch1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const char * const tsif0_error_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const char * const tgu_ch2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const char * const cam_mclk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const char * const ddr_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "gpio94", "gpio95", "gpio143", "gpio144",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const char * const pll_bypassnl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const char * const pll_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char * const cci_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "gpio107", "gpio108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const char * const qdss_gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "gpio94", "gpio95", "gpio96", "gpio97", "gpio98", "gpio99", "gpio100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "gpio101", "gpio102", "gpio103", "gpio104", "gpio105", "gpio106",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "gpio107", "gpio108", "gpio109", "gpio110", "gpio111", "gpio160",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "gpio161", "gpio162", "gpio163", "gpio164", "gpio165", "gpio166",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "gpio167", "gpio168", "gpio169", "gpio170", "gpio171", "gpio172",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) "gpio173", "gpio174", "gpio175", "gpio176", "gpio177",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const char * const gcc_gp1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "gpio106", "gpio136",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const char * const gcc_gp2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "gpio107", "gpio137",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const char * const gcc_gp3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "gpio108", "gpio138",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const char * const cci_timer0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const char * const cci_timer1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const char * const cci_timer2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "gpio111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const char * const cci_timer3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "gpio112",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const char * const cci_async_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "gpio112", "gpio113", "gpio114",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const char * const cci_timer4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const char * const qup2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "gpio115", "gpio116", "gpio117", "gpio118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const char * const qup3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const char * const tsense_pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const char * const tsense_pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const char * const qup9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "gpio125", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const char * const qup10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "gpio129", "gpio130", "gpio131", "gpio132",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const char * const mi2s2_sck_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "gpio133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char * const mi2s2_data0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const char * const mi2s2_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "gpio135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const char * const pri_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "gpio136",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const char * const sec_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "gpio137",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const char * const audio_ref_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "gpio137",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const char * const mi2s2_data1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "gpio137",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const char * const mi2s0_sck_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "gpio138",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const char * const mi2s0_data0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "gpio139",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const char * const mi2s0_data1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "gpio140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const char * const mi2s0_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "gpio141",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const char * const lpass_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "gpio142", "gpio143", "gpio144", "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const char * const mi2s1_sck_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "gpio142",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const char * const mi2s1_data0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "gpio143",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const char * const mi2s1_data1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "gpio144",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const char * const mi2s1_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const char * const cri_trng0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "gpio159",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const char * const cri_trng1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "gpio160",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static const char * const cri_trng_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "gpio161",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const char * const sp_cmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "gpio162",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const char * const prng_rosc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "gpio163",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const char * const qup19_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "gpio171", "gpio172", "gpio173", "gpio174", "gpio175", "gpio176",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "gpio177", "gpio178", "gpio179",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const char * const qdss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "gpio0", "gpio2", "gpio2", "gpio44", "gpio45", "gpio46", "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const char * const qup1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const char * const ibi_i3c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "gpio4", "gpio5", "gpio24", "gpio25", "gpio28", "gpio29", "gpio40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "gpio41",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const char * const qup_l4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "gpio6", "gpio14", "gpio46", "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const char * const qup_l5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "gpio7", "gpio15", "gpio47", "gpio124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const char * const qup4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "gpio8", "gpio9", "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const char * const qup5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const char * const qup6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const char * const qup7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "gpio20", "gpio21", "gpio22", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const char * const qup8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const char * const qup0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "gpio28", "gpio29", "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const char * const qup12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const char * const qup13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "gpio36", "gpio37", "gpio38", "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const char * const qup14_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "gpio40", "gpio41", "gpio42", "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const char * const ddr_pxi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "gpio40", "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const char * const ddr_pxi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const char * const vsense_trigger_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const char * const qup15_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "gpio44", "gpio45", "gpio46", "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const char * const dbg_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const char * const qup16_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "gpio48", "gpio49", "gpio50", "gpio51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const char * const qup17_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "gpio52", "gpio53", "gpio54", "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const char * const ddr_pxi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "gpio52", "gpio53",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const char * const jitter_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const char * const pll_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const char * const ddr_pxi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const char * const qup18_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "gpio56", "gpio57", "gpio58", "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const char * const qup11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const char * const usb2phy_ac_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "gpio64", "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const char * const qup_l6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "gpio64", "gpio77", "gpio92", "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const char * const usb_phy_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const char * const pll_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const char * const mdp_vsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) "gpio66", "gpio67", "gpio68", "gpio122", "gpio124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const char * const dp_lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) "gpio67",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const char * const dp_hot_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const char * const qspi_cs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) "gpio69", "gpio75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static const char * const tsif0_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) "gpio69",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const char * const qspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const char * const tsif0_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const char * const mdp_vsync0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const char * const mdp_vsync1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const char * const mdp_vsync2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const char * const mdp_vsync3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const char * const qspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const char * const tsif0_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const char * const sdc4_cmd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const char * const qspi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const char * const tsif0_sync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const char * const sdc43_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const char * const qspi_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "gpio73",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static const char * const tsif1_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "gpio73",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const char * const sdc4_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "gpio73",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const char * const qspi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static const char * const tsif1_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static const char * const sdc42_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static const struct msm_function sm8250_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) FUNCTION(aoss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) FUNCTION(atest),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) FUNCTION(audio_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) FUNCTION(cam_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) FUNCTION(cci_async),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) FUNCTION(cci_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) FUNCTION(cci_timer0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) FUNCTION(cci_timer1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) FUNCTION(cci_timer2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) FUNCTION(cci_timer3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) FUNCTION(cci_timer4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) FUNCTION(cri_trng),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) FUNCTION(cri_trng0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) FUNCTION(cri_trng1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FUNCTION(dbg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) FUNCTION(ddr_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) FUNCTION(ddr_pxi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) FUNCTION(ddr_pxi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) FUNCTION(ddr_pxi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) FUNCTION(ddr_pxi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) FUNCTION(dp_hot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) FUNCTION(dp_lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) FUNCTION(gcc_gp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) FUNCTION(gcc_gp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) FUNCTION(gcc_gp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) FUNCTION(ibi_i3c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) FUNCTION(jitter_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) FUNCTION(lpass_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) FUNCTION(mdp_vsync0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) FUNCTION(mdp_vsync1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) FUNCTION(mdp_vsync2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) FUNCTION(mdp_vsync3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) FUNCTION(mi2s0_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) FUNCTION(mi2s0_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) FUNCTION(mi2s0_sck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) FUNCTION(mi2s0_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) FUNCTION(mi2s1_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) FUNCTION(mi2s1_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) FUNCTION(mi2s1_sck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) FUNCTION(mi2s1_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) FUNCTION(mi2s2_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) FUNCTION(mi2s2_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) FUNCTION(mi2s2_sck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) FUNCTION(mi2s2_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) FUNCTION(pci_e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) FUNCTION(pci_e1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) FUNCTION(pci_e2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) FUNCTION(phase_flag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) FUNCTION(pll_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) FUNCTION(pll_bypassnl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) FUNCTION(pll_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) FUNCTION(pll_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) FUNCTION(pri_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) FUNCTION(prng_rosc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) FUNCTION(qdss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) FUNCTION(qdss_gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) FUNCTION(qspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) FUNCTION(qspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) FUNCTION(qspi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) FUNCTION(qspi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) FUNCTION(qspi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) FUNCTION(qspi_cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) FUNCTION(qup0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) FUNCTION(qup1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) FUNCTION(qup10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) FUNCTION(qup11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) FUNCTION(qup12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) FUNCTION(qup13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) FUNCTION(qup14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) FUNCTION(qup15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) FUNCTION(qup16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) FUNCTION(qup17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) FUNCTION(qup18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) FUNCTION(qup19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) FUNCTION(qup2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) FUNCTION(qup3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) FUNCTION(qup4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) FUNCTION(qup5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) FUNCTION(qup6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) FUNCTION(qup7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) FUNCTION(qup8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) FUNCTION(qup9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) FUNCTION(qup_l4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) FUNCTION(qup_l5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) FUNCTION(qup_l6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) FUNCTION(sd_write),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) FUNCTION(sdc40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) FUNCTION(sdc41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) FUNCTION(sdc42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) FUNCTION(sdc43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) FUNCTION(sdc4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) FUNCTION(sdc4_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) FUNCTION(sec_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) FUNCTION(sp_cmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) FUNCTION(tgu_ch0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) FUNCTION(tgu_ch1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) FUNCTION(tgu_ch2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) FUNCTION(tgu_ch3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) FUNCTION(tsense_pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) FUNCTION(tsense_pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) FUNCTION(tsif0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) FUNCTION(tsif0_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) FUNCTION(tsif0_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) FUNCTION(tsif0_error),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) FUNCTION(tsif0_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) FUNCTION(tsif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) FUNCTION(tsif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) FUNCTION(tsif1_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) FUNCTION(tsif1_error),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) FUNCTION(tsif1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) FUNCTION(usb2phy_ac),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) FUNCTION(usb_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) FUNCTION(vsense_trigger),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) /* Every pin is maintained as a single group, and missing or non-existing pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) * would be maintained as dummy group to synchronize pin group index with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) * pin descriptor registered with pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * Clients would not be able to request these dummy pin groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static const struct msm_pingroup sm8250_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) [0] = PINGROUP(0, SOUTH, qup19, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) [1] = PINGROUP(1, SOUTH, qup19, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) [2] = PINGROUP(2, SOUTH, qup19, qdss_cti, qdss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) [3] = PINGROUP(3, SOUTH, qup19, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) [4] = PINGROUP(4, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) [5] = PINGROUP(5, NORTH, qup1, ibi_i3c, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) [6] = PINGROUP(6, NORTH, qup1, qup_l4, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) [7] = PINGROUP(7, NORTH, qup1, qup_l5, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) [8] = PINGROUP(8, NORTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) [9] = PINGROUP(9, NORTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) [10] = PINGROUP(10, NORTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) [11] = PINGROUP(11, NORTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) [12] = PINGROUP(12, NORTH, qup5, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) [13] = PINGROUP(13, NORTH, qup5, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) [14] = PINGROUP(14, NORTH, qup5, qup_l4, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) [15] = PINGROUP(15, NORTH, qup5, qup_l5, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) [16] = PINGROUP(16, NORTH, qup6, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) [17] = PINGROUP(17, NORTH, qup6, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) [18] = PINGROUP(18, NORTH, qup6, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) [19] = PINGROUP(19, NORTH, qup6, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) [20] = PINGROUP(20, NORTH, qup7, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) [21] = PINGROUP(21, NORTH, qup7, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) [22] = PINGROUP(22, NORTH, qup7, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) [23] = PINGROUP(23, NORTH, qup7, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) [24] = PINGROUP(24, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) [25] = PINGROUP(25, SOUTH, qup8, ibi_i3c, atest, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) [26] = PINGROUP(26, SOUTH, qup8, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) [27] = PINGROUP(27, SOUTH, qup8, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) [28] = PINGROUP(28, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) [29] = PINGROUP(29, NORTH, qup0, ibi_i3c, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) [30] = PINGROUP(30, NORTH, qup0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) [31] = PINGROUP(31, NORTH, qup0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) [32] = PINGROUP(32, SOUTH, qup12, _, atest, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) [33] = PINGROUP(33, SOUTH, qup12, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) [34] = PINGROUP(34, SOUTH, qup12, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) [35] = PINGROUP(35, SOUTH, qup12, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) [36] = PINGROUP(36, SOUTH, qup13, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) [37] = PINGROUP(37, SOUTH, qup13, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) [38] = PINGROUP(38, SOUTH, qup13, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) [39] = PINGROUP(39, SOUTH, qup13, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) [40] = PINGROUP(40, SOUTH, qup14, ibi_i3c, _, ddr_pxi3, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) [41] = PINGROUP(41, SOUTH, qup14, ibi_i3c, _, ddr_pxi1, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) [42] = PINGROUP(42, SOUTH, qup14, vsense_trigger, ddr_pxi1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) [43] = PINGROUP(43, SOUTH, qup14, ddr_pxi3, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) [44] = PINGROUP(44, SOUTH, qup15, qdss_cti, dbg_out, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) [45] = PINGROUP(45, SOUTH, qup15, qdss_cti, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) [46] = PINGROUP(46, SOUTH, qup15, qup_l4, qdss_cti, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) [47] = PINGROUP(47, SOUTH, qup15, qup_l5, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) [48] = PINGROUP(48, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) [49] = PINGROUP(49, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) [50] = PINGROUP(50, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) [51] = PINGROUP(51, SOUTH, qup16, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) [52] = PINGROUP(52, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) [53] = PINGROUP(53, SOUTH, qup17, ddr_pxi0, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) [54] = PINGROUP(54, SOUTH, qup17, jitter_bist, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) [55] = PINGROUP(55, SOUTH, qup17, pll_bist, ddr_pxi2, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) [56] = PINGROUP(56, SOUTH, qup18, ddr_pxi2, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) [57] = PINGROUP(57, SOUTH, qup18, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) [58] = PINGROUP(58, SOUTH, qup18, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) [59] = PINGROUP(59, SOUTH, qup18, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) [60] = PINGROUP(60, SOUTH, qup11, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) [61] = PINGROUP(61, SOUTH, qup11, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) [62] = PINGROUP(62, SOUTH, qup11, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) [63] = PINGROUP(63, SOUTH, qup11, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) [64] = PINGROUP(64, SOUTH, usb2phy_ac, qup_l6, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) [65] = PINGROUP(65, SOUTH, usb_phy, pll_clk, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) [66] = PINGROUP(66, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) [67] = PINGROUP(67, NORTH, mdp_vsync, dp_lcd, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) [68] = PINGROUP(68, NORTH, mdp_vsync, dp_hot, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) [69] = PINGROUP(69, SOUTH, qspi_cs, tsif0_clk, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) [70] = PINGROUP(70, SOUTH, qspi0, tsif0_en, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, phase_flag, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) [71] = PINGROUP(71, SOUTH, qspi1, tsif0_data, sdc4_cmd, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) [72] = PINGROUP(72, SOUTH, qspi2, tsif0_sync, sdc43, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) [73] = PINGROUP(73, SOUTH, qspi_clk, tsif1_clk, sdc4_clk, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) [74] = PINGROUP(74, SOUTH, qspi3, tsif1_en, sdc42, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) [75] = PINGROUP(75, SOUTH, qspi_cs, tsif1_data, sdc41, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) [76] = PINGROUP(76, SOUTH, tsif1_sync, sdc40, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) [77] = PINGROUP(77, NORTH, qup_l6, aoss_cti, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) [78] = PINGROUP(78, NORTH, sd_write, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) [79] = PINGROUP(79, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) [80] = PINGROUP(80, NORTH, pci_e0, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) [81] = PINGROUP(81, NORTH, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) [82] = PINGROUP(82, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) [83] = PINGROUP(83, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) [84] = PINGROUP(84, NORTH, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) [85] = PINGROUP(85, SOUTH, pci_e2, tgu_ch0, atest, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) [86] = PINGROUP(86, SOUTH, pci_e2, tgu_ch3, atest, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) [87] = PINGROUP(87, SOUTH, atest, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) [88] = PINGROUP(88, SOUTH, _, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) [89] = PINGROUP(89, SOUTH, _, atest, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) [90] = PINGROUP(90, SOUTH, tsif1_error, usb2phy_ac, tgu_ch1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) [91] = PINGROUP(91, SOUTH, tsif0_error, tgu_ch2, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) [92] = PINGROUP(92, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) [93] = PINGROUP(93, NORTH, qup_l6, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) [94] = PINGROUP(94, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) [95] = PINGROUP(95, NORTH, cam_mclk, ddr_bist, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) [96] = PINGROUP(96, NORTH, cam_mclk, pll_bypassnl, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) [97] = PINGROUP(97, NORTH, cam_mclk, pll_reset, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) [98] = PINGROUP(98, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) [99] = PINGROUP(99, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) [100] = PINGROUP(100, NORTH, cam_mclk, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) [101] = PINGROUP(101, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) [102] = PINGROUP(102, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) [103] = PINGROUP(103, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) [104] = PINGROUP(104, NORTH, cci_i2c, phase_flag, _, qdss_gpio, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) [105] = PINGROUP(105, NORTH, cci_i2c, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) [106] = PINGROUP(106, NORTH, cci_i2c, gcc_gp1, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) [107] = PINGROUP(107, NORTH, cci_i2c, gcc_gp2, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) [108] = PINGROUP(108, NORTH, cci_i2c, gcc_gp3, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) [109] = PINGROUP(109, NORTH, cci_timer0, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) [110] = PINGROUP(110, NORTH, cci_timer1, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) [111] = PINGROUP(111, NORTH, cci_timer2, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) [112] = PINGROUP(112, NORTH, cci_timer3, cci_async, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) [113] = PINGROUP(113, NORTH, cci_timer4, cci_async, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) [114] = PINGROUP(114, NORTH, cci_async, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) [115] = PINGROUP(115, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) [116] = PINGROUP(116, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) [117] = PINGROUP(117, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) [118] = PINGROUP(118, NORTH, qup2, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) [119] = PINGROUP(119, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) [120] = PINGROUP(120, NORTH, qup3, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) [121] = PINGROUP(121, NORTH, qup3, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) [122] = PINGROUP(122, NORTH, qup3, mdp_vsync, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) [123] = PINGROUP(123, NORTH, qup_l4, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) [124] = PINGROUP(124, NORTH, qup_l5, mdp_vsync, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) [125] = PINGROUP(125, SOUTH, qup9, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) [126] = PINGROUP(126, SOUTH, qup9, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) [127] = PINGROUP(127, SOUTH, qup9, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) [128] = PINGROUP(128, SOUTH, qup9, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) [129] = PINGROUP(129, SOUTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) [130] = PINGROUP(130, SOUTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) [131] = PINGROUP(131, SOUTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) [132] = PINGROUP(132, SOUTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) [133] = PINGROUP(133, WEST, mi2s2_sck, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) [134] = PINGROUP(134, WEST, mi2s2_data0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) [135] = PINGROUP(135, WEST, mi2s2_ws, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) [136] = PINGROUP(136, WEST, pri_mi2s, gcc_gp1, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) [137] = PINGROUP(137, WEST, sec_mi2s, audio_ref, mi2s2_data1, gcc_gp2, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) [138] = PINGROUP(138, WEST, mi2s0_sck, gcc_gp3, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) [139] = PINGROUP(139, WEST, mi2s0_data0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) [140] = PINGROUP(140, WEST, mi2s0_data1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) [141] = PINGROUP(141, WEST, mi2s0_ws, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) [142] = PINGROUP(142, WEST, lpass_slimbus, mi2s1_sck, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) [143] = PINGROUP(143, WEST, lpass_slimbus, mi2s1_data0, ddr_bist, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) [144] = PINGROUP(144, WEST, lpass_slimbus, mi2s1_data1, ddr_bist, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) [145] = PINGROUP(145, WEST, lpass_slimbus, mi2s1_ws, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) [146] = PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) [147] = PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) [148] = PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) [149] = PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) [150] = PINGROUP(150, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) [151] = PINGROUP(151, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) [152] = PINGROUP(152, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) [153] = PINGROUP(153, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) [154] = PINGROUP(154, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) [155] = PINGROUP(155, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) [156] = PINGROUP(156, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) [157] = PINGROUP(157, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) [158] = PINGROUP(158, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) [159] = PINGROUP(159, WEST, cri_trng0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) [160] = PINGROUP(160, WEST, cri_trng1, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) [161] = PINGROUP(161, WEST, cri_trng, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) [162] = PINGROUP(162, WEST, sp_cmu, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) [163] = PINGROUP(163, WEST, prng_rosc, qdss_gpio, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) [164] = PINGROUP(164, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) [165] = PINGROUP(165, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) [166] = PINGROUP(166, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) [167] = PINGROUP(167, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) [168] = PINGROUP(168, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) [169] = PINGROUP(169, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) [170] = PINGROUP(170, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) [171] = PINGROUP(171, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) [172] = PINGROUP(172, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) [173] = PINGROUP(173, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) [174] = PINGROUP(174, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) [175] = PINGROUP(175, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) [176] = PINGROUP(176, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) [177] = PINGROUP(177, WEST, qdss_gpio, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) [178] = PINGROUP(178, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) [179] = PINGROUP(179, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) [180] = UFS_RESET(ufs_reset, 0xb8000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) [181] = SDC_PINGROUP(sdc2_clk, 0xb7000, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) [182] = SDC_PINGROUP(sdc2_cmd, 0xb7000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) [183] = SDC_PINGROUP(sdc2_data, 0xb7000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const struct msm_gpio_wakeirq_map sm8250_pdc_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { 0, 79 }, { 1, 84 }, { 2, 80 }, { 3, 82 }, { 4, 107 }, { 7, 43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { 11, 42 }, { 14, 44 }, { 15, 52 }, { 19, 67 }, { 23, 68 }, { 24, 105 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { 27, 92 }, { 28, 106 }, { 31, 69 }, { 35, 70 }, { 39, 37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { 40, 108 }, { 43, 71 }, { 45, 72 }, { 47, 83 }, { 51, 74 }, { 55, 77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) { 59, 78 }, { 63, 75 }, { 64, 81 }, { 65, 87 }, { 66, 88 }, { 67, 89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { 68, 54 }, { 70, 85 }, { 77, 46 }, { 80, 90 }, { 81, 91 }, { 83, 97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { 84, 98 }, { 86, 99 }, { 87, 100 }, { 88, 101 }, { 89, 102 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { 92, 103 }, { 93, 104 }, { 100, 53 }, { 103, 47 }, { 104, 48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { 108, 49 }, { 109, 94 }, { 110, 95 }, { 111, 96 }, { 112, 55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { 113, 56 }, { 118, 50 }, { 121, 51 }, { 122, 57 }, { 123, 58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) { 124, 45 }, { 126, 59 }, { 128, 76 }, { 129, 86 }, { 132, 93 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) { 133, 65 }, { 134, 66 }, { 136, 62 }, { 137, 63 }, { 138, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { 142, 60 }, { 143, 61 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static const struct msm_pinctrl_soc_data sm8250_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .pins = sm8250_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .npins = ARRAY_SIZE(sm8250_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) .functions = sm8250_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) .nfunctions = ARRAY_SIZE(sm8250_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) .groups = sm8250_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .ngroups = ARRAY_SIZE(sm8250_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .ngpios = 181,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .tiles = sm8250_tiles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .ntiles = ARRAY_SIZE(sm8250_tiles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .wakeirq_map = sm8250_pdc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) .nwakeirq_map = ARRAY_SIZE(sm8250_pdc_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) static int sm8250_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return msm_pinctrl_probe(pdev, &sm8250_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const struct of_device_id sm8250_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) { .compatible = "qcom,sm8250-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static struct platform_driver sm8250_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .name = "sm8250-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .of_match_table = sm8250_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .probe = sm8250_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static int __init sm8250_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return platform_driver_register(&sm8250_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) arch_initcall(sm8250_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static void __exit sm8250_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) platform_driver_unregister(&sm8250_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) module_exit(sm8250_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) MODULE_DESCRIPTION("QTI sm8250 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) MODULE_DEVICE_TABLE(of, sm8250_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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