^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static const char * const sm8150_tiles[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "north",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "south",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "east",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "west"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) NORTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) SOUTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) EAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) WEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) [msm_mux_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) msm_mux_gpio, /* gpio mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) msm_mux_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) msm_mux_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) msm_mux_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) msm_mux_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) msm_mux_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) msm_mux_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) msm_mux_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) msm_mux_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) msm_mux_##f9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .nfuncs = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .ctl_reg = 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .io_reg = 0x1000 * id + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .intr_cfg_reg = 0x1000 * id + 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .intr_status_reg = 0x1000 * id + 0xc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .intr_target_reg = 0x1000 * id + 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .tile = _tile, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .intr_target_kpss_val = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .tile = NORTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define UFS_RESET(pg_name, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .ctl_reg = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .io_reg = offset + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .tile = SOUTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .pull_bit = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .drv_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .out_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct pinctrl_pin_desc sm8150_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(114, "GPIO_114"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(115, "GPIO_115"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(116, "GPIO_116"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(117, "GPIO_117"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(118, "GPIO_118"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(119, "GPIO_119"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(120, "GPIO_120"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(121, "GPIO_121"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(122, "GPIO_122"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(123, "GPIO_123"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(124, "GPIO_124"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(125, "GPIO_125"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(126, "GPIO_126"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(127, "GPIO_127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(128, "GPIO_128"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(129, "GPIO_129"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(130, "GPIO_130"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(131, "GPIO_131"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(132, "GPIO_132"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(133, "GPIO_133"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(134, "GPIO_134"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(135, "GPIO_135"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(136, "GPIO_136"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(137, "GPIO_137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(138, "GPIO_138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(139, "GPIO_139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(140, "GPIO_140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(141, "GPIO_141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(142, "GPIO_142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(143, "GPIO_143"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(144, "GPIO_144"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(145, "GPIO_145"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(146, "GPIO_146"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(147, "GPIO_147"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(148, "GPIO_148"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(149, "GPIO_149"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(150, "GPIO_150"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(151, "GPIO_151"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(152, "GPIO_152"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(153, "GPIO_153"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(154, "GPIO_154"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(155, "GPIO_155"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(156, "GPIO_156"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(157, "GPIO_157"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(158, "GPIO_158"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(159, "GPIO_159"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(160, "GPIO_160"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(161, "GPIO_161"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(162, "GPIO_162"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(163, "GPIO_163"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(164, "GPIO_164"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(165, "GPIO_165"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(166, "GPIO_166"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(167, "GPIO_167"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(168, "GPIO_168"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) PINCTRL_PIN(169, "GPIO_169"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(170, "GPIO_170"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(171, "GPIO_171"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(172, "GPIO_172"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(173, "GPIO_173"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(174, "GPIO_174"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(175, "UFS_RESET"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(176, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(177, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(178, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define DECLARE_MSM_GPIO_PINS(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DECLARE_MSM_GPIO_PINS(114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DECLARE_MSM_GPIO_PINS(115);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DECLARE_MSM_GPIO_PINS(116);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DECLARE_MSM_GPIO_PINS(117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DECLARE_MSM_GPIO_PINS(118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DECLARE_MSM_GPIO_PINS(119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DECLARE_MSM_GPIO_PINS(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DECLARE_MSM_GPIO_PINS(121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DECLARE_MSM_GPIO_PINS(122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DECLARE_MSM_GPIO_PINS(123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DECLARE_MSM_GPIO_PINS(124);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DECLARE_MSM_GPIO_PINS(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DECLARE_MSM_GPIO_PINS(126);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DECLARE_MSM_GPIO_PINS(127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DECLARE_MSM_GPIO_PINS(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DECLARE_MSM_GPIO_PINS(129);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DECLARE_MSM_GPIO_PINS(130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DECLARE_MSM_GPIO_PINS(131);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DECLARE_MSM_GPIO_PINS(132);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DECLARE_MSM_GPIO_PINS(133);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DECLARE_MSM_GPIO_PINS(134);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DECLARE_MSM_GPIO_PINS(135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DECLARE_MSM_GPIO_PINS(136);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DECLARE_MSM_GPIO_PINS(137);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DECLARE_MSM_GPIO_PINS(138);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DECLARE_MSM_GPIO_PINS(139);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DECLARE_MSM_GPIO_PINS(140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DECLARE_MSM_GPIO_PINS(141);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DECLARE_MSM_GPIO_PINS(142);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DECLARE_MSM_GPIO_PINS(143);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DECLARE_MSM_GPIO_PINS(144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DECLARE_MSM_GPIO_PINS(145);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DECLARE_MSM_GPIO_PINS(146);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DECLARE_MSM_GPIO_PINS(147);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DECLARE_MSM_GPIO_PINS(148);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DECLARE_MSM_GPIO_PINS(149);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DECLARE_MSM_GPIO_PINS(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DECLARE_MSM_GPIO_PINS(151);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DECLARE_MSM_GPIO_PINS(152);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DECLARE_MSM_GPIO_PINS(153);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DECLARE_MSM_GPIO_PINS(154);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DECLARE_MSM_GPIO_PINS(155);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DECLARE_MSM_GPIO_PINS(156);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DECLARE_MSM_GPIO_PINS(157);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DECLARE_MSM_GPIO_PINS(158);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DECLARE_MSM_GPIO_PINS(159);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DECLARE_MSM_GPIO_PINS(160);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DECLARE_MSM_GPIO_PINS(161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DECLARE_MSM_GPIO_PINS(162);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DECLARE_MSM_GPIO_PINS(163);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DECLARE_MSM_GPIO_PINS(164);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DECLARE_MSM_GPIO_PINS(165);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DECLARE_MSM_GPIO_PINS(166);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DECLARE_MSM_GPIO_PINS(167);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DECLARE_MSM_GPIO_PINS(168);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DECLARE_MSM_GPIO_PINS(169);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DECLARE_MSM_GPIO_PINS(170);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DECLARE_MSM_GPIO_PINS(171);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DECLARE_MSM_GPIO_PINS(172);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DECLARE_MSM_GPIO_PINS(173);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DECLARE_MSM_GPIO_PINS(174);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const unsigned int ufs_reset_pins[] = { 175 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const unsigned int sdc2_clk_pins[] = { 176 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const unsigned int sdc2_cmd_pins[] = { 177 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static const unsigned int sdc2_data_pins[] = { 178 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) enum sm8150_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) msm_mux_adsp_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msm_mux_agera_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) msm_mux_aoss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) msm_mux_atest_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msm_mux_atest_char0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msm_mux_atest_char1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msm_mux_atest_char2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msm_mux_atest_char3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) msm_mux_atest_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) msm_mux_atest_usb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msm_mux_atest_usb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msm_mux_atest_usb11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msm_mux_atest_usb12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msm_mux_atest_usb13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msm_mux_atest_usb20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msm_mux_atest_usb21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msm_mux_atest_usb22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) msm_mux_atest_usb23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msm_mux_audio_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msm_mux_btfm_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_mux_cam_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msm_mux_cci_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msm_mux_cci_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msm_mux_cci_timer0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msm_mux_cci_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msm_mux_cci_timer2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) msm_mux_cci_timer3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msm_mux_cci_timer4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msm_mux_cri_trng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msm_mux_cri_trng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msm_mux_cri_trng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msm_mux_dbg_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) msm_mux_ddr_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msm_mux_ddr_pxi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) msm_mux_ddr_pxi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msm_mux_ddr_pxi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msm_mux_ddr_pxi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msm_mux_edp_hot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msm_mux_edp_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msm_mux_emac_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msm_mux_emac_pps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msm_mux_gcc_gp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msm_mux_gcc_gp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msm_mux_gcc_gp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) msm_mux_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) msm_mux_jitter_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msm_mux_hs1_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msm_mux_hs2_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) msm_mux_hs3_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) msm_mux_lpass_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) msm_mux_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) msm_mux_mdp_vsync0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msm_mux_mdp_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msm_mux_mdp_vsync2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msm_mux_mdp_vsync3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) msm_mux_mss_lte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msm_mux_m_voc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) msm_mux_nav_pps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msm_mux_pa_indicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msm_mux_pci_e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msm_mux_pci_e1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msm_mux_phase_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) msm_mux_pll_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) msm_mux_pll_bypassnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) msm_mux_pll_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msm_mux_pri_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msm_mux_pri_mi2s_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msm_mux_prng_rosc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msm_mux_qdss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) msm_mux_qdss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) msm_mux_qlink_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) msm_mux_qlink_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) msm_mux_qspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) msm_mux_qspi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msm_mux_qspi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) msm_mux_qspi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) msm_mux_qspi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) msm_mux_qspi_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msm_mux_qua_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) msm_mux_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) msm_mux_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) msm_mux_qup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msm_mux_qup3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) msm_mux_qup4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) msm_mux_qup5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) msm_mux_qup6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) msm_mux_qup7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msm_mux_qup8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) msm_mux_qup9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) msm_mux_qup10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) msm_mux_qup11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) msm_mux_qup12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) msm_mux_qup13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) msm_mux_qup14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) msm_mux_qup15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) msm_mux_qup16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) msm_mux_qup17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) msm_mux_qup18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) msm_mux_qup19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) msm_mux_qup_l4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) msm_mux_qup_l5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msm_mux_qup_l6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) msm_mux_rgmii,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) msm_mux_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msm_mux_sd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) msm_mux_sec_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msm_mux_spkr_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msm_mux_sp_cmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) msm_mux_ter_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) msm_mux_tgu_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) msm_mux_tgu_ch2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) msm_mux_tgu_ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) msm_mux_tgu_ch3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) msm_mux_tsense_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) msm_mux_tsense_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) msm_mux_tsif1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) msm_mux_tsif2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) msm_mux_uim1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) msm_mux_uim2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) msm_mux_uim_batt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) msm_mux_usb2phy_ac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) msm_mux_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) msm_mux_vfr_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) msm_mux_vsense_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) msm_mux_wlan1_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) msm_mux_wlan1_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) msm_mux_wlan2_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) msm_mux_wlan2_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) msm_mux_wmss_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) msm_mux__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const char * const phase_flag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "gpio18", "gpio19", "gpio20", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "gpio57", "gpio59", "gpio64", "gpio68", "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "gpio79", "gpio80", "gpio90", "gpio91", "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "gpio93", "gpio94", "gpio96", "gpio114", "gpio115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "gpio116", "gpio117", "gpio118", "gpio119", "gpio120",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "gpio121", "gpio122", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "gpio144", "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const char * const emac_pps_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "gpio81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const qup12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "gpio83", "gpio84", "gpio85", "gpio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const char * const qup16_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "gpio83", "gpio84", "gpio85", "gpio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const tsif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "gpio88", "gpio89", "gpio90", "gpio91", "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const char * const qup8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const char * const qspi_cs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "gpio88", "gpio94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const char * const tgu_ch3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const char * const qspi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const char * const mdp_vsync0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const char * const mdp_vsync1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const char * const mdp_vsync2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const char * const mdp_vsync3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const char * const tgu_ch0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const char * const qspi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char * const sdc4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "gpio90", "gpio91", "gpio92", "gpio93", "gpio94", "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const char * const tgu_ch1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const char * const wlan1_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const char * const qspi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const char * const vfr_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const char * const tgu_ch2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const char * const wlan1_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const char * const tsif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const char * const qup11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "gpio92", "gpio93", "gpio94", "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const char * const qspi_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const char * const wlan2_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const char * const qspi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const char * const wlan2_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const char * const sd_write_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const char * const qup7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "gpio98", "gpio99", "gpio100", "gpio101",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char * const ddr_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "gpio98", "gpio99", "gpio145", "gpio146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const char * const ddr_pxi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "gpio98", "gpio101",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const char * const atest_usb13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "gpio99",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const char * const ddr_pxi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "gpio99", "gpio100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const char * const pll_bypassnl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "gpio100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char * const atest_usb12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "gpio100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const char * const pll_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "gpio101",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const char * const pci_e1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "gpio102", "gpio103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const char * const uim2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "gpio105", "gpio106", "gpio107", "gpio108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const char * const uim1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "gpio109", "gpio110", "gpio111", "gpio112",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const char * const uim_batt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const char * const usb2phy_ac_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "gpio113", "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const char * const aoss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const char * const qup1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "gpio114", "gpio115", "gpio116", "gpio117",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const char * const rgmii_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "gpio4", "gpio5", "gpio6", "gpio7", "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "gpio114", "gpio115", "gpio116", "gpio117",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const char * const adsp_ext_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "gpio115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const char * const qup5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const char * const atest_usb22_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const char * const emac_phy_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "gpio124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const char * const hs3_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "gpio125", "gpio165", "gpio166", "gpio167", "gpio168",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const char * const sec_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "gpio126", "gpio127", "gpio128", "gpio129", "gpio130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const char * const qup2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "gpio126", "gpio127", "gpio128", "gpio129",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const char * const jitter_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "gpio129",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const char * const atest_usb21_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "gpio129",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const char * const pll_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "gpio130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const char * const atest_usb20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "gpio130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const char * const atest_char0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "gpio130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const char * const ter_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "gpio131", "gpio132", "gpio133", "gpio134", "gpio135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static const char * const gcc_gp1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) "gpio131", "gpio136",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const char * const atest_char1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "gpio133",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const char * const atest_char2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static const char * const atest_char3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "gpio135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const char * const qua_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "gpio136", "gpio137", "gpio138", "gpio139", "gpio140", "gpio141",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "gpio142",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static const char * const pri_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "gpio143", "gpio144", "gpio146", "gpio147",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const char * const qup3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "gpio144", "gpio145", "gpio146", "gpio147",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const char * const ddr_pxi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "gpio144", "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static const char * const pri_mi2s_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const char * const vsense_trigger_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const char * const atest_usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static const char * const atest_usb11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) "gpio146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const char * const ddr_pxi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "gpio146", "gpio147",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const char * const dbg_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "gpio147",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const char * const atest_usb10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "gpio147",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const char * const spkr_i2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const char * const audio_ref_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) "gpio148",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const char * const lpass_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) "gpio149", "gpio150", "gpio151", "gpio152",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const char * const tsense_pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "gpio150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const char * const tsense_pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) "gpio150",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const char * const btfm_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "gpio153", "gpio154",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const char * const hs1_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "gpio155", "gpio156", "gpio157", "gpio158", "gpio159",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) static const char * const cri_trng0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) "gpio159",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const char * const hs2_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const char * const cri_trng1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "gpio160",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const char * const cri_trng_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) "gpio161",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const char * const sp_cmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "gpio162",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const char * const prng_rosc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "gpio163",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const char * const qup0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) "gpio147", "gpio148", "gpio149", "gpio150", "gpio151", "gpio152",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "gpio153", "gpio154", "gpio155", "gpio156", "gpio157", "gpio158",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) "gpio159", "gpio160", "gpio161", "gpio162", "gpio163", "gpio164",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "gpio165", "gpio166", "gpio167", "gpio168", "gpio169", "gpio170",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) "gpio171", "gpio172", "gpio173", "gpio174",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const char * const qup6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static const char * const qup_l6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "gpio6", "gpio34", "gpio97", "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static const char * const qup_l5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) "gpio7", "gpio33", "gpio82", "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static const char * const mdp_vsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) "gpio8", "gpio9", "gpio10", "gpio81", "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const char * const edp_lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const char * const qup10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "gpio9", "gpio10", "gpio11", "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const char * const m_voc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const char * const edp_hot_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static const char * const cam_mclk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "gpio13", "gpio14", "gpio15", "gpio16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const char * const qdss_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "gpio13", "gpio14", "gpio15", "gpio16", "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "gpio23", "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "gpio33", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "gpio47", "gpio48", "gpio83", "gpio117", "gpio118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "gpio119", "gpio120", "gpio121", "gpio132",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const char * const cci_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "gpio17", "gpio18", "gpio19", "gpio20", "gpio31", "gpio32", "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static const char * const cci_timer0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const char * const gcc_gp2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "gpio21", "gpio137",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const char * const cci_timer1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const char * const gcc_gp3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "gpio22", "gpio138",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const char * const cci_timer2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static const char * const qup18_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "gpio23", "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static const char * const cci_timer3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static const char * const cci_async_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const char * const cci_timer4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const char * const qup15_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "gpio27", "gpio28", "gpio29", "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static const char * const pci_e0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "gpio35", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static const char * const qup_l4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "gpio37", "gpio59", "gpio81", "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const char * const agera_pll_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) static const char * const usb_phy_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "gpio38",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const char * const qup9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const char * const qup13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "gpio43", "gpio44", "gpio45", "gpio46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const char * const qdss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "gpio45", "gpio46", "gpio49", "gpio50", "gpio56", "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const char * const qup14_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "gpio47", "gpio48", "gpio49", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static const char * const qup4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) "gpio51", "gpio52", "gpio53", "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const char * const qup17_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) "gpio55", "gpio56", "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const char * const qup19_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) "gpio55", "gpio56", "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) static const char * const atest_char_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static const char * const nav_pps_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "gpio60", "gpio60", "gpio76", "gpio76", "gpio77", "gpio77", "gpio81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "gpio81", "gpio82", "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const char * const atest_usb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) "gpio60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const char * const qlink_request_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const char * const qlink_enable_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static const char * const wmss_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static const char * const atest_usb23_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static const char * const pa_indicator_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static const char * const mss_lte_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static const struct msm_function sm8150_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) FUNCTION(adsp_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) FUNCTION(agera_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) FUNCTION(aoss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) FUNCTION(ddr_pxi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) FUNCTION(atest_char),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) FUNCTION(atest_char0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) FUNCTION(atest_char1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) FUNCTION(atest_char2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) FUNCTION(atest_char3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) FUNCTION(audio_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) FUNCTION(atest_usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) FUNCTION(atest_usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) FUNCTION(atest_usb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) FUNCTION(atest_usb11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) FUNCTION(atest_usb12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) FUNCTION(atest_usb13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) FUNCTION(atest_usb20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) FUNCTION(atest_usb21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) FUNCTION(atest_usb22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) FUNCTION(atest_usb23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) FUNCTION(btfm_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) FUNCTION(cam_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) FUNCTION(cci_async),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) FUNCTION(cci_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) FUNCTION(cci_timer0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) FUNCTION(cci_timer1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) FUNCTION(cci_timer2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) FUNCTION(cci_timer3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) FUNCTION(cci_timer4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) FUNCTION(cri_trng),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) FUNCTION(cri_trng0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) FUNCTION(cri_trng1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) FUNCTION(dbg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) FUNCTION(ddr_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) FUNCTION(ddr_pxi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) FUNCTION(ddr_pxi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) FUNCTION(ddr_pxi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) FUNCTION(edp_hot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) FUNCTION(edp_lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) FUNCTION(emac_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) FUNCTION(emac_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) FUNCTION(gcc_gp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) FUNCTION(gcc_gp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) FUNCTION(gcc_gp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) FUNCTION(hs1_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) FUNCTION(hs2_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) FUNCTION(hs3_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) FUNCTION(jitter_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) FUNCTION(lpass_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) FUNCTION(mdp_vsync0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) FUNCTION(mdp_vsync1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) FUNCTION(mdp_vsync2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) FUNCTION(mdp_vsync3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) FUNCTION(mss_lte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) FUNCTION(m_voc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) FUNCTION(nav_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) FUNCTION(pa_indicator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) FUNCTION(pci_e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) FUNCTION(phase_flag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) FUNCTION(pll_bypassnl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) FUNCTION(pll_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) FUNCTION(pci_e1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) FUNCTION(pll_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) FUNCTION(pri_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) FUNCTION(pri_mi2s_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) FUNCTION(prng_rosc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) FUNCTION(qdss),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) FUNCTION(qdss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) FUNCTION(qlink_request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) FUNCTION(qlink_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) FUNCTION(qspi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) FUNCTION(qspi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) FUNCTION(qspi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) FUNCTION(qspi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) FUNCTION(qspi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) FUNCTION(qspi_cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) FUNCTION(qua_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) FUNCTION(qup0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) FUNCTION(qup1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) FUNCTION(qup2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) FUNCTION(qup3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) FUNCTION(qup4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) FUNCTION(qup5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) FUNCTION(qup6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) FUNCTION(qup7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) FUNCTION(qup8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) FUNCTION(qup9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) FUNCTION(qup10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) FUNCTION(qup11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) FUNCTION(qup12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) FUNCTION(qup13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) FUNCTION(qup14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) FUNCTION(qup15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) FUNCTION(qup16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) FUNCTION(qup17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) FUNCTION(qup18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) FUNCTION(qup19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) FUNCTION(qup_l4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) FUNCTION(qup_l5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) FUNCTION(qup_l6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) FUNCTION(rgmii),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) FUNCTION(sdc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) FUNCTION(sd_write),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) FUNCTION(sec_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) FUNCTION(spkr_i2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) FUNCTION(sp_cmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) FUNCTION(ter_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) FUNCTION(tgu_ch0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) FUNCTION(tgu_ch1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) FUNCTION(tgu_ch2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) FUNCTION(tgu_ch3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) FUNCTION(tsense_pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) FUNCTION(tsense_pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) FUNCTION(tsif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) FUNCTION(tsif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) FUNCTION(uim1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) FUNCTION(uim2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) FUNCTION(uim_batt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) FUNCTION(usb2phy_ac),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) FUNCTION(usb_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) FUNCTION(vfr_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) FUNCTION(vsense_trigger),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) FUNCTION(wlan1_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) FUNCTION(wlan1_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) FUNCTION(wlan2_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) FUNCTION(wlan2_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) FUNCTION(wmss_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * Every pin is maintained as a single group, and missing or non-existing pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * would be maintained as dummy group to synchronize pin group index with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * pin descriptor registered with pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Clients would not be able to request these dummy pin groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static const struct msm_pingroup sm8150_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) [0] = PINGROUP(0, SOUTH, qup0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) [1] = PINGROUP(1, SOUTH, qup0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) [2] = PINGROUP(2, SOUTH, qup0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) [3] = PINGROUP(3, SOUTH, qup0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) [4] = PINGROUP(4, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) [5] = PINGROUP(5, SOUTH, qup6, rgmii, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) [6] = PINGROUP(6, SOUTH, qup6, rgmii, qup_l6, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) [7] = PINGROUP(7, SOUTH, qup6, rgmii, qup_l5, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) [8] = PINGROUP(8, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) [9] = PINGROUP(9, NORTH, mdp_vsync, edp_lcd, qup10, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) [10] = PINGROUP(10, NORTH, mdp_vsync, m_voc, edp_hot, qup10, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) [11] = PINGROUP(11, NORTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) [12] = PINGROUP(12, NORTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) [13] = PINGROUP(13, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) [14] = PINGROUP(14, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) [15] = PINGROUP(15, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) [16] = PINGROUP(16, NORTH, cam_mclk, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) [17] = PINGROUP(17, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) [18] = PINGROUP(18, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) [19] = PINGROUP(19, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) [20] = PINGROUP(20, NORTH, cci_i2c, phase_flag, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) [21] = PINGROUP(21, EAST, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) [22] = PINGROUP(22, EAST, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) [23] = PINGROUP(23, EAST, cci_timer2, qup18, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) [24] = PINGROUP(24, EAST, cci_timer3, cci_async, qup18, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) [25] = PINGROUP(25, EAST, cci_timer4, cci_async, qup18, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) [26] = PINGROUP(26, EAST, cci_async, qup18, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) [27] = PINGROUP(27, EAST, qup15, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) [28] = PINGROUP(28, EAST, qup15, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) [29] = PINGROUP(29, EAST, qup15, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) [30] = PINGROUP(30, EAST, qup15, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) [31] = PINGROUP(31, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) [32] = PINGROUP(32, NORTH, cci_i2c, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) [33] = PINGROUP(33, NORTH, cci_i2c, qup_l5, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) [34] = PINGROUP(34, NORTH, cci_i2c, qup_l6, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) [35] = PINGROUP(35, NORTH, pci_e0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) [36] = PINGROUP(36, NORTH, pci_e0, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) [37] = PINGROUP(37, NORTH, qup_l4, agera_pll, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) [38] = PINGROUP(38, SOUTH, usb_phy, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) [39] = PINGROUP(39, NORTH, qup9, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) [40] = PINGROUP(40, NORTH, qup9, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) [41] = PINGROUP(41, NORTH, qup9, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) [42] = PINGROUP(42, NORTH, qup9, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) [43] = PINGROUP(43, EAST, qup13, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) [44] = PINGROUP(44, EAST, qup13, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) [45] = PINGROUP(45, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) [46] = PINGROUP(46, EAST, qup13, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) [47] = PINGROUP(47, EAST, qup14, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) [48] = PINGROUP(48, EAST, qup14, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) [49] = PINGROUP(49, EAST, qup14, _, qdss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) [50] = PINGROUP(50, EAST, qup14, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) [51] = PINGROUP(51, SOUTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) [52] = PINGROUP(52, SOUTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) [53] = PINGROUP(53, SOUTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) [54] = PINGROUP(54, SOUTH, qup4, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) [55] = PINGROUP(55, SOUTH, qup17, qup19, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) [56] = PINGROUP(56, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) [57] = PINGROUP(57, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) [58] = PINGROUP(58, SOUTH, qup17, qup19, qdss_cti, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) [59] = PINGROUP(59, SOUTH, rgmii, qup_l4, phase_flag, _, atest_char, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) [60] = PINGROUP(60, SOUTH, _, nav_pps, nav_pps, atest_usb2, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) [61] = PINGROUP(61, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) [62] = PINGROUP(62, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) [63] = PINGROUP(63, SOUTH, wmss_reset, atest_usb23, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) [64] = PINGROUP(64, SOUTH, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) [65] = PINGROUP(65, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) [66] = PINGROUP(66, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) [67] = PINGROUP(67, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) [68] = PINGROUP(68, SOUTH, _, pa_indicator, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) [69] = PINGROUP(69, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) [70] = PINGROUP(70, SOUTH, mss_lte, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) [71] = PINGROUP(71, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) [72] = PINGROUP(72, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) [73] = PINGROUP(73, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) [74] = PINGROUP(74, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) [75] = PINGROUP(75, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) [76] = PINGROUP(76, SOUTH, _, _, _, nav_pps, nav_pps, phase_flag, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) [77] = PINGROUP(77, SOUTH, _, _, _, nav_pps, nav_pps, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) [78] = PINGROUP(78, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) [79] = PINGROUP(79, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) [80] = PINGROUP(80, SOUTH, _, _, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) [81] = PINGROUP(81, SOUTH, _, _, _, nav_pps, nav_pps, qup_l4, mdp_vsync, emac_pps, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) [82] = PINGROUP(82, SOUTH, _, _, _, nav_pps, nav_pps, qup_l5, mdp_vsync, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) [83] = PINGROUP(83, NORTH, qup12, qup16, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) [84] = PINGROUP(84, NORTH, qup12, qup16, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) [85] = PINGROUP(85, NORTH, qup12, qup16, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) [86] = PINGROUP(86, NORTH, qup12, qup16, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) [87] = PINGROUP(87, EAST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) [88] = PINGROUP(88, NORTH, tsif1, qup8, qspi_cs, tgu_ch3, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) [89] = PINGROUP(89, NORTH, tsif1, qup8, qspi0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) [90] = PINGROUP(90, NORTH, tsif1, qup8, qspi1, sdc4, phase_flag, tgu_ch1, _, _, wlan1_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) [91] = PINGROUP(91, NORTH, tsif1, qup8, qspi2, sdc4, vfr_1, phase_flag, tgu_ch2, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) [92] = PINGROUP(92, NORTH, tsif2, qup11, qspi_clk, sdc4, phase_flag, _, wlan2_adc1, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) [93] = PINGROUP(93, NORTH, tsif2, qup11, qspi3, sdc4, phase_flag, _, wlan2_adc0, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) [94] = PINGROUP(94, NORTH, tsif2, qup11, qspi_cs, sdc4, phase_flag, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) [95] = PINGROUP(95, NORTH, tsif2, qup11, sdc4, qup_l4, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) [96] = PINGROUP(96, NORTH, tsif2, qup_l5, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) [97] = PINGROUP(97, NORTH, sd_write, tsif1, qup_l6, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) [98] = PINGROUP(98, SOUTH, qup7, ddr_bist, ddr_pxi3, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) [99] = PINGROUP(99, SOUTH, qup7, ddr_bist, atest_usb13, ddr_pxi1, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) [100] = PINGROUP(100, SOUTH, qup7, pll_bypassnl, atest_usb12, ddr_pxi1, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) [101] = PINGROUP(101, SOUTH, qup7, pll_reset, ddr_pxi3, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) [102] = PINGROUP(102, NORTH, pci_e1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) [103] = PINGROUP(103, NORTH, pci_e1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) [104] = PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) [105] = PINGROUP(105, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) [106] = PINGROUP(106, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) [107] = PINGROUP(107, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) [108] = PINGROUP(108, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) [109] = PINGROUP(109, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) [110] = PINGROUP(110, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) [111] = PINGROUP(111, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) [112] = PINGROUP(112, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) [113] = PINGROUP(113, WEST, uim_batt, usb2phy_ac, aoss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) [114] = PINGROUP(114, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) [115] = PINGROUP(115, SOUTH, qup1, rgmii, phase_flag, adsp_ext, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) [116] = PINGROUP(116, SOUTH, qup1, rgmii, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) [117] = PINGROUP(117, SOUTH, qup1, rgmii, phase_flag, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) [118] = PINGROUP(118, SOUTH, rgmii, phase_flag, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) [119] = PINGROUP(119, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) [120] = PINGROUP(120, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) [121] = PINGROUP(121, SOUTH, qup5, rgmii, phase_flag, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) [122] = PINGROUP(122, SOUTH, qup5, rgmii, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) [123] = PINGROUP(123, SOUTH, usb2phy_ac, qup_l6, atest_usb22, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) [124] = PINGROUP(124, SOUTH, emac_phy, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) [125] = PINGROUP(125, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) [126] = PINGROUP(126, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) [127] = PINGROUP(127, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) [128] = PINGROUP(128, SOUTH, sec_mi2s, qup2, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) [129] = PINGROUP(129, SOUTH, sec_mi2s, qup2, jitter_bist, atest_usb21, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) [130] = PINGROUP(130, SOUTH, sec_mi2s, pll_bist, atest_usb20, atest_char0, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) [131] = PINGROUP(131, SOUTH, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) [132] = PINGROUP(132, SOUTH, ter_mi2s, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) [133] = PINGROUP(133, SOUTH, ter_mi2s, qdss, atest_char1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) [134] = PINGROUP(134, SOUTH, ter_mi2s, qdss, atest_char2, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) [135] = PINGROUP(135, SOUTH, ter_mi2s, atest_char3, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) [136] = PINGROUP(136, SOUTH, qua_mi2s, gcc_gp1, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) [137] = PINGROUP(137, SOUTH, qua_mi2s, gcc_gp2, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) [138] = PINGROUP(138, SOUTH, qua_mi2s, gcc_gp3, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) [139] = PINGROUP(139, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) [140] = PINGROUP(140, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) [141] = PINGROUP(141, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) [142] = PINGROUP(142, SOUTH, qua_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) [143] = PINGROUP(143, SOUTH, pri_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) [144] = PINGROUP(144, SOUTH, pri_mi2s, qup3, phase_flag, _, ddr_pxi0, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) [145] = PINGROUP(145, SOUTH, pri_mi2s_ws, qup3, phase_flag, ddr_bist, _, vsense_trigger, atest_usb1, ddr_pxi0, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) [146] = PINGROUP(146, SOUTH, pri_mi2s, qup3, ddr_bist, atest_usb11, ddr_pxi2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) [147] = PINGROUP(147, SOUTH, pri_mi2s, qup3, dbg_out, atest_usb10, ddr_pxi2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) [148] = PINGROUP(148, SOUTH, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) [149] = PINGROUP(149, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) [150] = PINGROUP(150, SOUTH, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) [151] = PINGROUP(151, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) [152] = PINGROUP(152, SOUTH, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) [153] = PINGROUP(153, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) [154] = PINGROUP(154, SOUTH, btfm_slimbus, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) [155] = PINGROUP(155, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) [156] = PINGROUP(156, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) [157] = PINGROUP(157, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) [158] = PINGROUP(158, WEST, hs1_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) [159] = PINGROUP(159, WEST, hs1_mi2s, cri_trng0, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) [160] = PINGROUP(160, WEST, hs2_mi2s, cri_trng1, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) [161] = PINGROUP(161, WEST, hs2_mi2s, cri_trng, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) [162] = PINGROUP(162, WEST, hs2_mi2s, sp_cmu, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) [163] = PINGROUP(163, WEST, hs2_mi2s, prng_rosc, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) [164] = PINGROUP(164, WEST, hs2_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) [165] = PINGROUP(165, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) [166] = PINGROUP(166, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) [167] = PINGROUP(167, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) [168] = PINGROUP(168, WEST, hs3_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) [169] = PINGROUP(169, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) [170] = PINGROUP(170, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) [171] = PINGROUP(171, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) [172] = PINGROUP(172, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) [173] = PINGROUP(173, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) [174] = PINGROUP(174, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) [175] = UFS_RESET(ufs_reset, 0xB6000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) [176] = SDC_QDSD_PINGROUP(sdc2_clk, 0xB2000, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) [177] = SDC_QDSD_PINGROUP(sdc2_cmd, 0xB2000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) [178] = SDC_QDSD_PINGROUP(sdc2_data, 0xB2000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static const struct msm_pinctrl_soc_data sm8150_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .pins = sm8150_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .npins = ARRAY_SIZE(sm8150_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .functions = sm8150_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .nfunctions = ARRAY_SIZE(sm8150_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .groups = sm8150_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .ngroups = ARRAY_SIZE(sm8150_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .ngpios = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .tiles = sm8150_tiles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .ntiles = ARRAY_SIZE(sm8150_tiles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static int sm8150_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return msm_pinctrl_probe(pdev, &sm8150_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static const struct of_device_id sm8150_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) { .compatible = "qcom,sm8150-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static struct platform_driver sm8150_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .name = "sm8150-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .of_match_table = sm8150_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .probe = sm8150_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static int __init sm8150_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return platform_driver_register(&sm8150_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) arch_initcall(sm8150_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static void __exit sm8150_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) platform_driver_unregister(&sm8150_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) module_exit(sm8150_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) MODULE_DESCRIPTION("QTI sm8150 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) MODULE_DEVICE_TABLE(of, sm8150_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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