^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) [msm_mux_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NORTH 0x00500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SOUTH 0x00900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EAST 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .npins = ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) msm_mux_gpio, /* gpio mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) msm_mux_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) msm_mux_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) msm_mux_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) msm_mux_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) msm_mux_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) msm_mux_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) msm_mux_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) msm_mux_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) msm_mux_##f9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) msm_mux_##f10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .nfuncs = 11, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .ctl_reg = base + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .io_reg = base + 0x4 + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .intr_status_reg = base + 0xc + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .intr_target_reg = base + 0x8 + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .intr_target_kpss_val = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define UFS_RESET(pg_name, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .ctl_reg = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .io_reg = offset + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .pull_bit = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .drv_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .out_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct pinctrl_pin_desc sdm845_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(114, "GPIO_114"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(115, "GPIO_115"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(116, "GPIO_116"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(117, "GPIO_117"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(118, "GPIO_118"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(119, "GPIO_119"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(120, "GPIO_120"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(121, "GPIO_121"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(122, "GPIO_122"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(123, "GPIO_123"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(124, "GPIO_124"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(125, "GPIO_125"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(126, "GPIO_126"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(127, "GPIO_127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(128, "GPIO_128"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(129, "GPIO_129"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(130, "GPIO_130"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(131, "GPIO_131"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(132, "GPIO_132"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(133, "GPIO_133"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(134, "GPIO_134"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(135, "GPIO_135"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(136, "GPIO_136"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(137, "GPIO_137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(138, "GPIO_138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(139, "GPIO_139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(140, "GPIO_140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(141, "GPIO_141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(142, "GPIO_142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(143, "GPIO_143"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(144, "GPIO_144"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(145, "GPIO_145"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(146, "GPIO_146"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(147, "GPIO_147"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(148, "GPIO_148"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(149, "GPIO_149"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(150, "UFS_RESET"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(151, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(152, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(153, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DECLARE_MSM_GPIO_PINS(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DECLARE_MSM_GPIO_PINS(114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DECLARE_MSM_GPIO_PINS(115);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DECLARE_MSM_GPIO_PINS(116);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DECLARE_MSM_GPIO_PINS(117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DECLARE_MSM_GPIO_PINS(118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DECLARE_MSM_GPIO_PINS(119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DECLARE_MSM_GPIO_PINS(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DECLARE_MSM_GPIO_PINS(121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DECLARE_MSM_GPIO_PINS(122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DECLARE_MSM_GPIO_PINS(123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DECLARE_MSM_GPIO_PINS(124);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DECLARE_MSM_GPIO_PINS(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DECLARE_MSM_GPIO_PINS(126);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DECLARE_MSM_GPIO_PINS(127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DECLARE_MSM_GPIO_PINS(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DECLARE_MSM_GPIO_PINS(129);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DECLARE_MSM_GPIO_PINS(130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DECLARE_MSM_GPIO_PINS(131);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DECLARE_MSM_GPIO_PINS(132);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DECLARE_MSM_GPIO_PINS(133);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DECLARE_MSM_GPIO_PINS(134);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DECLARE_MSM_GPIO_PINS(135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECLARE_MSM_GPIO_PINS(136);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DECLARE_MSM_GPIO_PINS(137);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DECLARE_MSM_GPIO_PINS(138);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DECLARE_MSM_GPIO_PINS(139);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DECLARE_MSM_GPIO_PINS(140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DECLARE_MSM_GPIO_PINS(141);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DECLARE_MSM_GPIO_PINS(142);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DECLARE_MSM_GPIO_PINS(143);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DECLARE_MSM_GPIO_PINS(144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DECLARE_MSM_GPIO_PINS(145);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DECLARE_MSM_GPIO_PINS(146);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DECLARE_MSM_GPIO_PINS(147);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DECLARE_MSM_GPIO_PINS(148);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DECLARE_MSM_GPIO_PINS(149);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const unsigned int ufs_reset_pins[] = { 150 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const unsigned int sdc2_clk_pins[] = { 151 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const unsigned int sdc2_cmd_pins[] = { 152 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static const unsigned int sdc2_data_pins[] = { 153 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) enum sdm845_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msm_mux_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msm_mux_adsp_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msm_mux_agera_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) msm_mux_atest_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msm_mux_atest_tsens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msm_mux_atest_tsens2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msm_mux_atest_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msm_mux_atest_usb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) msm_mux_atest_usb11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msm_mux_atest_usb12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msm_mux_atest_usb13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) msm_mux_atest_usb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) msm_mux_atest_usb20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msm_mux_atest_usb21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msm_mux_atest_usb22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) msm_mux_atest_usb23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) msm_mux_audio_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) msm_mux_btfm_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msm_mux_cam_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) msm_mux_cci_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msm_mux_cci_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msm_mux_cci_timer0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) msm_mux_cci_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) msm_mux_cci_timer2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) msm_mux_cci_timer3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msm_mux_cci_timer4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msm_mux_cri_trng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msm_mux_cri_trng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msm_mux_cri_trng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msm_mux_dbg_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) msm_mux_ddr_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msm_mux_ddr_pxi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msm_mux_ddr_pxi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msm_mux_ddr_pxi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msm_mux_ddr_pxi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) msm_mux_edp_hot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) msm_mux_edp_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msm_mux_gcc_gp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msm_mux_gcc_gp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msm_mux_gcc_gp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msm_mux_jitter_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msm_mux_ldo_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msm_mux_ldo_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msm_mux_lpass_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msm_mux_m_voc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msm_mux_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msm_mux_mdp_vsync0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) msm_mux_mdp_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) msm_mux_mdp_vsync2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) msm_mux_mdp_vsync3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) msm_mux_mss_lte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) msm_mux_nav_pps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) msm_mux_pa_indicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) msm_mux_pci_e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) msm_mux_pci_e1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) msm_mux_phase_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) msm_mux_pll_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) msm_mux_pll_bypassnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) msm_mux_pll_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) msm_mux_pri_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) msm_mux_pri_mi2s_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msm_mux_prng_rosc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) msm_mux_qdss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) msm_mux_qdss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msm_mux_qlink_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msm_mux_qlink_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msm_mux_qspi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msm_mux_qspi_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) msm_mux_qspi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) msm_mux_qua_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msm_mux_qup0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msm_mux_qup1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msm_mux_qup10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msm_mux_qup11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msm_mux_qup12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msm_mux_qup13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msm_mux_qup14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) msm_mux_qup15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msm_mux_qup2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msm_mux_qup3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_mux_qup4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msm_mux_qup5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msm_mux_qup6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msm_mux_qup7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msm_mux_qup8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msm_mux_qup9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) msm_mux_qup_l4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msm_mux_qup_l5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msm_mux_qup_l6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msm_mux_sd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msm_mux_sdc4_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msm_mux_sdc4_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) msm_mux_sdc4_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msm_mux_sec_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) msm_mux_sp_cmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msm_mux_spkr_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msm_mux_ter_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msm_mux_tgu_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msm_mux_tgu_ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msm_mux_tgu_ch2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msm_mux_tgu_ch3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msm_mux_tsense_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msm_mux_tsense_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msm_mux_tsif1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) msm_mux_tsif1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) msm_mux_tsif1_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msm_mux_tsif1_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msm_mux_tsif1_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) msm_mux_tsif2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) msm_mux_tsif2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) msm_mux_tsif2_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) msm_mux_tsif2_error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msm_mux_tsif2_sync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msm_mux_uim1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msm_mux_uim1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) msm_mux_uim1_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msm_mux_uim1_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) msm_mux_uim2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msm_mux_uim2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msm_mux_uim2_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msm_mux_uim2_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msm_mux_uim_batt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) msm_mux_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) msm_mux_vfr_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) msm_mux_vsense_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msm_mux_wlan1_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msm_mux_wlan1_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msm_mux_wlan2_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msm_mux_wlan2_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) msm_mux__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const char * const ddr_pxi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "gpio12", "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const char * const cam_mclk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "gpio13", "gpio14", "gpio15", "gpio16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const char * const pll_bypassnl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const char * const qdss_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "gpio123", "gpio124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const char * const pll_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const char * const cci_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "gpio17", "gpio18", "gpio19", "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const char * const qup1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "gpio17", "gpio18", "gpio19", "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static const char * const cci_timer0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char * const gcc_gp2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "gpio21", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static const char * const cci_timer1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const char * const gcc_gp3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "gpio22", "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const char * const cci_timer2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const char * const cci_timer3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const char * const cci_async_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const char * const cci_timer4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const char * const qup2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "gpio27", "gpio28", "gpio29", "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const char * const phase_flag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "gpio29", "gpio30", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "gpio64", "gpio74", "gpio75", "gpio76", "gpio77", "gpio89", "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "gpio96", "gpio99", "gpio100", "gpio103", "gpio137", "gpio138",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "gpio139", "gpio140", "gpio141", "gpio142", "gpio143",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static const char * const qup11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "gpio31", "gpio32", "gpio33", "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static const char * const qup14_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "gpio31", "gpio32", "gpio33", "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const char * const pci_e0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "gpio35", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const char * const jitter_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const pll_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const char * const atest_tsens_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const char * const agera_pll_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char * const usb_phy_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) "gpio38",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const char * const lpass_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "gpio39", "gpio70", "gpio71", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const char * const sd_write_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) "gpio40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const char * const tsif1_error_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "gpio40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const char * const qup3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "gpio41", "gpio42", "gpio43", "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static const char * const qup6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "gpio45", "gpio46", "gpio47", "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const char * const qup12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "gpio49", "gpio50", "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const char * const qup10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const char * const qua_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static const char * const gcc_gp1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "gpio57", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static const char * const cri_trng0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "gpio60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const char * const cri_trng1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static const char * const cri_trng_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static const char * const pri_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "gpio64", "gpio65", "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const char * const sp_cmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) static const char * const qup8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "gpio65", "gpio66", "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static const char * const pri_mi2s_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static const char * const spkr_i2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "gpio69", "gpio70", "gpio71", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const char * const audio_ref_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) "gpio69",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const char * const tsense_pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const char * const tsense_pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static const char * const btfm_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "gpio73", "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const char * const atest_usb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "gpio73",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const char * const ter_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const char * const atest_usb23_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const char * const atest_usb22_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "gpio75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const char * const atest_usb21_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const char * const atest_usb20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const char * const sec_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const char * const qup15_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const char * const qup5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "gpio85", "gpio86", "gpio87", "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const char * const tsif1_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const char * const qup4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "gpio89", "gpio90", "gpio91", "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const char * const qspi_cs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "gpio89", "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const char * const tgu_ch3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char * const tsif1_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const char * const mdp_vsync0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const char * const mdp_vsync1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const char * const mdp_vsync2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const char * const mdp_vsync3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const char * const tgu_ch0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const char * const tsif1_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const char * const sdc4_cmd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const char * const qspi_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) "gpio91", "gpio92", "gpio93", "gpio94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const char * const tgu_ch1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static const char * const tsif2_error_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const char * const sdc4_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "gpio94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static const char * const vfr_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static const char * const tgu_ch2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const char * const tsif2_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static const char * const sdc4_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static const char * const qup7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "gpio93", "gpio94", "gpio95", "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static const char * const tsif2_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "gpio94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static const char * const tsif2_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static const char * const qspi_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static const char * const tsif2_sync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static const char * const ldo_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static const char * const ldo_update_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const char * const pci_e1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "gpio102", "gpio103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const char * const prng_rosc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "gpio102",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static const char * const uim2_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "gpio105",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const char * const qup13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "gpio105", "gpio106", "gpio107", "gpio108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const char * const uim2_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "gpio106",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const char * const uim2_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "gpio107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const char * const uim2_present_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "gpio108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const char * const uim1_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const char * const uim1_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const char * const uim1_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "gpio111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static const char * const uim1_present_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "gpio112",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static const char * const uim_batt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const char * const edp_hot_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const char * const nav_pps_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "gpio114", "gpio114", "gpio115", "gpio115", "gpio128", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "gpio129", "gpio129", "gpio143", "gpio143",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const char * const atest_char_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const char * const adsp_ext_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "gpio118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const char * const qlink_request_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "gpio130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const char * const qlink_enable_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "gpio131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const char * const pa_indicator_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "gpio135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const char * const mss_lte_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "gpio144", "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const char * const qup0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "gpio147", "gpio148", "gpio149",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const char * const qup9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const char * const qdss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "gpio4", "gpio5", "gpio51", "gpio52", "gpio62", "gpio63", "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const char * const ddr_pxi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const char * const ddr_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) "gpio7", "gpio8", "gpio9", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const char * const atest_tsens2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const char * const vsense_trigger_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const char * const atest_usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const char * const qup_l4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) "gpio8", "gpio35", "gpio105", "gpio123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const char * const wlan1_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static const char * const atest_usb13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const char * const ddr_pxi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) "gpio8", "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const char * const qup_l5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "gpio9", "gpio36", "gpio106", "gpio124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const char * const wlan1_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const char * const atest_usb12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const char * const mdp_vsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) "gpio10", "gpio11", "gpio12", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const char * const qup_l6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) "gpio10", "gpio37", "gpio107", "gpio125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static const char * const wlan2_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const char * const atest_usb11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const char * const ddr_pxi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const char * const edp_lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const char * const dbg_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const char * const wlan2_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const char * const atest_usb10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const char * const m_voc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const char * const tsif1_sync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const struct msm_function sdm845_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) FUNCTION(adsp_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) FUNCTION(agera_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) FUNCTION(atest_char),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) FUNCTION(atest_tsens),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) FUNCTION(atest_tsens2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) FUNCTION(atest_usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) FUNCTION(atest_usb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) FUNCTION(atest_usb11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) FUNCTION(atest_usb12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) FUNCTION(atest_usb13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) FUNCTION(atest_usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) FUNCTION(atest_usb20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) FUNCTION(atest_usb21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) FUNCTION(atest_usb22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) FUNCTION(atest_usb23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) FUNCTION(audio_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) FUNCTION(btfm_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) FUNCTION(cam_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) FUNCTION(cci_async),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) FUNCTION(cci_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) FUNCTION(cci_timer0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) FUNCTION(cci_timer1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) FUNCTION(cci_timer2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) FUNCTION(cci_timer3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) FUNCTION(cci_timer4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) FUNCTION(cri_trng),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) FUNCTION(cri_trng0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) FUNCTION(cri_trng1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) FUNCTION(dbg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) FUNCTION(ddr_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) FUNCTION(ddr_pxi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) FUNCTION(ddr_pxi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) FUNCTION(ddr_pxi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) FUNCTION(ddr_pxi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) FUNCTION(edp_hot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) FUNCTION(edp_lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) FUNCTION(gcc_gp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) FUNCTION(gcc_gp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) FUNCTION(gcc_gp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) FUNCTION(jitter_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) FUNCTION(ldo_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) FUNCTION(ldo_update),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) FUNCTION(lpass_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) FUNCTION(m_voc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) FUNCTION(mdp_vsync0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) FUNCTION(mdp_vsync1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) FUNCTION(mdp_vsync2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) FUNCTION(mdp_vsync3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) FUNCTION(mss_lte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) FUNCTION(nav_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) FUNCTION(pa_indicator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) FUNCTION(pci_e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) FUNCTION(pci_e1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) FUNCTION(phase_flag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) FUNCTION(pll_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) FUNCTION(pll_bypassnl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) FUNCTION(pll_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) FUNCTION(pri_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) FUNCTION(pri_mi2s_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) FUNCTION(prng_rosc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) FUNCTION(qdss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) FUNCTION(qdss),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) FUNCTION(qlink_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) FUNCTION(qlink_request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) FUNCTION(qspi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) FUNCTION(qspi_cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) FUNCTION(qspi_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) FUNCTION(qua_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) FUNCTION(qup0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) FUNCTION(qup1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) FUNCTION(qup10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) FUNCTION(qup11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) FUNCTION(qup12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) FUNCTION(qup13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) FUNCTION(qup14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) FUNCTION(qup15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) FUNCTION(qup2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) FUNCTION(qup3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) FUNCTION(qup4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) FUNCTION(qup5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) FUNCTION(qup6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) FUNCTION(qup7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) FUNCTION(qup8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) FUNCTION(qup9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) FUNCTION(qup_l4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) FUNCTION(qup_l5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) FUNCTION(qup_l6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) FUNCTION(sd_write),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) FUNCTION(sdc4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) FUNCTION(sdc4_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) FUNCTION(sdc4_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) FUNCTION(sec_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) FUNCTION(sp_cmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) FUNCTION(spkr_i2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) FUNCTION(ter_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) FUNCTION(tgu_ch0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) FUNCTION(tgu_ch1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) FUNCTION(tgu_ch2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) FUNCTION(tgu_ch3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) FUNCTION(tsense_pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) FUNCTION(tsense_pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) FUNCTION(tsif1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) FUNCTION(tsif1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) FUNCTION(tsif1_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) FUNCTION(tsif1_error),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) FUNCTION(tsif1_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) FUNCTION(tsif2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) FUNCTION(tsif2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) FUNCTION(tsif2_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) FUNCTION(tsif2_error),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) FUNCTION(tsif2_sync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) FUNCTION(uim1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) FUNCTION(uim1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) FUNCTION(uim1_present),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) FUNCTION(uim1_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) FUNCTION(uim2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) FUNCTION(uim2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) FUNCTION(uim2_present),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) FUNCTION(uim2_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) FUNCTION(uim_batt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) FUNCTION(usb_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) FUNCTION(vfr_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) FUNCTION(vsense_trigger),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) FUNCTION(wlan1_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) FUNCTION(wlan1_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) FUNCTION(wlan2_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) FUNCTION(wlan2_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Every pin is maintained as a single group, and missing or non-existing pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * would be maintained as dummy group to synchronize pin group index with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * pin descriptor registered with pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * Clients would not be able to request these dummy pin groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static const struct msm_pingroup sdm845_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) PINGROUP(0, EAST, qup0, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) PINGROUP(1, EAST, qup0, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) PINGROUP(2, EAST, qup0, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) PINGROUP(3, EAST, qup0, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) PINGROUP(4, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) PINGROUP(5, NORTH, qup9, qdss_cti, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) PINGROUP(6, NORTH, qup9, _, ddr_pxi0, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) PINGROUP(7, NORTH, qup9, ddr_bist, _, atest_tsens2, vsense_trigger, atest_usb1, ddr_pxi0, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) PINGROUP(8, EAST, qup_l4, _, ddr_bist, _, _, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) PINGROUP(9, EAST, qup_l5, ddr_bist, _, wlan1_adc0, atest_usb12, ddr_pxi1, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) PINGROUP(10, EAST, mdp_vsync, qup_l6, ddr_bist, wlan2_adc1, atest_usb11, ddr_pxi2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) PINGROUP(11, EAST, mdp_vsync, edp_lcd, dbg_out, wlan2_adc0, atest_usb10, ddr_pxi2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) PINGROUP(12, SOUTH, mdp_vsync, m_voc, tsif1_sync, ddr_pxi3, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, ddr_pxi3, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) PINGROUP(15, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) PINGROUP(16, SOUTH, cam_mclk, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) PINGROUP(17, SOUTH, cci_i2c, qup1, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PINGROUP(18, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) PINGROUP(19, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) PINGROUP(20, SOUTH, cci_i2c, qup1, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) PINGROUP(21, SOUTH, cci_timer0, gcc_gp2, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) PINGROUP(22, SOUTH, cci_timer1, gcc_gp3, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) PINGROUP(23, SOUTH, cci_timer2, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) PINGROUP(25, SOUTH, cci_timer4, cci_async, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) PINGROUP(26, SOUTH, cci_async, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) PINGROUP(27, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) PINGROUP(28, EAST, qup2, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) PINGROUP(29, EAST, qup2, _, phase_flag, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) PINGROUP(30, EAST, qup2, phase_flag, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) PINGROUP(31, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) PINGROUP(32, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) PINGROUP(33, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) PINGROUP(34, NORTH, qup11, qup14, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) PINGROUP(35, SOUTH, pci_e0, qup_l4, jitter_bist, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) PINGROUP(36, SOUTH, pci_e0, qup_l5, pll_bist, _, atest_tsens, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) PINGROUP(37, SOUTH, qup_l6, agera_pll, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) PINGROUP(38, NORTH, usb_phy, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) PINGROUP(39, EAST, lpass_slimbus, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PINGROUP(40, SOUTH, sd_write, tsif1_error, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) PINGROUP(41, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) PINGROUP(42, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) PINGROUP(43, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) PINGROUP(44, EAST, qup3, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) PINGROUP(45, EAST, qup6, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) PINGROUP(46, EAST, qup6, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) PINGROUP(47, EAST, qup6, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) PINGROUP(48, EAST, qup6, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) PINGROUP(49, NORTH, qup12, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PINGROUP(50, NORTH, qup12, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) PINGROUP(51, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) PINGROUP(52, NORTH, qup12, phase_flag, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) PINGROUP(53, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) PINGROUP(54, NORTH, qup10, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) PINGROUP(55, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) PINGROUP(56, NORTH, qup10, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) PINGROUP(57, NORTH, qua_mi2s, gcc_gp1, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) PINGROUP(58, NORTH, qua_mi2s, gcc_gp2, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) PINGROUP(59, NORTH, qua_mi2s, gcc_gp3, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) PINGROUP(60, NORTH, qua_mi2s, cri_trng0, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) PINGROUP(61, NORTH, qua_mi2s, cri_trng1, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) PINGROUP(62, NORTH, qua_mi2s, cri_trng, phase_flag, qdss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) PINGROUP(63, NORTH, qua_mi2s, _, phase_flag, qdss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) PINGROUP(64, NORTH, pri_mi2s, sp_cmu, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) PINGROUP(65, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) PINGROUP(66, NORTH, pri_mi2s_ws, qup8, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) PINGROUP(67, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) PINGROUP(68, NORTH, pri_mi2s, qup8, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) PINGROUP(69, EAST, spkr_i2s, audio_ref, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) PINGROUP(70, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) PINGROUP(71, EAST, lpass_slimbus, spkr_i2s, tsense_pwm1, tsense_pwm2, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) PINGROUP(72, EAST, lpass_slimbus, spkr_i2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) PINGROUP(73, EAST, btfm_slimbus, atest_usb2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) PINGROUP(74, EAST, btfm_slimbus, ter_mi2s, phase_flag, atest_usb23, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) PINGROUP(75, EAST, ter_mi2s, phase_flag, qdss, atest_usb22, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) PINGROUP(76, EAST, ter_mi2s, phase_flag, qdss, atest_usb21, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) PINGROUP(77, EAST, ter_mi2s, phase_flag, qdss, atest_usb20, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) PINGROUP(78, EAST, ter_mi2s, gcc_gp1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PINGROUP(79, NORTH, sec_mi2s, _, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) PINGROUP(80, NORTH, sec_mi2s, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) PINGROUP(81, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PINGROUP(82, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) PINGROUP(83, NORTH, sec_mi2s, qup15, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) PINGROUP(84, NORTH, qup15, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) PINGROUP(85, EAST, qup5, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) PINGROUP(86, EAST, qup5, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) PINGROUP(87, EAST, qup5, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PINGROUP(88, EAST, qup5, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) PINGROUP(89, SOUTH, tsif1_clk, qup4, qspi_cs, tgu_ch3, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) PINGROUP(90, SOUTH, tsif1_en, mdp_vsync0, qup4, qspi_cs, mdp_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) mdp_vsync2, mdp_vsync3, tgu_ch0, phase_flag, qdss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) PINGROUP(91, SOUTH, tsif1_data, sdc4_cmd, qup4, qspi_data, tgu_ch1, _, qdss_cti, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) PINGROUP(92, SOUTH, tsif2_error, sdc4_data, qup4, qspi_data, vfr_1, tgu_ch2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) PINGROUP(93, SOUTH, tsif2_clk, sdc4_clk, qup7, qspi_data, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) PINGROUP(94, SOUTH, tsif2_en, sdc4_data, qup7, qspi_data, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) PINGROUP(95, SOUTH, tsif2_data, sdc4_data, qup7, qspi_clk, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) PINGROUP(96, SOUTH, tsif2_sync, sdc4_data, qup7, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) PINGROUP(97, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) PINGROUP(98, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) PINGROUP(99, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) PINGROUP(100, NORTH, phase_flag, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) PINGROUP(102, NORTH, pci_e1, prng_rosc, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) PINGROUP(103, NORTH, pci_e1, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) PINGROUP(104, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) PINGROUP(105, NORTH, uim2_data, qup13, qup_l4, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) PINGROUP(106, NORTH, uim2_clk, qup13, qup_l5, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) PINGROUP(107, NORTH, uim2_reset, qup13, qup_l6, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) PINGROUP(108, NORTH, uim2_present, qup13, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) PINGROUP(113, NORTH, uim_batt, edp_hot, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) PINGROUP(114, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) PINGROUP(115, NORTH, _, nav_pps, nav_pps, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) PINGROUP(116, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) PINGROUP(117, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) PINGROUP(118, NORTH, adsp_ext, _, qdss, atest_char, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) PINGROUP(119, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) PINGROUP(120, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) PINGROUP(121, NORTH, _, qdss, atest_char, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) PINGROUP(122, EAST, _, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) PINGROUP(123, EAST, qup_l4, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) PINGROUP(124, EAST, qup_l5, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) PINGROUP(125, EAST, qup_l6, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) PINGROUP(126, EAST, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) PINGROUP(127, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PINGROUP(128, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) PINGROUP(129, NORTH, nav_pps, nav_pps, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) PINGROUP(130, NORTH, qlink_request, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) PINGROUP(131, NORTH, qlink_enable, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) PINGROUP(132, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) PINGROUP(133, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) PINGROUP(134, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) PINGROUP(135, NORTH, _, pa_indicator, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) PINGROUP(136, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) PINGROUP(137, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) PINGROUP(138, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) PINGROUP(139, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) PINGROUP(140, NORTH, _, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) PINGROUP(141, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) PINGROUP(142, NORTH, _, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) PINGROUP(143, NORTH, _, nav_pps, nav_pps, _, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) PINGROUP(144, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) PINGROUP(145, NORTH, mss_lte, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) PINGROUP(146, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) PINGROUP(147, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) PINGROUP(148, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) PINGROUP(149, NORTH, _, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) UFS_RESET(ufs_reset, 0x99f000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) SDC_QDSD_PINGROUP(sdc2_clk, 0x99a000, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SDC_QDSD_PINGROUP(sdc2_cmd, 0x99a000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) SDC_QDSD_PINGROUP(sdc2_data, 0x99a000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static const int sdm845_acpi_reserved_gpios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) 0, 1, 2, 3, 81, 82, 83, 84, -1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct msm_gpio_wakeirq_map sdm845_pdc_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { 1, 30 }, { 3, 31 }, { 5, 32 }, { 10, 33 }, { 11, 34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { 20, 35 }, { 22, 36 }, { 24, 37 }, { 26, 38 }, { 30, 39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { 31, 117 }, { 32, 41 }, { 34, 42 }, { 36, 43 }, { 37, 44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { 38, 45 }, { 39, 46 }, { 40, 47 }, { 41, 115 }, { 43, 49 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) { 44, 50 }, { 46, 51 }, { 48, 52 }, { 49, 118 }, { 52, 54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) { 53, 55 }, { 54, 56 }, { 56, 57 }, { 57, 58 }, { 58, 59 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) { 59, 60 }, { 60, 61 }, { 61, 62 }, { 62, 63 }, { 63, 64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { 64, 65 }, { 66, 66 }, { 68, 67 }, { 71, 68 }, { 73, 69 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) { 77, 70 }, { 78, 71 }, { 79, 72 }, { 80, 73 }, { 84, 74 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) { 85, 75 }, { 86, 76 }, { 88, 77 }, { 89, 116 }, { 91, 79 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) { 92, 80 }, { 95, 81 }, { 96, 82 }, { 97, 83 }, { 101, 84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) { 103, 85 }, { 104, 86 }, { 115, 90 }, { 116, 91 }, { 117, 92 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) { 118, 93 }, { 119, 94 }, { 120, 95 }, { 121, 96 }, { 122, 97 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { 123, 98 }, { 124, 99 }, { 125, 100 }, { 127, 102 }, { 128, 103 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) { 129, 104 }, { 130, 105 }, { 132, 106 }, { 133, 107 }, { 145, 108 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static const struct msm_pinctrl_soc_data sdm845_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .pins = sdm845_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) .npins = ARRAY_SIZE(sdm845_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) .functions = sdm845_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) .nfunctions = ARRAY_SIZE(sdm845_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .groups = sdm845_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .ngroups = ARRAY_SIZE(sdm845_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .ngpios = 151,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) .wakeirq_map = sdm845_pdc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) .nwakeirq_map = ARRAY_SIZE(sdm845_pdc_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .wakeirq_dual_edge_errata = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const struct msm_pinctrl_soc_data sdm845_acpi_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .pins = sdm845_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .npins = ARRAY_SIZE(sdm845_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .groups = sdm845_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .ngroups = ARRAY_SIZE(sdm845_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .reserved_gpios = sdm845_acpi_reserved_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .ngpios = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static int sdm845_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret = msm_pinctrl_probe(pdev, &sdm845_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) } else if (has_acpi_companion(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = msm_pinctrl_probe(pdev, &sdm845_acpi_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dev_err(&pdev->dev, "DT and ACPI disabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #ifdef CONFIG_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static const struct acpi_device_id sdm845_pinctrl_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { "QCOM0217"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) MODULE_DEVICE_TABLE(acpi, sdm845_pinctrl_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static const struct of_device_id sdm845_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) { .compatible = "qcom,sdm845-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static struct platform_driver sdm845_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .name = "sdm845-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .pm = &msm_pinctrl_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .of_match_table = sdm845_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .acpi_match_table = ACPI_PTR(sdm845_pinctrl_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .probe = sdm845_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static int __init sdm845_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return platform_driver_register(&sdm845_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) arch_initcall(sdm845_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static void __exit sdm845_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) platform_driver_unregister(&sdm845_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) module_exit(sdm845_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) MODULE_DESCRIPTION("QTI sdm845 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) MODULE_DEVICE_TABLE(of, sdm845_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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