^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2018, Craig Tatlor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) static const char * const sdm660_tiles[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "north",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "south"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) NORTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) CENTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) SOUTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define REG_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) [msm_mux_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .npins = (unsigned)ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) msm_mux_gpio, /* gpio mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) msm_mux_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) msm_mux_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) msm_mux_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) msm_mux_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) msm_mux_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) msm_mux_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) msm_mux_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) msm_mux_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) msm_mux_##f9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .nfuncs = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .ctl_reg = REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .io_reg = 0x4 + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .intr_cfg_reg = 0x8 + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .intr_status_reg = 0xc + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .intr_target_reg = 0x8 + REG_SIZE * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .tile = _tile, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .intr_target_kpss_val = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .npins = (unsigned)ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .tile = NORTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct pinctrl_pin_desc sdm660_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(114, "SDC1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(115, "SDC1_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(116, "SDC1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(117, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(118, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(119, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(120, "SDC1_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define DECLARE_MSM_GPIO_PINS(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int sdc1_clk_pins[] = { 114 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int sdc1_cmd_pins[] = { 115 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int sdc1_data_pins[] = { 116 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int sdc1_rclk_pins[] = { 120 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int sdc2_clk_pins[] = { 117 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int sdc2_cmd_pins[] = { 118 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int sdc2_data_pins[] = { 119 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) enum sdm660_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) msm_mux_adsp_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) msm_mux_agera_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) msm_mux_atest_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) msm_mux_atest_char0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) msm_mux_atest_char1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) msm_mux_atest_char2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) msm_mux_atest_char3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) msm_mux_atest_gpsadc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) msm_mux_atest_gpsadc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) msm_mux_atest_tsens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) msm_mux_atest_tsens2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) msm_mux_atest_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) msm_mux_atest_usb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) msm_mux_atest_usb11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msm_mux_atest_usb12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msm_mux_atest_usb13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msm_mux_atest_usb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msm_mux_atest_usb20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) msm_mux_atest_usb21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) msm_mux_atest_usb22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msm_mux_atest_usb23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) msm_mux_audio_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) msm_mux_bimc_dte0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) msm_mux_bimc_dte1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) msm_mux_blsp_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) msm_mux_blsp_i2c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) msm_mux_blsp_i2c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) msm_mux_blsp_i2c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) msm_mux_blsp_i2c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) msm_mux_blsp_i2c6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) msm_mux_blsp_i2c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msm_mux_blsp_i2c8_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) msm_mux_blsp_i2c8_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) msm_mux_blsp_spi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msm_mux_blsp_spi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) msm_mux_blsp_spi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) msm_mux_blsp_spi3_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) msm_mux_blsp_spi3_cs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) msm_mux_blsp_spi4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) msm_mux_blsp_spi5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) msm_mux_blsp_spi6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) msm_mux_blsp_spi7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) msm_mux_blsp_spi8_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) msm_mux_blsp_spi8_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) msm_mux_blsp_spi8_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) msm_mux_blsp_spi8_cs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) msm_mux_blsp_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msm_mux_blsp_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) msm_mux_blsp_uart5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msm_mux_blsp_uart6_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msm_mux_blsp_uart6_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) msm_mux_blsp_uim1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msm_mux_blsp_uim2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msm_mux_blsp_uim5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) msm_mux_blsp_uim6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msm_mux_cam_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) msm_mux_cci_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) msm_mux_cci_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msm_mux_cri_trng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msm_mux_cri_trng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) msm_mux_cri_trng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msm_mux_dbg_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) msm_mux_ddr_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) msm_mux_gcc_gp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) msm_mux_gcc_gp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) msm_mux_gcc_gp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) msm_mux_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) msm_mux_gps_tx_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) msm_mux_gps_tx_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) msm_mux_gps_tx_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msm_mux_isense_dbg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) msm_mux_jitter_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) msm_mux_ldo_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) msm_mux_ldo_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) msm_mux_m_voc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) msm_mux_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) msm_mux_mdss_vsync0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) msm_mux_mdss_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msm_mux_mdss_vsync2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msm_mux_mdss_vsync3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msm_mux_mss_lte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) msm_mux_nav_pps_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msm_mux_nav_pps_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msm_mux_nav_pps_c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msm_mux_pa_indicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msm_mux_phase_flag0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) msm_mux_phase_flag1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msm_mux_phase_flag2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msm_mux_phase_flag3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) msm_mux_phase_flag4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) msm_mux_phase_flag5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msm_mux_phase_flag6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msm_mux_phase_flag7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) msm_mux_phase_flag8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) msm_mux_phase_flag9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) msm_mux_phase_flag10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msm_mux_phase_flag11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) msm_mux_phase_flag12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msm_mux_phase_flag13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msm_mux_phase_flag14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) msm_mux_phase_flag15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) msm_mux_phase_flag16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) msm_mux_phase_flag17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msm_mux_phase_flag18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msm_mux_phase_flag19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msm_mux_phase_flag20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msm_mux_phase_flag21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msm_mux_phase_flag22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) msm_mux_phase_flag23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msm_mux_phase_flag24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msm_mux_phase_flag25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msm_mux_phase_flag26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msm_mux_phase_flag27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) msm_mux_phase_flag28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) msm_mux_phase_flag29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msm_mux_phase_flag30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msm_mux_phase_flag31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msm_mux_pll_bypassnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msm_mux_pll_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msm_mux_pri_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msm_mux_pri_mi2s_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msm_mux_prng_rosc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msm_mux_pwr_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msm_mux_pwr_modem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msm_mux_pwr_nav,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) msm_mux_qdss_cti0_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) msm_mux_qdss_cti0_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) msm_mux_qdss_cti1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) msm_mux_qdss_cti1_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) msm_mux_qdss_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) msm_mux_qdss_gpio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) msm_mux_qdss_gpio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) msm_mux_qdss_gpio10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) msm_mux_qdss_gpio11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) msm_mux_qdss_gpio12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) msm_mux_qdss_gpio13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) msm_mux_qdss_gpio14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) msm_mux_qdss_gpio15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) msm_mux_qdss_gpio2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msm_mux_qdss_gpio3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) msm_mux_qdss_gpio4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) msm_mux_qdss_gpio5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msm_mux_qdss_gpio6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msm_mux_qdss_gpio7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msm_mux_qdss_gpio8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msm_mux_qdss_gpio9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) msm_mux_qlink_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) msm_mux_qlink_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msm_mux_qspi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msm_mux_qspi_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msm_mux_qspi_data0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msm_mux_qspi_data1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msm_mux_qspi_data2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msm_mux_qspi_data3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msm_mux_qspi_resetn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) msm_mux_sec_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msm_mux_sndwire_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msm_mux_sndwire_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_mux_sp_cmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msm_mux_ssc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msm_mux_tgu_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msm_mux_tgu_ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msm_mux_tsense_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msm_mux_tsense_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) msm_mux_uim1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msm_mux_uim1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msm_mux_uim1_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msm_mux_uim1_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msm_mux_uim2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msm_mux_uim2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) msm_mux_uim2_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msm_mux_uim2_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) msm_mux_uim_batt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msm_mux_vfr_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msm_mux_vsense_clkout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msm_mux_vsense_data0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msm_mux_vsense_data1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msm_mux_vsense_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msm_mux_wlan1_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msm_mux_wlan1_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msm_mux_wlan2_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msm_mux_wlan2_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) msm_mux__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "gpio111", "gpio112", "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const char * const adsp_ext_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const char * const agera_pll_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "gpio34", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const char * const atest_char0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static const char * const atest_char1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const char * const atest_char2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "gpio60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const char * const atest_char3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static const char * const atest_char_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const char * const atest_gpsadc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const char * const atest_gpsadc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const char * const atest_tsens2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const char * const atest_tsens_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const char * const atest_usb10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const char * const atest_usb11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const char * const atest_usb12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const char * const atest_usb13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const char * const atest_usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const char * const atest_usb20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const atest_usb21_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const char * const atest_usb22_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const atest_usb23_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const char * const atest_usb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static const char * const audio_ref_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char * const bimc_dte0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "gpio9", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char * const bimc_dte1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "gpio8", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const char * const blsp_i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const char * const blsp_i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const char * const blsp_i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const char * const blsp_i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const char * const blsp_i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const blsp_i2c6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "gpio22", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static const char * const blsp_i2c7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const char * const blsp_i2c8_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const char * const blsp_i2c8_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "gpio44", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const char * const blsp_spi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "gpio0", "gpio1", "gpio2", "gpio3", "gpio46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const char * const blsp_spi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const char * const blsp_spi3_cs1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) static const char * const blsp_spi3_cs2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const char * const blsp_spi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "gpio8", "gpio9", "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const char * const blsp_spi4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "gpio12", "gpio13", "gpio14", "gpio15",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const char * const blsp_spi5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static const char * const blsp_spi6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "gpio49", "gpio52", "gpio22", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const char * const blsp_spi7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const char * const blsp_spi8_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "gpio28", "gpio29", "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static const char * const blsp_spi8_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "gpio40", "gpio41", "gpio44", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const char * const blsp_spi8_cs1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const char * const blsp_spi8_cs2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static const char * const blsp_uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const char * const blsp_uart2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const char * const blsp_uart5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static const char * const blsp_uart6_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "gpio24", "gpio25", "gpio26", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const char * const blsp_uart6_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "gpio28", "gpio29", "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const char * const blsp_uim1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "gpio0", "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const char * const blsp_uim2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "gpio4", "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const char * const blsp_uim5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "gpio16", "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const char * const blsp_uim6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const char * const cam_mclk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const char * const cci_async_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "gpio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const char * const cci_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "gpio36", "gpio37", "gpio38", "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const char * const cri_trng0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "gpio60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const char * const cri_trng1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const char * const cri_trng_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const char * const dbg_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const char * const ddr_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "gpio3", "gpio8", "gpio9", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const char * const gcc_gp1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "gpio57", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const char * const gcc_gp2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "gpio58", "gpio81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const char * const gcc_gp3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "gpio59", "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const char * const gps_tx_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const char * const gps_tx_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const char * const gps_tx_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "gpio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const char * const isense_dbg_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const char * const jitter_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const char * const ldo_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const char * const ldo_update_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static const char * const m_voc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const char * const mdp_vsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "gpio59", "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const char * const mdss_vsync0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const char * const mdss_vsync1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const char * const mdss_vsync2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const char * const mdss_vsync3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static const char * const mss_lte_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) "gpio81", "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const char * const nav_pps_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const char * const nav_pps_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static const char * const nav_pps_c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "gpio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const char * const pa_indicator_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const char * const phase_flag0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static const char * const phase_flag1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static const char * const phase_flag2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static const char * const phase_flag3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static const char * const phase_flag4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static const char * const phase_flag5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const char * const phase_flag6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "gpio53",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static const char * const phase_flag7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "gpio69",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const char * const phase_flag8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const char * const phase_flag9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static const char * const phase_flag10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const char * const phase_flag11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const char * const phase_flag12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static const char * const phase_flag13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static const char * const phase_flag14_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static const char * const phase_flag15_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "gpio51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static const char * const phase_flag16_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static const char * const phase_flag17_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static const char * const phase_flag18_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const char * const phase_flag19_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static const char * const phase_flag20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static const char * const phase_flag21_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) static const char * const phase_flag22_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "gpio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const char * const phase_flag23_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static const char * const phase_flag24_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static const char * const phase_flag25_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const char * const phase_flag26_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const char * const phase_flag27_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const char * const phase_flag28_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const char * const phase_flag29_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static const char * const phase_flag30_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static const char * const phase_flag31_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static const char * const pll_bypassnl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const char * const pll_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const char * const pri_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) "gpio12", "gpio14", "gpio15", "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static const char * const pri_mi2s_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static const char * const prng_rosc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) "gpio102",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const char * const pwr_crypto_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const char * const pwr_modem_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const char * const pwr_nav_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "gpio32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const char * const qdss_cti0_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "gpio49", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const char * const qdss_cti0_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "gpio13", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const char * const qdss_cti1_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "gpio53", "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const char * const qdss_cti1_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "gpio12", "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const char * const qdss_gpio0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "gpio32", "gpio67",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const char * const qdss_gpio10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "gpio43", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const char * const qdss_gpio11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "gpio44", "gpio79",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const char * const qdss_gpio12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "gpio45", "gpio80",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const char * const qdss_gpio13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "gpio46", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const char * const qdss_gpio14_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "gpio47", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const char * const qdss_gpio15_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "gpio48", "gpio73",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const char * const qdss_gpio1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "gpio33", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const char * const qdss_gpio2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "gpio34", "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const char * const qdss_gpio3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "gpio35", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const char * const qdss_gpio4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "gpio0", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const char * const qdss_gpio5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "gpio1", "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const char * const qdss_gpio6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "gpio38", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const char * const qdss_gpio7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "gpio39", "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const char * const qdss_gpio8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "gpio51", "gpio75",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const char * const qdss_gpio9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "gpio42", "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const char * const qdss_gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "gpio31", "gpio52", "gpio68", "gpio69",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const char * const qlink_enable_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "gpio100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const char * const qlink_request_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "gpio99",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const char * const qspi_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const char * const qspi_cs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) "gpio43", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const char * const qspi_data0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const char * const qspi_data1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const char * const qspi_data2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static const char * const qspi_data3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "gpio51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const char * const qspi_resetn_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const char * const sec_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "gpio24", "gpio25", "gpio26", "gpio27", "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const char * const sndwire_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const char * const sndwire_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const char * const sp_cmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const char * const ssc_irq_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) "gpio67", "gpio68", "gpio69", "gpio70", "gpio71", "gpio72", "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "gpio75", "gpio76",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static const char * const tgu_ch0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) "gpio0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static const char * const tgu_ch1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static const char * const tsense_pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static const char * const tsense_pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static const char * const uim1_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static const char * const uim1_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "gpio87",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const char * const uim1_present_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const char * const uim1_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const char * const uim2_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const char * const uim2_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "gpio83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const char * const uim2_present_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "gpio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const char * const uim2_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "gpio85",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const char * const uim_batt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) static const char * const vfr_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const char * const vsense_clkout_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const char * const vsense_data0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const char * const vsense_data1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static const char * const vsense_mode_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static const char * const wlan1_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) static const char * const wlan1_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static const char * const wlan2_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const char * const wlan2_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static const struct msm_function sdm660_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) FUNCTION(adsp_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) FUNCTION(agera_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) FUNCTION(atest_char),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) FUNCTION(atest_char0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) FUNCTION(atest_char1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) FUNCTION(atest_char2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) FUNCTION(atest_char3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) FUNCTION(atest_gpsadc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) FUNCTION(atest_gpsadc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) FUNCTION(atest_tsens),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) FUNCTION(atest_tsens2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) FUNCTION(atest_usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) FUNCTION(atest_usb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) FUNCTION(atest_usb11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) FUNCTION(atest_usb12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) FUNCTION(atest_usb13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) FUNCTION(atest_usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) FUNCTION(atest_usb20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) FUNCTION(atest_usb21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) FUNCTION(atest_usb22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) FUNCTION(atest_usb23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) FUNCTION(audio_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) FUNCTION(bimc_dte0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) FUNCTION(bimc_dte1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) FUNCTION(blsp_i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) FUNCTION(blsp_i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) FUNCTION(blsp_i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) FUNCTION(blsp_i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) FUNCTION(blsp_i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) FUNCTION(blsp_i2c6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) FUNCTION(blsp_i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) FUNCTION(blsp_i2c8_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) FUNCTION(blsp_i2c8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) FUNCTION(blsp_spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) FUNCTION(blsp_spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) FUNCTION(blsp_spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) FUNCTION(blsp_spi3_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) FUNCTION(blsp_spi3_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) FUNCTION(blsp_spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) FUNCTION(blsp_spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) FUNCTION(blsp_spi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) FUNCTION(blsp_spi7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) FUNCTION(blsp_spi8_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) FUNCTION(blsp_spi8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) FUNCTION(blsp_spi8_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) FUNCTION(blsp_spi8_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) FUNCTION(blsp_uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) FUNCTION(blsp_uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) FUNCTION(blsp_uart5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) FUNCTION(blsp_uart6_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) FUNCTION(blsp_uart6_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) FUNCTION(blsp_uim1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) FUNCTION(blsp_uim2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) FUNCTION(blsp_uim5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) FUNCTION(blsp_uim6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) FUNCTION(cam_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) FUNCTION(cci_async),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) FUNCTION(cci_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) FUNCTION(cri_trng),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) FUNCTION(cri_trng0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) FUNCTION(cri_trng1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) FUNCTION(dbg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) FUNCTION(ddr_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) FUNCTION(gcc_gp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) FUNCTION(gcc_gp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) FUNCTION(gcc_gp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) FUNCTION(gps_tx_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) FUNCTION(gps_tx_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) FUNCTION(gps_tx_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) FUNCTION(isense_dbg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) FUNCTION(jitter_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) FUNCTION(ldo_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) FUNCTION(ldo_update),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) FUNCTION(m_voc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) FUNCTION(mdss_vsync0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) FUNCTION(mdss_vsync1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) FUNCTION(mdss_vsync2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) FUNCTION(mdss_vsync3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) FUNCTION(mss_lte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) FUNCTION(nav_pps_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) FUNCTION(nav_pps_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) FUNCTION(nav_pps_c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) FUNCTION(pa_indicator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) FUNCTION(phase_flag0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) FUNCTION(phase_flag1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) FUNCTION(phase_flag2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) FUNCTION(phase_flag3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) FUNCTION(phase_flag4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) FUNCTION(phase_flag5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) FUNCTION(phase_flag6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) FUNCTION(phase_flag7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) FUNCTION(phase_flag8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) FUNCTION(phase_flag9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) FUNCTION(phase_flag10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) FUNCTION(phase_flag11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) FUNCTION(phase_flag12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) FUNCTION(phase_flag13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) FUNCTION(phase_flag14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) FUNCTION(phase_flag15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) FUNCTION(phase_flag16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) FUNCTION(phase_flag17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) FUNCTION(phase_flag18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) FUNCTION(phase_flag19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) FUNCTION(phase_flag20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) FUNCTION(phase_flag21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) FUNCTION(phase_flag22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) FUNCTION(phase_flag23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) FUNCTION(phase_flag24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) FUNCTION(phase_flag25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) FUNCTION(phase_flag26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) FUNCTION(phase_flag27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) FUNCTION(phase_flag28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) FUNCTION(phase_flag29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) FUNCTION(phase_flag30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) FUNCTION(phase_flag31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) FUNCTION(pll_bypassnl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) FUNCTION(pll_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) FUNCTION(pri_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) FUNCTION(pri_mi2s_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) FUNCTION(prng_rosc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) FUNCTION(pwr_crypto),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) FUNCTION(pwr_modem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) FUNCTION(pwr_nav),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) FUNCTION(qdss_cti0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) FUNCTION(qdss_cti0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) FUNCTION(qdss_cti1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) FUNCTION(qdss_cti1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) FUNCTION(qdss_gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) FUNCTION(qdss_gpio0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) FUNCTION(qdss_gpio1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) FUNCTION(qdss_gpio10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) FUNCTION(qdss_gpio11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) FUNCTION(qdss_gpio12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) FUNCTION(qdss_gpio13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) FUNCTION(qdss_gpio14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) FUNCTION(qdss_gpio15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) FUNCTION(qdss_gpio2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) FUNCTION(qdss_gpio3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) FUNCTION(qdss_gpio4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) FUNCTION(qdss_gpio5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) FUNCTION(qdss_gpio6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) FUNCTION(qdss_gpio7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) FUNCTION(qdss_gpio8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) FUNCTION(qdss_gpio9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) FUNCTION(qlink_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) FUNCTION(qlink_request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) FUNCTION(qspi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) FUNCTION(qspi_cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) FUNCTION(qspi_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) FUNCTION(qspi_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) FUNCTION(qspi_data2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) FUNCTION(qspi_data3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) FUNCTION(qspi_resetn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) FUNCTION(sec_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) FUNCTION(sndwire_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) FUNCTION(sndwire_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) FUNCTION(sp_cmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) FUNCTION(ssc_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) FUNCTION(tgu_ch0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) FUNCTION(tgu_ch1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) FUNCTION(tsense_pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) FUNCTION(tsense_pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) FUNCTION(uim1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) FUNCTION(uim1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) FUNCTION(uim1_present),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) FUNCTION(uim1_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) FUNCTION(uim2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) FUNCTION(uim2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) FUNCTION(uim2_present),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) FUNCTION(uim2_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) FUNCTION(uim_batt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) FUNCTION(vfr_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) FUNCTION(vsense_clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) FUNCTION(vsense_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) FUNCTION(vsense_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) FUNCTION(vsense_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) FUNCTION(wlan1_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) FUNCTION(wlan1_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) FUNCTION(wlan2_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) FUNCTION(wlan2_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) static const struct msm_pingroup sdm660_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) PINGROUP(0, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch0, _, _, qdss_gpio4, atest_gpsadc1, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) PINGROUP(1, SOUTH, blsp_spi1, blsp_uart1, blsp_uim1, tgu_ch1, _, _, qdss_gpio5, atest_gpsadc0, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) PINGROUP(2, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) PINGROUP(3, SOUTH, blsp_spi1, blsp_uart1, blsp_i2c1, ddr_bist, _, _, atest_tsens2, atest_usb1, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) PINGROUP(4, NORTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag3, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) PINGROUP(5, SOUTH, blsp_spi2, blsp_uim2, blsp_uart2, phase_flag14, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) PINGROUP(6, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, phase_flag31, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) PINGROUP(7, SOUTH, blsp_spi2, blsp_i2c2, blsp_uart2, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) PINGROUP(8, NORTH, blsp_spi3, ddr_bist, _, _, _, wlan1_adc1, atest_usb13, bimc_dte1, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) PINGROUP(9, NORTH, blsp_spi3, ddr_bist, _, _, _, wlan1_adc0, atest_usb12, bimc_dte0, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) PINGROUP(10, NORTH, blsp_spi3, blsp_i2c3, ddr_bist, _, _, wlan2_adc1, atest_usb11, bimc_dte1, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) PINGROUP(11, NORTH, blsp_spi3, blsp_i2c3, _, dbg_out, wlan2_adc0, atest_usb10, bimc_dte0, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) PINGROUP(12, NORTH, blsp_spi4, pri_mi2s, _, phase_flag26, qdss_cti1_b, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) PINGROUP(13, NORTH, blsp_spi4, _, pri_mi2s_ws, _, _, phase_flag27, qdss_cti0_b, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) PINGROUP(14, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, _, phase_flag28, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) PINGROUP(15, NORTH, blsp_spi4, blsp_i2c4, pri_mi2s, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) PINGROUP(16, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) PINGROUP(17, CENTER, blsp_uart5, blsp_spi5, blsp_uim5, _, phase_flag5, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) PINGROUP(18, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) PINGROUP(19, CENTER, blsp_uart5, blsp_spi5, blsp_i2c5, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) PINGROUP(20, SOUTH, _, _, blsp_uim6, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) PINGROUP(21, SOUTH, _, _, blsp_uim6, _, phase_flag11, qdss_cti0_b, vsense_data0, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) PINGROUP(22, CENTER, blsp_spi6, _, blsp_i2c6, _, phase_flag12, vsense_data1, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) PINGROUP(23, CENTER, blsp_spi6, _, blsp_i2c6, _, phase_flag13, vsense_mode, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) PINGROUP(24, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_clk, _, _, phase_flag17, vsense_clkout, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) PINGROUP(25, NORTH, blsp_spi7, blsp_uart6_a, sec_mi2s, sndwire_data, _, _, phase_flag18, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) PINGROUP(26, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, sec_mi2s, _, phase_flag19, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) PINGROUP(27, NORTH, blsp_spi7, blsp_uart6_a, blsp_i2c7, vfr_1, sec_mi2s, _, phase_flag20, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) PINGROUP(28, CENTER, blsp_spi8_a, blsp_uart6_b, m_voc, _, phase_flag21, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) PINGROUP(29, CENTER, blsp_spi8_a, blsp_uart6_b, _, _, phase_flag22, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) PINGROUP(30, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, blsp_spi3_cs1, _, phase_flag23, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) PINGROUP(31, CENTER, blsp_spi8_a, blsp_uart6_b, blsp_i2c8_a, pwr_modem, _, phase_flag24, qdss_gpio, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) PINGROUP(32, SOUTH, cam_mclk, pwr_nav, _, _, qdss_gpio0, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) PINGROUP(33, SOUTH, cam_mclk, qspi_data0, pwr_crypto, _, _, qdss_gpio1, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) PINGROUP(34, SOUTH, cam_mclk, qspi_data1, agera_pll, _, _, qdss_gpio2, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) PINGROUP(35, SOUTH, cam_mclk, qspi_data2, jitter_bist, _, _, qdss_gpio3, _, atest_usb2, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) PINGROUP(36, SOUTH, cci_i2c, pll_bypassnl, agera_pll, _, _, qdss_gpio4, atest_tsens, atest_usb21, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) PINGROUP(37, SOUTH, cci_i2c, pll_reset, _, _, qdss_gpio5, atest_usb23, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) PINGROUP(38, SOUTH, cci_i2c, _, _, qdss_gpio6, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) PINGROUP(39, SOUTH, cci_i2c, _, _, qdss_gpio7, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) PINGROUP(40, SOUTH, _, _, blsp_spi8_b, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) PINGROUP(41, SOUTH, _, _, blsp_spi8_b, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) PINGROUP(42, SOUTH, mdss_vsync0, mdss_vsync1, mdss_vsync2, mdss_vsync3, _, _, qdss_gpio9, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) PINGROUP(43, SOUTH, _, _, qspi_cs, _, _, qdss_gpio10, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) PINGROUP(44, SOUTH, _, _, blsp_spi8_b, blsp_i2c8_b, _, _, qdss_gpio11, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) PINGROUP(45, SOUTH, cci_async, _, _, qdss_gpio12, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) PINGROUP(46, SOUTH, blsp_spi1, _, _, qdss_gpio13, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) PINGROUP(47, SOUTH, qspi_clk, _, phase_flag30, qdss_gpio14, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) PINGROUP(48, SOUTH, _, phase_flag1, qdss_gpio15, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) PINGROUP(49, SOUTH, blsp_spi6, phase_flag2, qdss_cti0_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PINGROUP(50, SOUTH, qspi_cs, _, phase_flag9, qdss_cti0_a, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) PINGROUP(51, SOUTH, qspi_data3, _, phase_flag15, qdss_gpio8, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) PINGROUP(52, SOUTH, _, blsp_spi8_b, blsp_i2c8_b, blsp_spi6, phase_flag16, qdss_gpio, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) PINGROUP(53, NORTH, _, phase_flag6, qdss_cti1_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) PINGROUP(54, NORTH, _, _, phase_flag29, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) PINGROUP(55, SOUTH, _, phase_flag25, qdss_cti1_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) PINGROUP(56, SOUTH, _, phase_flag10, qdss_gpio3, _, atest_usb20, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) PINGROUP(57, SOUTH, gcc_gp1, _, phase_flag4, atest_usb22, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) PINGROUP(58, SOUTH, _, gcc_gp2, _, _, atest_char, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) PINGROUP(59, NORTH, mdp_vsync, gcc_gp3, _, _, atest_char3, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) PINGROUP(60, NORTH, cri_trng0, _, _, atest_char2, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) PINGROUP(61, NORTH, pri_mi2s, cri_trng1, _, _, atest_char1, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINGROUP(62, NORTH, sec_mi2s, audio_ref, _, cri_trng, _, _, atest_char0, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINGROUP(63, NORTH, _, _, _, qdss_gpio1, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINGROUP(64, SOUTH, blsp_spi8_cs1, sp_cmu, _, _, qdss_gpio2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINGROUP(65, SOUTH, _, nav_pps_a, nav_pps_a, gps_tx_a, blsp_spi3_cs2, adsp_ext, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINGROUP(66, NORTH, _, _, qdss_cti1_b, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINGROUP(67, NORTH, _, _, qdss_gpio0, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINGROUP(68, NORTH, isense_dbg, _, phase_flag0, qdss_gpio, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINGROUP(69, NORTH, _, phase_flag7, qdss_gpio, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINGROUP(70, NORTH, _, phase_flag8, qdss_gpio6, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINGROUP(71, NORTH, _, _, qdss_gpio7, tsense_pwm1, tsense_pwm2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINGROUP(72, NORTH, _, qdss_gpio14, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINGROUP(73, NORTH, _, _, qdss_gpio15, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINGROUP(74, NORTH, mdp_vsync, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINGROUP(75, NORTH, _, _, qdss_gpio8, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINGROUP(76, NORTH, blsp_spi8_cs2, _, _, _, qdss_gpio9, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINGROUP(77, NORTH, _, _, qdss_gpio10, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINGROUP(78, NORTH, gcc_gp1, _, qdss_gpio13, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINGROUP(79, SOUTH, _, _, qdss_gpio11, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINGROUP(80, SOUTH, nav_pps_b, nav_pps_b, gps_tx_c, _, _, qdss_gpio12, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINGROUP(81, CENTER, mss_lte, gcc_gp2, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINGROUP(82, CENTER, mss_lte, gcc_gp3, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINGROUP(83, SOUTH, uim2_data, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINGROUP(84, SOUTH, uim2_clk, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINGROUP(85, SOUTH, uim2_reset, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINGROUP(86, SOUTH, uim2_present, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINGROUP(87, SOUTH, uim1_data, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINGROUP(88, SOUTH, uim1_clk, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINGROUP(89, SOUTH, uim1_reset, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINGROUP(90, SOUTH, uim1_present, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINGROUP(91, SOUTH, uim_batt, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINGROUP(92, SOUTH, _, _, pa_indicator, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINGROUP(93, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINGROUP(94, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINGROUP(95, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINGROUP(96, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINGROUP(97, SOUTH, _, ldo_en, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINGROUP(98, SOUTH, _, nav_pps_c, nav_pps_c, gps_tx_b, ldo_update, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINGROUP(99, SOUTH, qlink_request, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINGROUP(100, SOUTH, qlink_enable, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINGROUP(101, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINGROUP(102, SOUTH, _, prng_rosc, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINGROUP(103, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINGROUP(104, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINGROUP(105, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINGROUP(106, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINGROUP(107, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINGROUP(108, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINGROUP(109, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINGROUP(110, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINGROUP(111, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINGROUP(112, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINGROUP(113, SOUTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) SDC_QDSD_PINGROUP(sdc1_clk, 0x9a000, 13, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) SDC_QDSD_PINGROUP(sdc1_cmd, 0x9a000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) SDC_QDSD_PINGROUP(sdc1_data, 0x9a000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) SDC_QDSD_PINGROUP(sdc2_clk, 0x9b000, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) SDC_QDSD_PINGROUP(sdc2_cmd, 0x9b000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) SDC_QDSD_PINGROUP(sdc2_data, 0x9b000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) SDC_QDSD_PINGROUP(sdc1_rclk, 0x9a000, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) static const struct msm_pinctrl_soc_data sdm660_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .pins = sdm660_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .npins = ARRAY_SIZE(sdm660_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .functions = sdm660_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .nfunctions = ARRAY_SIZE(sdm660_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .groups = sdm660_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .ngroups = ARRAY_SIZE(sdm660_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .ngpios = 114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) .tiles = sdm660_tiles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) .ntiles = ARRAY_SIZE(sdm660_tiles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) static int sdm660_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return msm_pinctrl_probe(pdev, &sdm660_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static const struct of_device_id sdm660_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) { .compatible = "qcom,sdm660-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) { .compatible = "qcom,sdm630-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) static struct platform_driver sdm660_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .name = "sdm660-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .of_match_table = sdm660_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .probe = sdm660_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static int __init sdm660_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return platform_driver_register(&sdm660_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) arch_initcall(sdm660_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) static void __exit sdm660_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) platform_driver_unregister(&sdm660_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) module_exit(sdm660_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) MODULE_DESCRIPTION("QTI sdm660 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) MODULE_DEVICE_TABLE(of, sdm660_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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