^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2019, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) static const char * const sc7180_tiles[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "north",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "south",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "west",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) NORTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) SOUTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) WEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [msm_mux_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PINGROUP(id, _tile, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .npins = ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) msm_mux_gpio, /* gpio mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) msm_mux_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) msm_mux_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) msm_mux_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) msm_mux_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) msm_mux_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) msm_mux_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) msm_mux_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) msm_mux_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) msm_mux_##f9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .nfuncs = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .ctl_reg = 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .io_reg = 0x1000 * id + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .intr_cfg_reg = 0x1000 * id + 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .intr_status_reg = 0x1000 * id + 0xc, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .intr_target_reg = 0x1000 * id + 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .tile = _tile, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .intr_target_kpss_val = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .tile = SOUTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define UFS_RESET(pg_name, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .ctl_reg = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .io_reg = offset + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .tile = SOUTH, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .pull_bit = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .drv_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .out_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct pinctrl_pin_desc sc7180_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(114, "GPIO_114"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(115, "GPIO_115"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(116, "GPIO_116"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(117, "GPIO_117"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(118, "GPIO_118"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(119, "UFS_RESET"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(120, "SDC1_RCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(121, "SDC1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(122, "SDC1_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(123, "SDC1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(124, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(125, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(126, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DECLARE_MSM_GPIO_PINS(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DECLARE_MSM_GPIO_PINS(114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DECLARE_MSM_GPIO_PINS(115);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DECLARE_MSM_GPIO_PINS(116);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DECLARE_MSM_GPIO_PINS(117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DECLARE_MSM_GPIO_PINS(118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const unsigned int ufs_reset_pins[] = { 119 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const unsigned int sdc1_rclk_pins[] = { 120 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const unsigned int sdc1_clk_pins[] = { 121 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const unsigned int sdc1_cmd_pins[] = { 122 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const unsigned int sdc1_data_pins[] = { 123 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const unsigned int sdc2_clk_pins[] = { 124 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const unsigned int sdc2_cmd_pins[] = { 125 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const unsigned int sdc2_data_pins[] = { 126 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) enum sc7180_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msm_mux_adsp_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) msm_mux_agera_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) msm_mux_aoss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msm_mux_atest_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) msm_mux_atest_char0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) msm_mux_atest_char1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) msm_mux_atest_char2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) msm_mux_atest_char3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) msm_mux_atest_tsens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) msm_mux_atest_tsens2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) msm_mux_atest_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) msm_mux_atest_usb2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) msm_mux_atest_usb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) msm_mux_atest_usb11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) msm_mux_atest_usb12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) msm_mux_atest_usb13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msm_mux_atest_usb20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) msm_mux_atest_usb21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msm_mux_atest_usb22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msm_mux_atest_usb23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) msm_mux_audio_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msm_mux_btfm_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msm_mux_cam_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) msm_mux_cci_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msm_mux_cci_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) msm_mux_cci_timer0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) msm_mux_cci_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msm_mux_cci_timer2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msm_mux_cci_timer3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) msm_mux_cci_timer4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msm_mux_cri_trng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) msm_mux_dbg_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) msm_mux_ddr_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) msm_mux_ddr_pxi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) msm_mux_ddr_pxi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) msm_mux_ddr_pxi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) msm_mux_ddr_pxi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) msm_mux_dp_hot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) msm_mux_edp_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msm_mux_gcc_gp1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) msm_mux_gcc_gp2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) msm_mux_gcc_gp3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) msm_mux_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) msm_mux_gp_pdm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) msm_mux_gp_pdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) msm_mux_gp_pdm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) msm_mux_gps_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msm_mux_jitter_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msm_mux_ldo_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msm_mux_ldo_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) msm_mux_lpass_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msm_mux_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msm_mux_mdp_vsync0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msm_mux_mdp_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msm_mux_mdp_vsync2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) msm_mux_mdp_vsync3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msm_mux_mi2s_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msm_mux_mi2s_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) msm_mux_mi2s_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) msm_mux_mss_lte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msm_mux_m_voc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msm_mux_pa_indicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) msm_mux_phase_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) msm_mux_PLL_BIST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) msm_mux_pll_bypassnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msm_mux_pll_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) msm_mux_prng_rosc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msm_mux_qdss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msm_mux_qdss_cti,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) msm_mux_qlink_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) msm_mux_qlink_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) msm_mux_qspi_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msm_mux_qspi_cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msm_mux_qspi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msm_mux_qup00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msm_mux_qup01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msm_mux_qup02_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) msm_mux_qup02_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msm_mux_qup03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msm_mux_qup04_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msm_mux_qup04_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msm_mux_qup05,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) msm_mux_qup10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) msm_mux_qup11_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msm_mux_qup11_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msm_mux_qup12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msm_mux_qup13_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msm_mux_qup13_uart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msm_mux_qup14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msm_mux_qup15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msm_mux_sdc1_tb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msm_mux_sdc2_tb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msm_mux_sd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msm_mux_sp_cmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) msm_mux_tgu_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) msm_mux_tgu_ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) msm_mux_tgu_ch2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) msm_mux_tgu_ch3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) msm_mux_tsense_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) msm_mux_tsense_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) msm_mux_uim1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) msm_mux_uim2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) msm_mux_uim_batt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) msm_mux_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) msm_mux_vfr_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) msm_mux__V_GPIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) msm_mux__V_PPS_IN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) msm_mux__V_PPS_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msm_mux_vsense_trigger,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) msm_mux_wlan1_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) msm_mux_wlan1_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msm_mux_wlan2_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msm_mux_wlan2_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msm_mux__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const char * const qup01_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "gpio0", "gpio1", "gpio2", "gpio3", "gpio12", "gpio94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "gpio117", "gpio118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const char * const phase_flag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "gpio0", "gpio1", "gpio2", "gpio8", "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "gpio11", "gpio12", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "gpio20", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "gpio37", "gpio38", "gpio39", "gpio42", "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "gpio56", "gpio57", "gpio58", "gpio63", "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "gpio108", "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const char * const cri_trng_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "gpio0", "gpio1", "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const char * const sp_cmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const char * const dbg_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const char * const qdss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "gpio3", "gpio4", "gpio8", "gpio9", "gpio33", "gpio44", "gpio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const char * const sdc1_tb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "gpio4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const char * const sdc2_tb_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static const char * const qup11_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const char * const qup11_uart_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const char * const ddr_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) "gpio7", "gpio8", "gpio9", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const char * const gp_pdm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "gpio8", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const char * const mdp_vsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "gpio10", "gpio11", "gpio12", "gpio70", "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const char * const edp_lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const char * const ddr_pxi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "gpio11", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static const char * const m_voc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const char * const wlan2_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const char * const atest_usb10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const char * const ddr_pxi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "gpio12", "gpio108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const char * const cam_mclk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "gpio13", "gpio14", "gpio15", "gpio16", "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const char * const pll_bypassnl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const char * const qdss_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "gpio13", "gpio86", "gpio14", "gpio87",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) "gpio15", "gpio88", "gpio16", "gpio89",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "gpio17", "gpio90", "gpio18", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "gpio19", "gpio21", "gpio20", "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "gpio23", "gpio54", "gpio24", "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "gpio25", "gpio57", "gpio26", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "gpio27", "gpio56", "gpio28", "gpio29",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "gpio30", "gpio35", "gpio93", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "gpio34", "gpio53", "gpio37", "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const char * const pll_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const char * const qup02_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) "gpio15", "gpio16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const char * const qup02_uart_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "gpio15", "gpio16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const char * const cci_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "gpio17", "gpio18", "gpio19", "gpio20", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const char * const wlan1_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const char * const atest_usb12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const char * const ddr_pxi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "gpio17", "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char * const atest_char_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const char * const agera_pll_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "gpio18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const char * const vsense_trigger_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "gpio18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char * const ddr_pxi0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "gpio18", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char * const atest_char3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "gpio18",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const atest_char2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const atest_char1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const char * const cci_timer0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const char * const gcc_gp2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const char * const atest_char0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const char * const cci_timer1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const char * const gcc_gp3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const char * const cci_timer2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const char * const cci_timer3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const char * const cci_async_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const char * const cci_timer4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const char * const qup05_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const char * const atest_tsens_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const char * const atest_usb11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const char * const PLL_BIST_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const char * const sd_write_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const char * const qup00_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "gpio34", "gpio35", "gpio36", "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static const char * const gp_pdm0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "gpio37", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const char * const qup03_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "gpio38", "gpio39", "gpio40", "gpio41",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const char * const atest_tsens2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const char * const wlan2_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const char * const atest_usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const char * const qup12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "gpio42", "gpio43", "gpio44", "gpio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const char * const wlan1_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const char * const atest_usb13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const char * const qup13_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "gpio46", "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const char * const qup13_uart_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "gpio46", "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const char * const gcc_gp1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "gpio48", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const char * const mi2s_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "gpio49", "gpio50", "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const char * const btfm_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "gpio49", "gpio50", "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const char * const atest_usb2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "gpio51",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const char * const atest_usb23_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const char * const mi2s_0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const char * const qup15_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const char * const atest_usb22_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "gpio53",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const char * const atest_usb21_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const char * const atest_usb20_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "gpio55",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const char * const lpass_ext_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const char * const audio_ref_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static const char * const jitter_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const char * const gp_pdm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const char * const qup10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "gpio59", "gpio60", "gpio61", "gpio62", "gpio68", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const char * const tgu_ch3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const char * const qspi_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char * const mdp_vsync0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const char * const mi2s_2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "gpio63", "gpio64", "gpio65", "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const char * const mdp_vsync1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const char * const mdp_vsync2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const char * const mdp_vsync3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const char * const tgu_ch0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const char * const qspi_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "gpio64", "gpio65", "gpio66", "gpio67",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const char * const tgu_ch1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const char * const vfr_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const char * const tgu_ch2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const char * const qspi_cs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "gpio68", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const char * const ldo_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const char * const ldo_update_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const char * const prng_rosc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const char * const uim2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "gpio75", "gpio76", "gpio77", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const char * const uim1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "gpio79", "gpio80", "gpio81", "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const char * const _V_GPIO_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "gpio83", "gpio84", "gpio107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const char * const _V_PPS_IN_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "gpio83", "gpio84", "gpio107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const char * const _V_PPS_OUT_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "gpio83", "gpio84", "gpio107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const char * const gps_tx_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "gpio83", "gpio84", "gpio107", "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const char * const uim_batt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "gpio85",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const char * const dp_hot_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "gpio85", "gpio117",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const char * const aoss_cti_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "gpio85",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const char * const qup14_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const char * const adsp_ext_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "gpio87",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const char * const tsense_pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const char * const tsense_pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const char * const qlink_request_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const char * const qlink_enable_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const char * const pa_indicator_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "gpio99",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const char * const usb_phy_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const char * const mss_lte_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "gpio108", "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const char * const qup04_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const char * const qup04_uart_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static const struct msm_function sc7180_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) FUNCTION(adsp_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) FUNCTION(agera_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) FUNCTION(aoss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) FUNCTION(atest_char),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) FUNCTION(atest_char0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) FUNCTION(atest_char1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) FUNCTION(atest_char2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) FUNCTION(atest_char3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) FUNCTION(atest_tsens),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) FUNCTION(atest_tsens2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) FUNCTION(atest_usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) FUNCTION(atest_usb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) FUNCTION(atest_usb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) FUNCTION(atest_usb11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) FUNCTION(atest_usb12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) FUNCTION(atest_usb13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) FUNCTION(atest_usb20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) FUNCTION(atest_usb21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) FUNCTION(atest_usb22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) FUNCTION(atest_usb23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) FUNCTION(audio_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) FUNCTION(btfm_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) FUNCTION(cam_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) FUNCTION(cci_async),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) FUNCTION(cci_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) FUNCTION(cci_timer0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) FUNCTION(cci_timer1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) FUNCTION(cci_timer2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) FUNCTION(cci_timer3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) FUNCTION(cci_timer4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) FUNCTION(cri_trng),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) FUNCTION(dbg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) FUNCTION(ddr_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) FUNCTION(ddr_pxi0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) FUNCTION(ddr_pxi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) FUNCTION(ddr_pxi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) FUNCTION(ddr_pxi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) FUNCTION(dp_hot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) FUNCTION(edp_lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) FUNCTION(gcc_gp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) FUNCTION(gcc_gp2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) FUNCTION(gcc_gp3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) FUNCTION(gp_pdm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) FUNCTION(gp_pdm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) FUNCTION(gp_pdm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) FUNCTION(gps_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) FUNCTION(jitter_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) FUNCTION(ldo_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) FUNCTION(ldo_update),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) FUNCTION(lpass_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) FUNCTION(mdp_vsync0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) FUNCTION(mdp_vsync1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) FUNCTION(mdp_vsync2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) FUNCTION(mdp_vsync3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) FUNCTION(mi2s_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) FUNCTION(mi2s_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) FUNCTION(mi2s_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) FUNCTION(mss_lte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) FUNCTION(m_voc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) FUNCTION(pa_indicator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) FUNCTION(phase_flag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) FUNCTION(PLL_BIST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) FUNCTION(pll_bypassnl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) FUNCTION(pll_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) FUNCTION(prng_rosc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) FUNCTION(qdss),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) FUNCTION(qdss_cti),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) FUNCTION(qlink_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) FUNCTION(qlink_request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) FUNCTION(qspi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) FUNCTION(qspi_cs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) FUNCTION(qspi_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) FUNCTION(qup00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) FUNCTION(qup01),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) FUNCTION(qup02_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) FUNCTION(qup02_uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) FUNCTION(qup03),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) FUNCTION(qup04_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) FUNCTION(qup04_uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) FUNCTION(qup05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) FUNCTION(qup10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) FUNCTION(qup11_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) FUNCTION(qup11_uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) FUNCTION(qup12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) FUNCTION(qup13_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) FUNCTION(qup13_uart),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) FUNCTION(qup14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) FUNCTION(qup15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) FUNCTION(sdc1_tb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) FUNCTION(sdc2_tb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) FUNCTION(sd_write),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) FUNCTION(sp_cmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) FUNCTION(tgu_ch0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) FUNCTION(tgu_ch1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) FUNCTION(tgu_ch2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) FUNCTION(tgu_ch3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) FUNCTION(tsense_pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) FUNCTION(tsense_pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) FUNCTION(uim1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) FUNCTION(uim2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) FUNCTION(uim_batt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) FUNCTION(usb_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) FUNCTION(vfr_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) FUNCTION(_V_GPIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) FUNCTION(_V_PPS_IN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) FUNCTION(_V_PPS_OUT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) FUNCTION(vsense_trigger),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) FUNCTION(wlan1_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) FUNCTION(wlan1_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) FUNCTION(wlan2_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) FUNCTION(wlan2_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* Every pin is maintained as a single group, and missing or non-existing pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * would be maintained as dummy group to synchronize pin group index with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * pin descriptor registered with pinctrl core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * Clients would not be able to request these dummy pin groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct msm_pingroup sc7180_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) [0] = PINGROUP(0, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) [1] = PINGROUP(1, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) [2] = PINGROUP(2, SOUTH, qup01, cri_trng, _, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) [3] = PINGROUP(3, SOUTH, qup01, sp_cmu, dbg_out, qdss_cti, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) [4] = PINGROUP(4, NORTH, sdc1_tb, _, qdss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) [5] = PINGROUP(5, NORTH, sdc2_tb, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) [6] = PINGROUP(6, NORTH, qup11_i2c, qup11_uart, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) [7] = PINGROUP(7, NORTH, qup11_i2c, qup11_uart, ddr_bist, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) [8] = PINGROUP(8, NORTH, gp_pdm1, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) [9] = PINGROUP(9, NORTH, ddr_bist, _, phase_flag, qdss_cti, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) [10] = PINGROUP(10, NORTH, mdp_vsync, ddr_bist, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) [11] = PINGROUP(11, NORTH, mdp_vsync, edp_lcd, _, phase_flag, ddr_pxi2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) [12] = PINGROUP(12, SOUTH, mdp_vsync, m_voc, qup01, _, phase_flag, wlan2_adc0, atest_usb10, ddr_pxi3, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) [13] = PINGROUP(13, SOUTH, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) [14] = PINGROUP(14, SOUTH, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) [15] = PINGROUP(15, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) [16] = PINGROUP(16, SOUTH, cam_mclk, qup02_i2c, qup02_uart, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) [17] = PINGROUP(17, SOUTH, cci_i2c, _, phase_flag, qdss, _, wlan1_adc0, atest_usb12, ddr_pxi1, atest_char),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) [18] = PINGROUP(18, SOUTH, cci_i2c, agera_pll, _, phase_flag, qdss, vsense_trigger, ddr_pxi0, atest_char3, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) [19] = PINGROUP(19, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) [20] = PINGROUP(20, SOUTH, cci_i2c, _, phase_flag, qdss, atest_char1, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) [21] = PINGROUP(21, NORTH, cci_timer0, gcc_gp2, _, qdss, atest_char0, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) [22] = PINGROUP(22, NORTH, cci_timer1, gcc_gp3, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) [23] = PINGROUP(23, SOUTH, cci_timer2, cam_mclk, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) [24] = PINGROUP(24, SOUTH, cci_timer3, cci_async, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) [25] = PINGROUP(25, SOUTH, cci_timer4, cci_async, qup05, _, phase_flag, qdss, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) [26] = PINGROUP(26, SOUTH, cci_async, qup05, _, phase_flag, qdss, atest_tsens, atest_usb11, ddr_pxi2, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) [27] = PINGROUP(27, SOUTH, cci_i2c, qup05, PLL_BIST, _, phase_flag, qdss, ddr_pxi0, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) [28] = PINGROUP(28, SOUTH, cci_i2c, qup05, _, phase_flag, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) [29] = PINGROUP(29, NORTH, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) [30] = PINGROUP(30, SOUTH, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) [31] = PINGROUP(31, NORTH, _, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) [32] = PINGROUP(32, NORTH, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) [33] = PINGROUP(33, NORTH, sd_write, _, phase_flag, qdss_cti, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) [34] = PINGROUP(34, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) [35] = PINGROUP(35, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) [36] = PINGROUP(36, SOUTH, qup00, _, phase_flag, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) [37] = PINGROUP(37, SOUTH, qup00, gp_pdm0, _, phase_flag, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) [38] = PINGROUP(38, SOUTH, qup03, _, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) [39] = PINGROUP(39, SOUTH, qup03, _, phase_flag, atest_tsens2, wlan2_adc1, atest_usb1, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) [40] = PINGROUP(40, SOUTH, qup03, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) [41] = PINGROUP(41, SOUTH, qup03, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) [42] = PINGROUP(42, NORTH, qup12, _, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) [43] = PINGROUP(43, NORTH, qup12, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) [44] = PINGROUP(44, NORTH, qup12, _, phase_flag, qdss_cti, wlan1_adc1, atest_usb13, ddr_pxi1, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) [45] = PINGROUP(45, NORTH, qup12, qdss_cti, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) [46] = PINGROUP(46, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) [47] = PINGROUP(47, NORTH, qup13_i2c, qup13_uart, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) [48] = PINGROUP(48, NORTH, gcc_gp1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) [49] = PINGROUP(49, WEST, mi2s_1, btfm_slimbus, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) [50] = PINGROUP(50, WEST, mi2s_1, btfm_slimbus, gp_pdm1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) [51] = PINGROUP(51, WEST, mi2s_1, btfm_slimbus, atest_usb2, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) [52] = PINGROUP(52, WEST, mi2s_1, btfm_slimbus, atest_usb23, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) [53] = PINGROUP(53, WEST, mi2s_0, qup15, qdss, atest_usb22, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) [54] = PINGROUP(54, WEST, mi2s_0, qup15, qdss, atest_usb21, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) [55] = PINGROUP(55, WEST, mi2s_0, qup15, qdss, atest_usb20, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) [56] = PINGROUP(56, WEST, mi2s_0, qup15, gcc_gp1, _, phase_flag, qdss, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) [57] = PINGROUP(57, WEST, lpass_ext, audio_ref, jitter_bist, gp_pdm2, _, phase_flag, qdss, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) [58] = PINGROUP(58, WEST, lpass_ext, _, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) [59] = PINGROUP(59, NORTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) [60] = PINGROUP(60, NORTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) [61] = PINGROUP(61, NORTH, qup10, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) [62] = PINGROUP(62, NORTH, qup10, tgu_ch3, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) [63] = PINGROUP(63, NORTH, qspi_clk, mdp_vsync0, mi2s_2, mdp_vsync1, mdp_vsync2, mdp_vsync3, tgu_ch0, _, phase_flag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) [64] = PINGROUP(64, NORTH, qspi_data, mi2s_2, tgu_ch1, _, phase_flag, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) [65] = PINGROUP(65, NORTH, qspi_data, mi2s_2, vfr_1, tgu_ch2, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) [66] = PINGROUP(66, NORTH, qspi_data, mi2s_2, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) [67] = PINGROUP(67, NORTH, qspi_data, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) [68] = PINGROUP(68, NORTH, qspi_cs, qup10, gp_pdm0, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) [69] = PINGROUP(69, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) [70] = PINGROUP(70, NORTH, _, _, mdp_vsync, ldo_en, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) [71] = PINGROUP(71, NORTH, _, mdp_vsync, ldo_update, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) [72] = PINGROUP(72, NORTH, qspi_cs, qup10, prng_rosc, _, qdss_cti, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) [73] = PINGROUP(73, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) [74] = PINGROUP(74, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) [75] = PINGROUP(75, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) [76] = PINGROUP(76, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) [77] = PINGROUP(77, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) [78] = PINGROUP(78, WEST, uim2, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) [79] = PINGROUP(79, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) [80] = PINGROUP(80, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) [81] = PINGROUP(81, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) [82] = PINGROUP(82, WEST, uim1, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) [83] = PINGROUP(83, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) [84] = PINGROUP(84, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) [85] = PINGROUP(85, WEST, uim_batt, dp_hot, aoss_cti, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) [86] = PINGROUP(86, NORTH, qup14, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) [87] = PINGROUP(87, NORTH, qup14, adsp_ext, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) [88] = PINGROUP(88, NORTH, qup14, qdss, tsense_pwm1, tsense_pwm2, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) [89] = PINGROUP(89, NORTH, qup14, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) [90] = PINGROUP(90, NORTH, qup14, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) [91] = PINGROUP(91, NORTH, qup14, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) [92] = PINGROUP(92, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) [93] = PINGROUP(93, NORTH, qdss, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) [94] = PINGROUP(94, SOUTH, qup01, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) [95] = PINGROUP(95, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) [96] = PINGROUP(96, WEST, qlink_request, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) [97] = PINGROUP(97, WEST, qlink_enable, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) [98] = PINGROUP(98, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) [99] = PINGROUP(99, WEST, _, pa_indicator, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) [100] = PINGROUP(100, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) [101] = PINGROUP(101, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) [102] = PINGROUP(102, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) [103] = PINGROUP(103, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) [104] = PINGROUP(104, WEST, usb_phy, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) [105] = PINGROUP(105, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) [106] = PINGROUP(106, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) [107] = PINGROUP(107, WEST, _, _V_GPIO, _V_PPS_IN, _V_PPS_OUT, gps_tx, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) [108] = PINGROUP(108, SOUTH, mss_lte, _, phase_flag, ddr_pxi3, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) [109] = PINGROUP(109, SOUTH, mss_lte, gps_tx, _, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) [110] = PINGROUP(110, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) [111] = PINGROUP(111, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) [112] = PINGROUP(112, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) [113] = PINGROUP(113, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) [114] = PINGROUP(114, NORTH, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) [115] = PINGROUP(115, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) [116] = PINGROUP(116, WEST, qup04_i2c, qup04_uart, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) [117] = PINGROUP(117, WEST, dp_hot, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) [118] = PINGROUP(118, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) [119] = UFS_RESET(ufs_reset, 0x7f000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) [120] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x7a000, 15, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) [121] = SDC_QDSD_PINGROUP(sdc1_clk, 0x7a000, 13, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) [122] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x7a000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) [123] = SDC_QDSD_PINGROUP(sdc1_data, 0x7a000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) [124] = SDC_QDSD_PINGROUP(sdc2_clk, 0x7b000, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) [125] = SDC_QDSD_PINGROUP(sdc2_cmd, 0x7b000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) [126] = SDC_QDSD_PINGROUP(sdc2_data, 0x7b000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const struct msm_gpio_wakeirq_map sc7180_pdc_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {0, 40}, {3, 50}, {4, 42}, {5, 70}, {6, 41}, {9, 35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {10, 80}, {11, 51}, {16, 20}, {21, 55}, {22, 90}, {23, 21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {24, 61}, {26, 52}, {28, 36}, {30, 100}, {31, 33}, {32, 81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {33, 62}, {34, 43}, {36, 91}, {37, 53}, {38, 63}, {39, 72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {41, 101}, {42, 7}, {43, 34}, {45, 73}, {47, 82}, {49, 17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {52, 109}, {53, 102}, {55, 92}, {56, 56}, {57, 57}, {58, 83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {59, 37}, {62, 110}, {63, 111}, {64, 74}, {65, 44}, {66, 93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {67, 58}, {68, 112}, {69, 32}, {70, 54}, {72, 59}, {73, 64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {74, 71}, {78, 31}, {82, 30}, {85, 103}, {86, 38}, {87, 39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {88, 45}, {89, 46}, {90, 47}, {91, 48}, {92, 60}, {93, 49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {94, 84}, {95, 94}, {98, 65}, {101, 66}, {104, 67}, {109, 104},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {110, 68}, {113, 69}, {114, 113}, {115, 108}, {116, 121},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {117, 114}, {118, 119},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static const struct msm_pinctrl_soc_data sc7180_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .pins = sc7180_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .npins = ARRAY_SIZE(sc7180_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .functions = sc7180_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .nfunctions = ARRAY_SIZE(sc7180_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .groups = sc7180_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .ngroups = ARRAY_SIZE(sc7180_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .ngpios = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .tiles = sc7180_tiles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .ntiles = ARRAY_SIZE(sc7180_tiles),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .wakeirq_map = sc7180_pdc_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .nwakeirq_map = ARRAY_SIZE(sc7180_pdc_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .wakeirq_dual_edge_errata = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int sc7180_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return msm_pinctrl_probe(pdev, &sc7180_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static const struct of_device_id sc7180_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) { .compatible = "qcom,sc7180-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static struct platform_driver sc7180_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .name = "sc7180-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .pm = &msm_pinctrl_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) .of_match_table = sc7180_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .probe = sc7180_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) static int __init sc7180_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return platform_driver_register(&sc7180_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) arch_initcall(sc7180_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static void __exit sc7180_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) platform_driver_unregister(&sc7180_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) module_exit(sc7180_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MODULE_DESCRIPTION("QTI sc7180 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) MODULE_DEVICE_TABLE(of, sc7180_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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