^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * GPIO and pin control functions on this SOC are handled by the "TLMM"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * device. The driver which controls this device is pinctrl-msm.c. Each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * SOC with a TLMM is expected to create a client driver that registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * with pinctrl-msm.c. This means that all TLMM drivers are pin control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * This pin control driver is intended to be used only an ACPI-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * system. As such, UEFI will handle all pin control configuration, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * this driver does not provide pin control functions. It is effectively
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * a GPIO-only driver. The alternative is to duplicate the GPIO code of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * pinctrl-msm.c into another driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX_GPIOS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NAME_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct msm_pinctrl_soc_data *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct msm_pingroup *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) char (*names)[NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int avail_gpios; /* The number of GPIOs we support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u8 gpios[MAX_GPIOS]; /* An array of supported GPIOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Query the number of GPIOs from ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) dev_err(&pdev->dev, "missing 'num-gpios' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!num_gpios || num_gpios > MAX_GPIOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* The number of GPIOs in the approved list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ret = device_property_count_u8(&pdev->dev, "gpios");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) dev_err(&pdev->dev, "missing 'gpios' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * The number of available GPIOs should be non-zero, and no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * more than the total number of GPIOS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!ret || ret > num_gpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_err(&pdev->dev, "invalid 'gpios' property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) avail_gpios = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) avail_gpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_err(&pdev->dev, "could not read list of GPIOs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pins = devm_kcalloc(&pdev->dev, num_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) groups = devm_kcalloc(&pdev->dev, num_gpios,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) sizeof(struct msm_pingroup), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (!pinctrl || !pins || !groups || !names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * Initialize the array. GPIOs not listed in the 'gpios' array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * still need a number, but nothing else.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) for (i = 0; i < num_gpios; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pins[i].number = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) groups[i].pins = &pins[i].number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Populate the entries that are meant to be exposed as GPIOs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) for (i = 0; i < avail_gpios; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int gpio = gpios[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) groups[gpio].npins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pins[gpio].name = names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) groups[gpio].name = names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) groups[gpio].ctl_reg = 0x10000 * gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) groups[gpio].mux_bit = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) groups[gpio].pull_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) groups[gpio].drv_bit = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) groups[gpio].oe_bit = 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) groups[gpio].in_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) groups[gpio].out_bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) groups[gpio].intr_enable_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) groups[gpio].intr_status_bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) groups[gpio].intr_target_bit = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) groups[gpio].intr_target_kpss_val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) groups[gpio].intr_raw_status_bit = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) groups[gpio].intr_polarity_bit = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) groups[gpio].intr_detection_bit = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) groups[gpio].intr_detection_width = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pinctrl->pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pinctrl->groups = groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) pinctrl->npins = num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) pinctrl->ngroups = num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pinctrl->ngpios = num_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return msm_pinctrl_probe(pdev, pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {"QCOM8002"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static struct platform_driver qdf2xxx_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .name = "qdf2xxx-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .acpi_match_table = ACPI_PTR(qdf2xxx_acpi_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .probe = qdf2xxx_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int __init qdf2xxx_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return platform_driver_register(&qdf2xxx_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) arch_initcall(qdf2xxx_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void __exit qdf2xxx_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) platform_driver_unregister(&qdf2xxx_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) module_exit(qdf2xxx_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_DESCRIPTION("Qualcomm Technologies QDF2xxx pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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