^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, Sony Mobile Communications AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct pinctrl_pin_desc msm8x74_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(114, "GPIO_114"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(115, "GPIO_115"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(116, "GPIO_116"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(117, "GPIO_117"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(118, "GPIO_118"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(119, "GPIO_119"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(120, "GPIO_120"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(121, "GPIO_121"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(122, "GPIO_122"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(123, "GPIO_123"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(124, "GPIO_124"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(125, "GPIO_125"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(126, "GPIO_126"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(127, "GPIO_127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(128, "GPIO_128"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(129, "GPIO_129"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(130, "GPIO_130"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(131, "GPIO_131"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(132, "GPIO_132"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(133, "GPIO_133"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(134, "GPIO_134"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(135, "GPIO_135"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(136, "GPIO_136"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(137, "GPIO_137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(138, "GPIO_138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(139, "GPIO_139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(140, "GPIO_140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(141, "GPIO_141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(142, "GPIO_142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(143, "GPIO_143"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(144, "GPIO_144"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(145, "GPIO_145"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(146, "SDC1_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(147, "SDC1_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(148, "SDC1_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(149, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(150, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(151, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(152, "HSIC_STROBE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(153, "HSIC_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_MSM_GPIO_PINS(114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_MSM_GPIO_PINS(115);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_MSM_GPIO_PINS(116);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_MSM_GPIO_PINS(117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DECLARE_MSM_GPIO_PINS(118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_MSM_GPIO_PINS(119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECLARE_MSM_GPIO_PINS(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DECLARE_MSM_GPIO_PINS(121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DECLARE_MSM_GPIO_PINS(122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DECLARE_MSM_GPIO_PINS(123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DECLARE_MSM_GPIO_PINS(124);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DECLARE_MSM_GPIO_PINS(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DECLARE_MSM_GPIO_PINS(126);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DECLARE_MSM_GPIO_PINS(127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DECLARE_MSM_GPIO_PINS(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DECLARE_MSM_GPIO_PINS(129);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECLARE_MSM_GPIO_PINS(130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DECLARE_MSM_GPIO_PINS(131);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) DECLARE_MSM_GPIO_PINS(132);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DECLARE_MSM_GPIO_PINS(133);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DECLARE_MSM_GPIO_PINS(134);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DECLARE_MSM_GPIO_PINS(135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DECLARE_MSM_GPIO_PINS(136);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DECLARE_MSM_GPIO_PINS(137);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_MSM_GPIO_PINS(138);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECLARE_MSM_GPIO_PINS(139);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DECLARE_MSM_GPIO_PINS(140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DECLARE_MSM_GPIO_PINS(141);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(142);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(143);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(145);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const unsigned int sdc1_clk_pins[] = { 146 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned int sdc1_cmd_pins[] = { 147 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const unsigned int sdc1_data_pins[] = { 148 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const unsigned int sdc2_clk_pins[] = { 149 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int sdc2_cmd_pins[] = { 150 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const unsigned int sdc2_data_pins[] = { 151 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const unsigned int hsic_strobe_pins[] = { 152 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int hsic_data_pins[] = { 153 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [MSM_MUX_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .npins = ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MSM_MUX_gpio, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MSM_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MSM_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) MSM_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) MSM_MUX_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) MSM_MUX_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MSM_MUX_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MSM_MUX_##f7 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .nfuncs = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .ctl_reg = 0x1000 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .io_reg = 0x1004 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .intr_cfg_reg = 0x1008 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .intr_status_reg = 0x100c + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .intr_target_reg = 0x1008 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .intr_target_kpss_val = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .intr_target_kpss_val = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define HSIC_PINGROUP(pg_name, ctl) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MSM_MUX_gpio, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) MSM_MUX_hsic_ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .nfuncs = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .mux_bit = 25, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .pull_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .drv_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .intr_target_kpss_val = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * TODO: Add the rest of the possible functions and fill out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * the pingroup table below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) enum msm8x74_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) MSM_MUX_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MSM_MUX_cci_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MSM_MUX_cci_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) MSM_MUX_blsp_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) MSM_MUX_blsp_i2c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) MSM_MUX_blsp_i2c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) MSM_MUX_blsp_i2c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) MSM_MUX_blsp_i2c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) MSM_MUX_blsp_i2c6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) MSM_MUX_blsp_i2c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) MSM_MUX_blsp_i2c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MSM_MUX_blsp_i2c9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MSM_MUX_blsp_i2c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MSM_MUX_blsp_i2c11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) MSM_MUX_blsp_i2c12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) MSM_MUX_blsp_spi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MSM_MUX_blsp_spi1_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MSM_MUX_blsp_spi1_cs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MSM_MUX_blsp_spi1_cs3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) MSM_MUX_blsp_spi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MSM_MUX_blsp_spi2_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MSM_MUX_blsp_spi2_cs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MSM_MUX_blsp_spi2_cs3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MSM_MUX_blsp_spi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MSM_MUX_blsp_spi4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MSM_MUX_blsp_spi5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) MSM_MUX_blsp_spi6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) MSM_MUX_blsp_spi7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) MSM_MUX_blsp_spi8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MSM_MUX_blsp_spi9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) MSM_MUX_blsp_spi10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MSM_MUX_blsp_spi10_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) MSM_MUX_blsp_spi10_cs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) MSM_MUX_blsp_spi10_cs3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MSM_MUX_blsp_spi11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MSM_MUX_blsp_spi12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) MSM_MUX_blsp_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) MSM_MUX_blsp_uart2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MSM_MUX_blsp_uart3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MSM_MUX_blsp_uart4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MSM_MUX_blsp_uart5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MSM_MUX_blsp_uart6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MSM_MUX_blsp_uart7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MSM_MUX_blsp_uart8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MSM_MUX_blsp_uart9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MSM_MUX_blsp_uart10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MSM_MUX_blsp_uart11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MSM_MUX_blsp_uart12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MSM_MUX_blsp_uim1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MSM_MUX_blsp_uim2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MSM_MUX_blsp_uim3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MSM_MUX_blsp_uim4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MSM_MUX_blsp_uim5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MSM_MUX_blsp_uim6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MSM_MUX_blsp_uim7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MSM_MUX_blsp_uim8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MSM_MUX_blsp_uim9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MSM_MUX_blsp_uim10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MSM_MUX_blsp_uim11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MSM_MUX_blsp_uim12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MSM_MUX_uim1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MSM_MUX_uim2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MSM_MUX_uim_batt_alarm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MSM_MUX_sdc3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MSM_MUX_sdc4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MSM_MUX_gcc_gp_clk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MSM_MUX_gcc_gp_clk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MSM_MUX_gcc_gp_clk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MSM_MUX_qua_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MSM_MUX_pri_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MSM_MUX_spkr_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MSM_MUX_ter_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MSM_MUX_sec_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MSM_MUX_hdmi_cec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MSM_MUX_hdmi_ddc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MSM_MUX_hdmi_hpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MSM_MUX_edp_hpd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MSM_MUX_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MSM_MUX_cam_mclk0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MSM_MUX_cam_mclk1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MSM_MUX_cam_mclk2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MSM_MUX_cam_mclk3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) MSM_MUX_cci_timer0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) MSM_MUX_cci_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) MSM_MUX_cci_timer2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) MSM_MUX_cci_timer3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) MSM_MUX_cci_timer4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) MSM_MUX_cci_async_in0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MSM_MUX_cci_async_in1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) MSM_MUX_cci_async_in2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) MSM_MUX_gp_pdm0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) MSM_MUX_gp_pdm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MSM_MUX_gp_pdm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MSM_MUX_gp0_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MSM_MUX_gp1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) MSM_MUX_gp_mn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) MSM_MUX_tsif1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) MSM_MUX_tsif2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) MSM_MUX_hsic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) MSM_MUX_grfc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) MSM_MUX_audio_ref_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MSM_MUX_bt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MSM_MUX_fm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) MSM_MUX_wlan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) MSM_MUX_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) MSM_MUX_hsic_ctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) MSM_MUX_NA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "hsic_data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "hsic_strobe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const char * const blsp_uart1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) "gpio0", "gpio1", "gpio2", "gpio3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const char * const blsp_uim1_groups[] = { "gpio0", "gpio1" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static const char * const blsp_i2c1_groups[] = { "gpio2", "gpio3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const char * const blsp_spi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "gpio0", "gpio1", "gpio2", "gpio3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const char * const blsp_spi1_cs1_groups[] = { "gpio8" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const char * const blsp_spi1_cs2_groups[] = { "gpio9", "gpio11" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const char * const blsp_spi1_cs3_groups[] = { "gpio10" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const char * const blsp_uart2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "gpio4", "gpio5", "gpio6", "gpio7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const char * const blsp_uim2_groups[] = { "gpio4", "gpio5" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const char * const blsp_spi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "gpio4", "gpio5", "gpio6", "gpio7"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const char * const blsp_spi2_cs1_groups[] = { "gpio53", "gpio62" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static const char * const blsp_spi2_cs2_groups[] = { "gpio54", "gpio63" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char * const blsp_spi2_cs3_groups[] = { "gpio66" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static const char * const blsp_uart3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "gpio8", "gpio9", "gpio10", "gpio11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static const char * const blsp_uim3_groups[] = { "gpio8", "gpio9" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static const char * const blsp_i2c3_groups[] = { "gpio10", "gpio11" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static const char * const blsp_spi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) "gpio8", "gpio9", "gpio10", "gpio11"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const char * const cci_i2c0_groups[] = { "gpio19", "gpio20" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static const char * const cci_i2c1_groups[] = { "gpio21", "gpio22" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static const char * const blsp_uart4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "gpio19", "gpio20", "gpio21", "gpio22"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const blsp_uim4_groups[] = { "gpio19", "gpio20" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const char * const blsp_i2c4_groups[] = { "gpio21", "gpio22" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const char * const blsp_spi4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "gpio19", "gpio20", "gpio21", "gpio22"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const blsp_uart5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "gpio23", "gpio24", "gpio25", "gpio26"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const char * const blsp_uim5_groups[] = { "gpio23", "gpio24" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const char * const blsp_i2c5_groups[] = { "gpio25", "gpio26" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static const char * const blsp_spi5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "gpio23", "gpio24", "gpio25", "gpio26"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char * const blsp_uart6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "gpio27", "gpio28", "gpio29", "gpio30"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static const char * const blsp_uim6_groups[] = { "gpio27", "gpio28" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const char * const blsp_spi6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "gpio27", "gpio28", "gpio29", "gpio30"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const char * const blsp_uart7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "gpio41", "gpio42", "gpio43", "gpio44"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static const char * const blsp_uim7_groups[] = { "gpio41", "gpio42" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const blsp_i2c7_groups[] = { "gpio43", "gpio44" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const char * const blsp_spi7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "gpio41", "gpio42", "gpio43", "gpio44"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const char * const blsp_uart8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "gpio45", "gpio46", "gpio47", "gpio48"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const char * const blsp_uim8_groups[] = { "gpio45", "gpio46" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const char * const blsp_i2c8_groups[] = { "gpio47", "gpio48" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const char * const blsp_spi8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "gpio45", "gpio46", "gpio47", "gpio48"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static const char * const blsp_uart9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "gpio49", "gpio50", "gpio51", "gpio52"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const char * const blsp_uim9_groups[] = { "gpio49", "gpio50" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const char * const blsp_i2c9_groups[] = { "gpio51", "gpio52" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) static const char * const blsp_spi9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "gpio49", "gpio50", "gpio51", "gpio52"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static const char * const blsp_uart10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "gpio53", "gpio54", "gpio55", "gpio56"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const char * const blsp_uim10_groups[] = { "gpio53", "gpio54" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const char * const blsp_i2c10_groups[] = { "gpio55", "gpio56" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const char * const blsp_spi10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "gpio53", "gpio54", "gpio55", "gpio56"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const char * const blsp_spi10_cs1_groups[] = { "gpio47", "gpio67" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static const char * const blsp_spi10_cs2_groups[] = { "gpio48", "gpio68" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const char * const blsp_spi10_cs3_groups[] = { "gpio90" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static const char * const blsp_uart11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "gpio81", "gpio82", "gpio83", "gpio84"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const char * const blsp_uim11_groups[] = { "gpio81", "gpio82" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const char * const blsp_spi11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "gpio81", "gpio82", "gpio83", "gpio84"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static const char * const blsp_uart12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "gpio85", "gpio86", "gpio87", "gpio88"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static const char * const blsp_uim12_groups[] = { "gpio85", "gpio86" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const char * const blsp_i2c12_groups[] = { "gpio87", "gpio88" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static const char * const blsp_spi12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "gpio85", "gpio86", "gpio87", "gpio88"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static const char * const uim1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "gpio97", "gpio98", "gpio99", "gpio100"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const char * const uim2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "gpio49", "gpio50", "gpio51", "gpio52"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static const char * const uim_batt_alarm_groups[] = { "gpio101" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const char * const sdc3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const char * const sdc4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "gpio91", "gpio92", "gpio93", "gpio94", "gpio95", "gpio96"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const char * const gp0_clk_groups[] = { "gpio26" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const char * const gp1_clk_groups[] = { "gpio27", "gpio57", "gpio78" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const char * const gp_mn_groups[] = { "gpio29" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static const char * const gcc_gp_clk1_groups[] = { "gpio57", "gpio78" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const char * const gcc_gp_clk2_groups[] = { "gpio58", "gpio81" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const char * const gcc_gp_clk3_groups[] = { "gpio59", "gpio82" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const char * const qua_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const char * const pri_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const char * const spkr_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "gpio69", "gpio70", "gpio71", "gpio72"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const char * const ter_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "gpio73", "gpio74", "gpio75", "gpio76", "gpio77"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static const char * const sec_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const char * const hdmi_cec_groups[] = { "gpio31" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const char * const hdmi_ddc_groups[] = { "gpio32", "gpio33" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const char * const hdmi_hpd_groups[] = { "gpio34" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const char * const edp_hpd_groups[] = { "gpio102" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const char * const mdp_vsync_groups[] = { "gpio12", "gpio13", "gpio14" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const char * const cam_mclk0_groups[] = { "gpio15" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const char * const cam_mclk1_groups[] = { "gpio16" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const char * const cam_mclk2_groups[] = { "gpio17" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const char * const cam_mclk3_groups[] = { "gpio18" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const char * const cci_timer0_groups[] = { "gpio23" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const char * const cci_timer1_groups[] = { "gpio24" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const char * const cci_timer2_groups[] = { "gpio25" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const char * const cci_timer3_groups[] = { "gpio26" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const char * const cci_timer4_groups[] = { "gpio27" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const char * const cci_async_in0_groups[] = { "gpio28" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const char * const cci_async_in1_groups[] = { "gpio26" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const char * const cci_async_in2_groups[] = { "gpio27" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const char * const gp_pdm0_groups[] = { "gpio54", "gpio68" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const char * const gp_pdm1_groups[] = { "gpio74", "gpio86" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const char * const gp_pdm2_groups[] = { "gpio63", "gpio79" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const char * const tsif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "gpio89", "gpio90", "gpio91", "gpio92"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const char * const tsif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "gpio93", "gpio94", "gpio95", "gpio96"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const char * const hsic_groups[] = { "gpio144", "gpio145" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const char * const grfc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "gpio104", "gpio105", "gpio106", "gpio107", "gpio108", "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "gpio110", "gpio111", "gpio112", "gpio113", "gpio114", "gpio115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio127",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "gpio128", "gpio136", "gpio137", "gpio141", "gpio143"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const char * const audio_ref_clk_groups[] = { "gpio69" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const char * const bt_groups[] = { "gpio35", "gpio43", "gpio44" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const char * const fm_groups[] = { "gpio41", "gpio42" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const char * const wlan_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const char * const hsic_ctl_groups[] = { "hsic_strobe", "hsic_data" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static const struct msm_function msm8x74_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) FUNCTION(cci_i2c0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) FUNCTION(cci_i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) FUNCTION(uim1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) FUNCTION(uim2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) FUNCTION(uim_batt_alarm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) FUNCTION(blsp_uim1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) FUNCTION(blsp_uim2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) FUNCTION(blsp_uim3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) FUNCTION(blsp_uim4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) FUNCTION(blsp_uim5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) FUNCTION(blsp_uim6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) FUNCTION(blsp_uim7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) FUNCTION(blsp_uim8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) FUNCTION(blsp_uim9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) FUNCTION(blsp_uim10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) FUNCTION(blsp_uim11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) FUNCTION(blsp_uim12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) FUNCTION(blsp_i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) FUNCTION(blsp_i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) FUNCTION(blsp_i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) FUNCTION(blsp_i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) FUNCTION(blsp_i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) FUNCTION(blsp_i2c6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) FUNCTION(blsp_i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) FUNCTION(blsp_i2c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) FUNCTION(blsp_i2c9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) FUNCTION(blsp_i2c10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) FUNCTION(blsp_i2c11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) FUNCTION(blsp_i2c12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) FUNCTION(blsp_spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) FUNCTION(blsp_spi1_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) FUNCTION(blsp_spi1_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) FUNCTION(blsp_spi1_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) FUNCTION(blsp_spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) FUNCTION(blsp_spi2_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) FUNCTION(blsp_spi2_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) FUNCTION(blsp_spi2_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) FUNCTION(blsp_spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) FUNCTION(blsp_spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) FUNCTION(blsp_spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) FUNCTION(blsp_spi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) FUNCTION(blsp_spi7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) FUNCTION(blsp_spi8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) FUNCTION(blsp_spi9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) FUNCTION(blsp_spi10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) FUNCTION(blsp_spi10_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) FUNCTION(blsp_spi10_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) FUNCTION(blsp_spi10_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) FUNCTION(blsp_spi11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) FUNCTION(blsp_spi12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) FUNCTION(blsp_uart1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) FUNCTION(blsp_uart2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) FUNCTION(blsp_uart3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) FUNCTION(blsp_uart4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) FUNCTION(blsp_uart5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) FUNCTION(blsp_uart6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) FUNCTION(blsp_uart7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) FUNCTION(blsp_uart8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) FUNCTION(blsp_uart9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) FUNCTION(blsp_uart10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) FUNCTION(blsp_uart11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) FUNCTION(blsp_uart12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) FUNCTION(sdc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) FUNCTION(sdc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) FUNCTION(gcc_gp_clk1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) FUNCTION(gcc_gp_clk2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) FUNCTION(gcc_gp_clk3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) FUNCTION(qua_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) FUNCTION(pri_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) FUNCTION(spkr_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) FUNCTION(ter_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) FUNCTION(sec_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) FUNCTION(cam_mclk0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) FUNCTION(cam_mclk1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) FUNCTION(cam_mclk2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) FUNCTION(cam_mclk3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) FUNCTION(cci_timer0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) FUNCTION(cci_timer1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) FUNCTION(cci_timer2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) FUNCTION(cci_timer3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) FUNCTION(cci_timer4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) FUNCTION(cci_async_in0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) FUNCTION(cci_async_in1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) FUNCTION(cci_async_in2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) FUNCTION(hdmi_cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) FUNCTION(hdmi_ddc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) FUNCTION(hdmi_hpd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) FUNCTION(edp_hpd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) FUNCTION(gp_pdm0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) FUNCTION(gp_pdm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) FUNCTION(gp_pdm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) FUNCTION(gp0_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) FUNCTION(gp1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) FUNCTION(gp_mn),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) FUNCTION(tsif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) FUNCTION(tsif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) FUNCTION(hsic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) FUNCTION(grfc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) FUNCTION(audio_ref_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) FUNCTION(bt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) FUNCTION(fm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) FUNCTION(wlan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) FUNCTION(slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) FUNCTION(hsic_ctl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const struct msm_pingroup msm8x74_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) PINGROUP(0, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) PINGROUP(1, blsp_spi1, blsp_uart1, blsp_uim1, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) PINGROUP(2, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) PINGROUP(3, blsp_spi1, blsp_uart1, blsp_i2c1, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) PINGROUP(4, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) PINGROUP(5, blsp_spi2, blsp_uart2, blsp_uim2, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) PINGROUP(6, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) PINGROUP(7, blsp_spi2, blsp_uart2, blsp_i2c2, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) PINGROUP(8, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs1, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) PINGROUP(9, blsp_spi3, blsp_uart3, blsp_uim3, blsp_spi1_cs2, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) PINGROUP(10, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs3, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) PINGROUP(11, blsp_spi3, blsp_uart3, blsp_i2c3, blsp_spi1_cs2, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) PINGROUP(12, mdp_vsync, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) PINGROUP(13, mdp_vsync, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) PINGROUP(14, mdp_vsync, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) PINGROUP(15, cam_mclk0, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) PINGROUP(16, cam_mclk1, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) PINGROUP(17, cam_mclk2, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) PINGROUP(18, cam_mclk3, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) PINGROUP(19, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) PINGROUP(20, cci_i2c0, blsp_spi4, blsp_uart4, blsp_uim4, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) PINGROUP(21, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) PINGROUP(22, cci_i2c1, blsp_spi4, blsp_uart4, blsp_i2c4, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) PINGROUP(23, cci_timer0, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) PINGROUP(24, cci_timer1, blsp_spi5, blsp_uart5, blsp_uim5, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) PINGROUP(25, cci_timer2, blsp_spi5, blsp_uart5, blsp_i2c5, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) PINGROUP(26, cci_timer3, cci_async_in1, blsp_spi5, blsp_uart5, blsp_i2c5, gp0_clk, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) PINGROUP(27, cci_timer4, cci_async_in2, blsp_spi6, blsp_uart6, blsp_i2c6, gp1_clk, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) PINGROUP(28, cci_async_in0, blsp_spi6, blsp_uart6, blsp_uim6, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) PINGROUP(29, blsp_spi6, blsp_uart6, blsp_i2c6, gp_mn, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) PINGROUP(30, blsp_spi6, blsp_uart6, blsp_i2c6, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) PINGROUP(31, hdmi_cec, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) PINGROUP(32, hdmi_ddc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) PINGROUP(33, hdmi_ddc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) PINGROUP(34, hdmi_hpd, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) PINGROUP(35, bt, sdc3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) PINGROUP(36, wlan, sdc3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) PINGROUP(37, wlan, sdc3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) PINGROUP(38, wlan, sdc3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) PINGROUP(39, wlan, sdc3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PINGROUP(40, wlan, sdc3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) PINGROUP(41, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) PINGROUP(42, fm, blsp_spi7, blsp_uart7, blsp_uim7, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) PINGROUP(43, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) PINGROUP(44, bt, blsp_spi7, blsp_uart7, blsp_i2c7, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) PINGROUP(45, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) PINGROUP(46, blsp_spi8, blsp_uart8, blsp_uim8, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) PINGROUP(47, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs1, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) PINGROUP(48, blsp_spi8, blsp_uart8, blsp_i2c8, blsp_spi10_cs2, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) PINGROUP(49, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) PINGROUP(50, uim2, blsp_spi9, blsp_uart9, blsp_uim9, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) PINGROUP(51, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) PINGROUP(52, uim2, blsp_spi9, blsp_uart9, blsp_i2c9, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) PINGROUP(53, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs1, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) PINGROUP(54, blsp_spi10, blsp_uart10, blsp_uim10, blsp_spi2_cs2, gp_pdm0, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) PINGROUP(55, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PINGROUP(56, blsp_spi10, blsp_uart10, blsp_i2c10, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) PINGROUP(57, qua_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PINGROUP(58, qua_mi2s, gcc_gp_clk2, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) PINGROUP(59, qua_mi2s, gcc_gp_clk3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) PINGROUP(60, qua_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) PINGROUP(61, qua_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PINGROUP(62, qua_mi2s, blsp_spi2_cs1, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) PINGROUP(63, qua_mi2s, blsp_spi2_cs2, gp_pdm2, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) PINGROUP(64, pri_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) PINGROUP(65, pri_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) PINGROUP(66, pri_mi2s, blsp_spi2_cs3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) PINGROUP(67, pri_mi2s, blsp_spi10_cs1, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) PINGROUP(68, pri_mi2s, blsp_spi10_cs2, gp_pdm0, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) PINGROUP(69, spkr_mi2s, audio_ref_clk, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PINGROUP(70, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) PINGROUP(71, slimbus, spkr_mi2s, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) PINGROUP(72, spkr_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) PINGROUP(73, ter_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) PINGROUP(74, ter_mi2s, gp_pdm1, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PINGROUP(75, ter_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) PINGROUP(76, ter_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) PINGROUP(77, ter_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) PINGROUP(78, sec_mi2s, gcc_gp_clk1, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) PINGROUP(79, sec_mi2s, gp_pdm2, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) PINGROUP(80, sec_mi2s, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) PINGROUP(81, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk2, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) PINGROUP(82, sec_mi2s, blsp_spi11, blsp_uart11, blsp_uim11, gcc_gp_clk3, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) PINGROUP(83, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) PINGROUP(84, blsp_spi11, blsp_uart11, blsp_i2c11, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PINGROUP(85, blsp_spi12, blsp_uart12, blsp_uim12, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) PINGROUP(86, blsp_spi12, blsp_uart12, blsp_uim12, gp_pdm1, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) PINGROUP(87, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PINGROUP(88, blsp_spi12, blsp_uart12, blsp_i2c12, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) PINGROUP(89, tsif1, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) PINGROUP(90, tsif1, blsp_spi10_cs3, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) PINGROUP(91, tsif1, sdc4, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) PINGROUP(92, tsif1, sdc4, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) PINGROUP(93, tsif2, sdc4, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) PINGROUP(94, tsif2, sdc4, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) PINGROUP(95, tsif2, sdc4, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) PINGROUP(96, tsif2, sdc4, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) PINGROUP(97, uim1, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) PINGROUP(98, uim1, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) PINGROUP(99, uim1, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) PINGROUP(100, uim1, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) PINGROUP(101, uim_batt_alarm, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) PINGROUP(102, edp_hpd, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) PINGROUP(104, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) PINGROUP(105, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) PINGROUP(106, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) PINGROUP(107, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) PINGROUP(108, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) PINGROUP(109, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) PINGROUP(110, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) PINGROUP(111, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) PINGROUP(112, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) PINGROUP(113, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) PINGROUP(114, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PINGROUP(115, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) PINGROUP(116, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) PINGROUP(117, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) PINGROUP(118, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) PINGROUP(119, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) PINGROUP(120, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) PINGROUP(121, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) PINGROUP(122, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) PINGROUP(123, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) PINGROUP(124, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) PINGROUP(125, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) PINGROUP(126, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) PINGROUP(127, grfc, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) PINGROUP(128, NA, grfc, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) PINGROUP(129, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) PINGROUP(130, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) PINGROUP(131, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) PINGROUP(132, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) PINGROUP(133, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) PINGROUP(134, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) PINGROUP(135, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) PINGROUP(136, NA, grfc, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) PINGROUP(137, NA, grfc, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PINGROUP(140, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) PINGROUP(141, NA, grfc, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) PINGROUP(142, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) PINGROUP(143, NA, grfc, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) PINGROUP(144, hsic, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) PINGROUP(145, hsic, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) HSIC_PINGROUP(hsic_strobe, 0x2050),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) HSIC_PINGROUP(hsic_data, 0x2054),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define NUM_GPIO_PINGROUPS 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .pins = msm8x74_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .npins = ARRAY_SIZE(msm8x74_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .functions = msm8x74_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .nfunctions = ARRAY_SIZE(msm8x74_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .groups = msm8x74_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .ngroups = ARRAY_SIZE(msm8x74_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .ngpios = NUM_GPIO_PINGROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static int msm8x74_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return msm_pinctrl_probe(pdev, &msm8x74_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static const struct of_device_id msm8x74_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) { .compatible = "qcom,msm8974-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static struct platform_driver msm8x74_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .name = "msm8x74-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .of_match_table = msm8x74_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .probe = msm8x74_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static int __init msm8x74_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return platform_driver_register(&msm8x74_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) arch_initcall(msm8x74_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static void __exit msm8x74_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) platform_driver_unregister(&msm8x74_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) module_exit(msm8x74_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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