^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define NORTH 0x500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define WEST 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EAST 0x900000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [msm_mux_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .npins = ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) msm_mux_gpio, /* gpio mode */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) msm_mux_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) msm_mux_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) msm_mux_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) msm_mux_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) msm_mux_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) msm_mux_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) msm_mux_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) msm_mux_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) msm_mux_##f9 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .nfuncs = 10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .ctl_reg = base + 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .io_reg = base + 0x4 + 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .intr_cfg_reg = base + 0x8 + 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .intr_status_reg = base + 0xc + 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .intr_target_reg = base + 0x8 + 0x1000 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .intr_target_bit = 5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .intr_target_kpss_val = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .intr_raw_status_bit = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .intr_detection_width = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define UFS_RESET(pg_name, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .ctl_reg = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .io_reg = offset + 0x4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .pull_bit = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .drv_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .out_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct pinctrl_pin_desc msm8998_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PINCTRL_PIN(69, "GPIO_69"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PINCTRL_PIN(70, "GPIO_70"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PINCTRL_PIN(71, "GPIO_71"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PINCTRL_PIN(72, "GPIO_72"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PINCTRL_PIN(73, "GPIO_73"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PINCTRL_PIN(74, "GPIO_74"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(75, "GPIO_75"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(76, "GPIO_76"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(77, "GPIO_77"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(78, "GPIO_78"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(79, "GPIO_79"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(80, "GPIO_80"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(81, "GPIO_81"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(82, "GPIO_82"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(83, "GPIO_83"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(84, "GPIO_84"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(85, "GPIO_85"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(86, "GPIO_86"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(87, "GPIO_87"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(88, "GPIO_88"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(89, "GPIO_89"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(90, "GPIO_90"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(91, "GPIO_91"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(92, "GPIO_92"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(93, "GPIO_93"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(94, "GPIO_94"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(95, "GPIO_95"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(96, "GPIO_96"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(97, "GPIO_97"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(98, "GPIO_98"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(99, "GPIO_99"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(100, "GPIO_100"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(101, "GPIO_101"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(102, "GPIO_102"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(103, "GPIO_103"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(104, "GPIO_104"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(105, "GPIO_105"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(106, "GPIO_106"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(107, "GPIO_107"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(108, "GPIO_108"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(109, "GPIO_109"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(110, "GPIO_110"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(111, "GPIO_111"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(112, "GPIO_112"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(113, "GPIO_113"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(114, "GPIO_114"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(115, "GPIO_115"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(116, "GPIO_116"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(117, "GPIO_117"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(118, "GPIO_118"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(119, "GPIO_119"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(120, "GPIO_120"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(121, "GPIO_121"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(122, "GPIO_122"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(123, "GPIO_123"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(124, "GPIO_124"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(125, "GPIO_125"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(126, "GPIO_126"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(127, "GPIO_127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(128, "GPIO_128"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(129, "GPIO_129"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(130, "GPIO_130"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(131, "GPIO_131"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(132, "GPIO_132"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(133, "GPIO_133"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(134, "GPIO_134"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(135, "GPIO_135"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(136, "GPIO_136"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(137, "GPIO_137"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(138, "GPIO_138"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(139, "GPIO_139"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(140, "GPIO_140"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(141, "GPIO_141"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(142, "GPIO_142"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(143, "GPIO_143"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(144, "GPIO_144"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(145, "GPIO_145"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(146, "GPIO_146"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(147, "GPIO_147"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(148, "GPIO_148"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(149, "GPIO_149"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(150, "SDC2_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(151, "SDC2_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(152, "SDC2_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(153, "UFS_RESET"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define DECLARE_MSM_GPIO_PINS(pin) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) DECLARE_MSM_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) DECLARE_MSM_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) DECLARE_MSM_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) DECLARE_MSM_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) DECLARE_MSM_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) DECLARE_MSM_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) DECLARE_MSM_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) DECLARE_MSM_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) DECLARE_MSM_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) DECLARE_MSM_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) DECLARE_MSM_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) DECLARE_MSM_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) DECLARE_MSM_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) DECLARE_MSM_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) DECLARE_MSM_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) DECLARE_MSM_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) DECLARE_MSM_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) DECLARE_MSM_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DECLARE_MSM_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DECLARE_MSM_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DECLARE_MSM_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DECLARE_MSM_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DECLARE_MSM_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) DECLARE_MSM_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DECLARE_MSM_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) DECLARE_MSM_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) DECLARE_MSM_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DECLARE_MSM_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DECLARE_MSM_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DECLARE_MSM_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) DECLARE_MSM_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) DECLARE_MSM_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) DECLARE_MSM_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) DECLARE_MSM_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DECLARE_MSM_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DECLARE_MSM_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DECLARE_MSM_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) DECLARE_MSM_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) DECLARE_MSM_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) DECLARE_MSM_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) DECLARE_MSM_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) DECLARE_MSM_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) DECLARE_MSM_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) DECLARE_MSM_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) DECLARE_MSM_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) DECLARE_MSM_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DECLARE_MSM_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) DECLARE_MSM_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) DECLARE_MSM_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) DECLARE_MSM_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) DECLARE_MSM_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) DECLARE_MSM_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) DECLARE_MSM_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) DECLARE_MSM_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) DECLARE_MSM_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) DECLARE_MSM_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) DECLARE_MSM_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DECLARE_MSM_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DECLARE_MSM_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DECLARE_MSM_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DECLARE_MSM_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) DECLARE_MSM_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) DECLARE_MSM_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DECLARE_MSM_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) DECLARE_MSM_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) DECLARE_MSM_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DECLARE_MSM_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) DECLARE_MSM_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) DECLARE_MSM_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) DECLARE_MSM_GPIO_PINS(69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) DECLARE_MSM_GPIO_PINS(70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) DECLARE_MSM_GPIO_PINS(71);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) DECLARE_MSM_GPIO_PINS(72);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) DECLARE_MSM_GPIO_PINS(73);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) DECLARE_MSM_GPIO_PINS(74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) DECLARE_MSM_GPIO_PINS(75);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) DECLARE_MSM_GPIO_PINS(76);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) DECLARE_MSM_GPIO_PINS(77);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) DECLARE_MSM_GPIO_PINS(78);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) DECLARE_MSM_GPIO_PINS(79);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) DECLARE_MSM_GPIO_PINS(80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) DECLARE_MSM_GPIO_PINS(81);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) DECLARE_MSM_GPIO_PINS(82);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) DECLARE_MSM_GPIO_PINS(83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) DECLARE_MSM_GPIO_PINS(84);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) DECLARE_MSM_GPIO_PINS(85);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) DECLARE_MSM_GPIO_PINS(86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) DECLARE_MSM_GPIO_PINS(87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) DECLARE_MSM_GPIO_PINS(88);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) DECLARE_MSM_GPIO_PINS(89);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) DECLARE_MSM_GPIO_PINS(90);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DECLARE_MSM_GPIO_PINS(91);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) DECLARE_MSM_GPIO_PINS(92);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DECLARE_MSM_GPIO_PINS(93);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) DECLARE_MSM_GPIO_PINS(94);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DECLARE_MSM_GPIO_PINS(95);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) DECLARE_MSM_GPIO_PINS(96);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) DECLARE_MSM_GPIO_PINS(97);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DECLARE_MSM_GPIO_PINS(98);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DECLARE_MSM_GPIO_PINS(99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) DECLARE_MSM_GPIO_PINS(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) DECLARE_MSM_GPIO_PINS(101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) DECLARE_MSM_GPIO_PINS(102);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) DECLARE_MSM_GPIO_PINS(103);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) DECLARE_MSM_GPIO_PINS(104);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) DECLARE_MSM_GPIO_PINS(105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DECLARE_MSM_GPIO_PINS(106);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) DECLARE_MSM_GPIO_PINS(107);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) DECLARE_MSM_GPIO_PINS(108);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) DECLARE_MSM_GPIO_PINS(109);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DECLARE_MSM_GPIO_PINS(110);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) DECLARE_MSM_GPIO_PINS(111);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DECLARE_MSM_GPIO_PINS(112);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) DECLARE_MSM_GPIO_PINS(113);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) DECLARE_MSM_GPIO_PINS(114);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DECLARE_MSM_GPIO_PINS(115);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DECLARE_MSM_GPIO_PINS(116);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DECLARE_MSM_GPIO_PINS(117);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DECLARE_MSM_GPIO_PINS(118);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DECLARE_MSM_GPIO_PINS(119);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DECLARE_MSM_GPIO_PINS(120);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DECLARE_MSM_GPIO_PINS(121);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DECLARE_MSM_GPIO_PINS(122);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DECLARE_MSM_GPIO_PINS(123);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DECLARE_MSM_GPIO_PINS(124);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DECLARE_MSM_GPIO_PINS(125);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DECLARE_MSM_GPIO_PINS(126);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DECLARE_MSM_GPIO_PINS(127);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DECLARE_MSM_GPIO_PINS(128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DECLARE_MSM_GPIO_PINS(129);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DECLARE_MSM_GPIO_PINS(130);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DECLARE_MSM_GPIO_PINS(131);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DECLARE_MSM_GPIO_PINS(132);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DECLARE_MSM_GPIO_PINS(133);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DECLARE_MSM_GPIO_PINS(134);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DECLARE_MSM_GPIO_PINS(135);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DECLARE_MSM_GPIO_PINS(136);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DECLARE_MSM_GPIO_PINS(137);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DECLARE_MSM_GPIO_PINS(138);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DECLARE_MSM_GPIO_PINS(139);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DECLARE_MSM_GPIO_PINS(140);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DECLARE_MSM_GPIO_PINS(141);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DECLARE_MSM_GPIO_PINS(142);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DECLARE_MSM_GPIO_PINS(143);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DECLARE_MSM_GPIO_PINS(144);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DECLARE_MSM_GPIO_PINS(145);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DECLARE_MSM_GPIO_PINS(146);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DECLARE_MSM_GPIO_PINS(147);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DECLARE_MSM_GPIO_PINS(148);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DECLARE_MSM_GPIO_PINS(149);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static const unsigned int sdc2_clk_pins[] = { 150 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const unsigned int sdc2_cmd_pins[] = { 151 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static const unsigned int sdc2_data_pins[] = { 152 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const unsigned int ufs_reset_pins[] = { 153 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) enum msm8998_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) msm_mux_adsp_ext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msm_mux_agera_pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msm_mux_atest_char,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) msm_mux_atest_gpsadc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) msm_mux_atest_gpsadc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) msm_mux_atest_tsens,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) msm_mux_atest_tsens2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) msm_mux_atest_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) msm_mux_atest_usb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) msm_mux_atest_usb11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) msm_mux_atest_usb12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) msm_mux_atest_usb13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) msm_mux_audio_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) msm_mux_bimc_dte0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msm_mux_bimc_dte1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) msm_mux_blsp10_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) msm_mux_blsp10_spi_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) msm_mux_blsp10_spi_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) msm_mux_blsp11_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) msm_mux_blsp1_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) msm_mux_blsp1_spi_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msm_mux_blsp1_spi_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) msm_mux_blsp2_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) msm_mux_blsp9_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) msm_mux_blsp_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) msm_mux_blsp_i2c10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) msm_mux_blsp_i2c11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) msm_mux_blsp_i2c12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) msm_mux_blsp_i2c2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msm_mux_blsp_i2c3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) msm_mux_blsp_i2c4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) msm_mux_blsp_i2c5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msm_mux_blsp_i2c6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) msm_mux_blsp_i2c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) msm_mux_blsp_i2c8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msm_mux_blsp_i2c9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) msm_mux_blsp_spi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) msm_mux_blsp_spi10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msm_mux_blsp_spi11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msm_mux_blsp_spi12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msm_mux_blsp_spi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msm_mux_blsp_spi3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) msm_mux_blsp_spi4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) msm_mux_blsp_spi5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msm_mux_blsp_spi6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msm_mux_blsp_spi7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msm_mux_blsp_spi8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msm_mux_blsp_spi9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) msm_mux_blsp_uart1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) msm_mux_blsp_uart1_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) msm_mux_blsp_uart2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) msm_mux_blsp_uart2_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) msm_mux_blsp_uart3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) msm_mux_blsp_uart3_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) msm_mux_blsp_uart7_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) msm_mux_blsp_uart7_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) msm_mux_blsp_uart8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) msm_mux_blsp_uart8_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) msm_mux_blsp_uart8_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) msm_mux_blsp_uart9_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) msm_mux_blsp_uart9_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) msm_mux_blsp_uim1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) msm_mux_blsp_uim1_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) msm_mux_blsp_uim2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) msm_mux_blsp_uim2_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) msm_mux_blsp_uim3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) msm_mux_blsp_uim3_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) msm_mux_blsp_uim7_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msm_mux_blsp_uim7_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) msm_mux_blsp_uim8_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) msm_mux_blsp_uim8_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msm_mux_blsp_uim9_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msm_mux_blsp_uim9_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msm_mux_bt_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) msm_mux_btfm_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msm_mux_cam_mclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msm_mux_cci_async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msm_mux_cci_i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) msm_mux_cci_timer0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msm_mux_cci_timer1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msm_mux_cci_timer2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_mux_cci_timer3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msm_mux_cci_timer4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msm_mux_cri_trng,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msm_mux_cri_trng0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msm_mux_cri_trng1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msm_mux_dbg_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) msm_mux_ddr_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msm_mux_edp_hot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msm_mux_edp_lcd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msm_mux_gcc_gp1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msm_mux_gcc_gp1_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msm_mux_gcc_gp2_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) msm_mux_gcc_gp2_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) msm_mux_gcc_gp3_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) msm_mux_gcc_gp3_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) msm_mux_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) msm_mux_hdmi_cec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) msm_mux_hdmi_ddc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) msm_mux_hdmi_hot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) msm_mux_hdmi_rcv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msm_mux_isense_dbg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) msm_mux_jitter_bist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) msm_mux_ldo_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msm_mux_ldo_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) msm_mux_lpass_slimbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) msm_mux_m_voc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msm_mux_mdp_vsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msm_mux_mdp_vsync0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) msm_mux_mdp_vsync1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) msm_mux_mdp_vsync2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) msm_mux_mdp_vsync3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) msm_mux_mdp_vsync_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) msm_mux_mdp_vsync_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) msm_mux_modem_tsync,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) msm_mux_mss_lte,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) msm_mux_nav_dr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) msm_mux_nav_pps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) msm_mux_pa_indicator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msm_mux_pci_e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msm_mux_phase_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msm_mux_pll_bypassnl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msm_mux_pll_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) msm_mux_pri_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) msm_mux_pri_mi2s_ws,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) msm_mux_prng_rosc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msm_mux_pwr_crypto,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msm_mux_pwr_modem,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msm_mux_pwr_nav,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msm_mux_qdss_cti0_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) msm_mux_qdss_cti0_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) msm_mux_qdss_cti1_a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) msm_mux_qdss_cti1_b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) msm_mux_qdss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) msm_mux_qlink_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msm_mux_qlink_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) msm_mux_qua_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) msm_mux_sd_card,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) msm_mux_sd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msm_mux_sdc40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) msm_mux_sdc41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) msm_mux_sdc42,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) msm_mux_sdc43,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) msm_mux_sdc4_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) msm_mux_sdc4_cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) msm_mux_sec_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) msm_mux_sp_cmu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) msm_mux_spkr_i2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msm_mux_ssbi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) msm_mux_ssc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) msm_mux_ter_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) msm_mux_tgu_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) msm_mux_tgu_ch1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) msm_mux_tsense_pwm1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) msm_mux_tsense_pwm2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) msm_mux_tsif0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) msm_mux_tsif1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) msm_mux_uim1_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) msm_mux_uim1_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) msm_mux_uim1_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) msm_mux_uim1_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) msm_mux_uim2_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) msm_mux_uim2_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) msm_mux_uim2_present,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) msm_mux_uim2_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msm_mux_uim_batt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) msm_mux_usb_phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msm_mux_vfr_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msm_mux_vsense_clkout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) msm_mux_vsense_data0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) msm_mux_vsense_data1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) msm_mux_vsense_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) msm_mux_wlan1_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) msm_mux_wlan1_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) msm_mux_wlan2_adc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) msm_mux_wlan2_adc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) msm_mux__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "gpio147", "gpio148", "gpio149",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char * const blsp_spi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const char * const blsp_uim1_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "gpio0", "gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static const char * const blsp_uart1_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "gpio0", "gpio1", "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const char * const blsp_i2c1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "gpio2", "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static const char * const blsp_spi8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static const char * const blsp_uart8_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static const char * const blsp_uim8_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "gpio4", "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static const char * const qdss_cti0_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "gpio4", "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const char * const blsp_i2c8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const char * const ddr_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "gpio7", "gpio8", "gpio9", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const char * const atest_tsens2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static const char * const atest_usb1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const char * const blsp_spi4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "gpio8", "gpio9", "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static const char * const blsp_uart1_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "gpio8", "gpio9", "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const char * const blsp_uim1_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "gpio8", "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static const char * const wlan1_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const char * const atest_usb13_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const char * const bimc_dte1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "gpio8", "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static const char * const wlan1_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const char * const atest_usb12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const char * const bimc_dte0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "gpio9", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const char * const mdp_vsync_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const char * const blsp_i2c4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const char * const atest_gpsadc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const char * const wlan2_adc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static const char * const atest_usb11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static const char * const edp_lcd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static const char * const dbg_out_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const char * const atest_gpsadc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const char * const wlan2_adc0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const char * const atest_usb10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const char * const mdp_vsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const char * const m_voc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const char * const cam_mclk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "gpio13", "gpio14", "gpio15", "gpio16",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const char * const pll_bypassnl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const char * const qdss_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "gpio13", "gpio14", "gpio15", "gpio16", "gpio17", "gpio18", "gpio19",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "gpio20", "gpio21", "gpio22", "gpio23", "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "gpio27", "gpio28", "gpio29", "gpio30", "gpio41", "gpio42", "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "gpio44", "gpio75", "gpio76", "gpio77", "gpio79", "gpio80", "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "gpio123", "gpio124",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const char * const pll_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const char * const cci_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "gpio17", "gpio18", "gpio19", "gpio20",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const char * const phase_flag_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "gpio18", "gpio19", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "gpio89", "gpio91", "gpio92", "gpio96", "gpio114", "gpio115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "gpio116", "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "gpio122", "gpio123", "gpio124", "gpio125", "gpio126", "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const char * const cci_timer4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const char * const blsp2_spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "gpio25", "gpio29", "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const char * const cci_timer0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const char * const vsense_data0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static const char * const cci_timer1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static const char * const vsense_data1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "gpio22",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const char * const cci_timer2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static const char * const blsp1_spi_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "gpio23", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const char * const vsense_mode_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "gpio23",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const char * const cci_timer3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static const char * const cci_async_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "gpio24", "gpio25", "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static const char * const blsp1_spi_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "gpio24", "gpio27",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static const char * const vsense_clkout_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) "gpio24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const char * const hdmi_rcv_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "gpio30",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static const char * const hdmi_cec_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static const char * const blsp_spi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "gpio31", "gpio32", "gpio33", "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static const char * const blsp_uart2_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "gpio31", "gpio32", "gpio33", "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const char * const blsp_uim2_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "gpio31", "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static const char * const pwr_modem_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const char * const hdmi_ddc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "gpio32", "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static const char * const blsp_i2c2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "gpio32", "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const char * const pwr_nav_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "gpio32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static const char * const pwr_crypto_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "gpio33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const char * const hdmi_hot_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const char * const edp_hot_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "gpio34",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const char * const pci_e0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "gpio35", "gpio36", "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static const char * const jitter_bist_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const char * const agera_pll_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "gpio36", "gpio37",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const char * const atest_tsens_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "gpio36",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const char * const usb_phy_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "gpio38",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const char * const lpass_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "gpio39", "gpio70", "gpio71", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const char * const sd_write_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "gpio40",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static const char * const blsp_spi6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "gpio41", "gpio42", "gpio43", "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static const char * const blsp_uart3_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "gpio41", "gpio42", "gpio43", "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static const char * const blsp_uim3_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const char * const blsp_i2c6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "gpio43", "gpio44",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static const char * const bt_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "gpio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static const char * const blsp_spi3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "gpio45", "gpio46", "gpio47", "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static const char * const blsp_uart3_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "gpio45", "gpio46", "gpio47", "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static const char * const blsp_uim3_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "gpio45", "gpio46",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static const char * const blsp_i2c3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "gpio47", "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static const char * const blsp_spi9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "gpio49", "gpio50", "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static const char * const blsp_uart9_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "gpio49", "gpio50", "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static const char * const blsp_uim9_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "gpio49", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const char * const blsp10_spi_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "gpio49", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const char * const qdss_cti0_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "gpio49", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static const char * const blsp_i2c9_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static const char * const blsp10_spi_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "gpio51", "gpio52",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const char * const blsp_spi7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const char * const blsp_uart7_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static const char * const blsp_uim7_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) "gpio53", "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) static const char * const blsp_i2c7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const char * const qua_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) static const char * const blsp10_spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static const char * const gcc_gp1_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) "gpio57",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const char * const ssc_irq_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const char * const blsp_spi11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) "gpio58", "gpio59", "gpio60", "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const char * const blsp_uart8_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) "gpio58", "gpio59", "gpio60", "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const char * const blsp_uim8_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) "gpio58", "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const char * const gcc_gp2_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const char * const qdss_cti1_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) "gpio58", "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const char * const gcc_gp3_a_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const char * const blsp_i2c11_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) "gpio60", "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const char * const cri_trng0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) "gpio60",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const char * const cri_trng1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const char * const cri_trng_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const char * const pri_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "gpio64", "gpio65", "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const char * const sp_cmu_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) "gpio64",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static const char * const blsp_spi10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) "gpio65", "gpio66", "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const char * const blsp_uart7_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) "gpio65", "gpio66", "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static const char * const blsp_uim7_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) "gpio65", "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const char * const pri_mi2s_ws_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const char * const blsp_i2c10_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const char * const spkr_i2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) "gpio69", "gpio70", "gpio71", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const char * const audio_ref_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "gpio69",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const char * const blsp9_spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "gpio70", "gpio71", "gpio72",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const char * const tsense_pwm1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const char * const tsense_pwm2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) "gpio71",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const char * const btfm_slimbus_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) "gpio73", "gpio74",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const char * const ter_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static const char * const gcc_gp1_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) "gpio78",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const char * const sec_mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const char * const blsp_spi12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const char * const blsp_uart9_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "gpio81", "gpio82", "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static const char * const blsp_uim9_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "gpio81", "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static const char * const gcc_gp2_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "gpio81",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static const char * const gcc_gp3_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "gpio82",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static const char * const blsp_i2c12_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "gpio83", "gpio84",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static const char * const blsp_spi5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "gpio85", "gpio86", "gpio87", "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static const char * const blsp_uart2_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "gpio85", "gpio86", "gpio87", "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) static const char * const blsp_uim2_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) "gpio85", "gpio86",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static const char * const blsp_i2c5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "gpio87", "gpio88",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const char * const tsif0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "gpio9", "gpio40", "gpio89", "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const char * const mdp_vsync0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static const char * const mdp_vsync1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const char * const mdp_vsync2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static const char * const mdp_vsync3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static const char * const blsp1_spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static const char * const tgu_ch0_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "gpio90",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const char * const qdss_cti1_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "gpio90", "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static const char * const sdc4_cmd_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const char * const tgu_ch1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "gpio91",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) static const char * const tsif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "gpio92", "gpio93", "gpio94", "gpio95", "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const char * const sdc43_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const char * const vfr_1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "gpio92",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static const char * const sdc4_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "gpio93",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static const char * const sdc42_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "gpio94",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const char * const sd_card_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static const char * const sdc41_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "gpio95",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const char * const sdc40_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) "gpio96",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static const char * const mdp_vsync_b_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "gpio97", "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static const char * const ldo_en_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "gpio97",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const char * const ldo_update_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "gpio98",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const char * const blsp_uart8_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "gpio100", "gpio101",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static const char * const blsp11_i2c_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "gpio102", "gpio103",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) static const char * const prng_rosc_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "gpio102",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const char * const uim2_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "gpio105",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const char * const uim2_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "gpio106",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static const char * const uim2_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) "gpio107",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) static const char * const uim2_present_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "gpio108",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const char * const uim1_data_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "gpio109",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static const char * const uim1_clk_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "gpio110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const char * const uim1_reset_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "gpio111",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static const char * const uim1_present_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "gpio112",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static const char * const uim_batt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) "gpio113",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const char * const nav_dr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "gpio115",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static const char * const atest_char_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "gpio117", "gpio118", "gpio119", "gpio120", "gpio121",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) static const char * const adsp_ext_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) "gpio118",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const char * const modem_tsync_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static const char * const nav_pps_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "gpio128",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static const char * const qlink_request_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "gpio130",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const char * const qlink_enable_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "gpio131",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) static const char * const pa_indicator_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "gpio135",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static const char * const ssbi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "gpio142",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static const char * const isense_dbg_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "gpio143",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static const char * const mss_lte_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) "gpio144", "gpio145",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static const struct msm_function msm8998_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) FUNCTION(adsp_ext),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) FUNCTION(agera_pll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) FUNCTION(atest_char),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) FUNCTION(atest_gpsadc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) FUNCTION(atest_gpsadc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) FUNCTION(atest_tsens),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) FUNCTION(atest_tsens2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) FUNCTION(atest_usb1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) FUNCTION(atest_usb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) FUNCTION(atest_usb11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) FUNCTION(atest_usb12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) FUNCTION(atest_usb13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) FUNCTION(audio_ref),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) FUNCTION(bimc_dte0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) FUNCTION(bimc_dte1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) FUNCTION(blsp10_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) FUNCTION(blsp10_spi_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) FUNCTION(blsp10_spi_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) FUNCTION(blsp11_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) FUNCTION(blsp1_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) FUNCTION(blsp1_spi_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) FUNCTION(blsp1_spi_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) FUNCTION(blsp2_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) FUNCTION(blsp9_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) FUNCTION(blsp_i2c1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) FUNCTION(blsp_i2c2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) FUNCTION(blsp_i2c3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) FUNCTION(blsp_i2c4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) FUNCTION(blsp_i2c5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) FUNCTION(blsp_i2c6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) FUNCTION(blsp_i2c7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) FUNCTION(blsp_i2c8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) FUNCTION(blsp_i2c9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) FUNCTION(blsp_i2c10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) FUNCTION(blsp_i2c11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) FUNCTION(blsp_i2c12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) FUNCTION(blsp_spi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) FUNCTION(blsp_spi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) FUNCTION(blsp_spi3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) FUNCTION(blsp_spi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) FUNCTION(blsp_spi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) FUNCTION(blsp_spi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) FUNCTION(blsp_spi7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) FUNCTION(blsp_spi8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) FUNCTION(blsp_spi9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) FUNCTION(blsp_spi10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) FUNCTION(blsp_spi11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) FUNCTION(blsp_spi12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) FUNCTION(blsp_uart1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) FUNCTION(blsp_uart1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) FUNCTION(blsp_uart2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) FUNCTION(blsp_uart2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) FUNCTION(blsp_uart3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) FUNCTION(blsp_uart3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) FUNCTION(blsp_uart7_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) FUNCTION(blsp_uart7_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) FUNCTION(blsp_uart8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) FUNCTION(blsp_uart8_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) FUNCTION(blsp_uart8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) FUNCTION(blsp_uart9_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) FUNCTION(blsp_uart9_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) FUNCTION(blsp_uim1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) FUNCTION(blsp_uim1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) FUNCTION(blsp_uim2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) FUNCTION(blsp_uim2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) FUNCTION(blsp_uim3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) FUNCTION(blsp_uim3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) FUNCTION(blsp_uim7_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) FUNCTION(blsp_uim7_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) FUNCTION(blsp_uim8_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) FUNCTION(blsp_uim8_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) FUNCTION(blsp_uim9_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) FUNCTION(blsp_uim9_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) FUNCTION(bt_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) FUNCTION(btfm_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) FUNCTION(cam_mclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) FUNCTION(cci_async),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) FUNCTION(cci_i2c),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) FUNCTION(cci_timer0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) FUNCTION(cci_timer1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) FUNCTION(cci_timer2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) FUNCTION(cci_timer3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) FUNCTION(cci_timer4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) FUNCTION(cri_trng),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) FUNCTION(cri_trng0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) FUNCTION(cri_trng1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) FUNCTION(dbg_out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) FUNCTION(ddr_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) FUNCTION(edp_hot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) FUNCTION(edp_lcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) FUNCTION(gcc_gp1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) FUNCTION(gcc_gp1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) FUNCTION(gcc_gp2_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) FUNCTION(gcc_gp2_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) FUNCTION(gcc_gp3_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) FUNCTION(gcc_gp3_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) FUNCTION(hdmi_cec),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) FUNCTION(hdmi_ddc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) FUNCTION(hdmi_hot),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) FUNCTION(hdmi_rcv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) FUNCTION(isense_dbg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) FUNCTION(jitter_bist),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) FUNCTION(ldo_en),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) FUNCTION(ldo_update),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) FUNCTION(lpass_slimbus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) FUNCTION(m_voc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) FUNCTION(mdp_vsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) FUNCTION(mdp_vsync0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) FUNCTION(mdp_vsync1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) FUNCTION(mdp_vsync2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) FUNCTION(mdp_vsync3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) FUNCTION(mdp_vsync_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) FUNCTION(mdp_vsync_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) FUNCTION(modem_tsync),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) FUNCTION(mss_lte),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) FUNCTION(nav_dr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) FUNCTION(nav_pps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) FUNCTION(pa_indicator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) FUNCTION(pci_e0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) FUNCTION(phase_flag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) FUNCTION(pll_bypassnl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) FUNCTION(pll_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) FUNCTION(pri_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) FUNCTION(pri_mi2s_ws),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) FUNCTION(prng_rosc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) FUNCTION(pwr_crypto),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) FUNCTION(pwr_modem),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) FUNCTION(pwr_nav),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) FUNCTION(qdss_cti0_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) FUNCTION(qdss_cti0_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) FUNCTION(qdss_cti1_a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) FUNCTION(qdss_cti1_b),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) FUNCTION(qdss),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) FUNCTION(qlink_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) FUNCTION(qlink_request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) FUNCTION(qua_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) FUNCTION(sd_card),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) FUNCTION(sd_write),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) FUNCTION(sdc40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) FUNCTION(sdc41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) FUNCTION(sdc42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) FUNCTION(sdc43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) FUNCTION(sdc4_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) FUNCTION(sdc4_cmd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) FUNCTION(sec_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) FUNCTION(sp_cmu),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) FUNCTION(spkr_i2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) FUNCTION(ssbi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) FUNCTION(ssc_irq),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) FUNCTION(ter_mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) FUNCTION(tgu_ch0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) FUNCTION(tgu_ch1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) FUNCTION(tsense_pwm1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) FUNCTION(tsense_pwm2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) FUNCTION(tsif0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) FUNCTION(tsif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) FUNCTION(uim1_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) FUNCTION(uim1_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) FUNCTION(uim1_present),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) FUNCTION(uim1_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) FUNCTION(uim2_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) FUNCTION(uim2_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) FUNCTION(uim2_present),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) FUNCTION(uim2_reset),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) FUNCTION(uim_batt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) FUNCTION(usb_phy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) FUNCTION(vfr_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) FUNCTION(vsense_clkout),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) FUNCTION(vsense_data0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) FUNCTION(vsense_data1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) FUNCTION(vsense_mode),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) FUNCTION(wlan1_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) FUNCTION(wlan1_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) FUNCTION(wlan2_adc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) FUNCTION(wlan2_adc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static const struct msm_pingroup msm8998_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, _, qdss_cti0_b, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, _, atest_tsens2, atest_usb1, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, _, ddr_bist, _, wlan1_adc1, atest_usb13, bimc_dte1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif0, ddr_bist, _, wlan1_adc0, atest_usb12, bimc_dte0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4, ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b, blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) PINGROUP(12, EAST, mdp_vsync, m_voc, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) PINGROUP(14, EAST, cam_mclk, pll_reset, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) PINGROUP(15, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) PINGROUP(16, EAST, cam_mclk, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) PINGROUP(17, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) PINGROUP(18, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) PINGROUP(19, EAST, cci_i2c, phase_flag, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) PINGROUP(20, EAST, cci_i2c, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) PINGROUP(21, EAST, cci_timer0, _, qdss, vsense_data0, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) PINGROUP(22, EAST, cci_timer1, _, qdss, vsense_data1, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss, vsense_mode, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, _, qdss, vsense_clkout, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) PINGROUP(26, EAST, cci_async, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) PINGROUP(27, EAST, blsp1_spi_a, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) PINGROUP(28, EAST, blsp1_spi_b, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) PINGROUP(29, EAST, blsp2_spi, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a, pwr_modem, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_nav, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2, pwr_crypto, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a, blsp_uim2_a, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) PINGROUP(35, NORTH, pci_e0, jitter_bist, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) PINGROUP(36, NORTH, pci_e0, agera_pll, _, atest_tsens, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) PINGROUP(37, NORTH, agera_pll, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) PINGROUP(38, WEST, usb_phy, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) PINGROUP(39, WEST, lpass_slimbus, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) PINGROUP(40, EAST, sd_write, tsif0, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, _, qdss, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, _, qdss_cti1_a, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b, gcc_gp3_a, _, qdss_cti1_a, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng0, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11, cri_trng1, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) PINGROUP(62, WEST, qua_mi2s, cri_trng, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PINGROUP(63, WEST, qua_mi2s, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) PINGROUP(64, WEST, pri_mi2s, sp_cmu, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) PINGROUP(69, WEST, spkr_i2s, audio_ref, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1, tsense_pwm2, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) PINGROUP(73, WEST, btfm_slimbus, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) PINGROUP(75, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) PINGROUP(76, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) PINGROUP(77, WEST, ter_mi2s, phase_flag, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) PINGROUP(79, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) PINGROUP(80, WEST, sec_mi2s, _, qdss, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b, gcc_gp3_b, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) PINGROUP(89, EAST, tsif0, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PINGROUP(90, EAST, tsif0, mdp_vsync0, mdp_vsync1, mdp_vsync2, mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) PINGROUP(91, EAST, tsif0, sdc4_cmd, tgu_ch1, phase_flag, qdss_cti1_b, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) PINGROUP(92, EAST, tsif1, sdc43, vfr_1, phase_flag, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) PINGROUP(93, EAST, tsif1, sdc4_clk, _, qdss, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) PINGROUP(94, EAST, tsif1, sdc42, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) PINGROUP(95, EAST, tsif1, sdc41, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) PINGROUP(96, EAST, tsif1, sdc40, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) PINGROUP(97, WEST, _, mdp_vsync_b, ldo_en, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) PINGROUP(98, WEST, _, mdp_vsync_b, ldo_update, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) PINGROUP(99, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) PINGROUP(100, WEST, _, _, blsp_uart8, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PINGROUP(101, WEST, _, blsp_uart8, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) PINGROUP(102, WEST, _, blsp11_i2c, prng_rosc, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) PINGROUP(103, WEST, _, blsp11_i2c, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) PINGROUP(104, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PINGROUP(105, NORTH, uim2_data, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) PINGROUP(106, NORTH, uim2_clk, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PINGROUP(107, NORTH, uim2_reset, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) PINGROUP(108, NORTH, uim2_present, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) PINGROUP(109, NORTH, uim1_data, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) PINGROUP(110, NORTH, uim1_clk, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) PINGROUP(111, NORTH, uim1_reset, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) PINGROUP(112, NORTH, uim1_present, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) PINGROUP(113, NORTH, uim_batt, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) PINGROUP(114, WEST, _, _, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) PINGROUP(115, WEST, _, nav_dr, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) PINGROUP(116, WEST, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) PINGROUP(117, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) PINGROUP(118, EAST, adsp_ext, phase_flag, qdss, atest_char, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) PINGROUP(119, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) PINGROUP(120, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) PINGROUP(121, EAST, phase_flag, qdss, atest_char, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) PINGROUP(122, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) PINGROUP(123, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) PINGROUP(124, EAST, phase_flag, qdss, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) PINGROUP(125, EAST, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) PINGROUP(126, EAST, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) PINGROUP(127, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) PINGROUP(129, WEST, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) PINGROUP(130, NORTH, qlink_request, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) PINGROUP(131, NORTH, qlink_enable, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) PINGROUP(132, WEST, _, phase_flag, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) PINGROUP(133, WEST, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) PINGROUP(134, WEST, phase_flag, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) PINGROUP(135, WEST, _, pa_indicator, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) PINGROUP(136, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) PINGROUP(137, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) PINGROUP(138, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) PINGROUP(139, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) PINGROUP(140, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) PINGROUP(141, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) PINGROUP(142, WEST, _, ssbi1, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) PINGROUP(143, WEST, isense_dbg, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) PINGROUP(144, WEST, mss_lte, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) PINGROUP(145, WEST, mss_lte, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) PINGROUP(146, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) PINGROUP(147, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) PINGROUP(148, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) PINGROUP(149, WEST, _, _, _, _, _, _, _, _, _),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) UFS_RESET(ufs_reset, 0x19d000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static const struct msm_pinctrl_soc_data msm8998_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .pins = msm8998_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) .npins = ARRAY_SIZE(msm8998_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) .functions = msm8998_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) .nfunctions = ARRAY_SIZE(msm8998_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .groups = msm8998_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .ngroups = ARRAY_SIZE(msm8998_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .ngpios = 150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static int msm8998_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return msm_pinctrl_probe(pdev, &msm8998_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const struct of_device_id msm8998_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) { .compatible = "qcom,msm8998-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static struct platform_driver msm8998_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .name = "msm8998-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .of_match_table = msm8998_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .probe = msm8998_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static int __init msm8998_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) return platform_driver_register(&msm8998_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) arch_initcall(msm8998_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) static void __exit msm8998_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) platform_driver_unregister(&msm8998_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) module_exit(msm8998_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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