^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, Sony Mobile Communications AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __PINCTRL_MSM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __PINCTRL_MSM_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) struct pinctrl_pin_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * struct msm_function - a pinmux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * @name: Name of the pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * @groups: List of pingroups for this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * @ngroups: Number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct msm_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * struct msm_pingroup - Qualcomm pingroup definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @name: Name of the pingroup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * @pins: A list of pins assigned to this pingroup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @npins: Number of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @funcs: A list of pinmux functions that can be selected for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * this group. The index of the selected function is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * for programming the function selector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Entries should be indices into the groups list of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * struct msm_pinctrl_soc_data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @ctl_reg: Offset of the register holding control bits for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @io_reg: Offset of the register holding input/output bits for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @intr_status_reg: Offset of the register holding the status bits for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @intr_target_reg: Offset of the register specifying routing of the interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * from this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @pull_bit: Offset in @ctl_reg for the bias configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @od_bit: Offset in @ctl_reg for controlling open drain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @oe_bit: Offset in @ctl_reg for controlling output enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @in_bit: Offset in @io_reg for the input bit value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @out_bit: Offset in @io_reg for the output bit value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @intr_target_kpss_val: Value in @intr_target_bit for specifying that the interrupt from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * this gpio should get routed to the KPSS processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @intr_detection_width: Number of bits used for specifying interrupt type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * Should be 2 for SoCs that can detect both edges in hardware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * otherwise 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct msm_pingroup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) const unsigned *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) unsigned *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 ctl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 io_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 intr_cfg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 intr_status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 intr_target_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int tile:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned mux_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) unsigned pull_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned drv_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned od_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned oe_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) unsigned in_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned out_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned intr_enable_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned intr_status_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned intr_ack_high:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned intr_target_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned intr_target_kpss_val:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned intr_raw_status_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned intr_polarity_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned intr_detection_bit:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned intr_detection_width:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * struct msm_gpio_wakeirq_map - Map of GPIOs and their wakeup pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @gpio: The GPIOs that are wakeup capable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @wakeirq: The interrupt at the always-on interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct msm_gpio_wakeirq_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @pins: An array describing all pins the pin controller affects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @npins: The number of entries in @pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @functions: An array describing all mux functions the SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @nfunctions: The number of entries in @functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * @groups: An array describing all pin groups the pin SoC supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @ngroups: The numbmer of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @ngpio: The number of pingroups the driver should expose as GPIOs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @pull_no_keeper: The SoC does not support keeper bias.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @wakeirq_map: The map of wakeup capable GPIOs and the pin at PDC/MPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @nwakeirq_map: The number of entries in @wakeirq_map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @wakeirq_dual_edge_errata: If true then GPIOs using the wakeirq_map need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * to be aware that their parent can't handle dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * edge interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @gpio_func: Which function number is GPIO (usually 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct msm_pinctrl_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct msm_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const struct msm_pingroup *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool pull_no_keeper;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *const *tiles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int ntiles;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const int *reserved_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct msm_gpio_wakeirq_map *wakeirq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int nwakeirq_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool wakeirq_dual_edge_errata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int gpio_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern const struct dev_pm_ops msm_pinctrl_dev_pm_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int msm_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct msm_pinctrl_soc_data *soc_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int msm_pinctrl_remove(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags