^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013, Sony Mobile Communications AB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2013, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/qcom_scm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/soc/qcom/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "../pinconf.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MAX_NR_GPIO 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MAX_NR_TILES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PS_HOLD_OFFSET 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * struct msm_pinctrl - state for a pinctrl-msm device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @dev: device handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @pctrl: pinctrl handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @chip: gpiochip handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @desc: pin controller descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @restart_nb: restart notifier block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @irq_chip: irq chip information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @irq: parent irq for the TLMM irq_chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @intr_target_use_scm: route irq to application cpu using scm calls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @lock: Spinlock to protect register resources as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * as msm_pinctrl data structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @enabled_irqs: Bitmap of currently enabled irqs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @skip_wake_irqs: Skip IRQs that are handled by wakeup interrupt controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @disabled_for_mux: These IRQs were disabled because we muxed away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @soc: Reference to soc_data of platform specific data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @regs: Base addresses for the TLMM tiles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @phys_base: Physical base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct msm_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct pinctrl_dev *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct gpio_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct pinctrl_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct notifier_block restart_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct irq_chip irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) bool intr_target_use_scm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) raw_spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct msm_pinctrl_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void __iomem *regs[MAX_NR_TILES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 phys_base[MAX_NR_TILES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MSM_ACCESSOR(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) const struct msm_pingroup *g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return readl(pctrl->regs[g->tile] + g->name##_reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const struct msm_pingroup *g) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel(val, pctrl->regs[g->tile] + g->name##_reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MSM_ACCESSOR(ctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MSM_ACCESSOR(io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MSM_ACCESSOR(intr_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MSM_ACCESSOR(intr_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) MSM_ACCESSOR(intr_target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct msm_pingroup *g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) msm_writel_intr_status(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static int msm_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return pctrl->soc->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return pctrl->soc->groups[group].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int msm_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) *pins = pctrl->soc->groups[group].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) *num_pins = pctrl->soc->groups[group].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const struct pinctrl_ops msm_pinctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .get_groups_count = msm_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .get_group_name = msm_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .get_group_pins = msm_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct gpio_chip *chip = &pctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int msm_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return pctrl->soc->nfunctions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return pctrl->soc->functions[function].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static int msm_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) *groups = pctrl->soc->functions[function].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *num_groups = pctrl->soc->functions[function].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct gpio_chip *gc = &pctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int irq = irq_find_mapping(gc->irq.domain, group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct irq_data *d = irq_get_irq_data(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int gpio_func = pctrl->soc->gpio_func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) g = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) for (i = 0; i < g->nfuncs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (g->funcs[i] == function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (WARN_ON(i == g->nfuncs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * If an GPIO interrupt is setup on this pin then we need special
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * handling. Specifically interrupt detection logic will still see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * the pin twiddle even when we're muxed away.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * When we see a pin with an interrupt setup on it then we'll disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * (mask) interrupts on it when we mux away until we mux back. Note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * that disable_irq() refcounts and interrupts are disabled as long as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * at least one disable_irq() has been called.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (d && i != gpio_func &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) disable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) val |= i << g->mux_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) msm_writel_ctl(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (d && i == gpio_func &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Clear interrupts detected while not GPIO since we only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * masked things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) msm_ack_intr_status(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enable_irq(irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const struct msm_pingroup *g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* No funcs? Probably ACPI so can't do anything here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (!g->nfuncs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct pinmux_ops msm_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .request = msm_pinmux_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .get_functions_count = msm_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .get_function_name = msm_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .get_function_groups = msm_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .gpio_request_enable = msm_pinmux_request_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .set_mux = msm_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int msm_config_reg(struct msm_pinctrl *pctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct msm_pingroup *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned *bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) *bit = g->pull_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) *mask = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *bit = g->od_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) *bit = g->drv_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *mask = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) *bit = g->oe_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) *mask = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MSM_NO_PULL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MSM_PULL_DOWN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MSM_KEEPER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MSM_PULL_UP_NO_KEEPER 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MSM_PULL_UP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static unsigned msm_regval_to_drive(u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return (val + 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static int msm_config_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) unsigned int group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) g = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = msm_config_reg(pctrl, g, param, &mask, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) val = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) arg = (val >> bit) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Convert register value to pinconf value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (arg != MSM_NO_PULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (arg != MSM_PULL_DOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (pctrl->soc->pull_no_keeper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (arg != MSM_KEEPER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (pctrl->soc->pull_no_keeper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) arg = arg == MSM_PULL_UP_NO_KEEPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) arg = arg == MSM_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Pin is not open-drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) arg = msm_regval_to_drive(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Pin is not output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (!arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) val = msm_readl_io(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) arg = !!(val & BIT(g->in_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Pin is output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int msm_config_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) g = &pctrl->soc->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ret = msm_config_reg(pctrl, g, param, &mask, &bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* Convert pinconf values to register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) arg = MSM_NO_PULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case PIN_CONFIG_BIAS_PULL_DOWN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) arg = MSM_PULL_DOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case PIN_CONFIG_BIAS_BUS_HOLD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (pctrl->soc->pull_no_keeper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) arg = MSM_KEEPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (pctrl->soc->pull_no_keeper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) arg = MSM_PULL_UP_NO_KEEPER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) arg = MSM_PULL_UP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case PIN_CONFIG_DRIVE_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case PIN_CONFIG_DRIVE_STRENGTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Check for invalid values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (arg > 16 || arg < 2 || (arg % 2) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) arg = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) arg = (arg / 2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) case PIN_CONFIG_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* set output value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val = msm_readl_io(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val |= BIT(g->out_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val &= ~BIT(g->out_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msm_writel_io(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /* enable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case PIN_CONFIG_INPUT_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /* disable output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Range-check user-supplied value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (arg & ~mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) val = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val &= ~(mask << bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val |= arg << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) msm_writel_ctl(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static const struct pinconf_ops msm_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .pin_config_group_get = msm_config_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .pin_config_group_set = msm_config_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) val = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) val &= ~BIT(g->oe_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msm_writel_ctl(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val = msm_readl_io(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val |= BIT(g->out_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) val &= ~BIT(g->out_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) msm_writel_io(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) val = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val |= BIT(g->oe_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) msm_writel_ctl(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) GPIO_LINE_DIRECTION_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val = msm_readl_io(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return !!(val & BIT(g->in_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val = msm_readl_io(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) val |= BIT(g->out_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) val &= ~BIT(g->out_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) msm_writel_io(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static void msm_gpio_dbg_show_one(struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct gpio_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) int is_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) int drive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) int pull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u32 ctl_reg, io_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static const char * const pulls_keeper[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "no pull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "pull down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "keeper",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "pull up"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const char * const pulls_no_keeper[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "no pull",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "pull down",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "pull up",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!gpiochip_line_is_valid(chip, offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) g = &pctrl->soc->groups[offset];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ctl_reg = msm_readl_ctl(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) io_reg = msm_readl_io(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) is_out = !!(ctl_reg & BIT(g->oe_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) func = (ctl_reg >> g->mux_bit) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) drive = (ctl_reg >> g->drv_bit) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) pull = (ctl_reg >> g->pull_bit) & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (is_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) val = !!(io_reg & BIT(g->out_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) val = !!(io_reg & BIT(g->in_bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) seq_printf(s, " %dmA", msm_regval_to_drive(drive));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (pctrl->soc->pull_no_keeper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) seq_printf(s, " %s", pulls_no_keeper[pull]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) seq_printf(s, " %s", pulls_keeper[pull]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) seq_puts(s, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) unsigned gpio = chip->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) for (i = 0; i < chip->ngpio; i++, gpio++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define msm_gpio_dbg_show NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned long *valid_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned int ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) unsigned int len, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) const int *reserved = pctrl->soc->reserved_gpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u16 *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) /* Driver provided reserved list overrides DT and ACPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (reserved) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) bitmap_fill(valid_mask, ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) for (i = 0; reserved[i] >= 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (i >= ngpios || reserved[i] >= ngpios) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) clear_bit(reserved[i], valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* The number of GPIOs in the ACPI tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) len = ret = device_property_count_u16(pctrl->dev, "gpios");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret > ngpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(pctrl->dev, "could not read list of GPIOs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) bitmap_zero(valid_mask, ngpios);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) for (i = 0; i < len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) set_bit(tmp[i], valid_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) kfree(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const struct gpio_chip msm_gpio_template = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .direction_input = msm_gpio_direction_input,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .direction_output = msm_gpio_direction_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .get_direction = msm_gpio_get_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .get = msm_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .set = msm_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .dbg_show = msm_gpio_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) /* For dual-edge interrupts in software, since some hardware has no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * such support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) * At appropriate moments, this function may be called to flip the polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) * settings of both-edge irq lines to try and catch the next edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) * The attempt is considered successful if:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * - the status bit goes high, indicating that an edge was caught, or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * - the input value of the gpio doesn't change during the attempt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * If the value changes twice during the process, that would cause the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * test to fail but would force the second, as two opposite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * transitions would cause a detection no matter the polarity setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * The do-loop tries to sledge-hammer closed the timing hole between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * the initial value-read and the polarity-write - if the line value changes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * during that window, an interrupt is lost, the new polarity setting is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * incorrect, and the first success test will fail, causing a retry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * Algorithm comes from Google's msmgpio driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) const struct msm_pingroup *g,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int loop_limit = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) unsigned val, val2, intstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unsigned pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) pol = msm_readl_intr_cfg(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) pol ^= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) msm_writel_intr_cfg(pol, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) intstat = msm_readl_intr_status(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (intstat || (val == val2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) } while (loop_limit-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) val, val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static void msm_gpio_irq_mask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (d->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) irq_chip_mask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) g = &pctrl->soc->groups[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) val = msm_readl_intr_cfg(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * There are two bits that control interrupt forwarding to the CPU. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) * RAW_STATUS_EN bit causes the level or edge sensed on the line to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * latched into the interrupt status register when the hardware detects
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * an irq that it's configured for (either edge for edge type or level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * for level type irq). The 'non-raw' status enable bit causes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * hardware to assert the summary interrupt to the CPU if the latched
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * status bit is set. There's a bug though, the edge detection logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * seems to have a problem where toggling the RAW_STATUS_EN bit may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * cause the status bit to latch spuriously when there isn't any edge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * so we can't touch that bit for edge type irqs and we have to keep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) * the bit set anyway so that edges are latched while the line is masked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * To make matters more complicated, leaving the RAW_STATUS_EN bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * enabled all the time causes level interrupts to re-latch into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * status register because the level is still present on the line after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) * we ack it. We clear the raw status enable bit during mask here and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) * set the bit on unmask so the interrupt can't latch into the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) * while it's masked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) val &= ~BIT(g->intr_raw_status_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) val &= ~BIT(g->intr_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) msm_writel_intr_cfg(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) clear_bit(d->hwirq, pctrl->enabled_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static void msm_gpio_irq_unmask(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (d->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) irq_chip_unmask_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) g = &pctrl->soc->groups[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) val = msm_readl_intr_cfg(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) val |= BIT(g->intr_raw_status_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) val |= BIT(g->intr_enable_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) msm_writel_intr_cfg(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) set_bit(d->hwirq, pctrl->enabled_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static void msm_gpio_irq_enable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (d->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) irq_chip_enable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) msm_gpio_irq_unmask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void msm_gpio_irq_disable(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (d->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) irq_chip_disable_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) msm_gpio_irq_mask(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * msm_gpio_update_dual_edge_parent() - Prime next edge for IRQs handled by parent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * @d: The irq dta.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * This is much like msm_gpio_update_dual_edge_pos() but for IRQs that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * normally handled by the parent irqchip. The logic here is slightly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * different due to what's easy to do with our parent, but in principle it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int loop_limit = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /* Read the value and make a guess about what edge we need to catch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Set the parent to catch the next edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) irq_chip_set_type_parent(d, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) * Possibly the line changed between when we last read "val"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * (and decided what edge we needed) and when set the edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * If the value didn't change (or changed and then changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * back) then we're done.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (type == IRQ_TYPE_EDGE_RISING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) type = IRQ_TYPE_EDGE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) } else if (type == IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) } while (loop_limit-- > 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static void msm_gpio_irq_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) msm_gpio_update_dual_edge_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) g = &pctrl->soc->groups[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) msm_ack_intr_status(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) msm_gpio_update_dual_edge_pos(pctrl, g, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return type == IRQ_TYPE_EDGE_BOTH &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) test_bit(d->hwirq, pctrl->skip_wake_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) bool was_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) set_bit(d->hwirq, pctrl->dual_edge_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) irq_set_handler_locked(d, handle_fasteoi_ack_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) msm_gpio_update_dual_edge_parent(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (d->parent_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) irq_chip_set_type_parent(d, type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) clear_bit(d->hwirq, pctrl->dual_edge_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) irq_set_handler_locked(d, handle_fasteoi_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) g = &pctrl->soc->groups[d->hwirq];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) raw_spin_lock_irqsave(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * For hw without possibility of detecting both edges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) set_bit(d->hwirq, pctrl->dual_edge_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) clear_bit(d->hwirq, pctrl->dual_edge_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Route interrupts to application cpu.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * With intr_target_use_scm interrupts are routed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * application cpu using scm calls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (pctrl->intr_target_use_scm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) qcom_scm_io_readl(addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) val &= ~(7 << g->intr_target_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) val |= g->intr_target_kpss_val << g->intr_target_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ret = qcom_scm_io_writel(addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_err(pctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) "Failed routing %lu interrupt to Apps proc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) val = msm_readl_intr_target(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) val &= ~(7 << g->intr_target_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) val |= g->intr_target_kpss_val << g->intr_target_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) msm_writel_intr_target(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Update configuration for gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * RAW_STATUS_EN is left on for all gpio irqs. Due to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * internal circuitry of TLMM, toggling the RAW_STATUS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * could cause the INTR_STATUS to be set for EDGE interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) val = msm_readl_intr_cfg(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) was_enabled = val & BIT(g->intr_raw_status_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) val |= BIT(g->intr_raw_status_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (g->intr_detection_width == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) val &= ~(3 << g->intr_detection_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) val &= ~(1 << g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) val |= 1 << g->intr_detection_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) val |= 2 << g->intr_detection_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) val |= 3 << g->intr_detection_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else if (g->intr_detection_width == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) val &= ~(1 << g->intr_detection_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) val &= ~(1 << g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) case IRQ_TYPE_EDGE_RISING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) val |= BIT(g->intr_detection_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) case IRQ_TYPE_EDGE_FALLING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) val |= BIT(g->intr_detection_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) case IRQ_TYPE_EDGE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) val |= BIT(g->intr_detection_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) case IRQ_TYPE_LEVEL_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case IRQ_TYPE_LEVEL_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) val |= BIT(g->intr_polarity_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) msm_writel_intr_cfg(val, pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * The first time we set RAW_STATUS_EN it could trigger an interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * Clear the interrupt. This is safe because we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * IRQCHIP_SET_TYPE_MASKED.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (!was_enabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) msm_ack_intr_status(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) msm_gpio_update_dual_edge_pos(pctrl, g, d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) raw_spin_unlock_irqrestore(&pctrl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * While they may not wake up when the TLMM is powered off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) * some GPIOs would like to wakeup the system from suspend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * when TLMM is powered on. To allow that, enable the GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) * summary line to be wakeup capable at GIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return irq_chip_set_wake_parent(d, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return irq_set_irq_wake(pctrl->irq, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int msm_gpio_irq_reqres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!try_module_get(gc->owner))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) msm_gpio_direction_input(gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (gpiochip_lock_as_irq(gc, d->hwirq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) dev_err(gc->parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "unable to lock HW IRQ %lu for IRQ\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * The disable / clear-enable workaround we do in msm_pinmux_set_mux()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * only works if disable is not lazy since we only clear any bogus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * interrupt in hardware. Explicitly mark the interrupt as UNLAZY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) module_put(gc->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static void msm_gpio_irq_relres(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) gpiochip_unlock_as_irq(gc, d->hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) module_put(gc->owner);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static int msm_gpio_irq_set_affinity(struct irq_data *d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) const struct cpumask *dest, bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return irq_chip_set_affinity_parent(d, dest, force);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static void msm_gpio_irq_handler(struct irq_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct gpio_chip *gc = irq_desc_get_handler_data(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) const struct msm_pingroup *g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct irq_chip *chip = irq_desc_get_chip(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) int irq_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) chained_irq_enter(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) * Each pin has it's own IRQ status register, so use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) * enabled_irq bitmap to limit the number of reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) g = &pctrl->soc->groups[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) val = msm_readl_intr_status(pctrl, g);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (val & BIT(g->intr_status_bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) irq_pin = irq_find_mapping(gc->irq.domain, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) generic_handle_irq(irq_pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* No interrupts were flagged */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (handled == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) handle_bad_irq(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) chained_irq_exit(chip, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static int msm_gpio_wakeirq(struct gpio_chip *gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) unsigned int child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) unsigned int child_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) unsigned int *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) unsigned int *parent_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) const struct msm_gpio_wakeirq_map *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) *parent = GPIO_NO_WAKE_IRQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) *parent_type = IRQ_TYPE_EDGE_RISING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) map = &pctrl->soc->wakeirq_map[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (map->gpio == child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) *parent = map->wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (pctrl->soc->reserved_gpios)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return device_property_count_u16(pctrl->dev, "gpios") > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static int msm_gpio_init(struct msm_pinctrl *pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct gpio_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct gpio_irq_chip *girq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) unsigned gpio, ngpio = pctrl->soc->ngpios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) bool skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (WARN_ON(ngpio > MAX_NR_GPIO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) chip = &pctrl->chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) chip->base = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) chip->ngpio = ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) chip->label = dev_name(pctrl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) chip->parent = pctrl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) chip->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) chip->of_node = pctrl->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (msm_gpio_needs_valid_mask(pctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) chip->init_valid_mask = msm_gpio_init_valid_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) pctrl->irq_chip.name = "msmgpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) IRQCHIP_SET_TYPE_MASKED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) chip->irq.parent_domain = irq_find_matching_host(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) DOMAIN_BUS_WAKEUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (!chip->irq.parent_domain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * Let's skip handling the GPIOs, if the parent irqchip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) * is handling the direct connect IRQ of the GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) gpio = pctrl->soc->wakeirq_map[i].gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) set_bit(gpio, pctrl->skip_wake_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) girq = &chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) girq->chip = &pctrl->irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) girq->parent_handler = msm_gpio_irq_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) girq->fwnode = pctrl->dev->fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) girq->num_parents = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (!girq->parents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) girq->default_type = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) girq->handler = handle_bad_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) girq->parents[0] = pctrl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = gpiochip_add_data(&pctrl->chip, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) dev_err(pctrl->dev, "Failed register gpiochip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * For DeviceTree-supported systems, the gpio core checks the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * pinctrl's device node for the "gpio-ranges" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * If it is present, it takes care of adding the pin ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * for the driver. In this case the driver can skip ahead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * In order to remain compatible with older, existing DeviceTree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * files which don't set the "gpio-ranges" property or systems that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * utilize ACPI the driver has to call gpiochip_add_pin_range().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = gpiochip_add_pin_range(&pctrl->chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) dev_name(pctrl->dev), 0, 0, chip->ngpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) dev_err(pctrl->dev, "Failed to add pin range\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) gpiochip_remove(&pctrl->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) mdelay(1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static struct msm_pinctrl *poweroff_pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static void msm_ps_hold_poweroff(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) const struct msm_function *func = pctrl->soc->functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) for (i = 0; i < pctrl->soc->nfunctions; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (!strcmp(func[i].name, "ps_hold")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) pctrl->restart_nb.priority = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (register_restart_handler(&pctrl->restart_nb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dev_err(pctrl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) "failed to setup restart handler.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) poweroff_pctrl = pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) pm_power_off = msm_ps_hold_poweroff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return pinctrl_force_sleep(pctrl->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static __maybe_unused int msm_pinctrl_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return pinctrl_force_default(pctrl->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) msm_pinctrl_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int msm_pinctrl_probe(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) const struct msm_pinctrl_soc_data *soc_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) struct msm_pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (!pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) pctrl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) pctrl->soc = soc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pctrl->chip = msm_gpio_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pctrl->intr_target_use_scm = of_device_is_compatible(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pctrl->dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) "qcom,ipq8064-pinctrl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) raw_spin_lock_init(&pctrl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (soc_data->tiles) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) for (i = 0; i < soc_data->ntiles; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) soc_data->tiles[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (IS_ERR(pctrl->regs[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) return PTR_ERR(pctrl->regs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (IS_ERR(pctrl->regs[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return PTR_ERR(pctrl->regs[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) pctrl->phys_base[0] = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) msm_pinctrl_setup_pm_reset(pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pctrl->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (pctrl->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return pctrl->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) pctrl->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) pctrl->desc.pctlops = &msm_pinctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) pctrl->desc.pmxops = &msm_pinmux_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) pctrl->desc.confops = &msm_pinconf_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) pctrl->desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) pctrl->desc.pins = pctrl->soc->pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) pctrl->desc.npins = pctrl->soc->npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (IS_ERR(pctrl->pctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) return PTR_ERR(pctrl->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = msm_gpio_init(pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) platform_set_drvdata(pdev, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) EXPORT_SYMBOL(msm_pinctrl_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) int msm_pinctrl_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) gpiochip_remove(&pctrl->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unregister_restart_handler(&pctrl->restart_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) EXPORT_SYMBOL(msm_pinctrl_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) MODULE_DESCRIPTION("Qualcomm Technologies, Inc. pinctrl-msm driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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