^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "pinctrl-msm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) static const struct pinctrl_pin_desc ipq8064_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PINCTRL_PIN(0, "GPIO_0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) PINCTRL_PIN(1, "GPIO_1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PINCTRL_PIN(2, "GPIO_2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PINCTRL_PIN(3, "GPIO_3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PINCTRL_PIN(4, "GPIO_4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PINCTRL_PIN(5, "GPIO_5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PINCTRL_PIN(6, "GPIO_6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PINCTRL_PIN(7, "GPIO_7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PINCTRL_PIN(8, "GPIO_8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PINCTRL_PIN(9, "GPIO_9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PINCTRL_PIN(10, "GPIO_10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PINCTRL_PIN(11, "GPIO_11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PINCTRL_PIN(12, "GPIO_12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PINCTRL_PIN(13, "GPIO_13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PINCTRL_PIN(14, "GPIO_14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PINCTRL_PIN(15, "GPIO_15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PINCTRL_PIN(16, "GPIO_16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PINCTRL_PIN(17, "GPIO_17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PINCTRL_PIN(18, "GPIO_18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PINCTRL_PIN(19, "GPIO_19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PINCTRL_PIN(20, "GPIO_20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PINCTRL_PIN(21, "GPIO_21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PINCTRL_PIN(22, "GPIO_22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PINCTRL_PIN(23, "GPIO_23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PINCTRL_PIN(24, "GPIO_24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PINCTRL_PIN(25, "GPIO_25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PINCTRL_PIN(26, "GPIO_26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PINCTRL_PIN(27, "GPIO_27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PINCTRL_PIN(28, "GPIO_28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PINCTRL_PIN(29, "GPIO_29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PINCTRL_PIN(30, "GPIO_30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PINCTRL_PIN(31, "GPIO_31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PINCTRL_PIN(32, "GPIO_32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PINCTRL_PIN(33, "GPIO_33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PINCTRL_PIN(34, "GPIO_34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PINCTRL_PIN(35, "GPIO_35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PINCTRL_PIN(36, "GPIO_36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PINCTRL_PIN(37, "GPIO_37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PINCTRL_PIN(38, "GPIO_38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PINCTRL_PIN(39, "GPIO_39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PINCTRL_PIN(40, "GPIO_40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PINCTRL_PIN(41, "GPIO_41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PINCTRL_PIN(42, "GPIO_42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PINCTRL_PIN(43, "GPIO_43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PINCTRL_PIN(44, "GPIO_44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PINCTRL_PIN(45, "GPIO_45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PINCTRL_PIN(46, "GPIO_46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PINCTRL_PIN(47, "GPIO_47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PINCTRL_PIN(48, "GPIO_48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PINCTRL_PIN(49, "GPIO_49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PINCTRL_PIN(50, "GPIO_50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PINCTRL_PIN(51, "GPIO_51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PINCTRL_PIN(52, "GPIO_52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PINCTRL_PIN(53, "GPIO_53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PINCTRL_PIN(54, "GPIO_54"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PINCTRL_PIN(55, "GPIO_55"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PINCTRL_PIN(56, "GPIO_56"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PINCTRL_PIN(57, "GPIO_57"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PINCTRL_PIN(58, "GPIO_58"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PINCTRL_PIN(59, "GPIO_59"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PINCTRL_PIN(60, "GPIO_60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PINCTRL_PIN(61, "GPIO_61"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PINCTRL_PIN(62, "GPIO_62"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PINCTRL_PIN(63, "GPIO_63"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PINCTRL_PIN(64, "GPIO_64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PINCTRL_PIN(65, "GPIO_65"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PINCTRL_PIN(66, "GPIO_66"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PINCTRL_PIN(67, "GPIO_67"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PINCTRL_PIN(68, "GPIO_68"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PINCTRL_PIN(69, "SDC3_CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PINCTRL_PIN(70, "SDC3_CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PINCTRL_PIN(71, "SDC3_DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DECLARE_IPQ_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DECLARE_IPQ_GPIO_PINS(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DECLARE_IPQ_GPIO_PINS(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DECLARE_IPQ_GPIO_PINS(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DECLARE_IPQ_GPIO_PINS(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DECLARE_IPQ_GPIO_PINS(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DECLARE_IPQ_GPIO_PINS(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DECLARE_IPQ_GPIO_PINS(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DECLARE_IPQ_GPIO_PINS(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) DECLARE_IPQ_GPIO_PINS(8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) DECLARE_IPQ_GPIO_PINS(9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) DECLARE_IPQ_GPIO_PINS(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) DECLARE_IPQ_GPIO_PINS(11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DECLARE_IPQ_GPIO_PINS(12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DECLARE_IPQ_GPIO_PINS(13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) DECLARE_IPQ_GPIO_PINS(14);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) DECLARE_IPQ_GPIO_PINS(15);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DECLARE_IPQ_GPIO_PINS(16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) DECLARE_IPQ_GPIO_PINS(17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) DECLARE_IPQ_GPIO_PINS(18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) DECLARE_IPQ_GPIO_PINS(19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) DECLARE_IPQ_GPIO_PINS(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) DECLARE_IPQ_GPIO_PINS(21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) DECLARE_IPQ_GPIO_PINS(22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) DECLARE_IPQ_GPIO_PINS(23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) DECLARE_IPQ_GPIO_PINS(24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) DECLARE_IPQ_GPIO_PINS(25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) DECLARE_IPQ_GPIO_PINS(26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) DECLARE_IPQ_GPIO_PINS(27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) DECLARE_IPQ_GPIO_PINS(28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) DECLARE_IPQ_GPIO_PINS(29);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) DECLARE_IPQ_GPIO_PINS(30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DECLARE_IPQ_GPIO_PINS(31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) DECLARE_IPQ_GPIO_PINS(32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DECLARE_IPQ_GPIO_PINS(33);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) DECLARE_IPQ_GPIO_PINS(34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) DECLARE_IPQ_GPIO_PINS(35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) DECLARE_IPQ_GPIO_PINS(36);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) DECLARE_IPQ_GPIO_PINS(37);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) DECLARE_IPQ_GPIO_PINS(38);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) DECLARE_IPQ_GPIO_PINS(39);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) DECLARE_IPQ_GPIO_PINS(40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DECLARE_IPQ_GPIO_PINS(41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DECLARE_IPQ_GPIO_PINS(42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) DECLARE_IPQ_GPIO_PINS(43);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) DECLARE_IPQ_GPIO_PINS(44);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DECLARE_IPQ_GPIO_PINS(45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) DECLARE_IPQ_GPIO_PINS(46);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) DECLARE_IPQ_GPIO_PINS(47);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) DECLARE_IPQ_GPIO_PINS(48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) DECLARE_IPQ_GPIO_PINS(49);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) DECLARE_IPQ_GPIO_PINS(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) DECLARE_IPQ_GPIO_PINS(51);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) DECLARE_IPQ_GPIO_PINS(52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) DECLARE_IPQ_GPIO_PINS(53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) DECLARE_IPQ_GPIO_PINS(54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) DECLARE_IPQ_GPIO_PINS(55);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) DECLARE_IPQ_GPIO_PINS(56);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) DECLARE_IPQ_GPIO_PINS(57);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) DECLARE_IPQ_GPIO_PINS(58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) DECLARE_IPQ_GPIO_PINS(59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) DECLARE_IPQ_GPIO_PINS(60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) DECLARE_IPQ_GPIO_PINS(61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) DECLARE_IPQ_GPIO_PINS(62);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) DECLARE_IPQ_GPIO_PINS(63);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) DECLARE_IPQ_GPIO_PINS(64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) DECLARE_IPQ_GPIO_PINS(65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DECLARE_IPQ_GPIO_PINS(66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) DECLARE_IPQ_GPIO_PINS(67);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) DECLARE_IPQ_GPIO_PINS(68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const unsigned int sdc3_clk_pins[] = { 69 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const unsigned int sdc3_cmd_pins[] = { 70 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned int sdc3_data_pins[] = { 71 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FUNCTION(fname) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) [IPQ_MUX_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9, f10) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "gpio" #id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .pins = gpio##id##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .npins = ARRAY_SIZE(gpio##id##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .funcs = (int[]){ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IPQ_MUX_gpio, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IPQ_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IPQ_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) IPQ_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) IPQ_MUX_##f4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) IPQ_MUX_##f5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) IPQ_MUX_##f6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) IPQ_MUX_##f7, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) IPQ_MUX_##f8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) IPQ_MUX_##f9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) IPQ_MUX_##f10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .nfuncs = 11, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .ctl_reg = 0x1000 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .io_reg = 0x1004 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .intr_cfg_reg = 0x1008 + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .intr_status_reg = 0x100c + 0x10 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .intr_target_reg = 0x400 + 0x4 * id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .mux_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .pull_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .drv_bit = 6, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .oe_bit = 9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .in_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .out_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .intr_enable_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .intr_status_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .intr_ack_high = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .intr_target_bit = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .intr_target_kpss_val = 4, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .intr_raw_status_bit = 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .intr_polarity_bit = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .intr_detection_bit = 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .intr_detection_width = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SDC_PINGROUP(pg_name, ctl, pull, drv) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = #pg_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .pins = pg_name##_pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .npins = ARRAY_SIZE(pg_name##_pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .ctl_reg = ctl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .io_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .intr_cfg_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .intr_status_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .intr_target_reg = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .mux_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .pull_bit = pull, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .drv_bit = drv, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .oe_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .in_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .out_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .intr_enable_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .intr_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .intr_target_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .intr_target_kpss_val = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .intr_raw_status_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .intr_polarity_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .intr_detection_bit = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .intr_detection_width = -1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) enum ipq8064_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) IPQ_MUX_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) IPQ_MUX_mdio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) IPQ_MUX_mi2s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) IPQ_MUX_pdm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IPQ_MUX_ssbi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) IPQ_MUX_spmi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) IPQ_MUX_audio_pcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) IPQ_MUX_gsbi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) IPQ_MUX_gsbi2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) IPQ_MUX_gsbi4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) IPQ_MUX_gsbi5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IPQ_MUX_gsbi5_spi_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) IPQ_MUX_gsbi5_spi_cs2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) IPQ_MUX_gsbi5_spi_cs3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) IPQ_MUX_gsbi6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) IPQ_MUX_gsbi7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) IPQ_MUX_nss_spi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) IPQ_MUX_sdc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) IPQ_MUX_spdif,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) IPQ_MUX_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) IPQ_MUX_tsif1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IPQ_MUX_tsif2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IPQ_MUX_usb_fs_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IPQ_MUX_usb_fs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IPQ_MUX_usb2_hsic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) IPQ_MUX_rgmii2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) IPQ_MUX_sata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) IPQ_MUX_pcie1_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) IPQ_MUX_pcie1_prsnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) IPQ_MUX_pcie1_pwrflt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) IPQ_MUX_pcie1_pwren_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) IPQ_MUX_pcie1_pwren,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) IPQ_MUX_pcie1_clk_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) IPQ_MUX_pcie2_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) IPQ_MUX_pcie2_prsnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) IPQ_MUX_pcie2_pwrflt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) IPQ_MUX_pcie2_pwren_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) IPQ_MUX_pcie2_pwren,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) IPQ_MUX_pcie2_clk_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) IPQ_MUX_pcie3_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) IPQ_MUX_pcie3_prsnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) IPQ_MUX_pcie3_pwrflt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) IPQ_MUX_pcie3_pwren_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) IPQ_MUX_pcie3_pwren,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) IPQ_MUX_pcie3_clk_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) IPQ_MUX_ps_hold,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) IPQ_MUX_NA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const char * const gpio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const char * const mdio_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "gpio0", "gpio1", "gpio2", "gpio10", "gpio11", "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const char * const mi2s_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "gpio33", "gpio55", "gpio56", "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const char * const pdm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "gpio3", "gpio16", "gpio17", "gpio22", "gpio30", "gpio31",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "gpio34", "gpio35", "gpio52", "gpio55", "gpio56", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "gpio59",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const char * const ssbi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const char * const spmi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "gpio10", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const char * const audio_pcm_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "gpio14", "gpio15", "gpio16", "gpio17",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const char * const gsbi1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "gpio51", "gpio52", "gpio53", "gpio54",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const gsbi2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "gpio22", "gpio23", "gpio24", "gpio25",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const char * const gsbi4_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "gpio10", "gpio11", "gpio12", "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const char * const gsbi5_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "gpio18", "gpio19", "gpio20", "gpio21",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const char * const gsbi5_spi_cs1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "gpio6", "gpio61",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const char * const gsbi5_spi_cs2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "gpio7", "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const char * const gsbi5_spi_cs3_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const char * const gsbi6_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "gpio27", "gpio28", "gpio29", "gpio30", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const char * const gsbi7_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "gpio6", "gpio7", "gpio8", "gpio9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const char * const nss_spi_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "gpio14", "gpio15", "gpio16", "gpio17", "gpio55", "gpio56",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const char * const sdc1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "gpio44", "gpio45", "gpio46", "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const char * const spdif_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "gpio10", "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) static const char * const nand_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "gpio34", "gpio35", "gpio36", "gpio37", "gpio38", "gpio39",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "gpio40", "gpio41", "gpio42", "gpio43", "gpio44", "gpio45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) "gpio46", "gpio47",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const char * const tsif1_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "gpio55", "gpio56", "gpio57", "gpio58",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const char * const tsif2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "gpio59", "gpio60", "gpio61", "gpio62",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const char * const usb_fs_n_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "gpio6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const char * const usb_fs_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "gpio6", "gpio7", "gpio8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const char * const usb2_hsic_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "gpio67", "gpio68",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const char * const rgmii2_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "gpio2", "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62", "gpio66",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const char * const sata_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) "gpio10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const char * const pcie1_rst_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "gpio3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const char * const pcie1_prsnt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "gpio3", "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static const char * const pcie1_pwren_n_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "gpio4", "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const char * const pcie1_pwren_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "gpio4", "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const char * const pcie1_pwrflt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "gpio5", "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const char * const pcie1_clk_req_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) "gpio5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const char * const pcie2_rst_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const char * const pcie2_prsnt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "gpio11", "gpio48",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const char * const pcie2_pwren_n_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "gpio12", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const char * const pcie2_pwren_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "gpio12", "gpio49",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const char * const pcie2_pwrflt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "gpio13", "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const char * const pcie2_clk_req_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "gpio50",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const char * const pcie3_rst_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "gpio63",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static const char * const pcie3_prsnt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "gpio11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static const char * const pcie3_pwren_n_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static const char * const pcie3_pwren_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "gpio12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const char * const pcie3_pwrflt_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "gpio13",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const char * const pcie3_clk_req_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "gpio65",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static const char * const ps_hold_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "gpio26",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static const struct msm_function ipq8064_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FUNCTION(gpio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) FUNCTION(mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) FUNCTION(ssbi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) FUNCTION(spmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) FUNCTION(mi2s),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) FUNCTION(pdm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) FUNCTION(audio_pcm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) FUNCTION(gsbi1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) FUNCTION(gsbi2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) FUNCTION(gsbi4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) FUNCTION(gsbi5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) FUNCTION(gsbi5_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) FUNCTION(gsbi5_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) FUNCTION(gsbi5_spi_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) FUNCTION(gsbi6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) FUNCTION(gsbi7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) FUNCTION(nss_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) FUNCTION(sdc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) FUNCTION(spdif),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) FUNCTION(nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) FUNCTION(tsif1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) FUNCTION(tsif2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) FUNCTION(usb_fs_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) FUNCTION(usb_fs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) FUNCTION(usb2_hsic),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) FUNCTION(rgmii2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) FUNCTION(sata),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) FUNCTION(pcie1_rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) FUNCTION(pcie1_prsnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) FUNCTION(pcie1_pwren_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) FUNCTION(pcie1_pwren),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) FUNCTION(pcie1_pwrflt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) FUNCTION(pcie1_clk_req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) FUNCTION(pcie2_rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) FUNCTION(pcie2_prsnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) FUNCTION(pcie2_pwren_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) FUNCTION(pcie2_pwren),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) FUNCTION(pcie2_pwrflt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) FUNCTION(pcie2_clk_req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) FUNCTION(pcie3_rst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) FUNCTION(pcie3_prsnt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) FUNCTION(pcie3_pwren_n),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) FUNCTION(pcie3_pwren),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) FUNCTION(pcie3_pwrflt),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) FUNCTION(pcie3_clk_req),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) FUNCTION(ps_hold),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static const struct msm_pingroup ipq8064_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINGROUP(0, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINGROUP(1, mdio, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINGROUP(2, gsbi5_spi_cs3, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) PINGROUP(3, pcie1_rst, pcie1_prsnt, pdm, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINGROUP(4, pcie1_pwren_n, pcie1_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINGROUP(5, pcie1_clk_req, pcie1_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINGROUP(6, gsbi7, usb_fs, gsbi5_spi_cs1, usb_fs_n, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINGROUP(7, gsbi7, usb_fs, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINGROUP(8, gsbi7, usb_fs, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINGROUP(9, gsbi7, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINGROUP(10, gsbi4, spdif, sata, ssbi, mdio, spmi, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINGROUP(11, gsbi4, pcie2_prsnt, pcie1_prsnt, pcie3_prsnt, ssbi, mdio, spmi, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINGROUP(12, gsbi4, pcie2_pwren_n, pcie1_pwren_n, pcie3_pwren_n, pcie2_pwren, pcie1_pwren, pcie3_pwren, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINGROUP(13, gsbi4, pcie2_pwrflt, pcie1_pwrflt, pcie3_pwrflt, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINGROUP(14, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINGROUP(15, audio_pcm, nss_spi, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINGROUP(16, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINGROUP(17, audio_pcm, nss_spi, pdm, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINGROUP(18, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINGROUP(19, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINGROUP(20, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINGROUP(21, gsbi5, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINGROUP(22, gsbi2, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINGROUP(23, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINGROUP(24, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINGROUP(25, gsbi2, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINGROUP(26, ps_hold, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINGROUP(27, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINGROUP(28, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINGROUP(29, mi2s, rgmii2, gsbi6, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINGROUP(30, mi2s, rgmii2, gsbi6, pdm, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINGROUP(31, mi2s, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINGROUP(32, mi2s, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINGROUP(33, mi2s, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINGROUP(34, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINGROUP(35, nand, pdm, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINGROUP(36, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINGROUP(37, nand, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINGROUP(38, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINGROUP(39, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINGROUP(40, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINGROUP(41, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINGROUP(42, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINGROUP(43, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINGROUP(44, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINGROUP(45, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINGROUP(46, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINGROUP(47, nand, sdc1, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINGROUP(48, pcie2_rst, spdif, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINGROUP(49, pcie2_pwren_n, pcie2_pwren, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINGROUP(50, pcie2_clk_req, pcie2_pwrflt, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINGROUP(51, gsbi1, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINGROUP(52, gsbi1, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINGROUP(53, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINGROUP(54, gsbi1, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINGROUP(55, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINGROUP(56, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINGROUP(57, tsif1, mi2s, gsbi6, nss_spi, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINGROUP(58, tsif1, mi2s, gsbi6, pdm, nss_spi, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINGROUP(59, tsif2, rgmii2, pdm, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINGROUP(60, tsif2, rgmii2, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINGROUP(61, tsif2, rgmii2, gsbi5_spi_cs1, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINGROUP(62, tsif2, rgmii2, gsbi5_spi_cs2, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINGROUP(63, pcie3_rst, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINGROUP(64, NA, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINGROUP(65, pcie3_clk_req, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINGROUP(66, rgmii2, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINGROUP(67, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINGROUP(68, usb2_hsic, NA, NA, NA, NA, NA, NA, NA, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) SDC_PINGROUP(sdc3_clk, 0x204a, 14, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) SDC_PINGROUP(sdc3_cmd, 0x204a, 11, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) SDC_PINGROUP(sdc3_data, 0x204a, 9, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define NUM_GPIO_PINGROUPS 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const struct msm_pinctrl_soc_data ipq8064_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .pins = ipq8064_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .npins = ARRAY_SIZE(ipq8064_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .functions = ipq8064_functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .nfunctions = ARRAY_SIZE(ipq8064_functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .groups = ipq8064_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .ngroups = ARRAY_SIZE(ipq8064_groups),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .ngpios = NUM_GPIO_PINGROUPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static int ipq8064_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return msm_pinctrl_probe(pdev, &ipq8064_pinctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const struct of_device_id ipq8064_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { .compatible = "qcom,ipq8064-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static struct platform_driver ipq8064_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .name = "ipq8064-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .of_match_table = ipq8064_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .probe = ipq8064_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .remove = msm_pinctrl_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int __init ipq8064_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return platform_driver_register(&ipq8064_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) arch_initcall(ipq8064_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static void __exit ipq8064_pinctrl_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) platform_driver_unregister(&ipq8064_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) module_exit(ipq8064_pinctrl_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MODULE_DESCRIPTION("Qualcomm IPQ8064 pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MODULE_DEVICE_TABLE(of, ipq8064_pinctrl_of_match);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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