Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Marvell PXA2xx family pin control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2015 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __PINCTRL_PXA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __PINCTRL_PXA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define PXA_FUNCTION(_dir, _af, _name)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		.name = _name,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 		.muxval = (_dir | (_af << 1)),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PXA_PIN(_pin, funcs...)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		.pin = _pin,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		.functions = (struct pxa_desc_function[]){	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 			funcs, { } },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PXA_GPIO_PIN(_pin, funcs...)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		.pin = _pin,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		.functions = (struct pxa_desc_function[]){	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			PXA_FUNCTION(0, 0, "gpio_in"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 			PXA_FUNCTION(1, 0, "gpio_out"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			funcs, { } },				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PXA_GPIO_ONLY_PIN(_pin)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	{							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		.pin = _pin,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		.functions = (struct pxa_desc_function[]){	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			PXA_FUNCTION(0, 0, "gpio_in"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 			PXA_FUNCTION(1, 0, "gpio_out"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 			{ } },					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PXA_PINCTRL_PIN(pin)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	PINCTRL_PIN(pin, "P" #pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct pxa_desc_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	u8		muxval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct pxa_desc_pin {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	struct pinctrl_pin_desc		pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	struct pxa_desc_function	*functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct pxa_pinctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	unsigned	pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct pxa_pinctrl_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 	const char	*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	const char	**groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	unsigned	ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct pxa_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	spinlock_t			lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	void __iomem			**base_gafr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	void __iomem			**base_gpdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 	void __iomem			**base_pgsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 	struct device			*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	struct pinctrl_desc		desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	struct pinctrl_dev		*pctl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	unsigned			npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	const struct pxa_desc_pin	*ppins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	unsigned			ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	struct pxa_pinctrl_group	*groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	unsigned			nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	struct pxa_pinctrl_function	*functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	char				*name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int pxa2xx_pinctrl_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 			const struct pxa_desc_pin *ppins, int npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 			void __iomem *base_gafr[], void __iomem *base_gpdr[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 			void __iomem *base_gpsr[]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif /* __PINCTRL_PXA_H */