Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell PXA2xx family pin control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pinctrl/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include "../pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include "pinctrl-pxa2xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) static int pxa2xx_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	return pctl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static const char *pxa2xx_pctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 					       unsigned tgroup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	struct pxa_pinctrl_group *group = pctl->groups + tgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return group->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static int pxa2xx_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 				       unsigned tgroup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 				       const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 				       unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct pxa_pinctrl_group *group = pctl->groups + tgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	*pins = (unsigned *)&group->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	*num_pins = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) static const struct pinctrl_ops pxa2xx_pctl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.dt_free_map		= pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.get_groups_count	= pxa2xx_pctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.get_group_name		= pxa2xx_pctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.get_group_pins		= pxa2xx_pctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) static struct pxa_desc_function *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) pxa_desc_by_func_group(struct pxa_pinctrl *pctl, const char *pin_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		       const char *func_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct pxa_desc_function *df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	for (i = 0; i < pctl->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		const struct pxa_desc_pin *pin = pctl->ppins + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		if (!strcmp(pin->pin.name, pin_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			for (df = pin->functions; df->name; df++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 				if (!strcmp(df->name, func_name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 					return df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int pxa2xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 					 struct pinctrl_gpio_range *range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 					 unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 					 bool input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	uint32_t val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	void __iomem *gpdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	gpdr = pctl->base_gpdr[pin / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dev_dbg(pctl->dev, "set_direction(pin=%d): dir=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		pin, !input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	val = readl_relaxed(gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	val = (val & ~BIT(pin % 32)) | (input ? 0 : BIT(pin % 32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	writel_relaxed(val, gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char *pxa2xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 					    unsigned function)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct pxa_pinctrl_function *pf = pctl->functions + function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return pf->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int pxa2xx_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	return pctl->nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static int pxa2xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 				      unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				      const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				      unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct pxa_pinctrl_function *pf = pctl->functions + function;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	*groups = pf->groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	*num_groups = pf->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int pxa2xx_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			      unsigned tgroup)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	struct pxa_pinctrl_group *group = pctl->groups + tgroup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	struct pxa_desc_function *df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	int pin, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	void __iomem *gafr, *gpdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	df = pxa_desc_by_func_group(pctl, group->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				    (pctl->functions + function)->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!df)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	pin = group->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	gafr = pctl->base_gafr[pin / 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	gpdr = pctl->base_gpdr[pin / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	shift = (pin % 16) << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	dev_dbg(pctl->dev, "set_mux(pin=%d): af=%d dir=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		pin, df->muxval >> 1, df->muxval & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	val = readl_relaxed(gafr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	val = (val & ~(0x3 << shift)) | ((df->muxval >> 1) << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	writel_relaxed(val, gafr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	val = readl_relaxed(gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	val = (val & ~BIT(pin % 32)) | ((df->muxval & 1) ? BIT(pin % 32) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	writel_relaxed(val, gpdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct pinmux_ops pxa2xx_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.get_functions_count = pxa2xx_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.get_function_name = pxa2xx_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.get_function_groups = pxa2xx_pmx_get_func_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.set_mux = pxa2xx_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.gpio_set_direction = pxa2xx_pmx_gpio_set_direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int pxa2xx_pconf_group_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				  unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				  unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct pxa_pinctrl_group *g = pctl->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	unsigned pin = g->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	void __iomem *pgsr = pctl->base_pgsr[pin / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	val = readl_relaxed(pgsr) & BIT(pin % 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	*config = val ? PIN_CONFIG_LOW_POWER_MODE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	dev_dbg(pctl->dev, "get sleep gpio state(pin=%d) %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		pin, !!val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int pxa2xx_pconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 				  unsigned group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 				  unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 				  unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct pxa_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct pxa_pinctrl_group *g = pctl->groups + group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	unsigned pin = g->pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	void __iomem *pgsr = pctl->base_pgsr[pin / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int i, is_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		switch (pinconf_to_config_param(configs[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 			is_set = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	dev_dbg(pctl->dev, "set sleep gpio state(pin=%d) %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		pin, is_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	spin_lock_irqsave(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	val = readl_relaxed(pgsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	val = (val & ~BIT(pin % 32)) | (is_set ? BIT(pin % 32) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	writel_relaxed(val, pgsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	spin_unlock_irqrestore(&pctl->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static const struct pinconf_ops pxa2xx_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.pin_config_group_get	= pxa2xx_pconf_group_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.pin_config_group_set	= pxa2xx_pconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.is_generic		= true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static struct pinctrl_desc pxa2xx_pinctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.confops	= &pxa2xx_pconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.pctlops	= &pxa2xx_pctl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.pmxops		= &pxa2xx_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct pxa_pinctrl_function *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) pxa2xx_find_function(struct pxa_pinctrl *pctl, const char *fname,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		     const struct pxa_pinctrl_function *functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	const struct pxa_pinctrl_function *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	for (func = functions; func->name; func++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		if (!strcmp(fname, func->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			return func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int pxa2xx_build_functions(struct pxa_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct pxa_pinctrl_function *functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct pxa_desc_function *df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	 * Each pin can have at most 6 alternate functions, and 2 gpio functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	 * which are common to each pin. As there are more than 2 pins without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	 * alternate function, 6 * npins is an absolute high limit of the number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	 * of functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	functions = devm_kcalloc(pctl->dev, pctl->npins * 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				 sizeof(*functions), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	if (!functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	for (i = 0; i < pctl->npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		for (df = pctl->ppins[i].functions; df->name; df++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			if (!pxa2xx_find_function(pctl, df->name, functions))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				(functions + pctl->nfuncs++)->name = df->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	pctl->functions = devm_kmemdup(pctl->dev, functions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				       pctl->nfuncs * sizeof(*functions),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				       GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (!pctl->functions)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	devm_kfree(pctl->dev, functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int pxa2xx_build_groups(struct pxa_pinctrl *pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	int i, j, ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	struct pxa_pinctrl_function *func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct pxa_desc_function *df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	char **gtmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	gtmp = devm_kmalloc_array(pctl->dev, pctl->npins, sizeof(*gtmp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 				  GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	if (!gtmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	for (i = 0; i < pctl->nfuncs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		ngroups = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		for (j = 0; j < pctl->npins; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 			for (df = pctl->ppins[j].functions; df->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			     df++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				if (!strcmp(pctl->functions[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 					    df->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 					gtmp[ngroups++] = (char *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 						pctl->ppins[j].pin.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		func = pctl->functions + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		func->ngroups = ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		func->groups =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			devm_kmalloc_array(pctl->dev, ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 					   sizeof(char *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		if (!func->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		memcpy(func->groups, gtmp, ngroups * sizeof(*gtmp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	devm_kfree(pctl->dev, gtmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int pxa2xx_build_state(struct pxa_pinctrl *pctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			      const struct pxa_desc_pin *ppins, int npins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	struct pxa_pinctrl_group *group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	struct pinctrl_pin_desc *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	pctl->npins = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	pctl->ppins = ppins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	pctl->ngroups = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	pctl->desc.npins = npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	pins = devm_kcalloc(pctl->dev, npins, sizeof(*pins), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (!pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	pctl->desc.pins = pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	for (i = 0; i < npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		pins[i] = ppins[i].pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	pctl->groups = devm_kmalloc_array(pctl->dev, pctl->ngroups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 					  sizeof(*pctl->groups), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	if (!pctl->groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	for (i = 0; i < npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		group = pctl->groups + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		group->name = ppins[i].pin.name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		group->pin = ppins[i].pin.number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	ret = pxa2xx_build_functions(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	ret = pxa2xx_build_groups(pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int pxa2xx_pinctrl_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			const struct pxa_desc_pin *ppins, int npins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			void __iomem *base_gafr[], void __iomem *base_gpdr[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 			void __iomem *base_pgsr[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct pxa_pinctrl *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	int ret, i, maxpin = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	for (i = 0; i < npins; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		maxpin = max_t(int, ppins[i].pin.number, maxpin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (!pctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	pctl->base_gafr = devm_kcalloc(&pdev->dev, roundup(maxpin, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 				       sizeof(*pctl->base_gafr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	pctl->base_gpdr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 				       sizeof(*pctl->base_gpdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	pctl->base_pgsr = devm_kcalloc(&pdev->dev, roundup(maxpin, 32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 				       sizeof(*pctl->base_pgsr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (!pctl->base_gafr || !pctl->base_gpdr || !pctl->base_pgsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	platform_set_drvdata(pdev, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	spin_lock_init(&pctl->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	pctl->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	pctl->desc = pxa2xx_pinctrl_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	pctl->desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	pctl->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	for (i = 0; i < roundup(maxpin, 16); i += 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		pctl->base_gafr[i / 16] = base_gafr[i / 16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	for (i = 0; i < roundup(maxpin, 32); i += 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		pctl->base_gpdr[i / 32] = base_gpdr[i / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		pctl->base_pgsr[i / 32] = base_pgsr[i / 32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	ret = pxa2xx_build_state(pctl, ppins, npins);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->desc, pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	if (IS_ERR(pctl->pctl_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		return PTR_ERR(pctl->pctl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	dev_info(&pdev->dev, "initialized pxa2xx pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) EXPORT_SYMBOL_GPL(pxa2xx_pinctrl_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) MODULE_DESCRIPTION("Marvell PXA2xx pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) MODULE_LICENSE("GPL v2");