^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell PXA25x family pin control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2016 Robert Jarzmik
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "pinctrl-pxa2xx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static const struct pxa_desc_pin pxa25x_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) PXA_GPIO_PIN(PXA_PINCTRL_PIN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PXA_FUNCTION(0, 1, "GP_RST")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(2)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(3)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(4)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PXA_GPIO_PIN(PXA_PINCTRL_PIN(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) PXA_FUNCTION(1, 1, "MMCCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PXA_GPIO_PIN(PXA_PINCTRL_PIN(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PXA_FUNCTION(1, 1, "48_MHz")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) PXA_GPIO_PIN(PXA_PINCTRL_PIN(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) PXA_FUNCTION(1, 1, "MMCCS0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PXA_GPIO_PIN(PXA_PINCTRL_PIN(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PXA_FUNCTION(1, 1, "MMCCS1")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PXA_GPIO_PIN(PXA_PINCTRL_PIN(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PXA_FUNCTION(1, 1, "RTCCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PXA_GPIO_PIN(PXA_PINCTRL_PIN(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PXA_FUNCTION(1, 1, "3_6_MHz")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PXA_GPIO_PIN(PXA_PINCTRL_PIN(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PXA_FUNCTION(1, 1, "32_kHz")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PXA_GPIO_PIN(PXA_PINCTRL_PIN(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PXA_FUNCTION(1, 2, "MBGNT")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) PXA_GPIO_PIN(PXA_PINCTRL_PIN(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) PXA_FUNCTION(0, 1, "MBREQ")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) PXA_GPIO_PIN(PXA_PINCTRL_PIN(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) PXA_FUNCTION(1, 2, "nCS_1")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PXA_GPIO_PIN(PXA_PINCTRL_PIN(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PXA_FUNCTION(1, 2, "PWM0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PXA_GPIO_PIN(PXA_PINCTRL_PIN(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PXA_FUNCTION(1, 2, "PWM1")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PXA_GPIO_PIN(PXA_PINCTRL_PIN(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PXA_FUNCTION(0, 1, "RDY")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) PXA_GPIO_PIN(PXA_PINCTRL_PIN(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) PXA_FUNCTION(0, 1, "DREQ[1]")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PXA_GPIO_PIN(PXA_PINCTRL_PIN(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PXA_FUNCTION(0, 1, "DREQ[0]")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(21)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PXA_GPIO_ONLY_PIN(PXA_PINCTRL_PIN(22)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PXA_GPIO_PIN(PXA_PINCTRL_PIN(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PXA_FUNCTION(1, 2, "SCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) PXA_GPIO_PIN(PXA_PINCTRL_PIN(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) PXA_FUNCTION(1, 2, "SFRM")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PXA_GPIO_PIN(PXA_PINCTRL_PIN(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PXA_FUNCTION(1, 2, "TXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PXA_GPIO_PIN(PXA_PINCTRL_PIN(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PXA_FUNCTION(0, 1, "RXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PXA_GPIO_PIN(PXA_PINCTRL_PIN(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PXA_FUNCTION(0, 1, "EXTCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PXA_GPIO_PIN(PXA_PINCTRL_PIN(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PXA_FUNCTION(0, 1, "BITCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PXA_FUNCTION(0, 2, "BITCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PXA_FUNCTION(1, 1, "BITCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PXA_GPIO_PIN(PXA_PINCTRL_PIN(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PXA_FUNCTION(0, 1, "SDATA_IN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PXA_FUNCTION(0, 2, "SDATA_IN")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) PXA_GPIO_PIN(PXA_PINCTRL_PIN(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) PXA_FUNCTION(1, 1, "SDATA_OUT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) PXA_FUNCTION(1, 2, "SDATA_OUT")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PXA_GPIO_PIN(PXA_PINCTRL_PIN(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) PXA_FUNCTION(1, 1, "SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) PXA_FUNCTION(1, 2, "SYNC")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) PXA_GPIO_PIN(PXA_PINCTRL_PIN(32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) PXA_FUNCTION(0, 1, "SDATA_IN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) PXA_FUNCTION(1, 1, "SYSCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) PXA_GPIO_PIN(PXA_PINCTRL_PIN(33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) PXA_FUNCTION(1, 2, "nCS[5]")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PXA_GPIO_PIN(PXA_PINCTRL_PIN(34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PXA_FUNCTION(0, 1, "FFRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PXA_FUNCTION(1, 2, "MMCCS0")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PXA_GPIO_PIN(PXA_PINCTRL_PIN(35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PXA_FUNCTION(0, 1, "CTS")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PXA_GPIO_PIN(PXA_PINCTRL_PIN(36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) PXA_FUNCTION(0, 1, "DCD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PXA_GPIO_PIN(PXA_PINCTRL_PIN(37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) PXA_FUNCTION(0, 1, "DSR")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) PXA_GPIO_PIN(PXA_PINCTRL_PIN(38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) PXA_FUNCTION(0, 1, "RI")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) PXA_GPIO_PIN(PXA_PINCTRL_PIN(39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) PXA_FUNCTION(1, 1, "MMCC1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) PXA_FUNCTION(1, 2, "FFTXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PXA_GPIO_PIN(PXA_PINCTRL_PIN(40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PXA_FUNCTION(1, 2, "DTR")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PXA_GPIO_PIN(PXA_PINCTRL_PIN(41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) PXA_FUNCTION(1, 2, "RTS")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PXA_GPIO_PIN(PXA_PINCTRL_PIN(42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PXA_FUNCTION(0, 1, "BTRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PXA_FUNCTION(0, 3, "HWRXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PXA_GPIO_PIN(PXA_PINCTRL_PIN(43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PXA_FUNCTION(1, 2, "BTTXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PXA_FUNCTION(1, 3, "HWTXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PXA_GPIO_PIN(PXA_PINCTRL_PIN(44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PXA_FUNCTION(0, 1, "BTCTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PXA_FUNCTION(0, 3, "HWCTS")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PXA_GPIO_PIN(PXA_PINCTRL_PIN(45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PXA_FUNCTION(1, 2, "BTRTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PXA_FUNCTION(1, 3, "HWRTS")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PXA_GPIO_PIN(PXA_PINCTRL_PIN(46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PXA_FUNCTION(0, 1, "ICP_RXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PXA_FUNCTION(0, 2, "RXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PXA_GPIO_PIN(PXA_PINCTRL_PIN(47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PXA_FUNCTION(1, 1, "TXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PXA_FUNCTION(1, 2, "ICP_TXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PXA_GPIO_PIN(PXA_PINCTRL_PIN(48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PXA_FUNCTION(1, 1, "HWTXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PXA_FUNCTION(1, 2, "nPOE")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PXA_GPIO_PIN(PXA_PINCTRL_PIN(49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PXA_FUNCTION(0, 1, "HWRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PXA_FUNCTION(1, 2, "nPWE")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PXA_GPIO_PIN(PXA_PINCTRL_PIN(50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PXA_FUNCTION(0, 1, "HWCTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PXA_FUNCTION(1, 2, "nPIOR")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PXA_GPIO_PIN(PXA_PINCTRL_PIN(51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PXA_FUNCTION(1, 1, "HWRTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PXA_FUNCTION(1, 2, "nPIOW")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PXA_GPIO_PIN(PXA_PINCTRL_PIN(52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PXA_FUNCTION(1, 2, "nPCE[1]")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PXA_GPIO_PIN(PXA_PINCTRL_PIN(53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PXA_FUNCTION(1, 1, "MMCCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PXA_FUNCTION(1, 2, "nPCE[2]")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PXA_GPIO_PIN(PXA_PINCTRL_PIN(54),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PXA_FUNCTION(1, 1, "MMCCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PXA_FUNCTION(1, 2, "nPSKTSEL")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PXA_GPIO_PIN(PXA_PINCTRL_PIN(55),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PXA_FUNCTION(1, 2, "nPREG")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PXA_GPIO_PIN(PXA_PINCTRL_PIN(56),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PXA_FUNCTION(0, 1, "nPWAIT")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PXA_GPIO_PIN(PXA_PINCTRL_PIN(57),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PXA_FUNCTION(0, 1, "nIOIS16")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PXA_GPIO_PIN(PXA_PINCTRL_PIN(58),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PXA_FUNCTION(1, 2, "LDD<0>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PXA_GPIO_PIN(PXA_PINCTRL_PIN(59),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PXA_FUNCTION(1, 2, "LDD<1>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PXA_GPIO_PIN(PXA_PINCTRL_PIN(60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PXA_FUNCTION(1, 2, "LDD<2>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PXA_GPIO_PIN(PXA_PINCTRL_PIN(61),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PXA_FUNCTION(1, 2, "LDD<3>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PXA_GPIO_PIN(PXA_PINCTRL_PIN(62),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PXA_FUNCTION(1, 2, "LDD<4>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PXA_GPIO_PIN(PXA_PINCTRL_PIN(63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PXA_FUNCTION(1, 2, "LDD<5>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PXA_GPIO_PIN(PXA_PINCTRL_PIN(64),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PXA_FUNCTION(1, 2, "LDD<6>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PXA_GPIO_PIN(PXA_PINCTRL_PIN(65),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PXA_FUNCTION(1, 2, "LDD<7>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PXA_GPIO_PIN(PXA_PINCTRL_PIN(66),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PXA_FUNCTION(0, 1, "MBREQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PXA_FUNCTION(1, 2, "LDD<8>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PXA_GPIO_PIN(PXA_PINCTRL_PIN(67),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PXA_FUNCTION(1, 1, "MMCCS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PXA_FUNCTION(1, 2, "LDD<9>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PXA_GPIO_PIN(PXA_PINCTRL_PIN(68),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PXA_FUNCTION(1, 1, "MMCCS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PXA_FUNCTION(1, 2, "LDD<10>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PXA_GPIO_PIN(PXA_PINCTRL_PIN(69),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PXA_FUNCTION(1, 1, "MMCCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PXA_FUNCTION(1, 2, "LDD<11>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PXA_GPIO_PIN(PXA_PINCTRL_PIN(70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PXA_FUNCTION(1, 1, "RTCCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PXA_FUNCTION(1, 2, "LDD<12>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PXA_GPIO_PIN(PXA_PINCTRL_PIN(71),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PXA_FUNCTION(1, 1, "3_6_MHz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PXA_FUNCTION(1, 2, "LDD<13>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PXA_GPIO_PIN(PXA_PINCTRL_PIN(72),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) PXA_FUNCTION(1, 1, "32_kHz"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) PXA_FUNCTION(1, 2, "LDD<14>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) PXA_GPIO_PIN(PXA_PINCTRL_PIN(73),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) PXA_FUNCTION(1, 1, "MBGNT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) PXA_FUNCTION(1, 2, "LDD<15>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) PXA_GPIO_PIN(PXA_PINCTRL_PIN(74),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) PXA_FUNCTION(1, 2, "LCD_FCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) PXA_GPIO_PIN(PXA_PINCTRL_PIN(75),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) PXA_FUNCTION(1, 2, "LCD_LCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PXA_GPIO_PIN(PXA_PINCTRL_PIN(76),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PXA_FUNCTION(1, 2, "LCD_PCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PXA_GPIO_PIN(PXA_PINCTRL_PIN(77),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PXA_FUNCTION(1, 2, "LCD_ACBIAS")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PXA_GPIO_PIN(PXA_PINCTRL_PIN(78),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PXA_FUNCTION(1, 2, "nCS<2>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PXA_GPIO_PIN(PXA_PINCTRL_PIN(79),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PXA_FUNCTION(1, 2, "nCS<3>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PXA_GPIO_PIN(PXA_PINCTRL_PIN(80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PXA_FUNCTION(1, 2, "nCS<4>")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PXA_GPIO_PIN(PXA_PINCTRL_PIN(81),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PXA_FUNCTION(0, 1, "NSSPSCLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PXA_FUNCTION(1, 1, "NSSPSCLK")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PXA_GPIO_PIN(PXA_PINCTRL_PIN(82),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PXA_FUNCTION(0, 1, "NSSPSFRM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PXA_FUNCTION(1, 1, "NSSPSFRM")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PXA_GPIO_PIN(PXA_PINCTRL_PIN(83),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PXA_FUNCTION(0, 2, "NSSPRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PXA_FUNCTION(1, 1, "NSSPTXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PXA_GPIO_PIN(PXA_PINCTRL_PIN(84),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PXA_FUNCTION(0, 2, "NSSPRXD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PXA_FUNCTION(1, 1, "NSSPTXD")),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int pxa25x_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) void __iomem *base_af[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) void __iomem *base_dir[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) void __iomem *base_sleep[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) base_af[0] = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (IS_ERR(base_af[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return PTR_ERR(base_af[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) base_dir[0] = devm_platform_ioremap_resource(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (IS_ERR(base_dir[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return PTR_ERR(base_dir[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) base_dir[3] = devm_platform_ioremap_resource(pdev, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (IS_ERR(base_dir[3]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return PTR_ERR(base_dir[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) base_sleep[0] = devm_platform_ioremap_resource(pdev, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (IS_ERR(base_sleep[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return PTR_ERR(base_sleep[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) for (i = 0; i < ARRAY_SIZE(base_af); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) base_af[i] = base_af[0] + sizeof(base_af[0]) * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) base_dir[i] = base_dir[0] + sizeof(base_dir[0]) * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) for (i = 0; i < ARRAY_SIZE(base_sleep); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) base_sleep[i] = base_sleep[0] + sizeof(base_af[0]) * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = pxa2xx_pinctrl_init(pdev, pxa25x_pins, ARRAY_SIZE(pxa25x_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) base_af, base_dir, base_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const struct of_device_id pxa25x_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { .compatible = "marvell,pxa25x-pinctrl", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MODULE_DEVICE_TABLE(of, pxa25x_pinctrl_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct platform_driver pxa25x_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .probe = pxa25x_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .name = "pxa25x-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .of_match_table = pxa25x_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) module_platform_driver(pxa25x_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) MODULE_DESCRIPTION("Marvell PXA25x pinctrl driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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