^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Zynq pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014 Xilinx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Sören Brinkmann <soren.brinkmann@xilinx.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "pinctrl-utils.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZYNQ_NUM_MIOS 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZYNQ_PCTRL_MIO_MST_TRI0 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZYNQ_PCTRL_MIO_MST_TRI1 0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZYNQ_PINMUX_MUX_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZYNQ_PINMUX_MUX_MASK (0x7f << ZYNQ_PINMUX_MUX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * struct zynq_pinctrl - driver data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @pctrl: Pinctrl device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @syscon: Syscon regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @pctrl_offset: Offset for pinctrl into the @syscon space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @groups: Pingroups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @ngroups: Number of @groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @funcs: Pinmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @nfuncs: Number of @funcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct zynq_pinctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct pinctrl_dev *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct regmap *syscon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 pctrl_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) const struct zynq_pctrl_group *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) const struct zynq_pinmux_function *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned int nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct zynq_pctrl_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const unsigned int npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * struct zynq_pinmux_function - a pinmux function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @name: Name of the pinmux function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @groups: List of pingroups for this function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @ngroups: Number of entries in @groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * @mux_val: Selector for this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @mux: Offset of function specific mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @mux_mask: Mask for function specific selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @mux_shift: Shift for function specific selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct zynq_pinmux_function {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int mux_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u8 mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum zynq_pinmux_functions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ZYNQ_PMUX_can0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) ZYNQ_PMUX_can1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ZYNQ_PMUX_ethernet0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ZYNQ_PMUX_ethernet1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ZYNQ_PMUX_gpio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ZYNQ_PMUX_i2c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ZYNQ_PMUX_i2c1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ZYNQ_PMUX_mdio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ZYNQ_PMUX_mdio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ZYNQ_PMUX_qspi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ZYNQ_PMUX_qspi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ZYNQ_PMUX_qspi_fbclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) ZYNQ_PMUX_qspi_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ZYNQ_PMUX_spi0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ZYNQ_PMUX_spi1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) ZYNQ_PMUX_spi0_ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ZYNQ_PMUX_spi1_ss,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ZYNQ_PMUX_sdio0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ZYNQ_PMUX_sdio0_pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ZYNQ_PMUX_sdio0_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ZYNQ_PMUX_sdio0_wp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ZYNQ_PMUX_sdio1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ZYNQ_PMUX_sdio1_pc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ZYNQ_PMUX_sdio1_cd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ZYNQ_PMUX_sdio1_wp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ZYNQ_PMUX_smc0_nor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ZYNQ_PMUX_smc0_nor_cs1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ZYNQ_PMUX_smc0_nor_addr25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ZYNQ_PMUX_smc0_nand,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ZYNQ_PMUX_ttc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ZYNQ_PMUX_ttc1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ZYNQ_PMUX_uart0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ZYNQ_PMUX_uart1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ZYNQ_PMUX_usb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ZYNQ_PMUX_usb1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ZYNQ_PMUX_swdt0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) ZYNQ_PMUX_MAX_FUNC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct pinctrl_pin_desc zynq_pins[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PINCTRL_PIN(0, "MIO0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PINCTRL_PIN(1, "MIO1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PINCTRL_PIN(2, "MIO2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PINCTRL_PIN(3, "MIO3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PINCTRL_PIN(4, "MIO4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PINCTRL_PIN(5, "MIO5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PINCTRL_PIN(6, "MIO6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PINCTRL_PIN(7, "MIO7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PINCTRL_PIN(8, "MIO8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PINCTRL_PIN(9, "MIO9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PINCTRL_PIN(10, "MIO10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PINCTRL_PIN(11, "MIO11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PINCTRL_PIN(12, "MIO12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PINCTRL_PIN(13, "MIO13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PINCTRL_PIN(14, "MIO14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PINCTRL_PIN(15, "MIO15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PINCTRL_PIN(16, "MIO16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PINCTRL_PIN(17, "MIO17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PINCTRL_PIN(18, "MIO18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PINCTRL_PIN(19, "MIO19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PINCTRL_PIN(20, "MIO20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PINCTRL_PIN(21, "MIO21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PINCTRL_PIN(22, "MIO22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PINCTRL_PIN(23, "MIO23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PINCTRL_PIN(24, "MIO24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) PINCTRL_PIN(25, "MIO25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) PINCTRL_PIN(26, "MIO26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) PINCTRL_PIN(27, "MIO27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) PINCTRL_PIN(28, "MIO28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) PINCTRL_PIN(29, "MIO29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PINCTRL_PIN(30, "MIO30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) PINCTRL_PIN(31, "MIO31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PINCTRL_PIN(32, "MIO32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PINCTRL_PIN(33, "MIO33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) PINCTRL_PIN(34, "MIO34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) PINCTRL_PIN(35, "MIO35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) PINCTRL_PIN(36, "MIO36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) PINCTRL_PIN(37, "MIO37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) PINCTRL_PIN(38, "MIO38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) PINCTRL_PIN(39, "MIO39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) PINCTRL_PIN(40, "MIO40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) PINCTRL_PIN(41, "MIO41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) PINCTRL_PIN(42, "MIO42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) PINCTRL_PIN(43, "MIO43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) PINCTRL_PIN(44, "MIO44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PINCTRL_PIN(45, "MIO45"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PINCTRL_PIN(46, "MIO46"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PINCTRL_PIN(47, "MIO47"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PINCTRL_PIN(48, "MIO48"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PINCTRL_PIN(49, "MIO49"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PINCTRL_PIN(50, "MIO50"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PINCTRL_PIN(51, "MIO51"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PINCTRL_PIN(52, "MIO52"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PINCTRL_PIN(53, "MIO53"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PINCTRL_PIN(54, "EMIO_SD0_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PINCTRL_PIN(55, "EMIO_SD0_CD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PINCTRL_PIN(56, "EMIO_SD1_WP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PINCTRL_PIN(57, "EMIO_SD1_CD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* pin groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const unsigned int ethernet0_0_pins[] = {16, 17, 18, 19, 20, 21, 22, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 24, 25, 26, 27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const unsigned int ethernet1_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 36, 37, 38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned int mdio0_0_pins[] = {52, 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned int mdio1_0_pins[] = {52, 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned int qspi0_0_pins[] = {1, 2, 3, 4, 5, 6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int qspi1_0_pins[] = {9, 10, 11, 12, 13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int qspi_cs1_pins[] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const unsigned int qspi_fbclk_pins[] = {8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const unsigned int spi0_0_pins[] = {16, 17, 21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const unsigned int spi0_0_ss0_pins[] = {18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int spi0_0_ss1_pins[] = {19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const unsigned int spi0_0_ss2_pins[] = {20,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const unsigned int spi0_1_pins[] = {28, 29, 33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const unsigned int spi0_1_ss0_pins[] = {30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned int spi0_1_ss1_pins[] = {31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const unsigned int spi0_1_ss2_pins[] = {32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned int spi0_2_pins[] = {40, 41, 45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const unsigned int spi0_2_ss0_pins[] = {42};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned int spi0_2_ss1_pins[] = {43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const unsigned int spi0_2_ss2_pins[] = {44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const unsigned int spi1_0_pins[] = {10, 11, 12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static const unsigned int spi1_0_ss0_pins[] = {13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const unsigned int spi1_0_ss1_pins[] = {14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const unsigned int spi1_0_ss2_pins[] = {15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const unsigned int spi1_1_pins[] = {22, 23, 24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned int spi1_1_ss0_pins[] = {25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned int spi1_1_ss1_pins[] = {26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const unsigned int spi1_1_ss2_pins[] = {27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const unsigned int spi1_2_pins[] = {34, 35, 36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned int spi1_2_ss0_pins[] = {37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const unsigned int spi1_2_ss1_pins[] = {38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned int spi1_2_ss2_pins[] = {39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const unsigned int spi1_3_pins[] = {46, 47, 48, 49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const unsigned int spi1_3_ss0_pins[] = {49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const unsigned int spi1_3_ss1_pins[] = {50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned int spi1_3_ss2_pins[] = {51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const unsigned int sdio0_0_pins[] = {16, 17, 18, 19, 20, 21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const unsigned int sdio0_1_pins[] = {28, 29, 30, 31, 32, 33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int sdio0_2_pins[] = {40, 41, 42, 43, 44, 45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned int sdio1_0_pins[] = {10, 11, 12, 13, 14, 15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned int sdio1_1_pins[] = {22, 23, 24, 25, 26, 27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const unsigned int sdio1_2_pins[] = {34, 35, 36, 37, 38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned int sdio1_3_pins[] = {46, 47, 48, 49, 50, 51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned int sdio0_emio_wp_pins[] = {54};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned int sdio0_emio_cd_pins[] = {55};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const unsigned int sdio1_emio_wp_pins[] = {56};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static const unsigned int sdio1_emio_cd_pins[] = {57};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned int smc0_nor_pins[] = {0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 15, 16, 17, 18, 19, 20, 21, 22, 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 24, 25, 26, 27, 28, 29, 30, 31, 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 33, 34, 35, 36, 37, 38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const unsigned int smc0_nor_cs1_pins[] = {1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const unsigned int smc0_nor_addr25_pins[] = {1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const unsigned int smc0_nand_pins[] = {0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 12, 13, 14, 16, 17, 18, 19, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 21, 22, 23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const unsigned int smc0_nand8_pins[] = {0, 2, 3, 4, 5, 6, 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 8, 9, 10, 11, 12, 13, 14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* Note: CAN MIO clock inputs are modeled in the clock framework */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const unsigned int can0_0_pins[] = {10, 11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const unsigned int can0_1_pins[] = {14, 15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const unsigned int can0_2_pins[] = {18, 19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const unsigned int can0_3_pins[] = {22, 23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const unsigned int can0_4_pins[] = {26, 27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const unsigned int can0_5_pins[] = {30, 31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const unsigned int can0_6_pins[] = {34, 35};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static const unsigned int can0_7_pins[] = {38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const unsigned int can0_8_pins[] = {42, 43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static const unsigned int can0_9_pins[] = {46, 47};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static const unsigned int can0_10_pins[] = {50, 51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const unsigned int can1_0_pins[] = {8, 9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const unsigned int can1_1_pins[] = {12, 13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const unsigned int can1_2_pins[] = {16, 17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const unsigned int can1_3_pins[] = {20, 21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const unsigned int can1_4_pins[] = {24, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const unsigned int can1_5_pins[] = {28, 29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const unsigned int can1_6_pins[] = {32, 33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const unsigned int can1_7_pins[] = {36, 37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const unsigned int can1_8_pins[] = {40, 41};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const unsigned int can1_9_pins[] = {44, 45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const unsigned int can1_10_pins[] = {48, 49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static const unsigned int can1_11_pins[] = {52, 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static const unsigned int uart0_0_pins[] = {10, 11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static const unsigned int uart0_1_pins[] = {14, 15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static const unsigned int uart0_2_pins[] = {18, 19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const unsigned int uart0_3_pins[] = {22, 23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static const unsigned int uart0_4_pins[] = {26, 27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const unsigned int uart0_5_pins[] = {30, 31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static const unsigned int uart0_6_pins[] = {34, 35};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned int uart0_7_pins[] = {38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const unsigned int uart0_8_pins[] = {42, 43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const unsigned int uart0_9_pins[] = {46, 47};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const unsigned int uart0_10_pins[] = {50, 51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const unsigned int uart1_0_pins[] = {8, 9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static const unsigned int uart1_1_pins[] = {12, 13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const unsigned int uart1_2_pins[] = {16, 17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const unsigned int uart1_3_pins[] = {20, 21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const unsigned int uart1_4_pins[] = {24, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const unsigned int uart1_5_pins[] = {28, 29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const unsigned int uart1_6_pins[] = {32, 33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static const unsigned int uart1_7_pins[] = {36, 37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static const unsigned int uart1_8_pins[] = {40, 41};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static const unsigned int uart1_9_pins[] = {44, 45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const unsigned int uart1_10_pins[] = {48, 49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const unsigned int uart1_11_pins[] = {52, 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const unsigned int i2c0_0_pins[] = {10, 11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const unsigned int i2c0_1_pins[] = {14, 15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const unsigned int i2c0_2_pins[] = {18, 19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const unsigned int i2c0_3_pins[] = {22, 23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const unsigned int i2c0_4_pins[] = {26, 27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const unsigned int i2c0_5_pins[] = {30, 31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const unsigned int i2c0_6_pins[] = {34, 35};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static const unsigned int i2c0_7_pins[] = {38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const unsigned int i2c0_8_pins[] = {42, 43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const unsigned int i2c0_9_pins[] = {46, 47};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const unsigned int i2c0_10_pins[] = {50, 51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const unsigned int i2c1_0_pins[] = {12, 13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned int i2c1_1_pins[] = {16, 17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const unsigned int i2c1_2_pins[] = {20, 21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const unsigned int i2c1_3_pins[] = {24, 25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const unsigned int i2c1_4_pins[] = {28, 29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const unsigned int i2c1_5_pins[] = {32, 33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const unsigned int i2c1_6_pins[] = {36, 37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static const unsigned int i2c1_7_pins[] = {40, 41};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const unsigned int i2c1_8_pins[] = {44, 45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const unsigned int i2c1_9_pins[] = {48, 49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const unsigned int i2c1_10_pins[] = {52, 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const unsigned int ttc0_0_pins[] = {18, 19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const unsigned int ttc0_1_pins[] = {30, 31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const unsigned int ttc0_2_pins[] = {42, 43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const unsigned int ttc1_0_pins[] = {16, 17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const unsigned int ttc1_1_pins[] = {28, 29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const unsigned int ttc1_2_pins[] = {40, 41};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const unsigned int swdt0_0_pins[] = {14, 15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const unsigned int swdt0_1_pins[] = {26, 27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const unsigned int swdt0_2_pins[] = {38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned int swdt0_3_pins[] = {50, 51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const unsigned int swdt0_4_pins[] = {52, 53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const unsigned int gpio0_0_pins[] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const unsigned int gpio0_1_pins[] = {1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const unsigned int gpio0_2_pins[] = {2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int gpio0_3_pins[] = {3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const unsigned int gpio0_4_pins[] = {4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const unsigned int gpio0_5_pins[] = {5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int gpio0_6_pins[] = {6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const unsigned int gpio0_7_pins[] = {7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const unsigned int gpio0_8_pins[] = {8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const unsigned int gpio0_9_pins[] = {9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static const unsigned int gpio0_10_pins[] = {10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) static const unsigned int gpio0_11_pins[] = {11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const unsigned int gpio0_12_pins[] = {12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const unsigned int gpio0_13_pins[] = {13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static const unsigned int gpio0_14_pins[] = {14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static const unsigned int gpio0_15_pins[] = {15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const unsigned int gpio0_16_pins[] = {16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const unsigned int gpio0_17_pins[] = {17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const unsigned int gpio0_18_pins[] = {18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static const unsigned int gpio0_19_pins[] = {19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int gpio0_20_pins[] = {20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const unsigned int gpio0_21_pins[] = {21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const unsigned int gpio0_22_pins[] = {22};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const unsigned int gpio0_23_pins[] = {23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const unsigned int gpio0_24_pins[] = {24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const unsigned int gpio0_25_pins[] = {25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static const unsigned int gpio0_26_pins[] = {26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int gpio0_27_pins[] = {27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const unsigned int gpio0_28_pins[] = {28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const unsigned int gpio0_29_pins[] = {29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const unsigned int gpio0_30_pins[] = {30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int gpio0_31_pins[] = {31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const unsigned int gpio0_32_pins[] = {32};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const unsigned int gpio0_33_pins[] = {33};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const unsigned int gpio0_34_pins[] = {34};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned int gpio0_35_pins[] = {35};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const unsigned int gpio0_36_pins[] = {36};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const unsigned int gpio0_37_pins[] = {37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const unsigned int gpio0_38_pins[] = {38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const unsigned int gpio0_39_pins[] = {39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const unsigned int gpio0_40_pins[] = {40};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static const unsigned int gpio0_41_pins[] = {41};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const unsigned int gpio0_42_pins[] = {42};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const unsigned int gpio0_43_pins[] = {43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const unsigned int gpio0_44_pins[] = {44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const unsigned int gpio0_45_pins[] = {45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const unsigned int gpio0_46_pins[] = {46};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const unsigned int gpio0_47_pins[] = {47};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const unsigned int gpio0_48_pins[] = {48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static const unsigned int gpio0_49_pins[] = {49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const unsigned int gpio0_50_pins[] = {50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static const unsigned int gpio0_51_pins[] = {51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static const unsigned int gpio0_52_pins[] = {52};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static const unsigned int gpio0_53_pins[] = {53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const unsigned int usb0_0_pins[] = {28, 29, 30, 31, 32, 33, 34, 35, 36,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 37, 38, 39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const unsigned int usb1_0_pins[] = {40, 41, 42, 43, 44, 45, 46, 47, 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 49, 50, 51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DEFINE_ZYNQ_PINCTRL_GRP(nm) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = #nm "_grp", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .pins = nm ## _pins, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .npins = ARRAY_SIZE(nm ## _pins), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const struct zynq_pctrl_group zynq_pctrl_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DEFINE_ZYNQ_PINCTRL_GRP(ethernet0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) DEFINE_ZYNQ_PINCTRL_GRP(ethernet1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DEFINE_ZYNQ_PINCTRL_GRP(mdio0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) DEFINE_ZYNQ_PINCTRL_GRP(mdio1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DEFINE_ZYNQ_PINCTRL_GRP(qspi0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DEFINE_ZYNQ_PINCTRL_GRP(qspi1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DEFINE_ZYNQ_PINCTRL_GRP(qspi_fbclk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) DEFINE_ZYNQ_PINCTRL_GRP(qspi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DEFINE_ZYNQ_PINCTRL_GRP(spi0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) DEFINE_ZYNQ_PINCTRL_GRP(spi0_0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) DEFINE_ZYNQ_PINCTRL_GRP(spi0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) DEFINE_ZYNQ_PINCTRL_GRP(spi0_1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DEFINE_ZYNQ_PINCTRL_GRP(spi0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DEFINE_ZYNQ_PINCTRL_GRP(spi0_2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) DEFINE_ZYNQ_PINCTRL_GRP(spi1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DEFINE_ZYNQ_PINCTRL_GRP(spi1_0_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DEFINE_ZYNQ_PINCTRL_GRP(spi1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DEFINE_ZYNQ_PINCTRL_GRP(spi1_1_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DEFINE_ZYNQ_PINCTRL_GRP(spi1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DEFINE_ZYNQ_PINCTRL_GRP(spi1_2_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DEFINE_ZYNQ_PINCTRL_GRP(spi1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DEFINE_ZYNQ_PINCTRL_GRP(spi1_3_ss2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DEFINE_ZYNQ_PINCTRL_GRP(sdio0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DEFINE_ZYNQ_PINCTRL_GRP(sdio0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DEFINE_ZYNQ_PINCTRL_GRP(sdio0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DEFINE_ZYNQ_PINCTRL_GRP(sdio1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DEFINE_ZYNQ_PINCTRL_GRP(sdio1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DEFINE_ZYNQ_PINCTRL_GRP(sdio1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DEFINE_ZYNQ_PINCTRL_GRP(sdio1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DEFINE_ZYNQ_PINCTRL_GRP(sdio0_emio_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DEFINE_ZYNQ_PINCTRL_GRP(sdio1_emio_cd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DEFINE_ZYNQ_PINCTRL_GRP(smc0_nor_addr25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DEFINE_ZYNQ_PINCTRL_GRP(smc0_nand8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) DEFINE_ZYNQ_PINCTRL_GRP(can0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) DEFINE_ZYNQ_PINCTRL_GRP(can0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DEFINE_ZYNQ_PINCTRL_GRP(can0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) DEFINE_ZYNQ_PINCTRL_GRP(can0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DEFINE_ZYNQ_PINCTRL_GRP(can0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) DEFINE_ZYNQ_PINCTRL_GRP(can0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DEFINE_ZYNQ_PINCTRL_GRP(can0_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DEFINE_ZYNQ_PINCTRL_GRP(can0_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) DEFINE_ZYNQ_PINCTRL_GRP(can0_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) DEFINE_ZYNQ_PINCTRL_GRP(can0_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DEFINE_ZYNQ_PINCTRL_GRP(can0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) DEFINE_ZYNQ_PINCTRL_GRP(can1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DEFINE_ZYNQ_PINCTRL_GRP(can1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) DEFINE_ZYNQ_PINCTRL_GRP(can1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) DEFINE_ZYNQ_PINCTRL_GRP(can1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DEFINE_ZYNQ_PINCTRL_GRP(can1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DEFINE_ZYNQ_PINCTRL_GRP(can1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DEFINE_ZYNQ_PINCTRL_GRP(can1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DEFINE_ZYNQ_PINCTRL_GRP(can1_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DEFINE_ZYNQ_PINCTRL_GRP(can1_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) DEFINE_ZYNQ_PINCTRL_GRP(can1_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) DEFINE_ZYNQ_PINCTRL_GRP(can1_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) DEFINE_ZYNQ_PINCTRL_GRP(can1_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DEFINE_ZYNQ_PINCTRL_GRP(uart0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) DEFINE_ZYNQ_PINCTRL_GRP(uart0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DEFINE_ZYNQ_PINCTRL_GRP(uart0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DEFINE_ZYNQ_PINCTRL_GRP(uart0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) DEFINE_ZYNQ_PINCTRL_GRP(uart0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) DEFINE_ZYNQ_PINCTRL_GRP(uart0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DEFINE_ZYNQ_PINCTRL_GRP(uart0_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DEFINE_ZYNQ_PINCTRL_GRP(uart0_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DEFINE_ZYNQ_PINCTRL_GRP(uart0_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) DEFINE_ZYNQ_PINCTRL_GRP(uart0_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) DEFINE_ZYNQ_PINCTRL_GRP(uart0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DEFINE_ZYNQ_PINCTRL_GRP(uart1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) DEFINE_ZYNQ_PINCTRL_GRP(uart1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DEFINE_ZYNQ_PINCTRL_GRP(uart1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) DEFINE_ZYNQ_PINCTRL_GRP(uart1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) DEFINE_ZYNQ_PINCTRL_GRP(uart1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) DEFINE_ZYNQ_PINCTRL_GRP(uart1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) DEFINE_ZYNQ_PINCTRL_GRP(uart1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) DEFINE_ZYNQ_PINCTRL_GRP(uart1_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) DEFINE_ZYNQ_PINCTRL_GRP(uart1_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) DEFINE_ZYNQ_PINCTRL_GRP(uart1_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) DEFINE_ZYNQ_PINCTRL_GRP(uart1_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DEFINE_ZYNQ_PINCTRL_GRP(uart1_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DEFINE_ZYNQ_PINCTRL_GRP(i2c0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) DEFINE_ZYNQ_PINCTRL_GRP(i2c1_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) DEFINE_ZYNQ_PINCTRL_GRP(ttc0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) DEFINE_ZYNQ_PINCTRL_GRP(ttc0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) DEFINE_ZYNQ_PINCTRL_GRP(ttc0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) DEFINE_ZYNQ_PINCTRL_GRP(ttc1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) DEFINE_ZYNQ_PINCTRL_GRP(ttc1_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) DEFINE_ZYNQ_PINCTRL_GRP(ttc1_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DEFINE_ZYNQ_PINCTRL_GRP(swdt0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) DEFINE_ZYNQ_PINCTRL_GRP(swdt0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) DEFINE_ZYNQ_PINCTRL_GRP(swdt0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DEFINE_ZYNQ_PINCTRL_GRP(swdt0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) DEFINE_ZYNQ_PINCTRL_GRP(swdt0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_33),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_34),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_35),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_36),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_37),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_38),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_39),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_41),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_42),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_43),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_44),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_45),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_46),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_47),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_48),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_49),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_51),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_52),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) DEFINE_ZYNQ_PINCTRL_GRP(gpio0_53),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) DEFINE_ZYNQ_PINCTRL_GRP(usb0_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) DEFINE_ZYNQ_PINCTRL_GRP(usb1_0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* function groups */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const char * const ethernet0_groups[] = {"ethernet0_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static const char * const ethernet1_groups[] = {"ethernet1_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const char * const usb0_groups[] = {"usb0_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static const char * const usb1_groups[] = {"usb1_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) static const char * const mdio0_groups[] = {"mdio0_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const char * const mdio1_groups[] = {"mdio1_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static const char * const qspi0_groups[] = {"qspi0_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const char * const qspi1_groups[] = {"qspi1_0_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static const char * const qspi_fbclk_groups[] = {"qspi_fbclk_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static const char * const qspi_cs1_groups[] = {"qspi_cs1_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const char * const spi0_groups[] = {"spi0_0_grp", "spi0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) "spi0_2_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static const char * const spi1_groups[] = {"spi1_0_grp", "spi1_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) "spi1_2_grp", "spi1_3_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const char * const spi0_ss_groups[] = {"spi0_0_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) "spi0_0_ss1_grp", "spi0_0_ss2_grp", "spi0_1_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) "spi0_1_ss1_grp", "spi0_1_ss2_grp", "spi0_2_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) "spi0_2_ss1_grp", "spi0_2_ss2_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const char * const spi1_ss_groups[] = {"spi1_0_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) "spi1_0_ss1_grp", "spi1_0_ss2_grp", "spi1_1_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) "spi1_1_ss1_grp", "spi1_1_ss2_grp", "spi1_2_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) "spi1_2_ss1_grp", "spi1_2_ss2_grp", "spi1_3_ss0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) "spi1_3_ss1_grp", "spi1_3_ss2_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static const char * const sdio0_groups[] = {"sdio0_0_grp", "sdio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) "sdio0_2_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const char * const sdio1_groups[] = {"sdio1_0_grp", "sdio1_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) "sdio1_2_grp", "sdio1_3_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const char * const sdio0_pc_groups[] = {"gpio0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "gpio0_50_grp", "gpio0_52_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const char * const sdio1_pc_groups[] = {"gpio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "gpio0_51_grp", "gpio0_53_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static const char * const sdio0_cd_groups[] = {"gpio0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "gpio0_10_grp", "gpio0_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "gpio0_3_grp", "gpio0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_cd_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static const char * const sdio0_wp_groups[] = {"gpio0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "gpio0_10_grp", "gpio0_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "gpio0_3_grp", "gpio0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "gpio0_51_grp", "gpio0_53_grp", "sdio0_emio_wp_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static const char * const sdio1_cd_groups[] = {"gpio0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "gpio0_10_grp", "gpio0_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) "gpio0_3_grp", "gpio0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_cd_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static const char * const sdio1_wp_groups[] = {"gpio0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "gpio0_10_grp", "gpio0_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "gpio0_3_grp", "gpio0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "gpio0_51_grp", "gpio0_53_grp", "sdio1_emio_wp_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const char * const smc0_nor_groups[] = {"smc0_nor_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static const char * const smc0_nor_cs1_groups[] = {"smc0_nor_cs1_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static const char * const smc0_nor_addr25_groups[] = {"smc0_nor_addr25_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const char * const smc0_nand_groups[] = {"smc0_nand_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "smc0_nand8_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static const char * const can0_groups[] = {"can0_0_grp", "can0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) "can0_2_grp", "can0_3_grp", "can0_4_grp", "can0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) "can0_6_grp", "can0_7_grp", "can0_8_grp", "can0_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "can0_10_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const char * const can1_groups[] = {"can1_0_grp", "can1_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "can1_2_grp", "can1_3_grp", "can1_4_grp", "can1_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "can1_6_grp", "can1_7_grp", "can1_8_grp", "can1_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "can1_10_grp", "can1_11_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const char * const uart0_groups[] = {"uart0_0_grp", "uart0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "uart0_2_grp", "uart0_3_grp", "uart0_4_grp", "uart0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "uart0_6_grp", "uart0_7_grp", "uart0_8_grp", "uart0_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "uart0_10_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const char * const uart1_groups[] = {"uart1_0_grp", "uart1_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "uart1_2_grp", "uart1_3_grp", "uart1_4_grp", "uart1_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "uart1_6_grp", "uart1_7_grp", "uart1_8_grp", "uart1_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "uart1_10_grp", "uart1_11_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const char * const i2c0_groups[] = {"i2c0_0_grp", "i2c0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "i2c0_2_grp", "i2c0_3_grp", "i2c0_4_grp", "i2c0_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "i2c0_6_grp", "i2c0_7_grp", "i2c0_8_grp", "i2c0_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "i2c0_10_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const char * const i2c1_groups[] = {"i2c1_0_grp", "i2c1_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "i2c1_2_grp", "i2c1_3_grp", "i2c1_4_grp", "i2c1_5_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "i2c1_6_grp", "i2c1_7_grp", "i2c1_8_grp", "i2c1_9_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "i2c1_10_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const char * const ttc0_groups[] = {"ttc0_0_grp", "ttc0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "ttc0_2_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const char * const ttc1_groups[] = {"ttc1_0_grp", "ttc1_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "ttc1_2_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const char * const swdt0_groups[] = {"swdt0_0_grp", "swdt0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "swdt0_2_grp", "swdt0_3_grp", "swdt0_4_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const char * const gpio0_groups[] = {"gpio0_0_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "gpio0_2_grp", "gpio0_4_grp", "gpio0_6_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "gpio0_8_grp", "gpio0_10_grp", "gpio0_12_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "gpio0_14_grp", "gpio0_16_grp", "gpio0_18_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "gpio0_20_grp", "gpio0_22_grp", "gpio0_24_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "gpio0_26_grp", "gpio0_28_grp", "gpio0_30_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "gpio0_32_grp", "gpio0_34_grp", "gpio0_36_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "gpio0_38_grp", "gpio0_40_grp", "gpio0_42_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "gpio0_44_grp", "gpio0_46_grp", "gpio0_48_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "gpio0_50_grp", "gpio0_52_grp", "gpio0_1_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "gpio0_3_grp", "gpio0_5_grp", "gpio0_7_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "gpio0_9_grp", "gpio0_11_grp", "gpio0_13_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "gpio0_15_grp", "gpio0_17_grp", "gpio0_19_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "gpio0_21_grp", "gpio0_23_grp", "gpio0_25_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "gpio0_27_grp", "gpio0_29_grp", "gpio0_31_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "gpio0_33_grp", "gpio0_35_grp", "gpio0_37_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) "gpio0_39_grp", "gpio0_41_grp", "gpio0_43_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "gpio0_45_grp", "gpio0_47_grp", "gpio0_49_grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "gpio0_51_grp", "gpio0_53_grp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #define DEFINE_ZYNQ_PINMUX_FUNCTION(fname, mval) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) [ZYNQ_PMUX_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .mux_val = mval, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(fname, mval, offset, mask, shift)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) [ZYNQ_PMUX_##fname] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .name = #fname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .groups = fname##_groups, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .ngroups = ARRAY_SIZE(fname##_groups), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .mux_val = mval, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .mux = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .mux_mask = mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .mux_shift = shift, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define ZYNQ_SDIO_WP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define ZYNQ_SDIO_WP_MASK (0x3f << ZYNQ_SDIO_WP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define ZYNQ_SDIO_CD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define ZYNQ_SDIO_CD_MASK (0x3f << ZYNQ_SDIO_CD_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static const struct zynq_pinmux_function zynq_pmux_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DEFINE_ZYNQ_PINMUX_FUNCTION(ethernet1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) DEFINE_ZYNQ_PINMUX_FUNCTION(usb0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) DEFINE_ZYNQ_PINMUX_FUNCTION(usb1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) DEFINE_ZYNQ_PINMUX_FUNCTION(mdio0, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DEFINE_ZYNQ_PINMUX_FUNCTION(mdio1, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) DEFINE_ZYNQ_PINMUX_FUNCTION(qspi0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DEFINE_ZYNQ_PINMUX_FUNCTION(qspi1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_fbclk, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) DEFINE_ZYNQ_PINMUX_FUNCTION(qspi_cs1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) DEFINE_ZYNQ_PINMUX_FUNCTION(spi0, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) DEFINE_ZYNQ_PINMUX_FUNCTION(spi1, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DEFINE_ZYNQ_PINMUX_FUNCTION(spi0_ss, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DEFINE_ZYNQ_PINMUX_FUNCTION(spi1_ss, 0x50),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DEFINE_ZYNQ_PINMUX_FUNCTION(sdio0_pc, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_wp, 0, 0x130, ZYNQ_SDIO_WP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ZYNQ_SDIO_WP_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio0_cd, 0, 0x130, ZYNQ_SDIO_CD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ZYNQ_SDIO_CD_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1, 0x40),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DEFINE_ZYNQ_PINMUX_FUNCTION(sdio1_pc, 0xc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_wp, 0, 0x134, ZYNQ_SDIO_WP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ZYNQ_SDIO_WP_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) DEFINE_ZYNQ_PINMUX_FUNCTION_MUX(sdio1_cd, 0, 0x134, ZYNQ_SDIO_CD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ZYNQ_SDIO_CD_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_cs1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nor_addr25, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) DEFINE_ZYNQ_PINMUX_FUNCTION(smc0_nand, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) DEFINE_ZYNQ_PINMUX_FUNCTION(can0, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) DEFINE_ZYNQ_PINMUX_FUNCTION(can1, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) DEFINE_ZYNQ_PINMUX_FUNCTION(uart0, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) DEFINE_ZYNQ_PINMUX_FUNCTION(uart1, 0x70),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DEFINE_ZYNQ_PINMUX_FUNCTION(i2c0, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) DEFINE_ZYNQ_PINMUX_FUNCTION(i2c1, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) DEFINE_ZYNQ_PINMUX_FUNCTION(ttc0, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DEFINE_ZYNQ_PINMUX_FUNCTION(ttc1, 0x60),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) DEFINE_ZYNQ_PINMUX_FUNCTION(swdt0, 0x30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) DEFINE_ZYNQ_PINMUX_FUNCTION(gpio0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int zynq_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return pctrl->ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) static const char *zynq_pctrl_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return pctrl->groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int zynq_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) const unsigned int **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned int *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *pins = pctrl->groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) *num_pins = pctrl->groups[selector].npins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static const struct pinctrl_ops zynq_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .get_groups_count = zynq_pctrl_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .get_group_name = zynq_pctrl_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .get_group_pins = zynq_pctrl_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .dt_node_to_map = pinconf_generic_dt_node_to_map_all,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .dt_free_map = pinctrl_utils_free_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* pinmux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int zynq_pmux_get_functions_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return pctrl->nfuncs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static const char *zynq_pmux_get_function_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return pctrl->funcs[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static int zynq_pmux_get_function_groups(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) *groups = pctrl->funcs[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *num_groups = pctrl->funcs[selector].ngroups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int zynq_pinmux_set_mux(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned int function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned int group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) const struct zynq_pctrl_group *pgrp = &pctrl->groups[group];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) const struct zynq_pinmux_function *func = &pctrl->funcs[function];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * SD WP & CD are special. They have dedicated registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * to mux them in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (function == ZYNQ_PMUX_sdio0_cd || function == ZYNQ_PMUX_sdio0_wp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) function == ZYNQ_PMUX_sdio1_cd ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) function == ZYNQ_PMUX_sdio1_wp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ret = regmap_read(pctrl->syscon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pctrl->pctrl_offset + func->mux, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) reg &= ~func->mux_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) reg |= pgrp->pins[0] << func->mux_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = regmap_write(pctrl->syscon,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) pctrl->pctrl_offset + func->mux, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) for (i = 0; i < pgrp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int pin = pgrp->pins[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u32 reg, addr = pctrl->pctrl_offset + (4 * pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = regmap_read(pctrl->syscon, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) reg &= ~ZYNQ_PINMUX_MUX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) reg |= func->mux_val << ZYNQ_PINMUX_MUX_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = regmap_write(pctrl->syscon, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static const struct pinmux_ops zynq_pinmux_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .get_functions_count = zynq_pmux_get_functions_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .get_function_name = zynq_pmux_get_function_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .get_function_groups = zynq_pmux_get_function_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .set_mux = zynq_pinmux_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* pinconfig */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define ZYNQ_PINCONF_TRISTATE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define ZYNQ_PINCONF_SPEED BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define ZYNQ_PINCONF_PULLUP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define ZYNQ_PINCONF_DISABLE_RECVR BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define ZYNQ_PINCONF_IOTYPE_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define ZYNQ_PINCONF_IOTYPE_MASK (7 << ZYNQ_PINCONF_IOTYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) enum zynq_io_standards {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) zynq_iostd_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) zynq_iostd_lvcmos18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) zynq_iostd_lvcmos25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) zynq_iostd_lvcmos33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) zynq_iostd_hstl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) zynq_iostd_max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * PIN_CONFIG_IOSTANDARD: if the pin can select an IO standard, the argument to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) * this parameter (on a custom format) tells the driver which alternative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * IO standard to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define PIN_CONFIG_IOSTANDARD (PIN_CONFIG_END + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const struct pinconf_generic_params zynq_dt_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {"io-standard", PIN_CONFIG_IOSTANDARD, zynq_iostd_lvcmos18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const struct pin_config_item zynq_conf_items[ARRAY_SIZE(zynq_dt_params)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) = { PCONFDUMP(PIN_CONFIG_IOSTANDARD, "IO-standard", NULL, true),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static unsigned int zynq_pinconf_iostd_get(u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return (reg & ZYNQ_PINCONF_IOTYPE_MASK) >> ZYNQ_PINCONF_IOTYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static int zynq_pinconf_cfg_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned int arg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned int param = pinconf_to_config_param(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (pin >= ZYNQ_NUM_MIOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (!(reg & ZYNQ_PINCONF_PULLUP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!(reg & ZYNQ_PINCONF_TRISTATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) arg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (reg & ZYNQ_PINCONF_PULLUP || reg & ZYNQ_PINCONF_TRISTATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) arg = !!(reg & ZYNQ_PINCONF_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) enum zynq_io_standards iostd = zynq_pinconf_iostd_get(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (iostd != zynq_iostd_hstl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!(reg & ZYNQ_PINCONF_DISABLE_RECVR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) arg = !!(reg & ZYNQ_PINCONF_DISABLE_RECVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case PIN_CONFIG_IOSTANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) arg = zynq_pinconf_iostd_get(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) *config = pinconf_to_config_packed(param, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int zynq_pinconf_cfg_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 pullup = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u32 tristate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (pin >= ZYNQ_NUM_MIOS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = regmap_read(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned int param = pinconf_to_config_param(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned int arg = pinconf_to_config_argument(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case PIN_CONFIG_BIAS_PULL_UP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) pullup = ZYNQ_PINCONF_PULLUP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) tristate = ZYNQ_PINCONF_TRISTATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) case PIN_CONFIG_BIAS_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) case PIN_CONFIG_SLEW_RATE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) reg |= ZYNQ_PINCONF_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) reg &= ~ZYNQ_PINCONF_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) case PIN_CONFIG_IOSTANDARD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (arg <= zynq_iostd_min || arg >= zynq_iostd_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev_warn(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "unsupported IO standard '%u'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) reg &= ~ZYNQ_PINCONF_IOTYPE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) reg |= arg << ZYNQ_PINCONF_IOTYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case PIN_CONFIG_LOW_POWER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) reg |= ZYNQ_PINCONF_DISABLE_RECVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) reg &= ~ZYNQ_PINCONF_DISABLE_RECVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_warn(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) "unsupported configuration parameter '%u'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (tristate || pullup) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) reg &= ~(ZYNQ_PINCONF_PULLUP | ZYNQ_PINCONF_TRISTATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) reg |= tristate | pullup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret = regmap_write(pctrl->syscon, pctrl->pctrl_offset + (4 * pin), reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int zynq_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) unsigned int selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) unsigned int num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct zynq_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) const struct zynq_pctrl_group *pgrp = &pctrl->groups[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) for (i = 0; i < pgrp->npins; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = zynq_pinconf_cfg_set(pctldev, pgrp->pins[i], configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const struct pinconf_ops zynq_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .pin_config_get = zynq_pinconf_cfg_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) .pin_config_set = zynq_pinconf_cfg_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .pin_config_group_set = zynq_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static struct pinctrl_desc zynq_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .name = "zynq_pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .pins = zynq_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .npins = ARRAY_SIZE(zynq_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .pctlops = &zynq_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .pmxops = &zynq_pinmux_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .confops = &zynq_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .num_custom_params = ARRAY_SIZE(zynq_dt_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .custom_params = zynq_dt_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .custom_conf_items = zynq_conf_items,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int zynq_pinctrl_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct zynq_pinctrl *pctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (!pctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) pctrl->syscon = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "syscon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (IS_ERR(pctrl->syscon)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_err(&pdev->dev, "unable to get syscon\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return PTR_ERR(pctrl->syscon);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_err(&pdev->dev, "missing IO resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pctrl->pctrl_offset = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pctrl->groups = zynq_pctrl_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pctrl->ngroups = ARRAY_SIZE(zynq_pctrl_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) pctrl->funcs = zynq_pmux_functions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pctrl->nfuncs = ARRAY_SIZE(zynq_pmux_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &zynq_desc, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (IS_ERR(pctrl->pctrl))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return PTR_ERR(pctrl->pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) platform_set_drvdata(pdev, pctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_info(&pdev->dev, "zynq pinctrl initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static const struct of_device_id zynq_pinctrl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) { .compatible = "xlnx,pinctrl-zynq" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static struct platform_driver zynq_pinctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .name = "zynq-pinctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .of_match_table = zynq_pinctrl_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .probe = zynq_pinctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int __init zynq_pinctrl_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return platform_driver_register(&zynq_pinctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) arch_initcall(zynq_pinctrl_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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