^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/pinctrl/pinmux-xway.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * based on linux/drivers/pinctrl/pinmux-pxa910.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012 John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2015 Martin Schiller <mschiller@tdt.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "pinctrl-lantiq.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <lantiq_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* we have up to 4 banks of 16 bit each */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PINS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PORT3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PORT(x) (x / PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PORT_PIN(x) (x % PINS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* we have 2 mux bits that can be set for each pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MUX_ALT0 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MUX_ALT1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * each bank has this offset apart from the 4th bank that is mixed into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * other 3 ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_OFF 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* these are the offsets to our registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GPIO_BASE(p) (REG_OFF * PORT(p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GPIO_OUT(p) GPIO_BASE(p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* the 4th port needs special offsets for some registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPIO3_OD (GPIO_BASE(0) + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* macros to help us access the registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MFP_XWAY(a, f0, f1, f2, f3) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .name = #a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .pin = a, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .func = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) XWAY_MUX_##f0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) XWAY_MUX_##f1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) XWAY_MUX_##f2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) XWAY_MUX_##f3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GRP_MUX(a, m, p) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FUNC_MUX(f, m) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { .func = f, .mux = XWAY_MUX_##m, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum xway_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) XWAY_MUX_GPIO = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) XWAY_MUX_SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) XWAY_MUX_ASC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) XWAY_MUX_USIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) XWAY_MUX_PCI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) XWAY_MUX_CBUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) XWAY_MUX_CGU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) XWAY_MUX_EBU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) XWAY_MUX_EBU2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) XWAY_MUX_JTAG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) XWAY_MUX_MCD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) XWAY_MUX_EXIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) XWAY_MUX_TDM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) XWAY_MUX_STP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) XWAY_MUX_SIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) XWAY_MUX_GPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) XWAY_MUX_NMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) XWAY_MUX_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) XWAY_MUX_MII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) XWAY_MUX_EPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) XWAY_MUX_DFE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) XWAY_MUX_SDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) XWAY_MUX_GPHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) XWAY_MUX_SSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) XWAY_MUX_WIFI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) XWAY_MUX_NONE = 0xffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* --------- DEPRECATED: xr9 related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* ---------- use xrx100/xrx200 instead ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XR9_MAX_PIN 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct ltq_mfp_pin xway_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) MFP_XWAY(GPIO5, GPIO, STP, GPHY, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned pins_asc0[] = {GPIO11, GPIO12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const unsigned pins_nmi[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned pins_mdio[] = {GPIO42, GPIO43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const unsigned pins_gphy0_led0[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const unsigned pins_gphy0_led1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned pins_gphy0_led2[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const unsigned pins_gphy1_led0[] = {GPIO44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const unsigned pins_gphy1_led1[] = {GPIO45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned pins_gphy1_led2[] = {GPIO47};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const unsigned pins_ebu_a24[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const unsigned pins_ebu_clk[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const unsigned pins_ebu_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned pins_ebu_a23[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const unsigned pins_ebu_wait[] = {GPIO26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const unsigned pins_ebu_a25[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const unsigned pins_ebu_rdy[] = {GPIO48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned pins_ebu_rd[] = {GPIO49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static const unsigned pins_nand_ale[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const unsigned pins_nand_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned pins_nand_cle[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const unsigned pins_nand_rdy[] = {GPIO48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const unsigned pins_nand_rd[] = {GPIO49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const unsigned pins_exin0[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static const unsigned pins_exin1[] = {GPIO1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const unsigned pins_exin2[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const unsigned pins_exin3[] = {GPIO39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const unsigned pins_exin4[] = {GPIO46};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const unsigned pins_exin5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const unsigned pins_spi_cs1[] = {GPIO15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static const unsigned pins_spi_cs2[] = {GPIO22};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const unsigned pins_spi_cs3[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned pins_spi_cs4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const unsigned pins_spi_cs5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const unsigned pins_spi_cs6[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned pins_gpt1[] = {GPIO28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned pins_gpt2[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const unsigned pins_gpt3[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned pins_clkout0[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned pins_clkout1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static const unsigned pins_clkout2[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const unsigned pins_clkout3[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned pins_pci_gnt1[] = {GPIO30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const unsigned pins_pci_gnt2[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const unsigned pins_pci_gnt3[] = {GPIO19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const unsigned pins_pci_gnt4[] = {GPIO38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const unsigned pins_pci_req1[] = {GPIO29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const unsigned pins_pci_req2[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const unsigned pins_pci_req3[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const unsigned pins_pci_req4[] = {GPIO37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static const struct ltq_pin_group xway_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) GRP_MUX("exin0", EXIN, pins_exin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) GRP_MUX("exin1", EXIN, pins_exin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) GRP_MUX("exin2", EXIN, pins_exin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) GRP_MUX("jtag", JTAG, pins_jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) GRP_MUX("ebu a23", EBU, pins_ebu_a23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) GRP_MUX("ebu a24", EBU, pins_ebu_a24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) GRP_MUX("ebu a25", EBU, pins_ebu_a25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) GRP_MUX("ebu clk", EBU, pins_ebu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) GRP_MUX("ebu wait", EBU, pins_ebu_wait),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) GRP_MUX("nand ale", EBU, pins_nand_ale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) GRP_MUX("nand cs1", EBU, pins_nand_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) GRP_MUX("nand cle", EBU, pins_nand_cle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) GRP_MUX("spi", SPI, pins_spi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) GRP_MUX("asc0", ASC, pins_asc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) GRP_MUX("stp", STP, pins_stp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) GRP_MUX("nmi", NMI, pins_nmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) GRP_MUX("gpt1", GPT, pins_gpt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) GRP_MUX("gpt2", GPT, pins_gpt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) GRP_MUX("gpt3", GPT, pins_gpt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) GRP_MUX("clkout0", CGU, pins_clkout0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) GRP_MUX("clkout1", CGU, pins_clkout1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) GRP_MUX("clkout2", CGU, pins_clkout2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) GRP_MUX("clkout3", CGU, pins_clkout3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) GRP_MUX("gnt1", PCI, pins_pci_gnt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) GRP_MUX("gnt2", PCI, pins_pci_gnt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) GRP_MUX("gnt3", PCI, pins_pci_gnt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) GRP_MUX("req1", PCI, pins_pci_req1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) GRP_MUX("req2", PCI, pins_pci_req2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) GRP_MUX("req3", PCI, pins_pci_req3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* xrx only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GRP_MUX("nand rdy", EBU, pins_nand_rdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) GRP_MUX("nand rd", EBU, pins_nand_rd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) GRP_MUX("exin3", EXIN, pins_exin3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) GRP_MUX("exin4", EXIN, pins_exin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GRP_MUX("exin5", EXIN, pins_exin5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) GRP_MUX("gnt4", PCI, pins_pci_gnt4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) GRP_MUX("req4", PCI, pins_pci_gnt4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) GRP_MUX("mdio", MDIO, pins_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "gnt3", "req1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "req2", "req3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "spi_cs2", "spi_cs3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "spi_cs4", "spi_cs5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "spi_cs6"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "clkout2", "clkout3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "ebu a25", "ebu cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "ebu wait", "ebu clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "nand ale", "nand cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "nand cle"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const char * const xway_jtag_grps[] = {"jtag"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const char * const xway_stp_grps[] = {"stp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const char * const xway_nmi_grps[] = {"nmi"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* ar9/vr9/gr9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const char * const xrx_mdio_grps[] = {"mdio"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "gphy0 led2", "gphy1 led0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "gphy1 led1", "gphy1 led2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "ebu a25", "ebu cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "ebu wait", "ebu clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "nand ale", "nand cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "nand cle", "nand rdy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "nand rd"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "exin3", "exin4", "exin5"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "gnt3", "gnt4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "req1", "req2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "req3", "req4"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct ltq_pmx_func xrx_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {"exin", ARRAY_AND_SIZE(xrx_exin_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* --------- ase related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define ASE_MAX_PIN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static const struct ltq_mfp_pin ase_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MFP_XWAY(GPIO21, GPIO, EBU, MII, EBU2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MFP_XWAY(GPIO24, GPIO, EBU, EBU2, MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MFP_XWAY(GPIO27, GPIO, EBU, NONE, MDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const unsigned ase_exin_pin_map[] = {GPIO6, GPIO29, GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static const unsigned ase_pins_exin0[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static const unsigned ase_pins_exin1[] = {GPIO29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const unsigned ase_pins_exin2[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const unsigned ase_pins_mdio[] = {GPIO24, GPIO27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const unsigned ase_pins_ephy_led0[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const unsigned ase_pins_ephy_led1[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static const unsigned ase_pins_ephy_led2[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const unsigned ase_pins_dfe_led0[] = {GPIO1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const unsigned ase_pins_dfe_led1[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10}; /* DEPRECATED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const unsigned ase_pins_spi_di[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const unsigned ase_pins_spi_do[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static const unsigned ase_pins_spi_clk[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static const unsigned ase_pins_spi_cs1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const unsigned ase_pins_spi_cs2[] = {GPIO15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const unsigned ase_pins_spi_cs3[] = {GPIO14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static const unsigned ase_pins_gpt1[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) static const unsigned ase_pins_gpt2[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const unsigned ase_pins_gpt3[] = {GPIO25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const unsigned ase_pins_clkout0[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static const unsigned ase_pins_clkout1[] = {GPIO22};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static const unsigned ase_pins_clkout2[] = {GPIO14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static const struct ltq_pin_group ase_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) GRP_MUX("exin0", EXIN, ase_pins_exin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) GRP_MUX("exin1", EXIN, ase_pins_exin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) GRP_MUX("exin2", EXIN, ase_pins_exin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) GRP_MUX("jtag", JTAG, ase_pins_jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) GRP_MUX("spi", SPI, ase_pins_spi), /* DEPRECATED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) GRP_MUX("spi_di", SPI, ase_pins_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) GRP_MUX("spi_do", SPI, ase_pins_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) GRP_MUX("spi_clk", SPI, ase_pins_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) GRP_MUX("asc", ASC, ase_pins_asc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) GRP_MUX("stp", STP, ase_pins_stp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) GRP_MUX("gpt1", GPT, ase_pins_gpt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) GRP_MUX("gpt2", GPT, ase_pins_gpt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) GRP_MUX("gpt3", GPT, ase_pins_gpt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) GRP_MUX("clkout0", CGU, ase_pins_clkout0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) GRP_MUX("clkout1", CGU, ase_pins_clkout1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) GRP_MUX("clkout2", CGU, ase_pins_clkout2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) GRP_MUX("mdio", MDIO, ase_pins_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) GRP_MUX("dfe led0", DFE, ase_pins_dfe_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) GRP_MUX("dfe led1", DFE, ase_pins_dfe_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) GRP_MUX("ephy led0", EPHY, ase_pins_ephy_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) GRP_MUX("ephy led1", EPHY, ase_pins_ephy_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) GRP_MUX("ephy led2", EPHY, ase_pins_ephy_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static const char * const ase_cgu_grps[] = {"clkout0", "clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "clkout2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static const char * const ase_mdio_grps[] = {"mdio"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const char * const ase_dfe_grps[] = {"dfe led0", "dfe led1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const char * const ase_ephy_grps[] = {"ephy led0", "ephy led1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "ephy led2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const char * const ase_asc_grps[] = {"asc"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const char * const ase_jtag_grps[] = {"jtag"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static const char * const ase_stp_grps[] = {"stp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const char * const ase_spi_grps[] = {"spi", /* DEPRECATED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) "spi_di", "spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) "spi_clk", "spi_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) "spi_cs2", "spi_cs3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct ltq_pmx_func ase_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {"cgu", ARRAY_AND_SIZE(ase_cgu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {"mdio", ARRAY_AND_SIZE(ase_mdio_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* --------- danube related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define DANUBE_MAX_PIN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static const struct ltq_mfp_pin danube_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MFP_XWAY(GPIO2, GPIO, CGU, EXIN, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MFP_XWAY(GPIO5, GPIO, STP, MII, DFE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) MFP_XWAY(GPIO7, GPIO, CGU, CBUS, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) MFP_XWAY(GPIO8, GPIO, CGU, NMI, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) MFP_XWAY(GPIO9, GPIO, ASC, SPI, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) MFP_XWAY(GPIO10, GPIO, ASC, SPI, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) MFP_XWAY(GPIO13, GPIO, EBU, SPI, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) MFP_XWAY(GPIO14, GPIO, CGU, CBUS, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) MFP_XWAY(GPIO15, GPIO, SPI, SDIO, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) MFP_XWAY(GPIO16, GPIO, SPI, SDIO, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) MFP_XWAY(GPIO17, GPIO, SPI, SDIO, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MFP_XWAY(GPIO18, GPIO, SPI, SDIO, JTAG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MFP_XWAY(GPIO19, GPIO, PCI, SDIO, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MFP_XWAY(GPIO20, GPIO, JTAG, SDIO, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) MFP_XWAY(GPIO22, GPIO, SPI, MCD, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) MFP_XWAY(GPIO28, GPIO, GPT, MII, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) MFP_XWAY(GPIO29, GPIO, PCI, CBUS, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MFP_XWAY(GPIO30, GPIO, PCI, CBUS, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MFP_XWAY(GPIO31, GPIO, EBU, PCI, MII),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const unsigned danube_exin_pin_map[] = {GPIO0, GPIO1, GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const unsigned danube_pins_exin0[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const unsigned danube_pins_exin1[] = {GPIO1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static const unsigned danube_pins_exin2[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static const unsigned danube_pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO18, GPIO20};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static const unsigned danube_pins_asc0[] = {GPIO11, GPIO12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static const unsigned danube_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static const unsigned danube_pins_stp[] = {GPIO4, GPIO5, GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static const unsigned danube_pins_nmi[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const unsigned danube_pins_dfe_led0[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const unsigned danube_pins_dfe_led1[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const unsigned danube_pins_ebu_a24[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static const unsigned danube_pins_ebu_clk[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const unsigned danube_pins_ebu_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) static const unsigned danube_pins_ebu_a23[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static const unsigned danube_pins_ebu_wait[] = {GPIO26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const unsigned danube_pins_ebu_a25[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const unsigned danube_pins_nand_ale[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const unsigned danube_pins_nand_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const unsigned danube_pins_nand_cle[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const unsigned danube_pins_spi[] = {GPIO16, GPIO17, GPIO18}; /* DEPRECATED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const unsigned danube_pins_spi_di[] = {GPIO16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static const unsigned danube_pins_spi_do[] = {GPIO17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const unsigned danube_pins_spi_clk[] = {GPIO18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const unsigned danube_pins_spi_cs1[] = {GPIO15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const unsigned danube_pins_spi_cs2[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const unsigned danube_pins_spi_cs3[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const unsigned danube_pins_spi_cs4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) static const unsigned danube_pins_spi_cs5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const unsigned danube_pins_spi_cs6[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const unsigned danube_pins_gpt1[] = {GPIO28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const unsigned danube_pins_gpt2[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const unsigned danube_pins_gpt3[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static const unsigned danube_pins_clkout0[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static const unsigned danube_pins_clkout1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static const unsigned danube_pins_clkout2[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static const unsigned danube_pins_clkout3[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const unsigned danube_pins_pci_gnt1[] = {GPIO30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const unsigned danube_pins_pci_gnt2[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const unsigned danube_pins_pci_gnt3[] = {GPIO19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const unsigned danube_pins_pci_req1[] = {GPIO29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const unsigned danube_pins_pci_req2[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const unsigned danube_pins_pci_req3[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct ltq_pin_group danube_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) GRP_MUX("exin0", EXIN, danube_pins_exin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) GRP_MUX("exin1", EXIN, danube_pins_exin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) GRP_MUX("exin2", EXIN, danube_pins_exin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) GRP_MUX("jtag", JTAG, danube_pins_jtag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) GRP_MUX("ebu a23", EBU, danube_pins_ebu_a23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) GRP_MUX("ebu a24", EBU, danube_pins_ebu_a24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) GRP_MUX("ebu a25", EBU, danube_pins_ebu_a25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) GRP_MUX("ebu clk", EBU, danube_pins_ebu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) GRP_MUX("ebu cs1", EBU, danube_pins_ebu_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) GRP_MUX("ebu wait", EBU, danube_pins_ebu_wait),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) GRP_MUX("nand ale", EBU, danube_pins_nand_ale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) GRP_MUX("nand cs1", EBU, danube_pins_nand_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) GRP_MUX("nand cle", EBU, danube_pins_nand_cle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) GRP_MUX("spi", SPI, danube_pins_spi), /* DEPRECATED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) GRP_MUX("spi_di", SPI, danube_pins_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) GRP_MUX("spi_do", SPI, danube_pins_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) GRP_MUX("spi_clk", SPI, danube_pins_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) GRP_MUX("spi_cs1", SPI, danube_pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) GRP_MUX("spi_cs2", SPI, danube_pins_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) GRP_MUX("spi_cs3", SPI, danube_pins_spi_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) GRP_MUX("spi_cs4", SPI, danube_pins_spi_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) GRP_MUX("spi_cs5", SPI, danube_pins_spi_cs5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) GRP_MUX("spi_cs6", SPI, danube_pins_spi_cs6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) GRP_MUX("asc0", ASC, danube_pins_asc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) GRP_MUX("asc0 cts rts", ASC, danube_pins_asc0_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) GRP_MUX("stp", STP, danube_pins_stp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) GRP_MUX("nmi", NMI, danube_pins_nmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) GRP_MUX("gpt1", GPT, danube_pins_gpt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) GRP_MUX("gpt2", GPT, danube_pins_gpt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) GRP_MUX("gpt3", GPT, danube_pins_gpt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) GRP_MUX("clkout0", CGU, danube_pins_clkout0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) GRP_MUX("clkout1", CGU, danube_pins_clkout1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) GRP_MUX("clkout2", CGU, danube_pins_clkout2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) GRP_MUX("clkout3", CGU, danube_pins_clkout3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) GRP_MUX("gnt1", PCI, danube_pins_pci_gnt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) GRP_MUX("gnt2", PCI, danube_pins_pci_gnt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) GRP_MUX("gnt3", PCI, danube_pins_pci_gnt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) GRP_MUX("req1", PCI, danube_pins_pci_req1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) GRP_MUX("req2", PCI, danube_pins_pci_req2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) GRP_MUX("req3", PCI, danube_pins_pci_req3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) GRP_MUX("dfe led0", DFE, danube_pins_dfe_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) GRP_MUX("dfe led1", DFE, danube_pins_dfe_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static const char * const danube_pci_grps[] = {"gnt1", "gnt2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) "gnt3", "req1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) "req2", "req3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static const char * const danube_spi_grps[] = {"spi", /* DEPRECATED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) "spi_di", "spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "spi_clk", "spi_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "spi_cs2", "spi_cs3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) "spi_cs4", "spi_cs5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) "spi_cs6"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char * const danube_cgu_grps[] = {"clkout0", "clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "clkout2", "clkout3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static const char * const danube_ebu_grps[] = {"ebu a23", "ebu a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "ebu a25", "ebu cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "ebu wait", "ebu clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "nand ale", "nand cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "nand cle"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const char * const danube_dfe_grps[] = {"dfe led0", "dfe led1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const char * const danube_exin_grps[] = {"exin0", "exin1", "exin2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static const char * const danube_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static const char * const danube_asc_grps[] = {"asc0", "asc0 cts rts"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const char * const danube_jtag_grps[] = {"jtag"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const char * const danube_stp_grps[] = {"stp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static const char * const danube_nmi_grps[] = {"nmi"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct ltq_pmx_func danube_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {"spi", ARRAY_AND_SIZE(danube_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {"asc", ARRAY_AND_SIZE(danube_asc_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {"cgu", ARRAY_AND_SIZE(danube_cgu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {"jtag", ARRAY_AND_SIZE(danube_jtag_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {"exin", ARRAY_AND_SIZE(danube_exin_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {"stp", ARRAY_AND_SIZE(danube_stp_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {"gpt", ARRAY_AND_SIZE(danube_gpt_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {"nmi", ARRAY_AND_SIZE(danube_nmi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {"pci", ARRAY_AND_SIZE(danube_pci_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {"ebu", ARRAY_AND_SIZE(danube_ebu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {"dfe", ARRAY_AND_SIZE(danube_dfe_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* --------- xrx100 related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define XRX100_MAX_PIN 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const struct ltq_mfp_pin xrx100_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) MFP_XWAY(GPIO4, GPIO, STP, DFE, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) MFP_XWAY(GPIO5, GPIO, STP, NONE, DFE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) MFP_XWAY(GPIO7, GPIO, CGU, CBUS, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) MFP_XWAY(GPIO10, GPIO, ASC, SPI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MFP_XWAY(GPIO11, GPIO, ASC, CBUS, SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MFP_XWAY(GPIO12, GPIO, ASC, CBUS, MCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MFP_XWAY(GPIO14, GPIO, CGU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) MFP_XWAY(GPIO22, GPIO, SPI, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) MFP_XWAY(GPIO25, GPIO, TDM, SDIO, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MFP_XWAY(GPIO27, GPIO, TDM, SDIO, ASC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) MFP_XWAY(GPIO28, GPIO, GPT, NONE, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) MFP_XWAY(GPIO29, GPIO, PCI, CBUS, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) MFP_XWAY(GPIO36, GPIO, SIN, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) MFP_XWAY(GPIO39, GPIO, NONE, EXIN, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) MFP_XWAY(GPIO44, GPIO, MII, SIN, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MFP_XWAY(GPIO45, GPIO, MII, NONE, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) MFP_XWAY(GPIO47, GPIO, MII, NONE, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static const unsigned xrx100_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static const unsigned xrx100_pins_exin0[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static const unsigned xrx100_pins_exin1[] = {GPIO1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const unsigned xrx100_pins_exin2[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static const unsigned xrx100_pins_exin3[] = {GPIO39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static const unsigned xrx100_pins_exin4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const unsigned xrx100_pins_exin5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static const unsigned xrx100_pins_asc0[] = {GPIO11, GPIO12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static const unsigned xrx100_pins_asc0_cts_rts[] = {GPIO9, GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static const unsigned xrx100_pins_stp[] = {GPIO4, GPIO5, GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) static const unsigned xrx100_pins_nmi[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static const unsigned xrx100_pins_mdio[] = {GPIO42, GPIO43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static const unsigned xrx100_pins_dfe_led0[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) static const unsigned xrx100_pins_dfe_led1[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const unsigned xrx100_pins_ebu_a24[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static const unsigned xrx100_pins_ebu_clk[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static const unsigned xrx100_pins_ebu_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static const unsigned xrx100_pins_ebu_a23[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static const unsigned xrx100_pins_ebu_wait[] = {GPIO26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned xrx100_pins_ebu_a25[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const unsigned xrx100_pins_nand_ale[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const unsigned xrx100_pins_nand_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const unsigned xrx100_pins_nand_cle[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const unsigned xrx100_pins_nand_rdy[] = {GPIO48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static const unsigned xrx100_pins_nand_rd[] = {GPIO49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const unsigned xrx100_pins_spi_di[] = {GPIO16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static const unsigned xrx100_pins_spi_do[] = {GPIO17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static const unsigned xrx100_pins_spi_clk[] = {GPIO18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static const unsigned xrx100_pins_spi_cs1[] = {GPIO15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const unsigned xrx100_pins_spi_cs2[] = {GPIO22};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static const unsigned xrx100_pins_spi_cs3[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static const unsigned xrx100_pins_spi_cs4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static const unsigned xrx100_pins_spi_cs5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const unsigned xrx100_pins_spi_cs6[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static const unsigned xrx100_pins_gpt1[] = {GPIO28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static const unsigned xrx100_pins_gpt2[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static const unsigned xrx100_pins_gpt3[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static const unsigned xrx100_pins_clkout0[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const unsigned xrx100_pins_clkout1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static const unsigned xrx100_pins_clkout2[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static const unsigned xrx100_pins_clkout3[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static const unsigned xrx100_pins_pci_gnt1[] = {GPIO30};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static const unsigned xrx100_pins_pci_gnt2[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static const unsigned xrx100_pins_pci_gnt3[] = {GPIO19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static const unsigned xrx100_pins_pci_gnt4[] = {GPIO38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const unsigned xrx100_pins_pci_req1[] = {GPIO29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static const unsigned xrx100_pins_pci_req2[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const unsigned xrx100_pins_pci_req3[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static const unsigned xrx100_pins_pci_req4[] = {GPIO37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct ltq_pin_group xrx100_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) GRP_MUX("exin0", EXIN, xrx100_pins_exin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) GRP_MUX("exin1", EXIN, xrx100_pins_exin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) GRP_MUX("exin2", EXIN, xrx100_pins_exin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) GRP_MUX("exin3", EXIN, xrx100_pins_exin3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) GRP_MUX("exin4", EXIN, xrx100_pins_exin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) GRP_MUX("exin5", EXIN, xrx100_pins_exin5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) GRP_MUX("ebu a23", EBU, xrx100_pins_ebu_a23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) GRP_MUX("ebu a24", EBU, xrx100_pins_ebu_a24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GRP_MUX("ebu a25", EBU, xrx100_pins_ebu_a25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) GRP_MUX("ebu clk", EBU, xrx100_pins_ebu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) GRP_MUX("ebu cs1", EBU, xrx100_pins_ebu_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) GRP_MUX("ebu wait", EBU, xrx100_pins_ebu_wait),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) GRP_MUX("nand ale", EBU, xrx100_pins_nand_ale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) GRP_MUX("nand cs1", EBU, xrx100_pins_nand_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) GRP_MUX("nand cle", EBU, xrx100_pins_nand_cle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) GRP_MUX("nand rdy", EBU, xrx100_pins_nand_rdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) GRP_MUX("nand rd", EBU, xrx100_pins_nand_rd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) GRP_MUX("spi_di", SPI, xrx100_pins_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) GRP_MUX("spi_do", SPI, xrx100_pins_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) GRP_MUX("spi_clk", SPI, xrx100_pins_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) GRP_MUX("spi_cs1", SPI, xrx100_pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) GRP_MUX("spi_cs2", SPI, xrx100_pins_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) GRP_MUX("spi_cs3", SPI, xrx100_pins_spi_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) GRP_MUX("spi_cs4", SPI, xrx100_pins_spi_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) GRP_MUX("spi_cs5", SPI, xrx100_pins_spi_cs5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) GRP_MUX("spi_cs6", SPI, xrx100_pins_spi_cs6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) GRP_MUX("asc0", ASC, xrx100_pins_asc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) GRP_MUX("asc0 cts rts", ASC, xrx100_pins_asc0_cts_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) GRP_MUX("stp", STP, xrx100_pins_stp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) GRP_MUX("nmi", NMI, xrx100_pins_nmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) GRP_MUX("gpt1", GPT, xrx100_pins_gpt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) GRP_MUX("gpt2", GPT, xrx100_pins_gpt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) GRP_MUX("gpt3", GPT, xrx100_pins_gpt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) GRP_MUX("clkout0", CGU, xrx100_pins_clkout0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) GRP_MUX("clkout1", CGU, xrx100_pins_clkout1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) GRP_MUX("clkout2", CGU, xrx100_pins_clkout2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) GRP_MUX("clkout3", CGU, xrx100_pins_clkout3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) GRP_MUX("gnt1", PCI, xrx100_pins_pci_gnt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) GRP_MUX("gnt2", PCI, xrx100_pins_pci_gnt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) GRP_MUX("gnt3", PCI, xrx100_pins_pci_gnt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) GRP_MUX("gnt4", PCI, xrx100_pins_pci_gnt4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) GRP_MUX("req1", PCI, xrx100_pins_pci_req1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) GRP_MUX("req2", PCI, xrx100_pins_pci_req2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) GRP_MUX("req3", PCI, xrx100_pins_pci_req3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) GRP_MUX("req4", PCI, xrx100_pins_pci_req4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) GRP_MUX("mdio", MDIO, xrx100_pins_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) GRP_MUX("dfe led0", DFE, xrx100_pins_dfe_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) GRP_MUX("dfe led1", DFE, xrx100_pins_dfe_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static const char * const xrx100_pci_grps[] = {"gnt1", "gnt2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "gnt3", "gnt4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "req1", "req2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "req3", "req4"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static const char * const xrx100_spi_grps[] = {"spi_di", "spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "spi_clk", "spi_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "spi_cs2", "spi_cs3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "spi_cs4", "spi_cs5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "spi_cs6"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) static const char * const xrx100_cgu_grps[] = {"clkout0", "clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "clkout2", "clkout3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static const char * const xrx100_ebu_grps[] = {"ebu a23", "ebu a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "ebu a25", "ebu cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "ebu wait", "ebu clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) "nand ale", "nand cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "nand cle", "nand rdy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "nand rd"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static const char * const xrx100_exin_grps[] = {"exin0", "exin1", "exin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "exin3", "exin4", "exin5"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static const char * const xrx100_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) static const char * const xrx100_asc_grps[] = {"asc0", "asc0 cts rts"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const char * const xrx100_stp_grps[] = {"stp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static const char * const xrx100_nmi_grps[] = {"nmi"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static const char * const xrx100_mdio_grps[] = {"mdio"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static const char * const xrx100_dfe_grps[] = {"dfe led0", "dfe led1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct ltq_pmx_func xrx100_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {"spi", ARRAY_AND_SIZE(xrx100_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {"asc", ARRAY_AND_SIZE(xrx100_asc_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {"cgu", ARRAY_AND_SIZE(xrx100_cgu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {"exin", ARRAY_AND_SIZE(xrx100_exin_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {"stp", ARRAY_AND_SIZE(xrx100_stp_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {"gpt", ARRAY_AND_SIZE(xrx100_gpt_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {"nmi", ARRAY_AND_SIZE(xrx100_nmi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {"pci", ARRAY_AND_SIZE(xrx100_pci_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {"ebu", ARRAY_AND_SIZE(xrx100_ebu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {"mdio", ARRAY_AND_SIZE(xrx100_mdio_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {"dfe", ARRAY_AND_SIZE(xrx100_dfe_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) /* --------- xrx200 related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define XRX200_MAX_PIN 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static const struct ltq_mfp_pin xrx200_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) MFP_XWAY(GPIO0, GPIO, EXIN, SDIO, TDM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) MFP_XWAY(GPIO1, GPIO, EXIN, CBUS, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) MFP_XWAY(GPIO3, GPIO, CGU, SDIO, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) MFP_XWAY(GPIO4, GPIO, STP, DFE, USIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) MFP_XWAY(GPIO5, GPIO, STP, GPHY, DFE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) MFP_XWAY(GPIO6, GPIO, STP, GPT, USIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) MFP_XWAY(GPIO7, GPIO, CGU, CBUS, GPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) MFP_XWAY(GPIO9, GPIO, USIF, SPI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) MFP_XWAY(GPIO11, GPIO, USIF, CBUS, SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) MFP_XWAY(GPIO12, GPIO, USIF, CBUS, MCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) MFP_XWAY(GPIO14, GPIO, CGU, CBUS, USIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) MFP_XWAY(GPIO15, GPIO, SPI, SDIO, MCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) MFP_XWAY(GPIO16, GPIO, SPI, SDIO, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) MFP_XWAY(GPIO17, GPIO, SPI, SDIO, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) MFP_XWAY(GPIO18, GPIO, SPI, SDIO, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) MFP_XWAY(GPIO19, GPIO, PCI, SDIO, CGU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) MFP_XWAY(GPIO20, GPIO, NONE, SDIO, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) MFP_XWAY(GPIO22, GPIO, SPI, CGU, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MFP_XWAY(GPIO25, GPIO, TDM, SDIO, USIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MFP_XWAY(GPIO26, GPIO, EBU, TDM, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) MFP_XWAY(GPIO27, GPIO, TDM, SDIO, USIF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MFP_XWAY(GPIO28, GPIO, GPT, PCI, SDIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) MFP_XWAY(GPIO29, GPIO, PCI, CBUS, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) MFP_XWAY(GPIO30, GPIO, PCI, CBUS, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) MFP_XWAY(GPIO32, GPIO, MII, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MFP_XWAY(GPIO33, GPIO, MII, NONE, EBU),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) MFP_XWAY(GPIO34, GPIO, SIN, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) MFP_XWAY(GPIO35, GPIO, SIN, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) MFP_XWAY(GPIO36, GPIO, SIN, SSI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) MFP_XWAY(GPIO37, GPIO, USIF, NONE, PCI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) MFP_XWAY(GPIO38, GPIO, PCI, USIF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MFP_XWAY(GPIO39, GPIO, USIF, EXIN, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MFP_XWAY(GPIO40, GPIO, MII, TDM, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MFP_XWAY(GPIO41, GPIO, MII, TDM, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) MFP_XWAY(GPIO44, GPIO, MII, SIN, GPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) MFP_XWAY(GPIO45, GPIO, MII, GPHY, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MFP_XWAY(GPIO46, GPIO, MII, NONE, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MFP_XWAY(GPIO47, GPIO, MII, GPHY, SIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const unsigned xrx200_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO10, GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static const unsigned xrx200_pins_exin0[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static const unsigned xrx200_pins_exin1[] = {GPIO1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const unsigned xrx200_pins_exin2[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static const unsigned xrx200_pins_exin3[] = {GPIO39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static const unsigned xrx200_pins_exin4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static const unsigned xrx200_pins_exin5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static const unsigned xrx200_pins_usif_uart_rx[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static const unsigned xrx200_pins_usif_uart_tx[] = {GPIO12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) static const unsigned xrx200_pins_usif_uart_rts[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static const unsigned xrx200_pins_usif_uart_cts[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static const unsigned xrx200_pins_usif_uart_dtr[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static const unsigned xrx200_pins_usif_uart_dsr[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static const unsigned xrx200_pins_usif_uart_dcd[] = {GPIO25};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static const unsigned xrx200_pins_usif_uart_ri[] = {GPIO27};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const unsigned xrx200_pins_usif_spi_di[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static const unsigned xrx200_pins_usif_spi_do[] = {GPIO12};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static const unsigned xrx200_pins_usif_spi_clk[] = {GPIO38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static const unsigned xrx200_pins_usif_spi_cs0[] = {GPIO37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static const unsigned xrx200_pins_usif_spi_cs1[] = {GPIO39};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const unsigned xrx200_pins_usif_spi_cs2[] = {GPIO14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const unsigned xrx200_pins_stp[] = {GPIO4, GPIO5, GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static const unsigned xrx200_pins_nmi[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static const unsigned xrx200_pins_mdio[] = {GPIO42, GPIO43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const unsigned xrx200_pins_dfe_led0[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static const unsigned xrx200_pins_dfe_led1[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static const unsigned xrx200_pins_gphy0_led0[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const unsigned xrx200_pins_gphy0_led1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const unsigned xrx200_pins_gphy0_led2[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static const unsigned xrx200_pins_gphy1_led0[] = {GPIO44};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static const unsigned xrx200_pins_gphy1_led1[] = {GPIO45};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const unsigned xrx200_pins_gphy1_led2[] = {GPIO47};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const unsigned xrx200_pins_ebu_a24[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static const unsigned xrx200_pins_ebu_clk[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static const unsigned xrx200_pins_ebu_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const unsigned xrx200_pins_ebu_a23[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const unsigned xrx200_pins_ebu_wait[] = {GPIO26};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const unsigned xrx200_pins_ebu_a25[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static const unsigned xrx200_pins_nand_ale[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const unsigned xrx200_pins_nand_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const unsigned xrx200_pins_nand_cle[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) static const unsigned xrx200_pins_nand_rdy[] = {GPIO48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static const unsigned xrx200_pins_nand_rd[] = {GPIO49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const unsigned xrx200_pins_spi_di[] = {GPIO16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const unsigned xrx200_pins_spi_do[] = {GPIO17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) static const unsigned xrx200_pins_spi_clk[] = {GPIO18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static const unsigned xrx200_pins_spi_cs1[] = {GPIO15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const unsigned xrx200_pins_spi_cs2[] = {GPIO22};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const unsigned xrx200_pins_spi_cs3[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const unsigned xrx200_pins_spi_cs4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static const unsigned xrx200_pins_spi_cs5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const unsigned xrx200_pins_spi_cs6[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static const unsigned xrx200_pins_gpt1[] = {GPIO28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static const unsigned xrx200_pins_gpt2[] = {GPIO21};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const unsigned xrx200_pins_gpt3[] = {GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const unsigned xrx200_pins_clkout0[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static const unsigned xrx200_pins_clkout1[] = {GPIO7};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const unsigned xrx200_pins_clkout2[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static const unsigned xrx200_pins_clkout3[] = {GPIO2};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const unsigned xrx200_pins_pci_gnt1[] = {GPIO28};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const unsigned xrx200_pins_pci_gnt2[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) static const unsigned xrx200_pins_pci_gnt3[] = {GPIO19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const unsigned xrx200_pins_pci_gnt4[] = {GPIO38};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const unsigned xrx200_pins_pci_req1[] = {GPIO29};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static const unsigned xrx200_pins_pci_req2[] = {GPIO31};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static const unsigned xrx200_pins_pci_req3[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static const unsigned xrx200_pins_pci_req4[] = {GPIO37};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static const struct ltq_pin_group xrx200_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GRP_MUX("exin0", EXIN, xrx200_pins_exin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) GRP_MUX("exin1", EXIN, xrx200_pins_exin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GRP_MUX("exin2", EXIN, xrx200_pins_exin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GRP_MUX("exin3", EXIN, xrx200_pins_exin3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GRP_MUX("exin4", EXIN, xrx200_pins_exin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GRP_MUX("exin5", EXIN, xrx200_pins_exin5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GRP_MUX("ebu a23", EBU, xrx200_pins_ebu_a23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GRP_MUX("ebu a24", EBU, xrx200_pins_ebu_a24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GRP_MUX("ebu a25", EBU, xrx200_pins_ebu_a25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GRP_MUX("ebu clk", EBU, xrx200_pins_ebu_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GRP_MUX("ebu cs1", EBU, xrx200_pins_ebu_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GRP_MUX("ebu wait", EBU, xrx200_pins_ebu_wait),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GRP_MUX("nand ale", EBU, xrx200_pins_nand_ale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GRP_MUX("nand cs1", EBU, xrx200_pins_nand_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GRP_MUX("nand cle", EBU, xrx200_pins_nand_cle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GRP_MUX("nand rdy", EBU, xrx200_pins_nand_rdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GRP_MUX("nand rd", EBU, xrx200_pins_nand_rd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GRP_MUX("spi_di", SPI, xrx200_pins_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GRP_MUX("spi_do", SPI, xrx200_pins_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GRP_MUX("spi_clk", SPI, xrx200_pins_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) GRP_MUX("spi_cs1", SPI, xrx200_pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GRP_MUX("spi_cs2", SPI, xrx200_pins_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GRP_MUX("spi_cs3", SPI, xrx200_pins_spi_cs3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GRP_MUX("spi_cs4", SPI, xrx200_pins_spi_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GRP_MUX("spi_cs5", SPI, xrx200_pins_spi_cs5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GRP_MUX("spi_cs6", SPI, xrx200_pins_spi_cs6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GRP_MUX("usif uart_rx", USIF, xrx200_pins_usif_uart_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GRP_MUX("usif uart_tx", USIF, xrx200_pins_usif_uart_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GRP_MUX("usif uart_rts", USIF, xrx200_pins_usif_uart_rts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GRP_MUX("usif uart_cts", USIF, xrx200_pins_usif_uart_cts),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) GRP_MUX("usif uart_dtr", USIF, xrx200_pins_usif_uart_dtr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GRP_MUX("usif uart_dsr", USIF, xrx200_pins_usif_uart_dsr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GRP_MUX("usif uart_dcd", USIF, xrx200_pins_usif_uart_dcd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GRP_MUX("usif uart_ri", USIF, xrx200_pins_usif_uart_ri),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GRP_MUX("usif spi_di", USIF, xrx200_pins_usif_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GRP_MUX("usif spi_do", USIF, xrx200_pins_usif_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GRP_MUX("usif spi_clk", USIF, xrx200_pins_usif_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GRP_MUX("usif spi_cs0", USIF, xrx200_pins_usif_spi_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GRP_MUX("usif spi_cs1", USIF, xrx200_pins_usif_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GRP_MUX("usif spi_cs2", USIF, xrx200_pins_usif_spi_cs2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GRP_MUX("stp", STP, xrx200_pins_stp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GRP_MUX("nmi", NMI, xrx200_pins_nmi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) GRP_MUX("gpt1", GPT, xrx200_pins_gpt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GRP_MUX("gpt2", GPT, xrx200_pins_gpt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) GRP_MUX("gpt3", GPT, xrx200_pins_gpt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) GRP_MUX("clkout0", CGU, xrx200_pins_clkout0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) GRP_MUX("clkout1", CGU, xrx200_pins_clkout1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) GRP_MUX("clkout2", CGU, xrx200_pins_clkout2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) GRP_MUX("clkout3", CGU, xrx200_pins_clkout3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) GRP_MUX("gnt1", PCI, xrx200_pins_pci_gnt1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) GRP_MUX("gnt2", PCI, xrx200_pins_pci_gnt2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) GRP_MUX("gnt3", PCI, xrx200_pins_pci_gnt3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) GRP_MUX("gnt4", PCI, xrx200_pins_pci_gnt4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) GRP_MUX("req1", PCI, xrx200_pins_pci_req1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) GRP_MUX("req2", PCI, xrx200_pins_pci_req2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) GRP_MUX("req3", PCI, xrx200_pins_pci_req3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) GRP_MUX("req4", PCI, xrx200_pins_pci_req4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) GRP_MUX("mdio", MDIO, xrx200_pins_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) GRP_MUX("dfe led0", DFE, xrx200_pins_dfe_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) GRP_MUX("dfe led1", DFE, xrx200_pins_dfe_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) GRP_MUX("gphy0 led0", GPHY, xrx200_pins_gphy0_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) GRP_MUX("gphy0 led1", GPHY, xrx200_pins_gphy0_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) GRP_MUX("gphy0 led2", GPHY, xrx200_pins_gphy0_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) GRP_MUX("gphy1 led0", GPHY, xrx200_pins_gphy1_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) GRP_MUX("gphy1 led1", GPHY, xrx200_pins_gphy1_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) GRP_MUX("gphy1 led2", GPHY, xrx200_pins_gphy1_led2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const char * const xrx200_pci_grps[] = {"gnt1", "gnt2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "gnt3", "gnt4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "req1", "req2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "req3", "req4"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) static const char * const xrx200_spi_grps[] = {"spi_di", "spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "spi_clk", "spi_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "spi_cs2", "spi_cs3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "spi_cs4", "spi_cs5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "spi_cs6"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static const char * const xrx200_cgu_grps[] = {"clkout0", "clkout1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "clkout2", "clkout3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) static const char * const xrx200_ebu_grps[] = {"ebu a23", "ebu a24",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "ebu a25", "ebu cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "ebu wait", "ebu clk",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "nand ale", "nand cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "nand cle", "nand rdy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "nand rd"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static const char * const xrx200_exin_grps[] = {"exin0", "exin1", "exin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) "exin3", "exin4", "exin5"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const char * const xrx200_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static const char * const xrx200_usif_grps[] = {"usif uart_rx", "usif uart_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "usif uart_rts", "usif uart_cts",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "usif uart_dtr", "usif uart_dsr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "usif uart_dcd", "usif uart_ri",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "usif spi_di", "usif spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "usif spi_clk", "usif spi_cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "usif spi_cs1", "usif spi_cs2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static const char * const xrx200_stp_grps[] = {"stp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const char * const xrx200_nmi_grps[] = {"nmi"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const char * const xrx200_mdio_grps[] = {"mdio"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const char * const xrx200_dfe_grps[] = {"dfe led0", "dfe led1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static const char * const xrx200_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "gphy0 led2", "gphy1 led0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "gphy1 led1", "gphy1 led2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct ltq_pmx_func xrx200_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {"spi", ARRAY_AND_SIZE(xrx200_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {"usif", ARRAY_AND_SIZE(xrx200_usif_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {"cgu", ARRAY_AND_SIZE(xrx200_cgu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {"exin", ARRAY_AND_SIZE(xrx200_exin_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {"stp", ARRAY_AND_SIZE(xrx200_stp_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {"gpt", ARRAY_AND_SIZE(xrx200_gpt_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {"nmi", ARRAY_AND_SIZE(xrx200_nmi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {"pci", ARRAY_AND_SIZE(xrx200_pci_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {"ebu", ARRAY_AND_SIZE(xrx200_ebu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {"mdio", ARRAY_AND_SIZE(xrx200_mdio_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {"dfe", ARRAY_AND_SIZE(xrx200_dfe_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {"gphy", ARRAY_AND_SIZE(xrx200_gphy_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) /* --------- xrx300 related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define XRX300_MAX_PIN 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const struct ltq_mfp_pin xrx300_mfp[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* pin f0 f1 f2 f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) MFP_XWAY(GPIO0, GPIO, EXIN, EPHY, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) MFP_XWAY(GPIO1, GPIO, NONE, EXIN, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) MFP_XWAY(GPIO2, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) MFP_XWAY(GPIO3, GPIO, CGU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) MFP_XWAY(GPIO4, GPIO, STP, DFE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) MFP_XWAY(GPIO5, GPIO, STP, EPHY, DFE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) MFP_XWAY(GPIO6, GPIO, STP, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) MFP_XWAY(GPIO7, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) MFP_XWAY(GPIO8, GPIO, CGU, GPHY, EPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) MFP_XWAY(GPIO9, GPIO, WIFI, NONE, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) MFP_XWAY(GPIO10, GPIO, USIF, SPI, EXIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MFP_XWAY(GPIO11, GPIO, USIF, WIFI, SPI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) MFP_XWAY(GPIO12, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) MFP_XWAY(GPIO13, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) MFP_XWAY(GPIO14, GPIO, CGU, USIF, EPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) MFP_XWAY(GPIO15, GPIO, SPI, NONE, MCD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) MFP_XWAY(GPIO16, GPIO, SPI, EXIN, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) MFP_XWAY(GPIO17, GPIO, SPI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) MFP_XWAY(GPIO18, GPIO, SPI, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) MFP_XWAY(GPIO19, GPIO, USIF, NONE, EPHY),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) MFP_XWAY(GPIO20, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) MFP_XWAY(GPIO21, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) MFP_XWAY(GPIO22, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) MFP_XWAY(GPIO23, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) MFP_XWAY(GPIO24, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) MFP_XWAY(GPIO25, GPIO, TDM, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) MFP_XWAY(GPIO26, GPIO, TDM, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) MFP_XWAY(GPIO27, GPIO, TDM, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) MFP_XWAY(GPIO28, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) MFP_XWAY(GPIO29, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) MFP_XWAY(GPIO30, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) MFP_XWAY(GPIO31, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) MFP_XWAY(GPIO32, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) MFP_XWAY(GPIO33, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) MFP_XWAY(GPIO34, GPIO, NONE, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) MFP_XWAY(GPIO35, GPIO, NONE, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) MFP_XWAY(GPIO36, GPIO, NONE, SSI, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) MFP_XWAY(GPIO37, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) MFP_XWAY(GPIO38, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) MFP_XWAY(GPIO39, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) MFP_XWAY(GPIO40, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) MFP_XWAY(GPIO41, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) MFP_XWAY(GPIO44, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) MFP_XWAY(GPIO45, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) MFP_XWAY(GPIO46, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) MFP_XWAY(GPIO47, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) MFP_XWAY(GPIO50, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) MFP_XWAY(GPIO51, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) MFP_XWAY(GPIO52, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) MFP_XWAY(GPIO53, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) MFP_XWAY(GPIO54, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) MFP_XWAY(GPIO55, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) MFP_XWAY(GPIO56, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) MFP_XWAY(GPIO57, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) MFP_XWAY(GPIO58, GPIO, EBU, TDM, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) MFP_XWAY(GPIO59, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) MFP_XWAY(GPIO60, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) MFP_XWAY(GPIO61, GPIO, EBU, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) MFP_XWAY(GPIO62, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) MFP_XWAY(GPIO63, NONE, NONE, NONE, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static const unsigned xrx300_exin_pin_map[] = {GPIO0, GPIO1, GPIO16, GPIO10, GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static const unsigned xrx300_pins_exin0[] = {GPIO0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) static const unsigned xrx300_pins_exin1[] = {GPIO1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static const unsigned xrx300_pins_exin2[] = {GPIO16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) /* EXIN3 is not available on xrX300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static const unsigned xrx300_pins_exin4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const unsigned xrx300_pins_exin5[] = {GPIO9};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const unsigned xrx300_pins_usif_uart_rx[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static const unsigned xrx300_pins_usif_uart_tx[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) static const unsigned xrx300_pins_usif_spi_di[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static const unsigned xrx300_pins_usif_spi_do[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const unsigned xrx300_pins_usif_spi_clk[] = {GPIO19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static const unsigned xrx300_pins_usif_spi_cs0[] = {GPIO14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static const unsigned xrx300_pins_stp[] = {GPIO4, GPIO5, GPIO6};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static const unsigned xrx300_pins_mdio[] = {GPIO42, GPIO43};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static const unsigned xrx300_pins_dfe_led0[] = {GPIO4};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static const unsigned xrx300_pins_dfe_led1[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static const unsigned xrx300_pins_ephy0_led0[] = {GPIO5};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) static const unsigned xrx300_pins_ephy0_led1[] = {GPIO8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static const unsigned xrx300_pins_ephy1_led0[] = {GPIO14};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const unsigned xrx300_pins_ephy1_led1[] = {GPIO19};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static const unsigned xrx300_pins_nand_ale[] = {GPIO13};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static const unsigned xrx300_pins_nand_cs1[] = {GPIO23};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static const unsigned xrx300_pins_nand_cle[] = {GPIO24};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static const unsigned xrx300_pins_nand_rdy[] = {GPIO48};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const unsigned xrx300_pins_nand_rd[] = {GPIO49};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static const unsigned xrx300_pins_nand_d1[] = {GPIO50};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static const unsigned xrx300_pins_nand_d0[] = {GPIO51};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static const unsigned xrx300_pins_nand_d2[] = {GPIO52};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static const unsigned xrx300_pins_nand_d7[] = {GPIO53};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static const unsigned xrx300_pins_nand_d6[] = {GPIO54};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static const unsigned xrx300_pins_nand_d5[] = {GPIO55};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static const unsigned xrx300_pins_nand_d4[] = {GPIO56};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static const unsigned xrx300_pins_nand_d3[] = {GPIO57};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static const unsigned xrx300_pins_nand_cs0[] = {GPIO58};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static const unsigned xrx300_pins_nand_wr[] = {GPIO59};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const unsigned xrx300_pins_nand_wp[] = {GPIO60};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static const unsigned xrx300_pins_nand_se[] = {GPIO61};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static const unsigned xrx300_pins_spi_di[] = {GPIO16};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static const unsigned xrx300_pins_spi_do[] = {GPIO17};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static const unsigned xrx300_pins_spi_clk[] = {GPIO18};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static const unsigned xrx300_pins_spi_cs1[] = {GPIO15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* SPI_CS2 is not available on xrX300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) /* SPI_CS3 is not available on xrX300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static const unsigned xrx300_pins_spi_cs4[] = {GPIO10};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* SPI_CS5 is not available on xrX300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static const unsigned xrx300_pins_spi_cs6[] = {GPIO11};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* CLKOUT0 is not available on xrX300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* CLKOUT1 is not available on xrX300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const unsigned xrx300_pins_clkout2[] = {GPIO3};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static const struct ltq_pin_group xrx300_grps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) GRP_MUX("exin0", EXIN, xrx300_pins_exin0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) GRP_MUX("exin1", EXIN, xrx300_pins_exin1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) GRP_MUX("exin2", EXIN, xrx300_pins_exin2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) GRP_MUX("exin4", EXIN, xrx300_pins_exin4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) GRP_MUX("exin5", EXIN, xrx300_pins_exin5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) GRP_MUX("nand ale", EBU, xrx300_pins_nand_ale),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) GRP_MUX("nand cs1", EBU, xrx300_pins_nand_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) GRP_MUX("nand cle", EBU, xrx300_pins_nand_cle),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) GRP_MUX("nand rdy", EBU, xrx300_pins_nand_rdy),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) GRP_MUX("nand rd", EBU, xrx300_pins_nand_rd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) GRP_MUX("nand d1", EBU, xrx300_pins_nand_d1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) GRP_MUX("nand d0", EBU, xrx300_pins_nand_d0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) GRP_MUX("nand d2", EBU, xrx300_pins_nand_d2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) GRP_MUX("nand d7", EBU, xrx300_pins_nand_d7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) GRP_MUX("nand d6", EBU, xrx300_pins_nand_d6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) GRP_MUX("nand d5", EBU, xrx300_pins_nand_d5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) GRP_MUX("nand d4", EBU, xrx300_pins_nand_d4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) GRP_MUX("nand d3", EBU, xrx300_pins_nand_d3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) GRP_MUX("nand cs0", EBU, xrx300_pins_nand_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) GRP_MUX("nand wr", EBU, xrx300_pins_nand_wr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) GRP_MUX("nand wp", EBU, xrx300_pins_nand_wp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) GRP_MUX("nand se", EBU, xrx300_pins_nand_se),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) GRP_MUX("spi_di", SPI, xrx300_pins_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) GRP_MUX("spi_do", SPI, xrx300_pins_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) GRP_MUX("spi_clk", SPI, xrx300_pins_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) GRP_MUX("spi_cs1", SPI, xrx300_pins_spi_cs1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) GRP_MUX("spi_cs4", SPI, xrx300_pins_spi_cs4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) GRP_MUX("spi_cs6", SPI, xrx300_pins_spi_cs6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) GRP_MUX("usif uart_rx", USIF, xrx300_pins_usif_uart_rx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) GRP_MUX("usif uart_tx", USIF, xrx300_pins_usif_uart_tx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) GRP_MUX("usif spi_di", USIF, xrx300_pins_usif_spi_di),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) GRP_MUX("usif spi_do", USIF, xrx300_pins_usif_spi_do),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) GRP_MUX("usif spi_clk", USIF, xrx300_pins_usif_spi_clk),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) GRP_MUX("usif spi_cs0", USIF, xrx300_pins_usif_spi_cs0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) GRP_MUX("stp", STP, xrx300_pins_stp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) GRP_MUX("clkout2", CGU, xrx300_pins_clkout2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) GRP_MUX("mdio", MDIO, xrx300_pins_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) GRP_MUX("dfe led0", DFE, xrx300_pins_dfe_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) GRP_MUX("dfe led1", DFE, xrx300_pins_dfe_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) GRP_MUX("ephy0 led0", GPHY, xrx300_pins_ephy0_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) GRP_MUX("ephy0 led1", GPHY, xrx300_pins_ephy0_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) GRP_MUX("ephy1 led0", GPHY, xrx300_pins_ephy1_led0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GRP_MUX("ephy1 led1", GPHY, xrx300_pins_ephy1_led1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static const char * const xrx300_spi_grps[] = {"spi_di", "spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "spi_clk", "spi_cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) "spi_cs4", "spi_cs6"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static const char * const xrx300_cgu_grps[] = {"clkout2"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) static const char * const xrx300_ebu_grps[] = {"nand ale", "nand cs1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) "nand cle", "nand rdy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) "nand rd", "nand d1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) "nand d0", "nand d2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) "nand d7", "nand d6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "nand d5", "nand d4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) "nand d3", "nand cs0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) "nand wr", "nand wp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "nand se"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const char * const xrx300_exin_grps[] = {"exin0", "exin1", "exin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) "exin4", "exin5"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static const char * const xrx300_usif_grps[] = {"usif uart_rx", "usif uart_tx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) "usif spi_di", "usif spi_do",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) "usif spi_clk", "usif spi_cs0"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) static const char * const xrx300_stp_grps[] = {"stp"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static const char * const xrx300_mdio_grps[] = {"mdio"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const char * const xrx300_dfe_grps[] = {"dfe led0", "dfe led1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static const char * const xrx300_gphy_grps[] = {"ephy0 led0", "ephy0 led1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) "ephy1 led0", "ephy1 led1"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static const struct ltq_pmx_func xrx300_funcs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {"spi", ARRAY_AND_SIZE(xrx300_spi_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {"usif", ARRAY_AND_SIZE(xrx300_usif_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {"cgu", ARRAY_AND_SIZE(xrx300_cgu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {"exin", ARRAY_AND_SIZE(xrx300_exin_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {"stp", ARRAY_AND_SIZE(xrx300_stp_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {"ebu", ARRAY_AND_SIZE(xrx300_ebu_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {"mdio", ARRAY_AND_SIZE(xrx300_mdio_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {"dfe", ARRAY_AND_SIZE(xrx300_dfe_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {"ephy", ARRAY_AND_SIZE(xrx300_gphy_grps)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /* --------- pinconf related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int xway_pinconf_get(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) int port = PORT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) case LTQ_PINCONF_PARAM_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) reg = GPIO3_OD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) reg = GPIO_OD(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) *config = LTQ_PINCONF_PACK(param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) !gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) case LTQ_PINCONF_PARAM_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) reg = GPIO3_PUDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) reg = GPIO_PUDEN(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) *config = LTQ_PINCONF_PACK(param, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) reg = GPIO3_PUDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) reg = GPIO_PUDSEL(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!gpio_getbit(info->membase[0], reg, PORT_PIN(pin)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) *config = LTQ_PINCONF_PACK(param, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) *config = LTQ_PINCONF_PACK(param, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) case LTQ_PINCONF_PARAM_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) reg = GPIO_DIR(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) *config = LTQ_PINCONF_PACK(param,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) gpio_getbit(info->membase[0], reg, PORT_PIN(pin)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_err(pctldev->dev, "Invalid config param %04x\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static int xway_pinconf_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) enum ltq_pinconf_param param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) int arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) int port = PORT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) param = LTQ_PINCONF_UNPACK_PARAM(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) arg = LTQ_PINCONF_UNPACK_ARG(configs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) switch (param) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) case LTQ_PINCONF_PARAM_OPEN_DRAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) reg = GPIO3_OD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) reg = GPIO_OD(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (arg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) gpio_setbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) gpio_clearbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) case LTQ_PINCONF_PARAM_PULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) reg = GPIO3_PUDEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) reg = GPIO_PUDEN(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (arg == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) gpio_clearbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) gpio_setbit(info->membase[0], reg, PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) reg = GPIO3_PUDSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) reg = GPIO_PUDSEL(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (arg == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) gpio_clearbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) else if (arg == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) gpio_setbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) "Invalid pull value %d\n", arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) case LTQ_PINCONF_PARAM_OUTPUT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) reg = GPIO_DIR(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (arg == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) gpio_clearbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) gpio_setbit(info->membase[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_err(pctldev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) "Invalid config param %04x\n", param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned long *configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) for (i = 0; i < info->grps[selector].npins && !ret; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = xway_pinconf_set(pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) info->grps[selector].pins[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) configs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) num_configs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static const struct pinconf_ops xway_pinconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .pin_config_get = xway_pinconf_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .pin_config_set = xway_pinconf_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .pin_config_group_set = xway_pinconf_group_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static struct pinctrl_desc xway_pctrl_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .confops = &xway_pinconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) int pin, int mux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) int port = PORT(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) u32 alt1_reg = GPIO_ALT1(pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (port == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) alt1_reg = GPIO3_ALT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (mux & MUX_ALT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (mux & MUX_ALT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static const struct ltq_cfg_param xway_cfg_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {"lantiq,output", LTQ_PINCONF_PARAM_OUTPUT},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static struct ltq_pinmux_info xway_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .desc = &xway_pctrl_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .apply_mux = xway_mux_apply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .params = xway_cfg_params,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .num_params = ARRAY_SIZE(xway_cfg_params),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) /* --------- gpio_chip related code --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) return !!gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (PORT(pin) == PORT3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) gpio_setbit(info->membase[0], GPIO3_OD, PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) gpio_setbit(info->membase[0], GPIO_OD(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) xway_gpio_set(chip, pin, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) * gpiolib gpiod_to_irq callback function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) * Returns the mapped IRQ (external interrupt) number for a given GPIO pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct ltq_pinmux_info *info = dev_get_drvdata(chip->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) for (i = 0; i < info->num_exin; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (info->exin[i] == offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return ltq_eiu_get_irq(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) static struct gpio_chip xway_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .label = "gpio-xway",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .direction_input = xway_gpio_dir_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .direction_output = xway_gpio_dir_out,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .get = xway_gpio_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .set = xway_gpio_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .request = gpiochip_generic_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) .free = gpiochip_generic_free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .to_irq = xway_gpio_to_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .base = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) /* --------- register the pinctrl layer --------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct pinctrl_xway_soc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) int pin_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) const struct ltq_mfp_pin *mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) const struct ltq_pin_group *grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) unsigned int num_grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) const struct ltq_pmx_func *funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) unsigned int num_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) const unsigned *exin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) unsigned int num_exin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* xway xr9 series (DEPRECATED: Use XWAY xRX100/xRX200 Family) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) static struct pinctrl_xway_soc xr9_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .pin_count = XR9_MAX_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .mfp = xway_mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .grps = xway_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .num_grps = ARRAY_SIZE(xway_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .funcs = xrx_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .num_funcs = ARRAY_SIZE(xrx_funcs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .exin = xway_exin_pin_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) .num_exin = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) /* XWAY AMAZON Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) static struct pinctrl_xway_soc ase_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .pin_count = ASE_MAX_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .mfp = ase_mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .grps = ase_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .num_grps = ARRAY_SIZE(ase_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .funcs = ase_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .num_funcs = ARRAY_SIZE(ase_funcs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .exin = ase_exin_pin_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .num_exin = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* XWAY DANUBE Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static struct pinctrl_xway_soc danube_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .pin_count = DANUBE_MAX_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .mfp = danube_mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .grps = danube_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .num_grps = ARRAY_SIZE(danube_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .funcs = danube_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .num_funcs = ARRAY_SIZE(danube_funcs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .exin = danube_exin_pin_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .num_exin = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) /* XWAY xRX100 Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct pinctrl_xway_soc xrx100_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .pin_count = XRX100_MAX_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .mfp = xrx100_mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .grps = xrx100_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .num_grps = ARRAY_SIZE(xrx100_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .funcs = xrx100_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .num_funcs = ARRAY_SIZE(xrx100_funcs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .exin = xrx100_exin_pin_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .num_exin = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) /* XWAY xRX200 Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static struct pinctrl_xway_soc xrx200_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .pin_count = XRX200_MAX_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .mfp = xrx200_mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .grps = xrx200_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .num_grps = ARRAY_SIZE(xrx200_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .funcs = xrx200_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .num_funcs = ARRAY_SIZE(xrx200_funcs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .exin = xrx200_exin_pin_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .num_exin = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) /* XWAY xRX300 Family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static struct pinctrl_xway_soc xrx300_pinctrl = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .pin_count = XRX300_MAX_PIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .mfp = xrx300_mfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .grps = xrx300_grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .num_grps = ARRAY_SIZE(xrx300_grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .funcs = xrx300_funcs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .num_funcs = ARRAY_SIZE(xrx300_funcs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .exin = xrx300_exin_pin_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .num_exin = 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) static struct pinctrl_gpio_range xway_gpio_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .name = "XWAY GPIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .gc = &xway_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) static const struct of_device_id xway_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) { .compatible = "lantiq,pinctrl-xway", .data = &danube_pinctrl}, /*DEPRECATED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) { .compatible = "lantiq,pinctrl-xr9", .data = &xr9_pinctrl}, /*DEPRECATED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) { .compatible = "lantiq,pinctrl-ase", .data = &ase_pinctrl}, /*DEPRECATED*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) { .compatible = "lantiq,ase-pinctrl", .data = &ase_pinctrl},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) { .compatible = "lantiq,danube-pinctrl", .data = &danube_pinctrl},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) { .compatible = "lantiq,xrx100-pinctrl", .data = &xrx100_pinctrl},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) { .compatible = "lantiq,xrx200-pinctrl", .data = &xrx200_pinctrl},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) { .compatible = "lantiq,xrx300-pinctrl", .data = &xrx300_pinctrl},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) MODULE_DEVICE_TABLE(of, xway_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static int pinmux_xway_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) const struct pinctrl_xway_soc *xway_soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* get and remap our register range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) xway_info.membase[0] = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (IS_ERR(xway_info.membase[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) return PTR_ERR(xway_info.membase[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) match = of_match_device(xway_match, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) xway_soc = (const struct pinctrl_xway_soc *) match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) xway_soc = &danube_pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) /* find out how many pads we have */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) xway_chip.ngpio = xway_soc->pin_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) /* load our pad descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) xway_info.pads = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) xway_chip.ngpio, sizeof(struct pinctrl_pin_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (!xway_info.pads)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) for (i = 0; i < xway_chip.ngpio; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) char *name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "io%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) xway_info.pads[i].number = GPIO0 + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) xway_info.pads[i].name = name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) xway_pctrl_desc.pins = xway_info.pads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) /* setup the data needed by pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) xway_pctrl_desc.name = dev_name(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) xway_pctrl_desc.npins = xway_chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) xway_info.num_pads = xway_chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) xway_info.num_mfp = xway_chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) xway_info.mfp = xway_soc->mfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) xway_info.grps = xway_soc->grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) xway_info.num_grps = xway_soc->num_grps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) xway_info.funcs = xway_soc->funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) xway_info.num_funcs = xway_soc->num_funcs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) xway_info.exin = xway_soc->exin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) xway_info.num_exin = xway_soc->num_exin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* register with the generic lantiq layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ret = ltq_pinctrl_register(pdev, &xway_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* register the gpio chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) xway_chip.parent = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) xway_chip.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) xway_chip.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) ret = devm_gpiochip_add_data(&pdev->dev, &xway_chip, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev_err(&pdev->dev, "Failed to register gpio chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * For DeviceTree-supported systems, the gpio core checks the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * pinctrl's device node for the "gpio-ranges" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) * If it is present, it takes care of adding the pin ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * for the driver. In this case the driver can skip ahead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) * In order to remain compatible with older, existing DeviceTree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * files which don't set the "gpio-ranges" property or systems that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) * utilize ACPI the driver has to call gpiochip_add_pin_range().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) if (!of_property_read_bool(pdev->dev.of_node, "gpio-ranges")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) /* finish with registering the gpio range in pinctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) xway_gpio_range.npins = xway_chip.ngpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) xway_gpio_range.base = xway_chip.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) dev_info(&pdev->dev, "Init done\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) static struct platform_driver pinmux_xway_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .probe = pinmux_xway_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) .name = "pinctrl-xway",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) .of_match_table = xway_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static int __init pinmux_xway_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) return platform_driver_register(&pinmux_xway_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) core_initcall_sync(pinmux_xway_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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