^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the U300 pin controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the original U300 padmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2009-2011 ST-Ericsson AB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Martin Persson <martin.persson@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * The DB3350 design and control registers are oriented around pads rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * pins, so we enumerate the pads we can mux rather than actual pins. The pads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * are connected to different pins in different packaging types, so it would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * be confusing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/pinctrl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pinctrl/pinmux.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pinctrl/pinconf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/pinconf-generic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "pinctrl-coh901.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Register definitions for the U300 Padmux control registers in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * system controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* PAD MUX Control register 1 (LOW) 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define U300_SYSCON_PMC1LR 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define U300_SYSCON_PMC1LR_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define U300_SYSCON_PMC1LR_CDI_MASK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define U300_SYSCON_PMC1LR_CDI_CDI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define U300_SYSCON_PMC1LR_CDI_EMIF 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* For BS335 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define U300_SYSCON_PMC1LR_CDI_CDI2 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define U300_SYSCON_PMC1LR_CDI_WCDMA_APP_GPIO 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* For BS365 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define U300_SYSCON_PMC1LR_CDI_GPIO 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define U300_SYSCON_PMC1LR_CDI_WCDMA 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Common defs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define U300_SYSCON_PMC1LR_PDI_MASK 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define U300_SYSCON_PMC1LR_PDI_PDI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define U300_SYSCON_PMC1LR_PDI_EGG 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define U300_SYSCON_PMC1LR_PDI_WCDMA 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define U300_SYSCON_PMC1LR_MMCSD_MASK 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define U300_SYSCON_PMC1LR_MMCSD_MMCSD 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define U300_SYSCON_PMC1LR_MMCSD_MSPRO 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define U300_SYSCON_PMC1LR_MMCSD_DSP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define U300_SYSCON_PMC1LR_MMCSD_WCDMA 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define U300_SYSCON_PMC1LR_ETM_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define U300_SYSCON_PMC1LR_ETM_ACC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define U300_SYSCON_PMC1LR_ETM_APP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define U300_SYSCON_PMC1LR_EMIF_1_CS2_NFIF 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define U300_SYSCON_PMC1LR_EMIF_1_CS2_STATIC_2GB 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define U300_SYSCON_PMC1LR_EMIF_1_CS1_NFIF 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SDRAM 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define U300_SYSCON_PMC1LR_EMIF_1_CS1_SEMI 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define U300_SYSCON_PMC1LR_EMIF_1_CS0_STATIC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SDRAM 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define U300_SYSCON_PMC1LR_EMIF_1_CS0_SEMI 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define U300_SYSCON_PMC1LR_EMIF_1_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define U300_SYSCON_PMC1LR_EMIF_1_STATIC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define U300_SYSCON_PMC1LR_EMIF_1_SDRAM1 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define U300_SYSCON_PMC1LR_EMIF_1 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* PAD MUX Control register 2 (HIGH) 16bit (R/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define U300_SYSCON_PMC1HR 0x007E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define U300_SYSCON_PMC1HR_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define U300_SYSCON_PMC1HR_MISC_2_MASK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define U300_SYSCON_PMC1HR_MISC_2_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define U300_SYSCON_PMC1HR_MISC_2_MSPRO 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define U300_SYSCON_PMC1HR_MISC_2_DSP 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define U300_SYSCON_PMC1HR_MISC_2_AAIF 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define U300_SYSCON_PMC1HR_APP_GPIO_2_MASK 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define U300_SYSCON_PMC1HR_APP_GPIO_2_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define U300_SYSCON_PMC1HR_APP_GPIO_2_NFIF 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define U300_SYSCON_PMC1HR_APP_GPIO_2_DSP 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define U300_SYSCON_PMC1HR_APP_GPIO_2_AAIF 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define U300_SYSCON_PMC1HR_APP_GPIO_1_MASK 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define U300_SYSCON_PMC1HR_APP_GPIO_1_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define U300_SYSCON_PMC1HR_APP_GPIO_1_MMC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define U300_SYSCON_PMC1HR_APP_GPIO_1_DSP 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define U300_SYSCON_PMC1HR_APP_GPIO_1_AAIF 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define U300_SYSCON_PMC1HR_APP_SPI_CS_2_AAIF 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define U300_SYSCON_PMC1HR_APP_SPI_CS_1_AAIF 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define U300_SYSCON_PMC1HR_APP_SPI_2_MASK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define U300_SYSCON_PMC1HR_APP_SPI_2_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define U300_SYSCON_PMC1HR_APP_SPI_2_SPI 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define U300_SYSCON_PMC1HR_APP_SPI_2_DSP 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define U300_SYSCON_PMC1HR_APP_SPI_2_AAIF 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define U300_SYSCON_PMC1HR_APP_UART0_2_MASK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define U300_SYSCON_PMC1HR_APP_UART0_2_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define U300_SYSCON_PMC1HR_APP_UART0_2_UART0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define U300_SYSCON_PMC1HR_APP_UART0_2_NFIF_CS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define U300_SYSCON_PMC1HR_APP_UART0_2_AAIF 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define U300_SYSCON_PMC1HR_APP_UART0_1_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define U300_SYSCON_PMC1HR_APP_UART0_1_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define U300_SYSCON_PMC1HR_APP_UART0_1_UART0 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define U300_SYSCON_PMC1HR_APP_UART0_1_AAIF 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Padmux 2 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define U300_SYSCON_PMC2R 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define U300_SYSCON_PMC2R_APP_MISC_0_MASK 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define U300_SYSCON_PMC2R_APP_MISC_0_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define U300_SYSCON_PMC2R_APP_MISC_0_EMIF_SDRAM 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define U300_SYSCON_PMC2R_APP_MISC_0_MMC 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define U300_SYSCON_PMC2R_APP_MISC_0_CDI2 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define U300_SYSCON_PMC2R_APP_MISC_1_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define U300_SYSCON_PMC2R_APP_MISC_1_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define U300_SYSCON_PMC2R_APP_MISC_1_EMIF_SDRAM 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define U300_SYSCON_PMC2R_APP_MISC_1_MMC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define U300_SYSCON_PMC2R_APP_MISC_1_CDI2 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define U300_SYSCON_PMC2R_APP_MISC_2_MASK 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define U300_SYSCON_PMC2R_APP_MISC_2_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define U300_SYSCON_PMC2R_APP_MISC_2_EMIF_SDRAM 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define U300_SYSCON_PMC2R_APP_MISC_2_MMC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define U300_SYSCON_PMC2R_APP_MISC_2_CDI2 0x0C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define U300_SYSCON_PMC2R_APP_MISC_3_MASK 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define U300_SYSCON_PMC2R_APP_MISC_3_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define U300_SYSCON_PMC2R_APP_MISC_3_EMIF_SDRAM 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define U300_SYSCON_PMC2R_APP_MISC_3_MMC 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define U300_SYSCON_PMC2R_APP_MISC_3_CDI2 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define U300_SYSCON_PMC2R_APP_MISC_4_MASK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define U300_SYSCON_PMC2R_APP_MISC_4_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define U300_SYSCON_PMC2R_APP_MISC_4_EMIF_SDRAM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define U300_SYSCON_PMC2R_APP_MISC_4_MMC 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define U300_SYSCON_PMC2R_APP_MISC_4_ACC_GPIO 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* TODO: More SYSCON registers missing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define U300_SYSCON_PMC3R 0x10C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define U300_SYSCON_PMC3R_APP_MISC_11_MASK 0xC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define U300_SYSCON_PMC3R_APP_MISC_11_SPI 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define U300_SYSCON_PMC3R_APP_MISC_10_MASK 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define U300_SYSCON_PMC3R_APP_MISC_10_SPI 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* TODO: Missing other configs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define U300_SYSCON_PMC4R 0x168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define U300_SYSCON_PMC4R_APP_MISC_12_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define U300_SYSCON_PMC4R_APP_MISC_13_MASK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define U300_SYSCON_PMC4R_APP_MISC_13_CDI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define U300_SYSCON_PMC4R_APP_MISC_13_SMIA2 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define U300_SYSCON_PMC4R_APP_MISC_13_APP_GPIO 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define U300_SYSCON_PMC4R_APP_MISC_14_MASK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define U300_SYSCON_PMC4R_APP_MISC_14_CDI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define U300_SYSCON_PMC4R_APP_MISC_14_SMIA 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define U300_SYSCON_PMC4R_APP_MISC_14_CDI2 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define U300_SYSCON_PMC4R_APP_MISC_14_APP_GPIO 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define U300_SYSCON_PMC4R_APP_MISC_16_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define U300_SYSCON_PMC4R_APP_MISC_16_APP_GPIO_13 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define U300_SYSCON_PMC4R_APP_MISC_16_APP_UART1_CTS 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define U300_SYSCON_PMC4R_APP_MISC_16_EMIF_1_STATIC_CS5_N 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DRIVER_NAME "pinctrl-u300"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * The DB3350 has 467 pads, I have enumerated the pads clockwise around the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * edges of the silicon, finger by finger. LTCORNER upper left is pad 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * Data taken from the PadRing chart, arranged like this:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * 0 ..... 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * 466 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * . .
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * 358 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * 357 .... 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define U300_NUM_PADS 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* Pad names for the pinmux subsystem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const struct pinctrl_pin_desc u300_pads[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Pads along the top edge of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) PINCTRL_PIN(0, "P PAD VDD 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) PINCTRL_PIN(1, "P PAD GND 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) PINCTRL_PIN(2, "PO SIM RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) PINCTRL_PIN(3, "VSSIO 25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PINCTRL_PIN(4, "VSSA ADDA ESDSUB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) PINCTRL_PIN(5, "PWR VSSCOMMON"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) PINCTRL_PIN(6, "PI ADC I1 POS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) PINCTRL_PIN(7, "PI ADC I1 NEG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) PINCTRL_PIN(8, "PWR VSSAD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) PINCTRL_PIN(9, "PWR VCCAD0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) PINCTRL_PIN(10, "PI ADC Q1 NEG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) PINCTRL_PIN(11, "PI ADC Q1 POS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) PINCTRL_PIN(12, "PWR VDDAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) PINCTRL_PIN(13, "PWR GNDAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) PINCTRL_PIN(14, "PI ADC I2 POS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) PINCTRL_PIN(15, "PI ADC I2 NEG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) PINCTRL_PIN(16, "PWR VSSAD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) PINCTRL_PIN(17, "PWR VCCAD1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) PINCTRL_PIN(18, "PI ADC Q2 NEG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) PINCTRL_PIN(19, "PI ADC Q2 POS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) PINCTRL_PIN(20, "VSSA ADDA ESDSUB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) PINCTRL_PIN(21, "PWR VCCGPAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PINCTRL_PIN(22, "PI TX POW"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) PINCTRL_PIN(23, "PWR VSSGPAD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PINCTRL_PIN(24, "PO DAC I POS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PINCTRL_PIN(25, "PO DAC I NEG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PINCTRL_PIN(26, "PO DAC Q POS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PINCTRL_PIN(27, "PO DAC Q NEG"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PINCTRL_PIN(28, "PWR VSSDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PINCTRL_PIN(29, "PWR VCCDA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PINCTRL_PIN(30, "VSSA ADDA ESDSUB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PINCTRL_PIN(31, "P PAD VDDIO 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PINCTRL_PIN(32, "PI PLL 26 FILTVDD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PINCTRL_PIN(33, "PI PLL 26 VCONT"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PINCTRL_PIN(34, "PWR AGNDPLL2V5 32 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PINCTRL_PIN(35, "PWR AVDDPLL2V5 32 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PINCTRL_PIN(36, "VDDA PLL ESD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PINCTRL_PIN(37, "VSSA PLL ESD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PINCTRL_PIN(38, "VSS PLL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PINCTRL_PIN(39, "VDDC PLL"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PINCTRL_PIN(40, "PWR AGNDPLL2V5 26 60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) PINCTRL_PIN(41, "PWR AVDDPLL2V5 26 60"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) PINCTRL_PIN(42, "PWR AVDDPLL2V5 26 208"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PINCTRL_PIN(43, "PWR AGNDPLL2V5 26 208"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) PINCTRL_PIN(44, "PWR AVDDPLL2V5 13 208"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) PINCTRL_PIN(45, "PWR AGNDPLL2V5 13 208"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) PINCTRL_PIN(46, "P PAD VSSIO 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) PINCTRL_PIN(47, "P PAD VSSIO 12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) PINCTRL_PIN(48, "PI POW RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) PINCTRL_PIN(49, "VDDC IO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PINCTRL_PIN(50, "P PAD VDDIO 16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) PINCTRL_PIN(51, "PO RF WCDMA EN 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) PINCTRL_PIN(52, "PO RF WCDMA EN 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PINCTRL_PIN(53, "PO RF WCDMA EN 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) PINCTRL_PIN(54, "PO RF WCDMA EN 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) PINCTRL_PIN(55, "PO RF WCDMA EN 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) PINCTRL_PIN(56, "PO GSM PA ENABLE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) PINCTRL_PIN(57, "PO RF DATA STRB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) PINCTRL_PIN(58, "PO RF DATA2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) PINCTRL_PIN(59, "PIO RF DATA1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) PINCTRL_PIN(60, "PIO RF DATA0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PINCTRL_PIN(61, "P PAD VDD 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) PINCTRL_PIN(62, "P PAD GND 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) PINCTRL_PIN(63, "P PAD VSSIO 16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) PINCTRL_PIN(64, "P PAD VDDIO 18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) PINCTRL_PIN(65, "PO RF CTRL STRB2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) PINCTRL_PIN(66, "PO RF CTRL STRB1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) PINCTRL_PIN(67, "PO RF CTRL STRB0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) PINCTRL_PIN(68, "PIO RF CTRL DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) PINCTRL_PIN(69, "PO RF CTRL CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) PINCTRL_PIN(70, "PO TX ADC STRB"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) PINCTRL_PIN(71, "PO ANT SW 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) PINCTRL_PIN(72, "PO ANT SW 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) PINCTRL_PIN(73, "PO ANT SW 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PINCTRL_PIN(74, "PO ANT SW 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) PINCTRL_PIN(75, "PO M CLKRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PINCTRL_PIN(76, "PI M CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PINCTRL_PIN(77, "PI RTC CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PINCTRL_PIN(78, "P PAD VDD 8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) PINCTRL_PIN(79, "P PAD GND 8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PINCTRL_PIN(80, "P PAD VSSIO 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PINCTRL_PIN(81, "P PAD VDDIO 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PINCTRL_PIN(82, "PO SYS 1 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PINCTRL_PIN(83, "PO SYS 2 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PINCTRL_PIN(84, "PO SYS 0 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PINCTRL_PIN(85, "PI SYS 0 CLKRQ"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) PINCTRL_PIN(86, "PO PWR MNGT CTRL 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) PINCTRL_PIN(87, "PO PWR MNGT CTRL 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) PINCTRL_PIN(88, "PO RESOUT2 RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) PINCTRL_PIN(89, "PO RESOUT1 RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) PINCTRL_PIN(90, "PO RESOUT0 RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) PINCTRL_PIN(91, "PI SERVICE N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) PINCTRL_PIN(92, "P PAD VDD 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PINCTRL_PIN(93, "P PAD GND 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) PINCTRL_PIN(94, "P PAD VSSIO 8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PINCTRL_PIN(95, "P PAD VDDIO 8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) PINCTRL_PIN(96, "PI EXT IRQ1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PINCTRL_PIN(97, "PI EXT IRQ0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) PINCTRL_PIN(98, "PIO DC ON"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PINCTRL_PIN(99, "PIO ACC APP I2C DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) PINCTRL_PIN(100, "PIO ACC APP I2C CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PINCTRL_PIN(101, "P PAD VDD 12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PINCTRL_PIN(102, "P PAD GND 12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) PINCTRL_PIN(103, "P PAD VSSIO 14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PINCTRL_PIN(104, "P PAD VDDIO 14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Pads along the right edge of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PINCTRL_PIN(105, "PIO APP I2C1 DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) PINCTRL_PIN(106, "PIO APP I2C1 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PINCTRL_PIN(107, "PO KEY OUT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) PINCTRL_PIN(108, "PO KEY OUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PINCTRL_PIN(109, "PO KEY OUT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) PINCTRL_PIN(110, "PO KEY OUT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PINCTRL_PIN(111, "PO KEY OUT4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) PINCTRL_PIN(112, "PI KEY IN0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) PINCTRL_PIN(113, "PI KEY IN1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PINCTRL_PIN(114, "PI KEY IN2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) PINCTRL_PIN(115, "P PAD VDDIO 15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PINCTRL_PIN(116, "P PAD VSSIO 15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) PINCTRL_PIN(117, "P PAD GND 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PINCTRL_PIN(118, "P PAD VDD 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) PINCTRL_PIN(119, "PI KEY IN3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PINCTRL_PIN(120, "PI KEY IN4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) PINCTRL_PIN(121, "PI KEY IN5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PINCTRL_PIN(122, "PIO APP PCM I2S1 DATA B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) PINCTRL_PIN(123, "PIO APP PCM I2S1 DATA A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PINCTRL_PIN(124, "PIO APP PCM I2S1 WS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) PINCTRL_PIN(125, "PIO APP PCM I2S1 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) PINCTRL_PIN(126, "PIO APP PCM I2S0 DATA B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PINCTRL_PIN(127, "PIO APP PCM I2S0 DATA A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) PINCTRL_PIN(128, "PIO APP PCM I2S0 WS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PINCTRL_PIN(129, "PIO APP PCM I2S0 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) PINCTRL_PIN(130, "P PAD VDD 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PINCTRL_PIN(131, "P PAD GND 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) PINCTRL_PIN(132, "P PAD VSSIO 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PINCTRL_PIN(133, "P PAD VDDIO 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) PINCTRL_PIN(134, "UART0 RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PINCTRL_PIN(135, "UART0 CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) PINCTRL_PIN(136, "UART0 TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) PINCTRL_PIN(137, "UART0 RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PINCTRL_PIN(138, "PIO ACC SPI DO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) PINCTRL_PIN(139, "PIO ACC SPI DI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PINCTRL_PIN(140, "PIO ACC SPI CS0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) PINCTRL_PIN(141, "PIO ACC SPI CS1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PINCTRL_PIN(142, "PIO ACC SPI CS2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) PINCTRL_PIN(143, "PIO ACC SPI CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PINCTRL_PIN(144, "PO PDI EXT RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) PINCTRL_PIN(145, "P PAD VDDIO 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) PINCTRL_PIN(146, "P PAD VSSIO 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PINCTRL_PIN(147, "P PAD GND 18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) PINCTRL_PIN(148, "P PAD VDD 18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) PINCTRL_PIN(149, "PIO PDI C0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) PINCTRL_PIN(150, "PIO PDI C1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PINCTRL_PIN(151, "PIO PDI C2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) PINCTRL_PIN(152, "PIO PDI C3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PINCTRL_PIN(153, "PIO PDI C4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) PINCTRL_PIN(154, "PIO PDI C5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PINCTRL_PIN(155, "PIO PDI D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) PINCTRL_PIN(156, "PIO PDI D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) PINCTRL_PIN(157, "PIO PDI D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PINCTRL_PIN(158, "PIO PDI D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) PINCTRL_PIN(159, "P PAD VDDIO 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) PINCTRL_PIN(160, "P PAD VSSIO 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PINCTRL_PIN(161, "PIO PDI D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) PINCTRL_PIN(162, "PIO PDI D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) PINCTRL_PIN(163, "PIO PDI D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) PINCTRL_PIN(164, "PIO PDI D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PINCTRL_PIN(165, "PIO MS INS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) PINCTRL_PIN(166, "MMC DATA DIR LS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) PINCTRL_PIN(167, "MMC DATA 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PINCTRL_PIN(168, "MMC DATA 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) PINCTRL_PIN(169, "MMC DATA 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) PINCTRL_PIN(170, "MMC DATA 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PINCTRL_PIN(171, "MMC CMD DIR LS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) PINCTRL_PIN(172, "P PAD VDD 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PINCTRL_PIN(173, "P PAD GND 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) PINCTRL_PIN(174, "P PAD VSSIO 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PINCTRL_PIN(175, "P PAD VDDIO 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) PINCTRL_PIN(176, "MMC CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) PINCTRL_PIN(177, "MMC CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PINCTRL_PIN(178, "PIO APP GPIO 14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) PINCTRL_PIN(179, "PIO APP GPIO 13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PINCTRL_PIN(180, "PIO APP GPIO 11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) PINCTRL_PIN(181, "PIO APP GPIO 25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PINCTRL_PIN(182, "PIO APP GPIO 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) PINCTRL_PIN(183, "PIO APP GPIO 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) PINCTRL_PIN(184, "PIO APP GPIO 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PINCTRL_PIN(185, "PIO APP GPIO 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) PINCTRL_PIN(186, "PIO APP GPIO 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) PINCTRL_PIN(187, "P PAD VDD 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) PINCTRL_PIN(188, "P PAD GND 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PINCTRL_PIN(189, "P PAD VSSIO 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PINCTRL_PIN(190, "P PAD VDDIO 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PINCTRL_PIN(191, "PIO APP GPIO 19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PINCTRL_PIN(192, "PIO APP GPIO 18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PINCTRL_PIN(193, "PIO APP GPIO 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PINCTRL_PIN(194, "PIO APP GPIO 16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PINCTRL_PIN(195, "PI CI D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PINCTRL_PIN(196, "PI CI D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PINCTRL_PIN(197, "PI CI HSYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PINCTRL_PIN(198, "PI CI VSYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PINCTRL_PIN(199, "PI CI EXT CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PINCTRL_PIN(200, "PO CI EXT RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PINCTRL_PIN(201, "P PAD VSSIO 43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PINCTRL_PIN(202, "P PAD VDDIO 43"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PINCTRL_PIN(203, "PI CI D6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PINCTRL_PIN(204, "PI CI D7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) PINCTRL_PIN(205, "PI CI D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) PINCTRL_PIN(206, "PI CI D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) PINCTRL_PIN(207, "PI CI D4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PINCTRL_PIN(208, "PI CI D5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PINCTRL_PIN(209, "PI CI D8"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PINCTRL_PIN(210, "PI CI D9"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PINCTRL_PIN(211, "P PAD VDD 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PINCTRL_PIN(212, "P PAD GND 20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PINCTRL_PIN(213, "P PAD VSSIO 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PINCTRL_PIN(214, "P PAD VDDIO 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PINCTRL_PIN(215, "P PAD VDDIO 26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PINCTRL_PIN(216, "PO EMIF 1 A26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PINCTRL_PIN(217, "PO EMIF 1 A25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PINCTRL_PIN(218, "P PAD VSSIO 26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PINCTRL_PIN(219, "PO EMIF 1 A24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PINCTRL_PIN(220, "PO EMIF 1 A23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Pads along the bottom edge of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PINCTRL_PIN(221, "PO EMIF 1 A22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) PINCTRL_PIN(222, "PO EMIF 1 A21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) PINCTRL_PIN(223, "P PAD VDD 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PINCTRL_PIN(224, "P PAD GND 21"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PINCTRL_PIN(225, "P PAD VSSIO 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PINCTRL_PIN(226, "P PAD VDDIO 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PINCTRL_PIN(227, "PO EMIF 1 A20"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PINCTRL_PIN(228, "PO EMIF 1 A19"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PINCTRL_PIN(229, "PO EMIF 1 A18"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PINCTRL_PIN(230, "PO EMIF 1 A17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PINCTRL_PIN(231, "P PAD VDDIO 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PINCTRL_PIN(232, "P PAD VSSIO 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PINCTRL_PIN(233, "PO EMIF 1 A16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PINCTRL_PIN(234, "PIO EMIF 1 D15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PINCTRL_PIN(235, "PO EMIF 1 A15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PINCTRL_PIN(236, "PIO EMIF 1 D14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) PINCTRL_PIN(237, "P PAD VDD 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) PINCTRL_PIN(238, "P PAD GND 22"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) PINCTRL_PIN(239, "P PAD VSSIO 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PINCTRL_PIN(240, "P PAD VDDIO 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PINCTRL_PIN(241, "PO EMIF 1 A14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PINCTRL_PIN(242, "PIO EMIF 1 D13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PINCTRL_PIN(243, "PO EMIF 1 A13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PINCTRL_PIN(244, "PIO EMIF 1 D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PINCTRL_PIN(245, "P PAD VSSIO 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PINCTRL_PIN(246, "P PAD VDDIO 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PINCTRL_PIN(247, "PO EMIF 1 A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PINCTRL_PIN(248, "PIO EMIF 1 D11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PINCTRL_PIN(249, "PO EMIF 1 A11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) PINCTRL_PIN(250, "PIO EMIF 1 D10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) PINCTRL_PIN(251, "P PAD VSSIO 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PINCTRL_PIN(252, "P PAD VDDIO 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) PINCTRL_PIN(253, "PO EMIF 1 A10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) PINCTRL_PIN(254, "PIO EMIF 1 D09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) PINCTRL_PIN(255, "PO EMIF 1 A09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) PINCTRL_PIN(256, "P PAD VDDIO 32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) PINCTRL_PIN(257, "P PAD VSSIO 32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) PINCTRL_PIN(258, "P PAD GND 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PINCTRL_PIN(259, "P PAD VDD 24"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) PINCTRL_PIN(260, "PIO EMIF 1 D08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PINCTRL_PIN(261, "PO EMIF 1 A08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) PINCTRL_PIN(262, "PIO EMIF 1 D07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) PINCTRL_PIN(263, "PO EMIF 1 A07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) PINCTRL_PIN(264, "P PAD VDDIO 33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) PINCTRL_PIN(265, "P PAD VSSIO 33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PINCTRL_PIN(266, "PIO EMIF 1 D06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PINCTRL_PIN(267, "PO EMIF 1 A06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PINCTRL_PIN(268, "PIO EMIF 1 D05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PINCTRL_PIN(269, "PO EMIF 1 A05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PINCTRL_PIN(270, "P PAD VDDIO 34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PINCTRL_PIN(271, "P PAD VSSIO 34"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) PINCTRL_PIN(272, "PIO EMIF 1 D04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PINCTRL_PIN(273, "PO EMIF 1 A04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PINCTRL_PIN(274, "PIO EMIF 1 D03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) PINCTRL_PIN(275, "PO EMIF 1 A03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) PINCTRL_PIN(276, "P PAD VDDIO 35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) PINCTRL_PIN(277, "P PAD VSSIO 35"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) PINCTRL_PIN(278, "P PAD GND 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) PINCTRL_PIN(279, "P PAD VDD 23"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) PINCTRL_PIN(280, "PIO EMIF 1 D02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) PINCTRL_PIN(281, "PO EMIF 1 A02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PINCTRL_PIN(282, "PIO EMIF 1 D01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PINCTRL_PIN(283, "PO EMIF 1 A01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PINCTRL_PIN(284, "P PAD VDDIO 36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PINCTRL_PIN(285, "P PAD VSSIO 36"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PINCTRL_PIN(286, "PIO EMIF 1 D00"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) PINCTRL_PIN(287, "PO EMIF 1 BE1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PINCTRL_PIN(288, "PO EMIF 1 BE0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) PINCTRL_PIN(289, "PO EMIF 1 ADV N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) PINCTRL_PIN(290, "P PAD VDDIO 37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) PINCTRL_PIN(291, "P PAD VSSIO 37"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) PINCTRL_PIN(292, "PO EMIF 1 SD CKE0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) PINCTRL_PIN(293, "PO EMIF 1 OE N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PINCTRL_PIN(294, "PO EMIF 1 WE N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PINCTRL_PIN(295, "P PAD VDDIO 38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PINCTRL_PIN(296, "P PAD VSSIO 38"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PINCTRL_PIN(297, "PO EMIF 1 CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) PINCTRL_PIN(298, "PIO EMIF 1 SD CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) PINCTRL_PIN(299, "P PAD VSSIO 45 (not bonded)"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) PINCTRL_PIN(300, "P PAD VDDIO 42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PINCTRL_PIN(301, "P PAD VSSIO 42"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) PINCTRL_PIN(302, "P PAD GND 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) PINCTRL_PIN(303, "P PAD VDD 31"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) PINCTRL_PIN(304, "PI EMIF 1 RET CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) PINCTRL_PIN(305, "PI EMIF 1 WAIT N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) PINCTRL_PIN(306, "PI EMIF 1 NFIF READY"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) PINCTRL_PIN(307, "PO EMIF 1 SD CKE1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) PINCTRL_PIN(308, "PO EMIF 1 CS3 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) PINCTRL_PIN(309, "P PAD VDD 25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) PINCTRL_PIN(310, "P PAD GND 25"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) PINCTRL_PIN(311, "P PAD VSSIO 39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) PINCTRL_PIN(312, "P PAD VDDIO 39"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) PINCTRL_PIN(313, "PO EMIF 1 CS2 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) PINCTRL_PIN(314, "PO EMIF 1 CS1 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) PINCTRL_PIN(315, "PO EMIF 1 CS0 N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) PINCTRL_PIN(316, "PO ETM TRACE PKT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) PINCTRL_PIN(317, "PO ETM TRACE PKT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) PINCTRL_PIN(318, "PO ETM TRACE PKT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) PINCTRL_PIN(319, "P PAD VDD 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) PINCTRL_PIN(320, "P PAD GND 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) PINCTRL_PIN(321, "P PAD VSSIO 44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) PINCTRL_PIN(322, "P PAD VDDIO 44"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) PINCTRL_PIN(323, "PO ETM TRACE PKT3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) PINCTRL_PIN(324, "PO ETM TRACE PKT4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) PINCTRL_PIN(325, "PO ETM TRACE PKT5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) PINCTRL_PIN(326, "PO ETM TRACE PKT6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) PINCTRL_PIN(327, "PO ETM TRACE PKT7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) PINCTRL_PIN(328, "PO ETM PIPE STAT0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) PINCTRL_PIN(329, "P PAD VDD 26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) PINCTRL_PIN(330, "P PAD GND 26"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) PINCTRL_PIN(331, "P PAD VSSIO 40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) PINCTRL_PIN(332, "P PAD VDDIO 40"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) PINCTRL_PIN(333, "PO ETM PIPE STAT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) PINCTRL_PIN(334, "PO ETM PIPE STAT2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) PINCTRL_PIN(335, "PO ETM TRACE CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) PINCTRL_PIN(336, "PO ETM TRACE SYNC"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) PINCTRL_PIN(337, "PIO ACC GPIO 33"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) PINCTRL_PIN(338, "PIO ACC GPIO 32"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) PINCTRL_PIN(339, "PIO ACC GPIO 30"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) PINCTRL_PIN(340, "PIO ACC GPIO 29"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) PINCTRL_PIN(341, "P PAD VDDIO 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) PINCTRL_PIN(342, "P PAD VSSIO 17"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PINCTRL_PIN(343, "P PAD GND 15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) PINCTRL_PIN(344, "P PAD VDD 15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) PINCTRL_PIN(345, "PIO ACC GPIO 28"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) PINCTRL_PIN(346, "PIO ACC GPIO 27"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) PINCTRL_PIN(347, "PIO ACC GPIO 16"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) PINCTRL_PIN(348, "PI TAP TMS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) PINCTRL_PIN(349, "PI TAP TDI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) PINCTRL_PIN(350, "PO TAP TDO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) PINCTRL_PIN(351, "PI TAP RST N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /* Pads along the left edge of the chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) PINCTRL_PIN(352, "PI EMU MODE 0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) PINCTRL_PIN(353, "PO TAP RET CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) PINCTRL_PIN(354, "PI TAP CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) PINCTRL_PIN(355, "PO EMIF 0 SD CS N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) PINCTRL_PIN(356, "PO EMIF 0 SD CAS N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) PINCTRL_PIN(357, "PO EMIF 0 SD WE N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) PINCTRL_PIN(358, "P PAD VDDIO 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) PINCTRL_PIN(359, "P PAD VSSIO 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) PINCTRL_PIN(360, "P PAD GND 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) PINCTRL_PIN(361, "P PAD VDD 1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) PINCTRL_PIN(362, "PO EMIF 0 SD CKE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) PINCTRL_PIN(363, "PO EMIF 0 SD DQML"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) PINCTRL_PIN(364, "PO EMIF 0 SD DQMU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) PINCTRL_PIN(365, "PO EMIF 0 SD RAS N"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) PINCTRL_PIN(366, "PIO EMIF 0 D15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) PINCTRL_PIN(367, "PO EMIF 0 A15"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) PINCTRL_PIN(368, "PIO EMIF 0 D14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) PINCTRL_PIN(369, "PO EMIF 0 A14"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) PINCTRL_PIN(370, "PIO EMIF 0 D13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) PINCTRL_PIN(371, "PO EMIF 0 A13"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) PINCTRL_PIN(372, "P PAD VDDIO 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) PINCTRL_PIN(373, "P PAD VSSIO 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) PINCTRL_PIN(374, "P PAD GND 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) PINCTRL_PIN(375, "P PAD VDD 2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PINCTRL_PIN(376, "PIO EMIF 0 D12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) PINCTRL_PIN(377, "PO EMIF 0 A12"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) PINCTRL_PIN(378, "PIO EMIF 0 D11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) PINCTRL_PIN(379, "PO EMIF 0 A11"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PINCTRL_PIN(380, "PIO EMIF 0 D10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) PINCTRL_PIN(381, "PO EMIF 0 A10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) PINCTRL_PIN(382, "PIO EMIF 0 D09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) PINCTRL_PIN(383, "PO EMIF 0 A09"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) PINCTRL_PIN(384, "PIO EMIF 0 D08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) PINCTRL_PIN(385, "PO EMIF 0 A08"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) PINCTRL_PIN(386, "PIO EMIF 0 D07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) PINCTRL_PIN(387, "PO EMIF 0 A07"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) PINCTRL_PIN(388, "P PAD VDDIO 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) PINCTRL_PIN(389, "P PAD VSSIO 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) PINCTRL_PIN(390, "P PAD GND 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) PINCTRL_PIN(391, "P PAD VDD 3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) PINCTRL_PIN(392, "PO EFUSE RDOUT1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) PINCTRL_PIN(393, "PIO EMIF 0 D06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) PINCTRL_PIN(394, "PO EMIF 0 A06"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) PINCTRL_PIN(395, "PIO EMIF 0 D05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) PINCTRL_PIN(396, "PO EMIF 0 A05"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) PINCTRL_PIN(397, "PIO EMIF 0 D04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) PINCTRL_PIN(398, "PO EMIF 0 A04"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) PINCTRL_PIN(399, "A PADS/A VDDCO1v82v5 GND 80U SF LIN VDDCO AF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) PINCTRL_PIN(400, "PWR VDDCO AF"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) PINCTRL_PIN(401, "PWR EFUSE HV1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) PINCTRL_PIN(402, "P PAD VSSIO 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) PINCTRL_PIN(403, "P PAD VDDIO 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) PINCTRL_PIN(404, "P PAD GND 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) PINCTRL_PIN(405, "P PAD VDD 4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) PINCTRL_PIN(406, "PIO EMIF 0 D03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) PINCTRL_PIN(407, "PO EMIF 0 A03"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) PINCTRL_PIN(408, "PWR EFUSE HV2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) PINCTRL_PIN(409, "PWR EFUSE HV3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) PINCTRL_PIN(410, "PIO EMIF 0 D02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) PINCTRL_PIN(411, "PO EMIF 0 A02"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) PINCTRL_PIN(412, "PIO EMIF 0 D01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) PINCTRL_PIN(413, "P PAD VDDIO 5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PINCTRL_PIN(414, "P PAD VSSIO 5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) PINCTRL_PIN(415, "P PAD GND 5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PINCTRL_PIN(416, "P PAD VDD 5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) PINCTRL_PIN(417, "PO EMIF 0 A01"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PINCTRL_PIN(418, "PIO EMIF 0 D00"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) PINCTRL_PIN(419, "IF 0 SD CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PINCTRL_PIN(420, "APP SPI CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) PINCTRL_PIN(421, "APP SPI DO"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PINCTRL_PIN(422, "APP SPI DI"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) PINCTRL_PIN(423, "APP SPI CS0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PINCTRL_PIN(424, "APP SPI CS1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) PINCTRL_PIN(425, "APP SPI CS2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) PINCTRL_PIN(426, "PIO APP GPIO 10"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PINCTRL_PIN(427, "P PAD VDDIO 41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PINCTRL_PIN(428, "P PAD VSSIO 41"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) PINCTRL_PIN(429, "P PAD GND 6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PINCTRL_PIN(430, "P PAD VDD 6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PINCTRL_PIN(431, "PIO ACC SDIO0 CMD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) PINCTRL_PIN(432, "PIO ACC SDIO0 CK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PINCTRL_PIN(433, "PIO ACC SDIO0 D3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PINCTRL_PIN(434, "PIO ACC SDIO0 D2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) PINCTRL_PIN(435, "PIO ACC SDIO0 D1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PINCTRL_PIN(436, "PIO ACC SDIO0 D0"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PINCTRL_PIN(437, "PIO USB PU"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) PINCTRL_PIN(438, "PIO USB SP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PINCTRL_PIN(439, "PIO USB DAT VP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PINCTRL_PIN(440, "PIO USB SE0 VM"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) PINCTRL_PIN(441, "PIO USB OE"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PINCTRL_PIN(442, "PIO USB SUSP"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PINCTRL_PIN(443, "P PAD VSSIO 6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) PINCTRL_PIN(444, "P PAD VDDIO 6"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) PINCTRL_PIN(445, "PIO USB PUEN"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) PINCTRL_PIN(446, "PIO ACC UART0 RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) PINCTRL_PIN(447, "PIO ACC UART0 TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) PINCTRL_PIN(448, "PIO ACC UART0 CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) PINCTRL_PIN(449, "PIO ACC UART0 RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) PINCTRL_PIN(450, "PIO ACC UART3 RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) PINCTRL_PIN(451, "PIO ACC UART3 TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) PINCTRL_PIN(452, "PIO ACC UART3 CTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) PINCTRL_PIN(453, "PIO ACC UART3 RTS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) PINCTRL_PIN(454, "PIO ACC IRDA TX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) PINCTRL_PIN(455, "P PAD VDDIO 7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) PINCTRL_PIN(456, "P PAD VSSIO 7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) PINCTRL_PIN(457, "P PAD GND 7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) PINCTRL_PIN(458, "P PAD VDD 7"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) PINCTRL_PIN(459, "PIO ACC IRDA RX"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) PINCTRL_PIN(460, "PIO ACC PCM I2S CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) PINCTRL_PIN(461, "PIO ACC PCM I2S WS"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) PINCTRL_PIN(462, "PIO ACC PCM I2S DATA A"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) PINCTRL_PIN(463, "PIO ACC PCM I2S DATA B"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) PINCTRL_PIN(464, "PO SIM CLK"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) PINCTRL_PIN(465, "PIO ACC IRDA SD"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) PINCTRL_PIN(466, "PIO SIM DATA"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * @dev: a pointer back to containing device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * @virtbase: the offset to the controller in virtual memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct u300_pmx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct pinctrl_dev *pctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * u300_pmx_registers - the array of registers read/written for each pinmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * shunt setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static const u32 u300_pmx_registers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) U300_SYSCON_PMC1LR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) U300_SYSCON_PMC1HR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) U300_SYSCON_PMC2R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) U300_SYSCON_PMC3R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) U300_SYSCON_PMC4R,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) * struct u300_pin_group - describes a U300 pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * @name: the name of this specific pin group
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * @pins: an array of discrete physical pins used in this group, taken
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * from the driver-local pin enumeration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * @num_pins: the number of pins in this group array, i.e. the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * elements in .pins so we can iterate over that array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct u300_pin_group {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) const unsigned int *pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) const unsigned num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) * struct pmx_onmask - mask bits to enable/disable padmux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * @mask: mask bits to disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * @val: mask bits to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * onmask lazy dog:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * onmask = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * {"PMC1LR" mask, "PMC1LR" value},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * {"PMC1HR" mask, "PMC1HR" value},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * {"PMC2R" mask, "PMC2R" value},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * {"PMC3R" mask, "PMC3R" value},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * {"PMC4R" mask, "PMC4R" value}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct u300_pmx_mask {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u16 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* The chip power pins are VDD, GND, VDDIO and VSSIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static const unsigned power_pins[] = { 0, 1, 3, 31, 46, 47, 49, 50, 61, 62, 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 64, 78, 79, 80, 81, 92, 93, 94, 95, 101, 102, 103, 104, 115, 116, 117,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 118, 130, 131, 132, 133, 145, 146, 147, 148, 159, 160, 172, 173, 174,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 175, 187, 188, 189, 190, 201, 202, 211, 212, 213, 214, 215, 218, 223,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 224, 225, 226, 231, 232, 237, 238, 239, 240, 245, 246, 251, 252, 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 257, 258, 259, 264, 265, 270, 271, 276, 277, 278, 279, 284, 285, 290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 291, 295, 296, 299, 300, 301, 302, 303, 309, 310, 311, 312, 319, 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 321, 322, 329, 330, 331, 332, 341, 342, 343, 344, 358, 359, 360, 361,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 372, 373, 374, 375, 388, 389, 390, 391, 402, 403, 404, 405, 413, 414,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 415, 416, 427, 428, 429, 430, 443, 444, 455, 456, 457, 458 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static const unsigned emif0_pins[] = { 355, 356, 357, 362, 363, 364, 365, 366,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 367, 368, 369, 370, 371, 376, 377, 378, 379, 380, 381, 382, 383, 384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 385, 386, 387, 393, 394, 395, 396, 397, 398, 406, 407, 410, 411, 412,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 417, 418 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static const unsigned emif1_pins[] = { 216, 217, 219, 220, 221, 222, 227, 228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 229, 230, 233, 234, 235, 236, 241, 242, 243, 244, 247, 248, 249, 250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 253, 254, 255, 260, 261, 262, 263, 266, 267, 268, 269, 272, 273, 274,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 275, 280, 281, 282, 283, 286, 287, 288, 289, 292, 293, 294, 297, 298,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 304, 305, 306, 307, 308, 313, 314, 315 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static const unsigned uart0_pins[] = { 134, 135, 136, 137 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const unsigned mmc0_pins[] = { 166, 167, 168, 169, 170, 171, 176, 177 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static const unsigned spi0_pins[] = { 420, 421, 422, 423, 424, 425 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static const struct u300_pmx_mask emif0_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static const struct u300_pmx_mask emif1_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * This connects the SDRAM to CS2 and a NAND flash to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * CS0 on the EMIF.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) U300_SYSCON_PMC1LR_EMIF_1_CS2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) U300_SYSCON_PMC1LR_EMIF_1_CS1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) U300_SYSCON_PMC1LR_EMIF_1_CS0_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) U300_SYSCON_PMC1LR_EMIF_1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) U300_SYSCON_PMC1LR_EMIF_1_CS2_SDRAM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) U300_SYSCON_PMC1LR_EMIF_1_CS1_STATIC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) U300_SYSCON_PMC1LR_EMIF_1_CS0_NFIF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) U300_SYSCON_PMC1LR_EMIF_1_SDRAM0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static const struct u300_pmx_mask uart0_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) U300_SYSCON_PMC1HR_APP_UART0_1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) U300_SYSCON_PMC1HR_APP_UART0_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) U300_SYSCON_PMC1HR_APP_UART0_1_UART0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) U300_SYSCON_PMC1HR_APP_UART0_2_UART0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const struct u300_pmx_mask mmc0_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) { U300_SYSCON_PMC1LR_MMCSD_MASK, U300_SYSCON_PMC1LR_MMCSD_MMCSD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) { U300_SYSCON_PMC4R_APP_MISC_12_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) U300_SYSCON_PMC4R_APP_MISC_12_APP_GPIO }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const struct u300_pmx_mask spi0_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) U300_SYSCON_PMC1HR_APP_SPI_2_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) U300_SYSCON_PMC1HR_APP_SPI_CS_1_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) U300_SYSCON_PMC1HR_APP_SPI_CS_2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) U300_SYSCON_PMC1HR_APP_SPI_2_SPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) U300_SYSCON_PMC1HR_APP_SPI_CS_1_SPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) U300_SYSCON_PMC1HR_APP_SPI_CS_2_SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static const struct u300_pin_group u300_pin_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .name = "powergrp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .pins = power_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .num_pins = ARRAY_SIZE(power_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .name = "emif0grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .pins = emif0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .num_pins = ARRAY_SIZE(emif0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .name = "emif1grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .pins = emif1_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .num_pins = ARRAY_SIZE(emif1_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .name = "uart0grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .pins = uart0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .num_pins = ARRAY_SIZE(uart0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .name = "mmc0grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .pins = mmc0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .num_pins = ARRAY_SIZE(mmc0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .name = "spi0grp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .pins = spi0_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .num_pins = ARRAY_SIZE(spi0_pins),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int u300_get_groups_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return ARRAY_SIZE(u300_pin_groups);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static const char *u300_get_group_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return u300_pin_groups[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int u300_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) const unsigned **pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned *num_pins)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *pins = u300_pin_groups[selector].pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) *num_pins = u300_pin_groups[selector].num_pins;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) seq_printf(s, " " DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static const struct pinctrl_ops u300_pctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) .get_groups_count = u300_get_groups_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .get_group_name = u300_get_group_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .get_group_pins = u300_get_group_pins,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .pin_dbg_show = u300_pin_dbg_show,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * Here we define the available functions and their corresponding pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * struct u300_pmx_func - describes U300 pinmux functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * @name: the name of this specific function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * @groups: corresponding pin groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * @onmask: bits to set to enable this when doing pin muxing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct u300_pmx_func {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) const char * const *groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) const unsigned num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) const struct u300_pmx_mask *mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static const char * const powergrps[] = { "powergrp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const char * const emif0grps[] = { "emif0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static const char * const emif1grps[] = { "emif1grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) static const char * const uart0grps[] = { "uart0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const char * const mmc0grps[] = { "mmc0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) static const char * const spi0grps[] = { "spi0grp" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const struct u300_pmx_func u300_pmx_functions[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) .name = "power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .groups = powergrps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .num_groups = ARRAY_SIZE(powergrps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Mask is N/A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) .name = "emif0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .groups = emif0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .num_groups = ARRAY_SIZE(emif0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .mask = emif0_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) .name = "emif1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .groups = emif1grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .num_groups = ARRAY_SIZE(emif1grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .mask = emif1_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .name = "uart0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .groups = uart0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .num_groups = ARRAY_SIZE(uart0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .mask = uart0_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .name = "mmc0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .groups = mmc0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .num_groups = ARRAY_SIZE(mmc0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .mask = mmc0_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .name = "spi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .groups = spi0grps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .num_groups = ARRAY_SIZE(spi0grps),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .mask = spi0_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static void u300_pmx_endisable(struct u300_pmx *upmx, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u16 regval, val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) const struct u300_pmx_mask *upmx_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) upmx_mask = u300_pmx_functions[selector].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) for (i = 0; i < ARRAY_SIZE(u300_pmx_registers); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) val = upmx_mask->bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) mask = upmx_mask->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (mask != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) regval = readw(upmx->virtbase + u300_pmx_registers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) regval &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) regval |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) writew(regval, upmx->virtbase + u300_pmx_registers[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) upmx_mask++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int u300_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) unsigned group)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct u300_pmx *upmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* There is nothing to do with the power pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (selector == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) upmx = pinctrl_dev_get_drvdata(pctldev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u300_pmx_endisable(upmx, selector, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int u300_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ARRAY_SIZE(u300_pmx_functions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static const char *u300_pmx_get_func_name(struct pinctrl_dev *pctldev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return u300_pmx_functions[selector].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) const char * const **groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned * const num_groups)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) *groups = u300_pmx_functions[selector].groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) *num_groups = u300_pmx_functions[selector].num_groups;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const struct pinmux_ops u300_pmx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .get_functions_count = u300_pmx_get_funcs_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .get_function_name = u300_pmx_get_func_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .get_function_groups = u300_pmx_get_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .set_mux = u300_pmx_set_mux,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static int u300_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned long *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct pinctrl_gpio_range *range =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) pinctrl_find_gpio_range_from_pin(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* We get config for those pins we CAN get it for and that's it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return u300_gpio_config_get(range->gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) (pin - range->pin_base + range->base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) unsigned long *configs, unsigned num_configs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct pinctrl_gpio_range *range =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) pinctrl_find_gpio_range_from_pin(pctldev, pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!range)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) for (i = 0; i < num_configs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* Note: none of these configurations take any argument */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = u300_gpio_config_set(range->gc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) (pin - range->pin_base + range->base),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) pinconf_to_config_param(configs[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) } /* for each config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static const struct pinconf_ops u300_pconf_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .is_generic = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .pin_config_get = u300_pin_config_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .pin_config_set = u300_pin_config_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static struct pinctrl_desc u300_pmx_desc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .pins = u300_pads,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .npins = ARRAY_SIZE(u300_pads),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .pctlops = &u300_pctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .pmxops = &u300_pmx_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .confops = &u300_pconf_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int u300_pmx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct u300_pmx *upmx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /* Create state holders etc for this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) upmx = devm_kzalloc(&pdev->dev, sizeof(*upmx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (!upmx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) upmx->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) upmx->virtbase = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (IS_ERR(upmx->virtbase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return PTR_ERR(upmx->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) upmx->pctl = devm_pinctrl_register(&pdev->dev, &u300_pmx_desc, upmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (IS_ERR(upmx->pctl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev_err(&pdev->dev, "could not register U300 pinmux driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return PTR_ERR(upmx->pctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) platform_set_drvdata(pdev, upmx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_info(&pdev->dev, "initialized U300 pin control driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct of_device_id u300_pinctrl_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) { .compatible = "stericsson,pinctrl-u300" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static struct platform_driver u300_pmx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .of_match_table = u300_pinctrl_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .probe = u300_pmx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static int __init u300_pmx_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return platform_driver_register(&u300_pmx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) arch_initcall(u300_pmx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static void __exit u300_pmx_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) platform_driver_unregister(&u300_pmx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) module_exit(u300_pmx_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) MODULE_DESCRIPTION("U300 pin control driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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